WO2018145347A1 - 显示驱动电路及液晶显示面板 - Google Patents

显示驱动电路及液晶显示面板 Download PDF

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Publication number
WO2018145347A1
WO2018145347A1 PCT/CN2017/076772 CN2017076772W WO2018145347A1 WO 2018145347 A1 WO2018145347 A1 WO 2018145347A1 CN 2017076772 W CN2017076772 W CN 2017076772W WO 2018145347 A1 WO2018145347 A1 WO 2018145347A1
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Prior art keywords
gate
tft
pixel
control signal
signal
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PCT/CN2017/076772
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English (en)
French (fr)
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左清成
李曼
袁小玲
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武汉华星光电技术有限公司
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Priority to US15/516,898 priority Critical patent/US10304401B2/en
Publication of WO2018145347A1 publication Critical patent/WO2018145347A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a display driving circuit and a liquid crystal display panel.
  • a liquid crystal display includes a plurality of pixels arranged in an array, each of which generally includes three colors of red, green, and blue sub-pixels, each of which is controlled by one scan line. And a data line, the scan line is used to control the opening and closing of the sub-pixel, and the data line displays different gray scales by applying different data voltage signals to the sub-pixels, thereby realizing the display of the full-color picture.
  • a conventional multiplexed display driving circuit includes:
  • Each of the pixel units P includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, which are sequentially arranged from left to right, and a first switching TFT T1 electrically connected to the red sub-pixel R. a second switching TFT T2 connected to the green sub-pixel G and a third switching TFT T3 electrically connected to the blue sub-pixel B; each multiplexing module DM includes a column corresponding to the red sub-pixel R and a green sub-pixel G, respectively The column, the first control TFT T10, the second control TFT T20, and the third control TFT T30 are disposed in column B of the blue sub-pixel.
  • n and m be positive integers.
  • the gate of the first switching TFT T1 the gate of the second switching TFT T2, and the gate of the third switching TFT T3 are electrically uniform.
  • the source of the first switching TFT T1, the source of the second switching TFT T2, and the source of the third switching TFT T3 are electrically respectively Connecting the drain of the first control TFT T10, the drain of the second control TFT T20, and the drain of the third control TFT T30 in the mth multiplexing module DM corresponding to the pixel unit P of the mth column, first Switching TFT
  • the drain of T1, the drain of the second switching TFT T2, and the drain of the third switching TFT T3 are electrically connected to the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B, respectively.
  • the gate of the first control TFT T10, the gate of the second control TFT T20, and the gate of the third control TFT T30 are respectively connected to the first shunt control signal MUXR,
  • the two-way control signal MUXG and the third shunt control signal MUXB, the source of the first control TFT T10, the source of the second control TFT T20, and the source of the third control TFT T30 are electrically connected correspondingly to the mth The mth data line D(m) set by the column pixel unit P.
  • step S100 the scan signal in the nth scan line G(n) changes from low to high, and all the first switch TFT T1, the second switch TFT T2, and the third switch TFT T3 of the nth row are turned on, and the elapsed time After ⁇ t, the first shunt control signal MUXR is pulled high, at which time all the first control TFTs T10 are simultaneously turned on, and the data signals in the respective data lines are turned on by the first control TFT T10 and the first switching TFT T1. Start charging all the red sub-pixels R of the nth row.
  • the first shunt control signal MUXR is pulled low, and after the lapse of time ⁇ t, the second shunt control signal MUXG is pulled high, and all the second control is performed at this time.
  • the TFT T20 is simultaneously turned on, and the data signals in the respective data lines are turned on by the second control TFT T20 and the second switching TFT T2 which are turned on to charge all the green sub-pixels G of the nth row.
  • the second shunt control signal MUXG is pulled low, and after the lapse of time ⁇ t, the third shunt control signal MUXB is pulled high, and all the third controls are performed at this time.
  • the TFT T30 is simultaneously turned on, and the data signals in the respective data lines are charged by the third control TFT T30 and the third switching TFT T3 which are turned on to charge all the blue sub-pixels B of the nth row.
  • Step S400 After all the blue sub-pixels B in the nth row are charged, the third shunt control signal MUXB is pulled low, and after the elapse of time ⁇ t, the scan signal in the nth scan line G(n) is pulled low. Complete charging of a line cycle signal.
  • step S500 the scan signal in the next scan line is changed from low to high, and the above steps S100 to S400 are repeated to complete the entire LCD charging.
  • the existing multiplexed display driving circuit sequentially pulls up the first shunt control signal MUXR, the second shunt control signal MUXG, and the third shunt control signal MUXB in a time period in which one row of scan signals is pulled high. To complete charging of a row of red sub-pixels R, green sub-pixels G, and blue sub-pixels B.
  • Another object of the present invention is to provide a liquid crystal display panel which has less signal glitch, higher signal quality, and better picture display quality.
  • the present invention firstly provides a display driving circuit including a plurality of pixel units arranged in a matrix, scan lines corresponding to each row of pixel units, data lines corresponding to each column of pixel units, and corresponding columns.
  • a multiplexing unit provided by the pixel unit, and first and second AND gates, and a third AND gate;
  • the two input ends of the first AND gate respectively access the first shunt control signal and the adjustment signal, and the two input ends of the second AND gate respectively access the second shunt control signal and the adjustment signal, the third The two input ends of the AND gate respectively access the third branch control signal and the adjustment signal;
  • Each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel arranged in order from left to right, and a first switching TFT electrically connected to the red sub-pixel, and a second switch electrically connected to the green sub-pixel a TFT, and a third switching TFT electrically connected to the blue sub-pixel;
  • each multiplexing module includes a first control TFT respectively corresponding to the red sub-pixel column, the green sub-pixel column, and the blue sub-pixel column, a second control TFT, and a third control TFT;
  • n and m be positive integers.
  • the gate of the first switching TFT, the gate of the second switching TFT, and the gate of the third switching TFT are electrically connected to the corresponding nth.
  • the nth scan line of the pixel unit, the source of the first switching TFT, the source of the second switching TFT, and the source of the third switching TFT are electrically connected to the mth corresponding to the pixel unit of the mth column a drain of the first control TFT, a drain of the second control TFT, and a drain of the third control TFT, a drain of the first switching TFT, a drain of the second switching TFT, and a third
  • the drains of the switching TFTs are electrically connected to the red sub-pixel, the green sub-pixel, and the blue sub-pixel, respectively;
  • the gate of the first control TFT, the gate of the second control TFT, and the gate of the third control TFT are electrically connected to the output end of the first AND gate, respectively, and the second AND gate
  • the output end and the output end of the third AND gate, the source of the first control TFT, the source of the second control TFT, and the source of the third control TFT are electrically connected correspondingly to the pixel unit of the mth column m data lines.
  • the high potential duration of the scan signal in the nth scan line is greater than the first shunt control signal, The sum of the two-way control signal and the high-potential duration of the third shunt control signal; the adjustment signal respectively corresponding to the high-potential duration of the first shunt control signal, the second shunt control signal, and the third shunt control signal
  • the high-low potential conversion is performed several times to maintain the high potential, and the signals outputted by the output terminals of the first AND gate, the second AND gate, and the third AND gate are first made to perform high-low potential conversion and then remain high.
  • the high potential duration and the low potential duration are both a preset duration.
  • the first shunt control signal, the second shunt control signal, and the third shunt control signal are sequentially generated in sequence, and the rising edge of the second shunt control signal is later than the falling edge of the first shunt control signal.
  • the rising edge of the third shunt control signal is later than the falling edge of the second shunt control signal.
  • the first switching TFT, the second switching TFT, the third switching TFT, the first control TFT, the second control TFT, and the third control TFT are all low temperature polysilicon TFTs, oxide semiconductor TFTs, or amorphous silicon TFTs.
  • the present invention also provides a liquid crystal display panel having a display driving circuit, the display driving circuit comprising a plurality of pixel units arranged in a matrix, scan lines corresponding to each row of pixel units, and data corresponding to each column of pixel units a line, a multiplexing module corresponding to each column of pixel units, and a first AND gate, a second AND gate, and a third AND gate;
  • the two input ends of the first AND gate respectively access the first shunt control signal and the adjustment signal, and the two input ends of the second AND gate respectively access the second shunt control signal and the adjustment signal, the third The two input ends of the AND gate respectively access the third branch control signal and the adjustment signal;
  • Each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel arranged in order from left to right, and a first switching TFT electrically connected to the red sub-pixel, and a second switch electrically connected to the green sub-pixel a TFT, and a third switching TFT electrically connected to the blue sub-pixel;
  • each multiplexing module includes a first control TFT respectively corresponding to the red sub-pixel column, the green sub-pixel column, and the blue sub-pixel column, a second control TFT, and a third control TFT;
  • n and m be positive integers.
  • the gate of the first switching TFT, the gate of the second switching TFT, and the gate of the third switching TFT are electrically connected to the corresponding nth.
  • the nth scan line of the pixel unit, the source of the first switching TFT, the source of the second switching TFT, and the source of the third switching TFT are electrically connected to the mth corresponding to the pixel unit of the mth column a drain of the first control TFT, a drain of the second control TFT, and a drain of the third control TFT, a drain of the first switching TFT, a drain of the second switching TFT, and a third
  • the drains of the switching TFTs are electrically connected to the red sub-pixel, the green sub-pixel, and the blue sub-pixel, respectively;
  • the gate of the first control TFT, the gate of the second control TFT, and the gate of the third control TFT are electrically connected to the output end of the first AND gate, respectively, and the second AND gate of The output end and the output end of the third AND gate, the source of the first control TFT, the source of the second control TFT, and the source of the third control TFT are electrically connected to the mth corresponding to the pixel unit of the mth column Data line.
  • the high potential duration of the scan signal in the nth scan line is greater than the sum of the first shunt control signal, the second shunt control signal, and the high potential duration of the third shunt control signal;
  • the high-low potential conversion is performed several times and then the high potential is maintained, correspondingly making the first AND gate, the second AND gate, and the first
  • the signal output from the output of the three-AND gate is first turned on high and low potentials to maintain a high potential.
  • the high potential duration and the low potential duration are both a preset duration.
  • the first shunt control signal, the second shunt control signal, and the third shunt control signal are sequentially generated in sequence, and the rising edge of the second shunt control signal is later than the falling edge of the first shunt control signal.
  • the rising edge of the third shunt control signal is later than the falling edge of the second shunt control signal.
  • the first switching TFT, the second switching TFT, the third switching TFT, the first control TFT, the second control TFT, and the third control TFT are all low temperature polysilicon TFTs, oxide semiconductor TFTs, or amorphous silicon TFTs.
  • the present invention also provides a liquid crystal display panel having a display driving circuit, the display driving circuit comprising a plurality of pixel units arranged in a matrix, scan lines corresponding to each row of pixel units, and data corresponding to each column of pixel units a line, a multiplexing module corresponding to each column of pixel units, and a first AND gate, a second AND gate, and a third AND gate;
  • the two input ends of the first AND gate respectively access the first shunt control signal and the adjustment signal, and the two input ends of the second AND gate respectively access the second shunt control signal and the adjustment signal, the third The two input ends of the AND gate respectively access the third branch control signal and the adjustment signal;
  • Each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel arranged in order from left to right, and a first switching TFT electrically connected to the red sub-pixel, and a second switch electrically connected to the green sub-pixel a TFT, and a third switching TFT electrically connected to the blue sub-pixel;
  • each multiplexing module includes a first control TFT respectively corresponding to the red sub-pixel column, the green sub-pixel column, and the blue sub-pixel column, a second control TFT, and a third control TFT;
  • n and m be positive integers.
  • the gate of the first switching TFT, the gate of the second switching TFT, and the gate of the third switching TFT are electrically connected to the corresponding nth.
  • the nth scan line of the pixel unit, the source of the first switching TFT, the source of the second switching TFT, and the source of the third switching TFT are electrically connected to the mth corresponding to the pixel unit of the mth column a drain of the first control TFT, a drain of the second control TFT, and a third control in the multiplexing module a drain of the TFT, a drain of the first switching TFT, a drain of the second switching TFT, and a drain of the third switching TFT are electrically connected to the red sub-pixel, the green sub-pixel, and the blue sub-pixel, respectively;
  • the gate of the first control TFT, the gate of the second control TFT, and the gate of the third control TFT are electrically connected to the output end of the first AND gate, respectively, and the second AND gate
  • the output end and the output end of the third AND gate, the source of the first control TFT, the source of the second control TFT, and the source of the third control TFT are electrically connected correspondingly to the pixel unit of the mth column m data lines;
  • the high potential duration of the scan signal in the nth scan line is greater than the sum of the first shunt control signal, the second shunt control signal, and the high potential duration of the third shunt control signal;
  • the high-low potential conversion is performed several times to maintain the high potential, and the first and second gates are correspondingly correspondingly
  • the signal outputted by the output of the third AND gate is first turned on high and low potentials to maintain a high potential;
  • the first switching TFT, the second switching TFT, the third switching TFT, the first control TFT, the second control TFT, and the third control TFT are all low temperature polysilicon TFTs, oxide semiconductor TFTs, or amorphous silicon TFTs. .
  • a display driving circuit and a liquid crystal display panel are provided, and a first AND gate, a second AND gate, and a third sum are added to the existing multiplexed display driving circuit.
  • a first branch control signal and an adjustment signal are respectively input to the two input ends of the first AND gate
  • the second branch control signal and the adjustment signal are respectively input to the two input ends of the second AND gate
  • the two input ends of the third AND gate respectively access the third shunt control signal and the adjustment signal; the adjustment signals respectively correspond to the first shunt control signal, the second shunt control signal, and the third shunt control signal
  • the signals outputted by the output terminals of the first AND gate, the second AND gate, and the third AND gate are first turned into high-low potential conversion and then maintained at a high potential.
  • the TFT and the third control TFT are different in the near state of the signal and the remote end of the signal, so that each sub-pixel is inconsistent with the time at which the maximum current appears at the near end of the signal and the far end of the signal, thereby avoiding signal glitch formed by excessive transient load.
  • 1 is a circuit diagram of a conventional multiplex type display driving circuit
  • FIG. 2 is a timing chart corresponding to the conventional multiplex type display driving circuit shown in FIG. 1;
  • FIG. 3 is an actual signal waveform diagram corresponding to the conventional multiplex type display driving circuit shown in FIG. 1;
  • FIG. 4 is a circuit diagram of a display driving circuit of the present invention.
  • Figure 5 is a timing chart of the display driving circuit of the present invention.
  • FIG. 6 is a waveform diagram of signals outputted by the output ends of the first AND gate, the second AND gate, and the third AND gate in the display driving circuit of the present invention
  • FIG. 7 is a schematic diagram showing the waveforms of the control TFTs at the near end of the signal in the stage of the high and low potential conversion of the display signal in the display driving circuit of the present invention, wherein the thin line is an ideal waveform and the thick line is an actual waveform;
  • FIG. 8 is a schematic diagram of waveforms of the control TFTs at the far end of the signal in the stage of high and low potential conversion of the display driving circuit of the present invention, wherein the thin line is an ideal waveform and the thick line is an actual waveform.
  • the present invention firstly provides a display driving circuit, including a plurality of pixel units P arranged in a matrix, scan lines corresponding to each row of pixel units P, data lines corresponding to each column of pixel units P, The multiplexing module DM provided for each column of pixel units P, and the first AND gate AND1, the second AND gate AND2, and the third AND gate AND3.
  • the two input ends of the first AND gate AND1 are respectively connected to the first shunt control signal MUXR and the adjustment signal BURR, and the two input ends of the second AND gate AND2 are respectively connected to the second shunt control signal MUXG and the adjustment signal BURR, the two input ends of the third AND gate AND3 are respectively connected to the third branch control signal MUXB and the adjustment signal BURR.
  • Each of the pixel units P includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B arranged in order from left to right, and a first switching TFT T1 electrically connected to the red sub-pixel R, electrically connected to the green a second switching TFT T2 of the sub-pixel G and a third switching TFT T3 electrically connected to the blue sub-pixel B; each multiplexing module DM includes a column corresponding to a red sub-pixel R, a green sub-pixel G, The first control TFT T10, the second control TFT T20, and the third control TFT T30 are disposed in column B of the blue sub-pixel.
  • n and m be positive integers.
  • the gate of the first switching TFT T1 the gate of the second switching TFT T2, and the gate of the third switching TFT T3 are electrically uniform.
  • the source of the first switching TFT T1, the source of the second switching TFT T2, and the source of the third switching TFT T3 are electrically respectively Connecting the drain of the first control TFT T10, the drain of the second control TFT T20, and the drain of the third control TFT T30 in the mth multiplexing module DM corresponding to the pixel unit P of the mth column, first The drain of the switching TFT T1, the drain of the second switching TFT T2, and the drain of the third switching TFT T3 are electrically connected to the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B, respectively.
  • the gate of the first control TFT T10, the gate of the second control TFT T20, and the gate of the third control TFT T30 are electrically connected to the output of the first AND gate AND1, respectively.
  • the output end of the second AND gate AND2, and the output end of the third AND gate AND3, the source of the first control TFT T10, the source of the second control TFT T20, and the source uniformity of the third control TFT T30 The mth data line D(m) corresponding to the pixel unit P of the mth column is connected.
  • the high potential duration of the scan signal in the nth scan line G(n) is greater than the first shunt control signal MUXR, the second shunt control signal MUXG, and the third shunt control signal MUXB.
  • the sum of the high potential durations; the adjustment signal BURR respectively performs the high and low potential conversions in the high potential duration corresponding to the first shunt control signal MUXR, the second shunt control signal MUXG, and the third shunt control signal MUXB, respectively.
  • the high potential is maintained, and the signals outputted by the output terminals of the first AND gate AND1, the second AND gate AND2, and the third AND gate AND3 are first turned on several times to maintain a high potential.
  • the first switching TFT T1, the second switching TFT T2, the third switching TFT T3, the first control TFT T10, the second control TFT T20, and the third control TFT T30 are all low temperature polysilicon TFTs and oxide semiconductors. TFT, or amorphous silicon TFT;
  • the first shunt control signal MUXR, the second shunt control signal MUXG, and the third shunt control signal MUXB are sequentially generated in sequence, and the rising edge of the second shunt control signal MUXG is later than the first shunt control signal.
  • the falling edge of the MUXR, the rising edge of the third shunt control signal MUXB is later than the falling edge of the second shunt control signal MUXG.
  • the working process of the display driving circuit is:
  • the scan signal in the nth scan line G(n) changes from low to high, and all the first switching TFT T1, the second switching TFT T2, and the third switching TFT T3 in the nth row are turned on, after After the time t1, the first shunt control signal MUXR and the adjustment signal BURR are simultaneously pulled high, and the output end of the first AND gate AND1 outputs a high potential signal, and the first end electrically connected to the output end of the first AND gate AND1
  • the control TFT T10 is turned on, and the first control TFT T10 and the first switching TFT T1, which are turned on by the data signals in the respective data lines, start charging the red sub-pixels R of the nth row. Electricity, the duration is a preset duration t;
  • Step 3 repeat steps 1 and 2 several times.
  • the signal is near the end of the adjustment signal BURR.
  • the first control TFT T10 has a good on state, and the on-state of the first control TFT T10 at the far end of the signal is poor, so the charging current of the red sub-pixel R at the near end of the signal is larger than the far end, and the red end of the signal is remote.
  • the charging current of the pixel R is small or no current state.
  • the red sub-pixel R at the near end of the signal basically reaches the charging requirement, and the red sub-pixel R at the far end of the signal is due to the A reason for controlling the TFT T10 to be in a state of poor state, the power change is little or no change, which avoids the high current charging state of the signal near end and the signal far end, reducing the occurrence of instantaneous large current, thereby avoiding excessive load due to transient load.
  • the resulting signal glitch improves signal quality and improves picture display quality.
  • the adjustment signal BURR is continuously pulled high to maintain the high potential, and the charging of all the red sub-pixels R in the nth row is completed, the duration is t2, and t2 is greater than the preset time length t.
  • the first control TFT T10 of the signal near and far ends is in a good on state, but due to the near end of the signal
  • the red sub-pixel R has substantially reached the required amount of charge, the current flow is relatively small, the charging speed is slowed, and the red sub-pixel R at the far end of the signal is relatively large due to the opening state of the first control TFT T10.
  • the current also avoids the high current charging state between the near end of the signal and the far end of the signal, reducing the occurrence of instantaneous large currents, thereby avoiding signal glitch formed by excessive transient load, improving signal quality, and improving picture display quality.
  • Step 5 similar to steps 1 to 4, first pull the second shunt control signal MUXG and the adjustment signal BURR simultaneously, and after the preset duration t, the adjustment signal BURR is pulled low, and then the preset duration is continued. t, then repeats several times, and finally the adjustment signal BURR is continuously pulled high for a duration of t2, and the charging of all the green sub-pixels G of the nth row is completed, and the near-end signal and the far-end of the signal can be prevented from being in a large current charging state. It reduces the occurrence of large currents in an instant, thereby avoiding signal glitch formed by excessive transient load, improving signal quality, and improving picture display quality.
  • Step 6 similar to steps 1 to 4, first pull the third shunt control signal MUXB and the adjustment signal BURR at the same time, and after the preset duration t, the adjustment signal BURR is pulled low, and then the preset duration is continued. t, then repeat several times, and finally the adjustment signal BURR continues to be pulled up for a duration of T2, the charging of all the blue sub-pixels B in the nth row is completed, and the high-current charging state of the signal near-end and the signal far-end is avoided, and the instantaneous large current is reduced, thereby avoiding the formation of the transient load. Signal glitches improve signal quality and improve picture quality.
  • step 7 the scan signal in the next scan line changes from low to high, and the above steps 1 to 6 are repeated to complete the entire LCD charging.
  • the present invention further provides a liquid crystal display panel having the above display driving circuit, which has fewer signal spurs, higher signal quality, and better picture display quality, and the structure of the display driving circuit is not repeatedly described herein. And the work process.
  • the first AND gate, the second AND gate, and the third AND gate are added to the conventional multiplexed display driving circuit.
  • the two input ends of the first AND gate are respectively connected to the first shunt control signal and the adjustment signal, and the two input ends of the second AND gate are respectively connected to the second shunt control signal and the adjustment signal, and the third AND gate
  • the two input ends respectively input the third shunt control signal and the adjustment signal; the adjustment signals are respectively within a high potential duration corresponding to the first shunt control signal, the second shunt control signal, and the third shunt control signal, First, do a few high and low potential conversions and then maintain a high potential.
  • the signals output from the output terminals of the first AND, the second AND, and the third AND gate are first turned into high and low potentials to maintain a high potential, because the circuit itself goes.
  • the resistance-capacitance delay characteristic of the line is respectively controlled by the signal outputted by the output of the first AND gate, the signal outputted by the output of the second AND gate, and the first control TFT and the second controlled by the signal outputted by the output of the third AND gate Control TFT, third control TFT
  • the near-end state of the signal is different from the open state of the signal remote end, so that each sub-pixel is inconsistent with the time when the maximum current appears at the near end of the signal and the far end of the signal, thereby avoiding signal glitch formed by excessive transient load, improving signal quality, and improving the picture. Display quality.

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Abstract

一种显示驱动电路及液晶显示面板，增设了第一与门(AND1)、第二与门(AND2)、和第三与门(AND3)，三者各自的两输入端分别接入一分路控制信号与调节信号(BURR)，调节信号(BURR)分别在对应各分路控制信号的高电位时长内先做数次高低电位转换再保持高电位，使得第一与门(AND1)、第二与门(AND2)、第三与门(AND3)的输出端输出的信号先做数次高低电位转换再保持高电位，从而使分别受第一与门(AND1)、第二与门(AND2)、第三与门(AND3)的输出端输出的信号控制的控制TFT在信号近端与信号远端的开启状态不同，各子像素在信号近端与信号远端出现最大电流的时间不一致，从而避免因瞬间负载过重形成的信号毛刺。

Description

显示驱动电路及液晶显示面板 技术领域
本发明涉及液晶显示技术领域，尤其涉及一种显示驱动电路及液晶显示面板。
背景技术
在液晶显示装置(Liquid Crystal Display，LCD)中包括多个呈阵列式排布的像素，每个像素通常包括红、绿、蓝三种颜色的子像素，每个子像素均受控于一条扫描线与一条数据线，扫描线用于控制子像素的开启和关闭，数据线通过向子像素施加不同的数据电压信号，使子像素显示不同的灰阶，从而实现全彩画面的显示。
随着液晶显示技术的发展，人们不仅对LCD显示屏幕的需求越来越大，也对显示的清晰度要求也越来越高，对画面显示品质的追求越来越严格，因此，如何提高画面的显示品质，改善每一个输入输出信号单元的信号质量，成为一个值得研究和探讨的课题。
为了减少布线，目前LCD多采用多路复用型(MUX)显示驱动电路。请参阅图1，现有的一种多路复用型显示驱动电路，包括：
呈矩阵式排布的多个像素单元P、对应每一行像素单元P设置的扫描线、对应每一列像素单元P设置的数据线、及对应每一列像素单元P设置的多路复用模块DM。
其中，每一像素单元P均包括自左至右依次排列的红色子像素R、绿色子像素G、与蓝色子像素B，以及电性连接红色子像素R的第一开关TFT T1、电性连接绿色子像素G的第二开关TFT T2、与电性连接蓝色子像素B的第三开关TFT T3；每一多路复用模块DM包括分别对应于红色子像素R列、绿色子像素G列、与蓝色子像素B列设置的第一控制TFT T10、第二控制TFT T20、及第三控制TFT T30。
设n、m均为正整数，对于第n行第m列像素单元P：第一开关TFT T1的栅极、第二开关TFT T2的栅极、及第三开关TFT T3的栅极均电性连接对应第n行素单元P设置的第n条扫描线G(n)，第一开关TFT T1的源极、第二开关TFT T2的源极、及第三开关TFT T3的源极分别电性连接对应第m列像素单元P设置的第m个多路复用模块DM中第一控制TFT T10的漏极、第二控制TFT T20的漏极、及第三控制TFT T30的漏极，第一开关TFT  T1的漏极、第二开关TFT T2的漏极、及第三开关TFT T3的漏极分别电性连接红色子像素R、绿色子像素G、及蓝色子像素B。对于第m个多路复用模块DM：第一控制TFT T10的栅极、第二控制TFT T20的栅极、及第三控制TFT T30的栅极分别接入第一分路控制信号MUXR、第二分路控制信号MUXG、及第三分路控制信号MUXB，第一控制TFT T10的源极、第二控制TFT T20的源极、及第三控制TFT T30的源极均电性连接对应第m列像素单元P设置的第m条数据线D(m)。
结合图1与图2，该现有的多路复用型显示驱动电路的工作过程为：
步骤S100、第n条扫描线G(n)内的扫描信号由低到高变化，第n行的所有第一开关TFT T1、第二开关TFT T2、与第三开关TFT T3均开启，经过时间△t后，将第一分路控制信号MUXR拉高，此时所有的第一控制TFT T10同时开启，各条数据线内的数据信号经导通的第一控制TFT T10与第一开关TFT T1开始对第n行的所有红色子像素R进行充电。
步骤S200、第n行的所有红色子像素R充电完成后，第一分路控制信号MUXR拉低，经过时间△t后，将第二分路控制信号MUXG拉高，此时所有的第二控制TFT T20同时开启，各条数据线内的数据信号经导通的第二控制TFT T20与第二开关TFT T2开始对第n行的所有绿色子像素G进行充电。
步骤S300、第n行的所有绿色子像素G充电完成后，第二分路控制信号MUXG拉低，经过时间△t后，将第三分路控制信号MUXB拉高，此时所有的第三控制TFT T30同时开启，各条数据线内的数据信号经导通的第三控制TFT T30与第三开关TFT T3开始对第n行的所有蓝色子像素B进行充电。
步骤S400、第n行的所有蓝色子像素B充电完成后，第三分路控制信号MUXB拉低，经过时间△t后，将第n条扫描线G(n)内的扫描信号拉低，完成一个行周期信号的充电。
步骤S500、随后下一条扫描线内的扫描信号由低到高变化，重复以上步骤S100至S400完成整个LCD充电。
该现有的多路复用型显示驱动电路在一行扫描信号拉高的时间周期内，分别先后拉高第一分路控制信号MUXR、第二分路控制信号MUXG、第三分路控制信号MUXB，以完成对一行红色子像素R、绿色子像素G、蓝色子像素B的充电。然而，当第一分路控制信号MUXR(或第二分路控制信号MUXG或第三分路控制信号MUXB)拉高的时候，相应行的所有红色子像素R(或绿色子像素G或蓝色子像素B)均处于较大充电电流的状 态，从而会导致液晶模组(LCM)瞬间对液晶面板驱动集成电路(IC)形成一个较大的电流抽载，造成IC输出，即驱动电路的实际输入信号出现如图3所示的毛刺。
发明内容
本发明的目的在于提供一种显示驱动电路，能够避免因负载过重形成的信号毛刺，改善信号质量。
本发明的另一目的在于提供一种液晶显示面板，其信号毛刺较少，信号质量较高，画面显示品质较好。
为实现上述目的，本发明首先提供一种显示驱动电路，包括呈矩阵式排布的多个像素单元、对应每一行像素单元设置的扫描线、对应每一列像素单元设置的数据线、对应每一列像素单元设置的多路复用模块、以及第一与门、第二与门、和第三与门；
所述第一与门的两输入端分别接入第一分路控制信号与调节信号，所述第二与门的两输入端分别接入第二分路控制信号与调节信号，所述第三与门的两输入端分别接入第三分路控制信号与调节信号；
每一像素单元均包括自左至右依次排列的红色子像素、绿色子像素、与蓝色子像素，以及电性连接红色子像素的第一开关TFT、电性连接绿色子像素的第二开关TFT、与电性连接蓝色子像素的第三开关TFT；每一多路复用模块包括分别对应于红色子像素列、绿色子像素列、与蓝色子像素列设置的第一控制TFT、第二控制TFT、及第三控制TFT；
设n、m均为正整数，对于第n行第m列像素单元：第一开关TFT的栅极、第二开关TFT的栅极、及第三开关TFT的栅极均电性连接对应第n行素单元设置的第n条扫描线，第一开关TFT的源极、第二开关TFT的源极、及第三开关TFT的源极分别电性连接对应第m列像素单元设置的第m个多路复用模块中第一控制TFT的漏极、第二控制TFT的漏极、及第三控制TFT的漏极，第一开关TFT的漏极、第二开关TFT的漏极、及第三开关TFT的漏极分别电性连接红色子像素、绿色子像素、及蓝色子像素；
对于第m个多路复用模块：第一控制TFT的栅极、第二控制TFT的栅极、及第三控制TFT的栅极分别电性连接第一与门的输出端、第二与门的输出端、及第三与门的输出端，第一控制TFT的源极、第二控制TFT的源极、及第三控制TFT的源极均电性连接对应第m列像素单元设置的第m条数据线。
第n条扫描线内的扫描信号的高电位时长大于第一分路控制信号、第 二分路控制信号、与第三分路控制信号的高电位时长之和；所述调节信号分别在对应第一分路控制信号、第二分路控制信号、第三分路控制信号的高电位时长内，先做数次高低电位转换再保持高电位，相应使得第一与门、第二与门、第三与门的输出端输出的信号先做数次高低电位转换再保持高电位。
在调节信号做数次高低电位转换的过程中，高电位持续时间与低电位持续时间均为一预设时长。
所述第一分路控制信号、第二分路控制信号、与第三分路控制信号按时序先后产生，且第二分路控制信号的上升沿晚于第一分路控制信号的下降沿，第三分路控制信号的上升沿晚于第二分路控制信号的下降沿。
所述第一开关TFT、第二开关TFT、第三开关TFT、第一控制TFT、第二控制TFT、及第三控制TFT均为低温多晶硅TFT、氧化物半导体TFT、或非晶硅TFT。
本发明还提供一种液晶显示面板，具有显示驱动电路，所述显示驱动电路包括呈矩阵式排布的多个像素单元、对应每一行像素单元设置的扫描线、对应每一列像素单元设置的数据线、对应每一列像素单元设置的多路复用模块、以及第一与门、第二与门、和第三与门；
所述第一与门的两输入端分别接入第一分路控制信号与调节信号，所述第二与门的两输入端分别接入第二分路控制信号与调节信号，所述第三与门的两输入端分别接入第三分路控制信号与调节信号；
每一像素单元均包括自左至右依次排列的红色子像素、绿色子像素、与蓝色子像素，以及电性连接红色子像素的第一开关TFT、电性连接绿色子像素的第二开关TFT、与电性连接蓝色子像素的第三开关TFT；每一多路复用模块包括分别对应于红色子像素列、绿色子像素列、与蓝色子像素列设置的第一控制TFT、第二控制TFT、及第三控制TFT；
设n、m均为正整数，对于第n行第m列像素单元：第一开关TFT的栅极、第二开关TFT的栅极、及第三开关TFT的栅极均电性连接对应第n行素单元设置的第n条扫描线，第一开关TFT的源极、第二开关TFT的源极、及第三开关TFT的源极分别电性连接对应第m列像素单元设置的第m个多路复用模块中第一控制TFT的漏极、第二控制TFT的漏极、及第三控制TFT的漏极，第一开关TFT的漏极、第二开关TFT的漏极、及第三开关TFT的漏极分别电性连接红色子像素、绿色子像素、及蓝色子像素；
对于第m个多路复用模块：第一控制TFT的栅极、第二控制TFT的栅极、及第三控制TFT的栅极分别电性连接第一与门的输出端、第二与门的 输出端、及第三与门的输出端，第一控制TFT的源极、第二控制TFT的源极、及第三控制TFT的源极均电性连接对应第m列像素单元设置的第m条数据线。
第n条扫描线内的扫描信号的高电位时长大于第一分路控制信号、第二分路控制信号、与第三分路控制信号的高电位时长之和；所述调节信号分别在对应第一分路控制信号、第二分路控制信号、第三分路控制信号的高电位时长内，先做数次高低电位转换再保持高电位，相应使得第一与门、第二与门、第三与门的输出端输出的信号先做数次高低电位转换再保持高电位。
在调节信号做数次高低电位转换的过程中，高电位持续时间与低电位持续时间均为一预设时长。
所述第一分路控制信号、第二分路控制信号、与第三分路控制信号按时序先后产生，且第二分路控制信号的上升沿晚于第一分路控制信号的下降沿，第三分路控制信号的上升沿晚于第二分路控制信号的下降沿。
所述第一开关TFT、第二开关TFT、第三开关TFT、第一控制TFT、第二控制TFT、及第三控制TFT均为低温多晶硅TFT、氧化物半导体TFT、或非晶硅TFT。
本发明还提供一种液晶显示面板，具有显示驱动电路，所述显示驱动电路包括呈矩阵式排布的多个像素单元、对应每一行像素单元设置的扫描线、对应每一列像素单元设置的数据线、对应每一列像素单元设置的多路复用模块、以及第一与门、第二与门、和第三与门；
所述第一与门的两输入端分别接入第一分路控制信号与调节信号，所述第二与门的两输入端分别接入第二分路控制信号与调节信号，所述第三与门的两输入端分别接入第三分路控制信号与调节信号；
每一像素单元均包括自左至右依次排列的红色子像素、绿色子像素、与蓝色子像素，以及电性连接红色子像素的第一开关TFT、电性连接绿色子像素的第二开关TFT、与电性连接蓝色子像素的第三开关TFT；每一多路复用模块包括分别对应于红色子像素列、绿色子像素列、与蓝色子像素列设置的第一控制TFT、第二控制TFT、及第三控制TFT；
设n、m均为正整数，对于第n行第m列像素单元：第一开关TFT的栅极、第二开关TFT的栅极、及第三开关TFT的栅极均电性连接对应第n行素单元设置的第n条扫描线，第一开关TFT的源极、第二开关TFT的源极、及第三开关TFT的源极分别电性连接对应第m列像素单元设置的第m个多路复用模块中第一控制TFT的漏极、第二控制TFT的漏极、及第三控 制TFT的漏极，第一开关TFT的漏极、第二开关TFT的漏极、及第三开关TFT的漏极分别电性连接红色子像素、绿色子像素、及蓝色子像素；
对于第m个多路复用模块：第一控制TFT的栅极、第二控制TFT的栅极、及第三控制TFT的栅极分别电性连接第一与门的输出端、第二与门的输出端、及第三与门的输出端，第一控制TFT的源极、第二控制TFT的源极、及第三控制TFT的源极均电性连接对应第m列像素单元设置的第m条数据线；
其中，第n条扫描线内的扫描信号的高电位时长大于第一分路控制信号、第二分路控制信号、与第三分路控制信号的高电位时长之和；所述调节信号分别在对应第一分路控制信号、第二分路控制信号、第三分路控制信号的高电位时长内，先做数次高低电位转换再保持高电位，相应使得第一与门、第二与门、第三与门的输出端输出的信号先做数次高低电位转换再保持高电位；
其中，所述第一开关TFT、第二开关TFT、第三开关TFT、第一控制TFT、第二控制TFT、及第三控制TFT均为低温多晶硅TFT、氧化物半导体TFT、或非晶硅TFT。
本发明的有益效果：本发明提供的一种显示驱动电路及液晶显示面板，在现有的多路复用型显示驱动电路的基础上增设第一与门、第二与门、和第三与门，所述第一与门的两输入端分别接入第一分路控制信号与调节信号，所述第二与门的两输入端分别接入第二分路控制信号与调节信号，所述第三与门的两输入端分别接入第三分路控制信号与调节信号；所述调节信号分别在对应第一分路控制信号、第二分路控制信号、第三分路控制信号的高电位时长内，先做数次高低电位转换再保持高电位，相应使得第一与门、第二与门、第三与门的输出端输出的信号先做数次高低电位转换再保持高电位，由于电路自身走线的阻容延迟特性，分别受第一与门的输出端输出的信号、第二与门的输出端输出的信号、第三与门的输出端输出的信号控制的第一控制TFT、第二控制TFT、第三控制TFT，在信号近端与信号远端的开启状态不同，使得各子像素在信号近端与信号远端出现最大电流的时间不一致，从而避免因瞬间负载过重形成的信号毛刺，改善信号质量，提升画面显示品质。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发 明加以限制。
附图中，
图1为现有的多路复用型显示驱动电路的电路图；
图2为对应于图1所示的现有的多路复用型显示驱动电路的时序图；
图3为对应于图1所示的现有的多路复用型显示驱动电路的实际信号波形图；
图4为本发明的显示驱动电路的电路图；
图5为本发明的显示驱动电路的时序图；
图6为本发明的显示驱动电路中第一与门、第二与门、第三与门的输出端输出的信号波形图；
图7为本发明的显示驱动电路在调节信号做数次高低电位转换阶段中各控制TFT在信号近端的波形示意图，其中细线为理想波形，粗线为实际波形；
图8为本发明的显示驱动电路在调节信号做数次高低电位转换阶段中各控制TFT在信号远端的波形示意图，其中细线为理想波形，粗线为实际波形。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图4，本发明首先提供一种显示驱动电路，包括呈矩阵式排布的多个像素单元P、对应每一行像素单元P设置的扫描线、对应每一列像素单元P设置的数据线、对应每一列像素单元P设置的多路复用模块DM、以及第一与门AND1、第二与门AND2、和第三与门AND3。
所述第一与门AND1的两输入端分别接入第一分路控制信号MUXR与调节信号BURR，所述第二与门AND2的两输入端分别接入第二分路控制信号MUXG与调节信号BURR，所述第三与门AND3的两输入端分别接入第三分路控制信号MUXB与调节信号BURR。
每一像素单元P均包括自左至右依次排列的红色子像素R、绿色子像素G、与蓝色子像素B，以及电性连接红色子像素R的第一开关TFT T1、电性连接绿色子像素G的第二开关TFT T2、与电性连接蓝色子像素B的第三开关TFT T3；每一多路复用模块DM包括分别对应于红色子像素R列、绿色子像素G列、与蓝色子像素B列设置的第一控制TFT T10、第二控制TFT T20、及第三控制TFT T30。
设n、m均为正整数，对于第n行第m列像素单元P：第一开关TFT T1的栅极、第二开关TFT T2的栅极、及第三开关TFT T3的栅极均电性连接对应第n行素单元P设置的第n条扫描线G(n)，第一开关TFT T1的源极、第二开关TFT T2的源极、及第三开关TFT T3的源极分别电性连接对应第m列像素单元P设置的第m个多路复用模块DM中第一控制TFT T10的漏极、第二控制TFT T20的漏极、及第三控制TFT T30的漏极，第一开关TFT T1的漏极、第二开关TFT T2的漏极、及第三开关TFT T3的漏极分别电性连接红色子像素R、绿色子像素G、及蓝色子像素B。
对于第m个多路复用模块DM：第一控制TFT T10的栅极、第二控制TFT T20的栅极、及第三控制TFT T30的栅极分别电性连接第一与门AND1的输出端、第二与门AND2的输出端、及第三与门AND3的输出端，第一控制TFT T10的源极、第二控制TFT T20的源极、及第三控制TFT T30的源极均电性连接对应第m列像素单元P设置的第m条数据线D(m)。
结合图5与图6，第n条扫描线G(n)内的扫描信号的高电位时长大于第一分路控制信号MUXR、第二分路控制信号MUXG、与第三分路控制信号MUXB的高电位时长之和；所述调节信号BURR分别在对应第一分路控制信号MUXR、第二分路控制信号MUXG、第三分路控制信号MUXB的高电位时长内，先做数次高低电位转换再保持高电位，相应使得第一与门AND1、第二与门AND2、第三与门AND3的输出端输出的信号先做数次高低电位转换再保持高电位。
具体地，所述第一开关TFT T1、第二开关TFT T2、第三开关TFT T3、第一控制TFT T10、第二控制TFT T20、及第三控制TFT T30均为低温多晶硅TFT、氧化物半导体TFT、或非晶硅TFT；
所述第一分路控制信号MUXR、第二分路控制信号MUXG、与第三分路控制信号MUXB按时序先后产生，且第二分路控制信号MUXG的上升沿晚于第一分路控制信号MUXR的下降沿，第三分路控制信号MUXB的上升沿晚于第二分路控制信号MUXG的下降沿。
该显示驱动电路的工作过程为：
第1步、第n条扫描线G(n)内的扫描信号由低到高变化，第n行的所有第一开关TFT T1、第二开关TFT T2、与第三开关TFT T3均开启，经过时间t1后，同时将第一分路控制信号MUXR和调节信号BURR拉高，第一与门AND1的输出端输出高电位信号，此时与第一与门AND1的输出端电性连接的第一控制TFT T10开启，各条数据线内的数据信号经导通的第一控制TFT T10与第一开关TFT T1开始对第n行的红色子像素R进行充 电，持续时间为一预设时长t；
第2步、之后，将调节信号BURR拉低，此时第一分路控制信号MUXR和调节信号BURR经过第一与门AND1后，由第一与门AND1的输出端输出低电位信号，与第一与门AND1的输出端电性连接的第一控制TFT T10关闭，停止对第n行的红色子像素R进行充电，持续时间为预设时长t。
第3步、重复第1步与第2步数次。
结合图7与图8，由于电路自身走线的阻容延迟(RC Delay)特性，当调节信号BURR处于做数次高低电位转换阶段，在调节信号BURR短暂拉高的时间t内，信号近端的第一控制TFT T10的开启状态好，信号远端的第一控制TFT T10的开启状态差，因此信号近端的红色子像素R的充电电流相对远端要大，而信号远端的红色子像素R的充电电流很小或是无电流状态，在调节信号BURR做完数次高低电位转换后，信号近端的红色子像素R基本达到充电要求，而信号远端的红色子像素R由于第一控制TFT T10开启状态差的原因，电量变化很小或无变化，这就避免了信号近端与信号远端都处于大电流充电状态，减少瞬间大电流出现，从而能够避免因瞬间负载过重形成的信号毛刺，改善信号质量，提升画面显示品质。
第4步、将调节信号BURR持续拉高，使其保持高电位，完成第n行所有红色子像素R的充电，时长为t2，且t2大于预设时长t。
在调节信号BURR持续拉高的时间t2内，由于第一控制TFT T10的开启时间相对较长，信号近端与远端的第一控制TFT T10都处于较好的开启状态，但由于信号近端的红色子像素R已经基本达到需要的充电量，电流流动相对较小，充电速度变缓，而信号远端的红色子像素R则由于第一控制TFT T10的开启状态变好形成相对较大的电流，同样避免了信号近端与信号远端都处于大电流充电状态，减少瞬间大电流出现，从而能够避免因瞬间负载过重形成的信号毛刺，改善信号质量，提升画面显示品质。
第5步、类似于第1步至第4步，先同时将第二分路控制信号MUXG和调节信号BURR拉高，持续预设时长t后，将调节信号BURR拉低，再持续预设时长t，然后重复数次，最后将调节信号BURR持续拉高，时长为t2，完成对第n行所有绿色子像素G的充电，同样能够实现避免信号近端与信号远端都处于大电流充电状态，减少瞬间大电流出现，从而能够避免因瞬间负载过重形成的信号毛刺，改善信号质量，提升画面显示品质。
第6步、类似于第1步至第4步，先同时将第三分路控制信号MUXB和调节信号BURR拉高，持续预设时长t后，将调节信号BURR拉低，再持续预设时长t，然后重复数次，最后将调节信号BURR持续拉高，时长为 t2，完成对第n行所有蓝色子像素B的充电，同样能够实现避免信号近端与信号远端都处于大电流充电状态，减少瞬间大电流出现，从而能够避免因瞬间负载过重形成的信号毛刺，改善信号质量，提升画面显示品质。
第7步、随后下一条扫描线内的扫描信号由低到高变化，重复以上第1步至第6步，完成整个LCD充电。
基于同一发明构思，本发明还提供一种液晶显示面板，具有上述显示驱动电路，信号毛刺较少，信号质量较高，画面显示品质较好，此处不再重复描述所述显示驱动电路的结构及工作过程。
综上所述，本发明的显示驱动电路及液晶显示面板，在现有的多路复用型显示驱动电路的基础上增设第一与门、第二与门、和第三与门，所述第一与门的两输入端分别接入第一分路控制信号与调节信号，所述第二与门的两输入端分别接入第二分路控制信号与调节信号，所述第三与门的两输入端分别接入第三分路控制信号与调节信号；所述调节信号分别在对应第一分路控制信号、第二分路控制信号、第三分路控制信号的高电位时长内，先做数次高低电位转换再保持高电位，相应使得第一与门、第二与门、第三与门的输出端输出的信号先做数次高低电位转换再保持高电位，由于电路自身走线的阻容延迟特性，分别受第一与门的输出端输出的信号、第二与门的输出端输出的信号、第三与门的输出端输出的信号控制的第一控制TFT、第二控制TFT、第三控制TFT，在信号近端与信号远端的开启状态不同，使得各子像素在信号近端与信号远端出现最大电流的时间不一致，从而避免因瞬间负载过重形成的信号毛刺，改善信号质量，提升画面显示品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (13)

  1. 一种显示驱动电路，包括呈矩阵式排布的多个像素单元、对应每一行像素单元设置的扫描线、对应每一列像素单元设置的数据线、对应每一列像素单元设置的多路复用模块、以及第一与门、第二与门、和第三与门；
    所述第一与门的两输入端分别接入第一分路控制信号与调节信号，所述第二与门的两输入端分别接入第二分路控制信号与调节信号，所述第三与门的两输入端分别接入第三分路控制信号与调节信号；
    每一像素单元均包括自左至右依次排列的红色子像素、绿色子像素、与蓝色子像素，以及电性连接红色子像素的第一开关TFT、电性连接绿色子像素的第二开关TFT、与电性连接蓝色子像素的第三开关TFT；每一多路复用模块包括分别对应于红色子像素列、绿色子像素列、与蓝色子像素列设置的第一控制TFT、第二控制TFT、及第三控制TFT；
    设n、m均为正整数，对于第n行第m列像素单元：第一开关TFT的栅极、第二开关TFT的栅极、及第三开关TFT的栅极均电性连接对应第n行素单元设置的第n条扫描线，第一开关TFT的源极、第二开关TFT的源极、及第三开关TFT的源极分别电性连接对应第m列像素单元设置的第m个多路复用模块中第一控制TFT的漏极、第二控制TFT的漏极、及第三控制TFT的漏极，第一开关TFT的漏极、第二开关TFT的漏极、及第三开关TFT的漏极分别电性连接红色子像素、绿色子像素、及蓝色子像素；
    对于第m个多路复用模块：第一控制TFT的栅极、第二控制TFT的栅极、及第三控制TFT的栅极分别电性连接第一与门的输出端、第二与门的输出端、及第三与门的输出端，第一控制TFT的源极、第二控制TFT的源极、及第三控制TFT的源极均电性连接对应第m列像素单元设置的第m条数据线。
  2. 如权利要求1所述的显示驱动电路，其中，第n条扫描线内的扫描信号的高电位时长大于第一分路控制信号、第二分路控制信号、与第三分路控制信号的高电位时长之和；所述调节信号分别在对应第一分路控制信号、第二分路控制信号、第三分路控制信号的高电位时长内，先做数次高低电位转换再保持高电位，相应使得第一与门、第二与门、第三与门的输出端输出的信号先做数次高低电位转换再保持高电位。
  3. 如权利要求2所述的显示驱动电路，其中，在调节信号做数次高低电位转换的过程中，高电位持续时间与低电位持续时间均为一预设时长。
  4. 如权利要求2所述的显示驱动电路，其中，所述第一分路控制信号、第二分路控制信号、与第三分路控制信号按时序先后产生，且第二分路控制信号的上升沿晚于第一分路控制信号的下降沿，第三分路控制信号的上升沿晚于第二分路控制信号的下降沿。
  5. 如权利要求1所述的显示驱动电路，其中，所述第一开关TFT、第二开关TFT、第三开关TFT、第一控制TFT、第二控制TFT、及第三控制TFT均为低温多晶硅TFT、氧化物半导体TFT、或非晶硅TFT。
  6. 一种液晶显示面板，具有显示驱动电路，所述显示驱动电路包括呈矩阵式排布的多个像素单元、对应每一行像素单元设置的扫描线、对应每一列像素单元设置的数据线、对应每一列像素单元设置的多路复用模块、以及第一与门、第二与门、和第三与门；
    所述第一与门的两输入端分别接入第一分路控制信号与调节信号，所述第二与门的两输入端分别接入第二分路控制信号与调节信号，所述第三与门的两输入端分别接入第三分路控制信号与调节信号；
    每一像素单元均包括自左至右依次排列的红色子像素、绿色子像素、与蓝色子像素，以及电性连接红色子像素的第一开关TFT、电性连接绿色子像素的第二开关TFT、与电性连接蓝色子像素的第三开关TFT；每一多路复用模块包括分别对应于红色子像素列、绿色子像素列、与蓝色子像素列设置的第一控制TFT、第二控制TFT、及第三控制TFT；
    设n、m均为正整数，对于第n行第m列像素单元：第一开关TFT的栅极、第二开关TFT的栅极、及第三开关TFT的栅极均电性连接对应第n行素单元设置的第n条扫描线，第一开关TFT的源极、第二开关TFT的源极、及第三开关TFT的源极分别电性连接对应第m列像素单元设置的第m个多路复用模块中第一控制TFT的漏极、第二控制TFT的漏极、及第三控制TFT的漏极，第一开关TFT的漏极、第二开关TFT的漏极、及第三开关TFT的漏极分别电性连接红色子像素、绿色子像素、及蓝色子像素；
    对于第m个多路复用模块：第一控制TFT的栅极、第二控制TFT的栅极、及第三控制TFT的栅极分别电性连接第一与门的输出端、第二与门的输出端、及第三与门的输出端，第一控制TFT的源极、第二控制TFT的源极、及第三控制TFT的源极均电性连接对应第m列像素单元设置的第m条数据线。
  7. 如权利要求6所述的液晶显示面板，其中，第n条扫描线内的扫描信号的高电位时长大于第一分路控制信号、第二分路控制信号、与第三分路控制信号的高电位时长之和；所述调节信号分别在对应第一分路控制信 号、第二分路控制信号、第三分路控制信号的高电位时长内，先做数次高低电位转换再保持高电位，相应使得第一与门、第二与门、第三与门的输出端输出的信号先做数次高低电位转换再保持高电位。
  8. 如权利要求7所述的液晶显示面板，其中，在调节信号做数次高低电位转换的过程中，高电位持续时间与低电位持续时间均为一预设时长。
  9. 如权利要求7所述的液晶显示面板，其中，所述第一分路控制信号、第二分路控制信号、与第三分路控制信号按时序先后产生，且第二分路控制信号的上升沿晚于第一分路控制信号的下降沿，第三分路控制信号的上升沿晚于第二分路控制信号的下降沿。
  10. 如权利要求6所述的液晶显示面板，其中，所述第一开关TFT、第二开关TFT、第三开关TFT、第一控制TFT、第二控制TFT、及第三控制TFT均为低温多晶硅TFT、氧化物半导体TFT、或非晶硅TFT。
  11. 一种液晶显示面板，具有显示驱动电路，所述显示驱动电路包括呈矩阵式排布的多个像素单元、对应每一行像素单元设置的扫描线、对应每一列像素单元设置的数据线、对应每一列像素单元设置的多路复用模块、以及第一与门、第二与门、和第三与门；
    所述第一与门的两输入端分别接入第一分路控制信号与调节信号，所述第二与门的两输入端分别接入第二分路控制信号与调节信号，所述第三与门的两输入端分别接入第三分路控制信号与调节信号；
    每一像素单元均包括自左至右依次排列的红色子像素、绿色子像素、与蓝色子像素，以及电性连接红色子像素的第一开关TFT、电性连接绿色子像素的第二开关TFT、与电性连接蓝色子像素的第三开关TFT；每一多路复用模块包括分别对应于红色子像素列、绿色子像素列、与蓝色子像素列设置的第一控制TFT、第二控制TFT、及第三控制TFT；
    设n、m均为正整数，对于第n行第m列像素单元：第一开关TFT的栅极、第二开关TFT的栅极、及第三开关TFT的栅极均电性连接对应第n行素单元设置的第n条扫描线，第一开关TFT的源极、第二开关TFT的源极、及第三开关TFT的源极分别电性连接对应第m列像素单元设置的第m个多路复用模块中第一控制TFT的漏极、第二控制TFT的漏极、及第三控制TFT的漏极，第一开关TFT的漏极、第二开关TFT的漏极、及第三开关TFT的漏极分别电性连接红色子像素、绿色子像素、及蓝色子像素；
    对于第m个多路复用模块：第一控制TFT的栅极、第二控制TFT的栅极、及第三控制TFT的栅极分别电性连接第一与门的输出端、第二与门的输出端、及第三与门的输出端，第一控制TFT的源极、第二控制TFT的源 极、及第三控制TFT的源极均电性连接对应第m列像素单元设置的第m条数据线；
    其中，第n条扫描线内的扫描信号的高电位时长大于第一分路控制信号、第二分路控制信号、与第三分路控制信号的高电位时长之和；所述调节信号分别在对应第一分路控制信号、第二分路控制信号、第三分路控制信号的高电位时长内，先做数次高低电位转换再保持高电位，相应使得第一与门、第二与门、第三与门的输出端输出的信号先做数次高低电位转换再保持高电位；
    其中，所述第一开关TFT、第二开关TFT、第三开关TFT、第一控制TFT、第二控制TFT、及第三控制TFT均为低温多晶硅TFT、氧化物半导体TFT、或非晶硅TFT。
  12. 如权利要求11所述的液晶显示面板，其中，在调节信号做数次高低电位转换的过程中，高电位持续时间与低电位持续时间均为一预设时长。
  13. 如权利要求11所述的液晶显示面板，其中，所述第一分路控制信号、第二分路控制信号、与第三分路控制信号按时序先后产生，且第二分路控制信号的上升沿晚于第一分路控制信号的下降沿，第三分路控制信号的上升沿晚于第二分路控制信号的下降沿。
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