WO2018139704A1 - Method for forming polycrystalline silicon thin film - Google Patents

Method for forming polycrystalline silicon thin film Download PDF

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WO2018139704A1
WO2018139704A1 PCT/KR2017/002623 KR2017002623W WO2018139704A1 WO 2018139704 A1 WO2018139704 A1 WO 2018139704A1 KR 2017002623 W KR2017002623 W KR 2017002623W WO 2018139704 A1 WO2018139704 A1 WO 2018139704A1
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thin film
oxide layer
polycrystalline silicon
metal layer
silicon thin
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PCT/KR2017/002623
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French (fr)
Korean (ko)
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윤종환
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강원대학교산학협력단
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Definitions

  • the present invention relates to a method of forming a polycrystalline silicon thin film.
  • Silicon has been widely applied as a semiconductor device in electronic devices because of its economic advantages of raw materials and easy integration with existing devices.
  • polycrystalline silicon thin films have a contact resistance with a metal and thermoelectric photoelectric properties. Due to the characteristics of photoelectronic properties and high conversion efficiency, application possibilities are emerging for manufacturing devices such as solar cells and transistors.
  • Korean Patent Publication No. 10-1011806 (filed date: April 30, 2009, published date: January 24, 2011) is given below.
  • Technology has been proposed to form a polycrystalline silicon thin film using amorphous silicon.
  • the prior art uses a metal induced crystallization method (MIC) to induce crystallization of amorphous silicon by coating a metal catalyst, that is, a metal layer on the amorphous silicon and then heat treatment.
  • MIC metal induced crystallization method
  • MIC metal induction crystallization method
  • a double layer composed of an aluminum layer and an amorphous silicon layer deposited on the substrate is annealed at a temperature below the Al-Si alloy-based eutectic temperature ( ⁇ 557 ° C.), where amorphous Si atoms separated from the silicon layer diffuse into the aluminum layer across the oxide layer located at the interface between the aluminum layer and the amorphous silicon layer, and then Si nucleation occurs in the Al layer.
  • a problem of this process is that the oxide layer formed on the aluminum layer, that is, the difficulty of controlling the formation of the aluminum oxide layer and the high cost of manufacturing the amorphous silicon layer are involved.
  • the layer exchange between the amorphous silicon layer and the metal layer is not performed, so that the crystallization of the amorphous silicon is not performed smoothly.
  • prior art requires forming an oxide layer separately from depositing a metal layer and an amorphous silicon layer on a substrate in order to achieve a layer exchange between the metal layer and the amorphous silicon layer in forming a polycrystalline silicon thin film. It had to be included.
  • An object of the present invention is to provide a method of forming a polycrystalline silicon thin film in which the formation process is simplified by replacing amorphous silicon and solving the above problems.
  • a method of forming a polycrystalline silicon thin film includes depositing a metal layer on a substrate, which serves as a catalyst for forming the polycrystalline silicon thin film; A silicon oxide layer deposition step of depositing a silicon oxide layer on the metal layer deposited in the metal layer deposition step; And annealing to heat-treat the polycrystalline silicon thin film layer to be formed on the substrate on which the metal layer and the silicon oxide layer are deposited through the metal layer deposition step and the silicon oxide layer deposition step.
  • the metal layer may be aluminum (Al).
  • the silicon oxide layer deposition step may use a plasma enhanced chemical vapor deposition (PECVD, "PECVD”) method.
  • PECVD plasma enhanced chemical vapor deposition
  • the silicon oxide layer deposition step by placing the substrate on which the metal layer is deposited in the metal layer deposition step in a PECVD reactor, and supplying a mixed gas in the PECVD reactor to deposit a silicon oxide layer on the metal layer, the mixing
  • the gas may include xylene (SiH 4 ) and nitrous oxide (N 2 O).
  • the metal layer is exposed to an oxygen plasma generated by oxygen atoms included in the mixed gas such that an oxide layer is formed at an interface between the metal layer and the silicon oxide layer. Can be formed.
  • the silicon oxide layer is a Si-rich oxide (Si-rich oxide) is SiO x , where 0 ⁇ x ⁇ 2.
  • the annealing step may be annealed at a temperature below the Al-Si alloy eutectic temperature range.
  • the annealing step may be annealed at a temperature within the range of 500 °C to 600 °C.
  • the substrate on which the polycrystalline silicon thin film is formed may be manufactured by the aforementioned polycrystalline silicon thin film forming method.
  • the solar cell may be manufactured using the substrate on which the polycrystalline silicon thin film is formed.
  • a transistor can be manufactured using a substrate on which a polycrystalline silicon thin film is formed.
  • the mixed gas (SiH 4 + N 2 O) to be supplied in the course of using the plasma chemical vapor deposition (PECVD) method depositing a silicon layer (SiO x) oxidizing the metal layer upper portion
  • the oxide layer is naturally formed on the metal layer by the oxygen plasma generated by the oxygen atom, which is a process of forming the polycrystalline silicon thin film because the oxide layer is naturally formed during the formation of the silicon oxide in the silicon oxide layer deposition step.
  • the polycrystalline silicon thin film forming method of the present invention can also reduce the manufacturing cost of a solar cell or a transistor manufactured using a substrate on which a polycrystalline silicon thin film is formed.
  • FIG. 1 is a flowchart illustrating a method of forming a polycrystalline silicon thin film according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram schematically showing a method of forming a polycrystalline silicon thin film according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram illustrating a substrate on which a metal layer, an oxide layer, and a silicon oxide layer are deposited to form a polycrystalline silicon thin film according to an embodiment of the present invention.
  • 4 (a) is then annealed at 550 °C for 5 hours, EDX (energy dispersive x-ray spectroscopy ) SiO 1 .45 for measurement (220nm) / Al (60nm) / glass cross-section of the sample TEM (transmission electron consisting of microscope image. I, II, III, and IV shown are identifiers for identifying layers.
  • 4 (b), 4 (c) and 4 (d) show an energy dispersive x-ray spectroscopy (EDX) mapping distribution of Si, O and Al atoms, respectively.
  • FIG. 4 (e) shows the positional distribution of Si, O, and Al atoms determined by EDX line scanning along the line shown in FIG. 4 (a).
  • FIG. 5 (a) is then annealed at 550 °C for 5 hours, an optical microscope image of a sample consisting of SiO 1 .45 (220nm) / Al (60nm) / glass (optical microscopic image). Red dots and markers indicate Raman measurement points.
  • FIG. 5 (b) shows Raman spectra measured at different points shown in FIG. 5 (a).
  • FIG. 1 is a flowchart illustrating a method of forming a polycrystalline silicon thin film according to an embodiment of the present invention
  • FIG. 2 is a schematic view illustrating a method of forming a polycrystalline silicon thin film according to an embodiment of the present invention
  • the polycrystalline silicon thin film forming method using a silicon oxide thin film according to an embodiment of the present invention is a metal layer deposition step (S100), silicon oxide layer deposition step (S200) and annealing step (S300) It may include.
  • the metal layer deposition step S100 is a step of depositing the metal layer 120 on the substrate 110.
  • the metal layer 120 may act as a catalyst for forming the polycrystalline silicon thin film.
  • the metal layer 120 may be made of aluminum (Al).
  • the deposition of the metal layer 120 may be performed by a thermal vapeation method at room temperature, but is not limited thereto.
  • the metal layer 120 may have a thickness of about 60 nm.
  • a glass substrate may be used as the substrate 110, and when the glass substrate is used as the substrate 110, a Corning No. 7059 glass substrates may be used.
  • the buffer layer deposition step (not shown) may be preceded by the metal layer deposition step S100, but the buffer layer deposition step (not shown) may be omitted since the buffer layer SiO 2 is a component such as glass.
  • Silicon oxide layer deposition step (S200) is a step of depositing the silicon oxide layer 140 on the metal layer 120 deposited on the substrate 110 in the above-described metal layer forming step (S100).
  • the silicon oxide layer deposition step (S200) may be formed using a PECVD method.
  • the silicon oxide layer deposition step (S200) is located in the above-described metal layer deposition step (S100) the substrate coated with the metal layer 110 in a PECVD reactor capable of vacuum formation, and supplies a mixed gas in the PECVD reactor.
  • the mixed gas is ionized by the electrode generating the plasma in the PECVD reactor, and the ionized mixed gas reaches the substrate on which the metal layer located in the PECVD reactor is deposited to deposit the silicon oxide layer 140.
  • the silicon oxide layer 140 may have a thickness of about 220 nm.
  • the mixed gas may be made of 5% xylene (SiH 4 ) and nitrous oxide (N 2 O) diluted with nitrogen, and SiO x (0 ⁇ x ⁇ 2) having different x values depending on the mixing ratio of the two gases. That is, the silicon oxide layer 140 may be formed.
  • xylene (SiH 4 ) gas may be used by mixing expensive xylene (SiH 4 ) gas with nitrous oxide (N 2 O) to reduce the manufacturing cost of polycrystalline silicon thin film formation.
  • SiO 1 .45 done, but not limited thereto.
  • the temperature of the substrate 110 may be maintained at 200 ° C. to 400 ° C., preferably about 300 ° C., during the PECVD method.
  • the silicon oxide layer 140 is preferably an oxide containing excess Si, that is, a Si rich oxide having SiO x (0 ⁇ x ⁇ 2).
  • oxygen ions in a plasma state generated by ionization of nitrous oxide (N 2 O) in the PECVD reactor are deposited on the metal layer 120, that is, on the substrate. , May react with aluminum (Al).
  • aluminum (Al), that is, aluminum oxide (Al 2 O 3 ), that is, the oxide layer 130 is formed on the metal layer 120.
  • aluminum oxide may be formed while the silicon oxide layer 140 is deposited, and the silicon oxide layer 140 may be formed on the aluminum oxide (Al 2 O 3 ).
  • the present invention is a metal layer in the silicon oxide layer deposition step (S200) without forming a separate oxide layer 130
  • An oxide layer 130 may be formed at an interface between the 120 and the silicon oxide thin film layer 150.
  • Annealing step (S300) is a heat treatment to form a polycrystalline silicon thin film layer 220 on the substrate 110, the metal layer 120, the silicon oxide layer 140 is deposited through the above-described metal layer deposition step and silicon oxide layer deposition step Step.
  • the substrate 110 on which the silicon oxide layer 140 and the metal layer 120 are deposited is placed in a quartz tube reactor using high purity nitrogen (99.999%) as an ambient gas, and the Al-Si alloy-based eutectic temperature ( ⁇ Heat treatment, that is, annealing, at a temperature of 577 ° C. or less.
  • ⁇ Heat treatment that is, annealing, at a temperature of 577 ° C. or less.
  • the oxide layer 130 formed as the silicon oxide layer 140 is deposited, that is, aluminum oxide, is a metal atom of the metal layer 120, that is, aluminum (Al) acts as a catalyst.
  • the silicon oxide layer 140 may act as a diffusion path that is diffused into the silicon oxide layer 140, and the oxide layer 130 may contribute to layer exchange between the silicon oxide layer 140 and the metal layer 120.
  • the heating rate in the annealing step (S300) was maintained at a constant 5 °C / min as an example, the substrate 110 on which the silicon oxide layer 140, the metal layer 120 and the like is deposited within the range of 500 °C to 600 °C Heat treatment at temperature.
  • the diffusion of the material through the oxide layer 130 may not be performed well, on the contrary, when the temperature is higher than the above-mentioned range, the silicon oxide layer 140, the metal layer ( 120 may cause damage to the deposited substrate 110.
  • the above-described range may be directly connected to the crystallinity of the polycrystalline silicon thin film layer 220 formed through annealing.
  • the polycrystalline silicon thin film layer 220 formed when heat-treated at 550 ° C. for 5 hours is used.
  • the crystallinity of was excellent.
  • the cooling rate may also be maintained at 5 ° C./min, as described above, and when the temperature of the substrate 110 on which the silicon oxide layer 140 and the metal layer 120 are deposited is less than 100 ° C., the quartz tube reactor Can be taken out from within.
  • the polycrystalline silicon thin film layer 220 may be formed on the substrate.
  • the substrate 200 in which the polycrystalline silicon thin film is formed may be manufactured by the aforementioned polycrystalline silicon thin film forming method, and the solar cell, the transistor, and the like may be manufactured using the substrate 200 in which the polycrystalline silicon thin film is formed.
  • 4 (a) is then annealed at 550 °C for 5 hours, EDX (energy dispersive x-ray spectroscopy ) SiO 1 .45 for measurement (220nm) / Al (60nm) / glass cross-section of the sample TEM (transmission electron consisting of microscope image. I, II, III, and IV shown are identifiers for identifying layers.
  • 4 (b), 4 (c) and 4 (d) show an energy dispersive x-ray spectroscopy (EDX) mapping distribution of Si, O and Al atoms, respectively.
  • FIG. 4 (e) shows the positional distribution of Si, O, and Al atoms determined by EDX line scanning along the line shown in FIG. 4 (a).
  • Fig. 4 (a) clearly shows the four-layer structure after annealing, wherein I, II, III, and IV shown are identification symbols for identifying the layers.
  • the Si atoms of the II layer is induced by the heat treatment performed in the annealing step (S300) described above, and shows that the II layer is no longer the metal layer 120 as a result of EDX mapping and line scanning.
  • Al atoms are mainly distributed at the interface between the I layer and the II layer. This result is due to the diffusion of Al atoms from the Al layer to the II layer having the Si phase.
  • the I layer is confirmed, but by changing the annealing conditions such as increasing the annealing time, the I layer can be crystallized to form the polycrystalline silicon thin film. have.
  • Is also 5 (a) is then annealed at 550 °C for 5 hours SiO 1 .45 (220nm) / Al (60nm) / an optical microscope image (optical microscopic image) of the sample made of a glass. Red dots and markers indicate Raman measurement points.
  • FIG. 5 (b) shows Raman spectra measured at different points shown in FIG. 5 (a).
  • Figure 5 (a) was taken using a built-in optical microscope attached to a micro-Raman spectrometer
  • Figure 8 (a) shows a different color depending on the crystallinity and the crystal orientation of the particles.
  • Fig. 5 (b) is measured at different positions indicated by a to f in Fig. 5 (a), and as shown in Fig. 5 (b), regardless of the measurement position, the characteristics of crystalline silicon can be said. 520cm that - the symmetrical spectrum with a peak in the vicinity of one was confirmed.
  • the above-mentioned data means that the produced polycrystalline silicon has preferential orientation in the (111) direction, and is consistent with the result shown in FIG.
  • the diffraction peaks related to the ⁇ -Al 2 O 3 phase are due to the reaction between aluminum and oxygen in the silicon oxide layer 140 made of SiOx and the metal layer 120 made of aluminum.
  • the formation of the polycrystalline silicon thin film may be generally performed by Al induced layer exchange (ALILE), and the silicon oxide layer deposition step (S200) in the polycrystalline silicon thin film formation method according to an embodiment of the present invention.
  • the oxide layer 130 generated, i.e., Al 2 O 3 is formed at the interface between the silicon oxide layer 140 and the metal layer 120 to serve as a diffusion path of Si atoms diffused into the metal layer 120.
  • the Si atoms generated by the Al atoms and the existing excess Si atoms present in the silicon oxide layer 140 diffuse across the oxide layer 130 to the metal layer 120 to generate Si crystal nuclei, and subsequently As a result, polycrystalline silicon particles with a preferential (111) orientation grow.
  • the ⁇ -Al 2 O 3 layer which induces Si atoms oriented in the (111) direction is preferentially formed and positioned at the interface between the silicon oxide layer 140 and the polycrystalline silicon thin film layer 220.
  • the present invention by the oxygen atom contained in the mixed gas (SiH 4 + N 2 O) supplied in the process of depositing the silicon oxide layer (SiO x ) on the metal layer by the plasma chemical vapor deposition (PECVD) method
  • the oxide layer is naturally generated on the metal layer by the generated oxygen plasma, which can simplify the formation process in forming the polycrystalline silicon thin film because the oxide layer is naturally formed during the formation of the silicon oxide in the silicon oxide layer deposition step.

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Abstract

The present invention provides a method for forming a polycrystalline silicon thin film, the method comprising: a metal layer deposition step of depositing, on a substrate, a metal acting as a catalyst for forming a polycrystalline silicon thin film; a silicon oxide layer deposition step of depositing a silicon oxide layer on the metal layer deposited in the metal layer deposition step; and an annealing step of performing heat treatment so as to form a polycrystalline silicon thin film layer on the substrate on which the metal layer and the silicon oxide layer have been deposited through the metal layer deposition step and the silicon oxide layer deposition step.

Description

다결정 실리콘 박막 형성 방법Polycrystalline Silicon Thin Film Formation Method
본 발명은 다결정 실리콘 박막 형성 방법에 관한 것이다.The present invention relates to a method of forming a polycrystalline silicon thin film.
실리콘은 원료 자체의 경제적 이점과 기존 소자와의 집적이 용이한 장점을 가지고 있어 전자소자에서는 반도체 소자로 널리 응용되고 있으며, 특히, 다결정 실리콘 박막은 금속과의 접촉저항 및 열전자적(thermoelectric)광전적(photoelectronic) 성질의 특성과 높은 변환효율을 가지기에 태양전지나 트랜지스터 등의 소자 제조에 그 응용 가능성이 대두되고 있다.Silicon has been widely applied as a semiconductor device in electronic devices because of its economic advantages of raw materials and easy integration with existing devices. In particular, polycrystalline silicon thin films have a contact resistance with a metal and thermoelectric photoelectric properties. Due to the characteristics of photoelectronic properties and high conversion efficiency, application possibilities are emerging for manufacturing devices such as solar cells and transistors.
그렇기에, 다결정 실리콘 박막을 제조하기 위한 다양한 연구가 수행되고 있으며, 이러한 연구의 일환으로 대한민국 등록특허공보 제10-1011806호(출원일 : 2009. 04. 30, 공고일 : 2011. 01. 24, 이하 ‘선행기술’이라 칭함)에서 비정질 실리콘을 이용하여 다결정 실리콘 박막을 형성하는 기술을 제시한 바 있다.As a result, various studies have been conducted to manufacture polycrystalline silicon thin films, and as part of such research, Korean Patent Publication No. 10-1011806 (filed date: April 30, 2009, published date: January 24, 2011) is given below. Technology ”has been proposed to form a polycrystalline silicon thin film using amorphous silicon.
여기서, 선행기술은 금속유도결정화법(MIC, Metal Induced Crystallization)을 이용하여 비정질 실리콘에 금속 촉매 즉, 금속층을 코팅한 후 열처리하여 비정질 실리콘의 결정화를 유도하고 있다.Here, the prior art uses a metal induced crystallization method (MIC) to induce crystallization of amorphous silicon by coating a metal catalyst, that is, a metal layer on the amorphous silicon and then heat treatment.
이때, 금속유도결정화법(MIC)의 일 예로, 알루미늄(Aluminum; Al)으로 이루어진 금속층과 비정질 실리콘층 간의 층교환을 통해 다결정 실리콘 박막을 형성하는 방법이 있다.In this case, as an example of the metal induction crystallization method (MIC), there is a method of forming a polycrystalline silicon thin film through layer exchange between a metal layer made of aluminum (Aluminum) and an amorphous silicon layer.
여기서, 알루미늄층과 비정질 실리콘층 사이 계면에는 알루미늄층과 비정질 실리콘층 간의 층교환을 위해 SiO2 또는 Al2O3 중 하나로 형성될 수 있는 산화물층이 필수적으로 요구된다. Here, at the interface between the aluminum layer and the amorphous silicon layer, SiO 2 or Al 2 O 3 for layer exchange between the aluminum layer and the amorphous silicon layer There is essentially a need for an oxide layer that can be formed with either.
이 경우, 다결정 실리콘 박막을 형성하기 위하여 기판 상에 증착된 알루미늄층과 비정질 실리콘층으로 이루어진 이중층을 Al-Si 합금 계 공융온도(~557℃) 이하의 온도에서 어닐링(Annealing)하며, 이때, 비정질 실리콘층으로부터 분리된 Si 원자는 알루미늄층과 비정질 실리콘층 사이 계면에 위치한 상기 산화물층을 가로질러 알루미늄층으로 확산된 후, Al 층 내에서 Si 결정핵생성(nucleation)이 이루어진다.In this case, in order to form a polycrystalline silicon thin film, a double layer composed of an aluminum layer and an amorphous silicon layer deposited on the substrate is annealed at a temperature below the Al-Si alloy-based eutectic temperature (˜557 ° C.), where amorphous Si atoms separated from the silicon layer diffuse into the aluminum layer across the oxide layer located at the interface between the aluminum layer and the amorphous silicon layer, and then Si nucleation occurs in the Al layer.
그러나, 이 공정의 문제점은 알루미늄층 상에 형성되는 산화물층 즉, 산화알루미늄층 형성 제어의 어려움과 비정질 실리콘층을 제조하는데 고비용이 수반되는 것이다.However, a problem of this process is that the oxide layer formed on the aluminum layer, that is, the difficulty of controlling the formation of the aluminum oxide layer and the high cost of manufacturing the amorphous silicon layer are involved.
또한, 산화물층이 포함되지 않을 경우, 비정질 실리콘층과 금속층 간의 층교환이 이루어지지 않아 비정질 실리콘의 결정화가 원활하게 이루어지지 않는다.In addition, when the oxide layer is not included, the layer exchange between the amorphous silicon layer and the metal layer is not performed, so that the crystallization of the amorphous silicon is not performed smoothly.
그렇기에, 선행기술을 포함한 종래기술은 다결정 실리콘 박막을 형성하는데 있어서 금속층과 비정질 실리콘층 간의 층교환이 이루어지기 위하여 기판 상에 금속층 및 비정질 실리콘층을 증착하는 단계와 별도로 산화물층을 형성하는 단계가 반드시 포함되어야 하였다.As such, prior art, including the prior art, requires forming an oxide layer separately from depositing a metal layer and an amorphous silicon layer on a substrate in order to achieve a layer exchange between the metal layer and the amorphous silicon layer in forming a polycrystalline silicon thin film. It had to be included.
본 발명은 상술한 문제점을 해결하기 위한 것으로 비정질 실리콘을 대체하여 형성 과정이 단순화된 다결정 실리콘 박막의 형성 방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of forming a polycrystalline silicon thin film in which the formation process is simplified by replacing amorphous silicon and solving the above problems.
이러한 목적을 달성하기 위하여 본 발명의 일 실시예에 다결정 실리콘 박막 형성 방법은 다결정 실리콘 박막을 형성하기 위한 촉매로 작용하는 금속을 기판 상에 증착하는 금속층 증착단계; 상기 금속층 증착단계에서 증착된 금속층 상에 산화실리콘층을 증착하는 산화실리콘층 증착단계; 및 상기 금속층 증착단계 및 상기 산화실리콘층 증착단계를 통해 상기 금속층 및 산화실리콘층이 증착된 기판 상에 다결정 실리콘 박막층이 형성되도록 열처리하는 어닐링 단계;를 포함할 수 있다.In order to achieve the above object, a method of forming a polycrystalline silicon thin film according to an embodiment of the present invention includes depositing a metal layer on a substrate, which serves as a catalyst for forming the polycrystalline silicon thin film; A silicon oxide layer deposition step of depositing a silicon oxide layer on the metal layer deposited in the metal layer deposition step; And annealing to heat-treat the polycrystalline silicon thin film layer to be formed on the substrate on which the metal layer and the silicon oxide layer are deposited through the metal layer deposition step and the silicon oxide layer deposition step.
이때, 상기 금속층 증착단계에서, 상기 금속층은 알루미늄(Al)일 수 있다.At this time, in the metal layer deposition step, the metal layer may be aluminum (Al).
그리고, 상기 산화실리콘층 증착단계는, 플라즈마 화학기상증착(plasma enhanced chemical vapor deposition ;PECVD, 이하 ‘PECVD’라 칭함) 방법을 사용할 수 있다.In addition, the silicon oxide layer deposition step may use a plasma enhanced chemical vapor deposition (PECVD, "PECVD") method.
또한, 상기 산화실리콘층 증착단계는, 상기 금속층 증착단계에서 상기 금속층이 증착된 기판을 PECVD 반응기 내에 위치시키고, 상기 PECVD 반응기 내에 혼합가스를 공급하여 상기 금속층 상에 산화실리콘층을 증착하며,상기 혼합가스는 사일렌(SiH4) 및 아산화질소(N2O)를 포함할 수 있다.In addition, the silicon oxide layer deposition step, by placing the substrate on which the metal layer is deposited in the metal layer deposition step in a PECVD reactor, and supplying a mixed gas in the PECVD reactor to deposit a silicon oxide layer on the metal layer, the mixing The gas may include xylene (SiH 4 ) and nitrous oxide (N 2 O).
그리고, 상기 산화실리콘층 증착단계에서 상기 산화실리콘층을 증착하는 동안 상기 금속층이 상기 혼합가스에 포함된 산소 원자에 의해 발생하는 산소 플라즈마에 노출되어 상기 금속층과 상기 산화실리콘층 사이 계면에 산화물층이 형성될 수 있다.In addition, during the deposition of the silicon oxide layer in the silicon oxide layer deposition step, the metal layer is exposed to an oxygen plasma generated by oxygen atoms included in the mixed gas such that an oxide layer is formed at an interface between the metal layer and the silicon oxide layer. Can be formed.
또한, 상기 산화실리콘층 증착단계에서, 상기 산화실리콘층은 SiOx인 Si 풍부 산화물(Si-rich oxide)이고, 여기서, 0<x<2일 수 있다.In addition, in the silicon oxide layer deposition step, the silicon oxide layer is a Si-rich oxide (Si-rich oxide) is SiO x , where 0 <x <2.
그리고, 상기 어닐링 단계는, Al-Si 합금 계 공융온도 범위 이하의 온도에서 어닐링(Annealing)할 수 있다.The annealing step may be annealed at a temperature below the Al-Si alloy eutectic temperature range.
또한, 상기 어닐링 단계는, 500℃ 내지 600℃ 범위 내 온도에서 어닐링할 수 있다.In addition, the annealing step may be annealed at a temperature within the range of 500 ℃ to 600 ℃.
한편, 상술한 다결정 실리콘 박막 형성 방법으로 다결정 실리콘 박막이 형성된 기판을 제조할 수 있다.Meanwhile, the substrate on which the polycrystalline silicon thin film is formed may be manufactured by the aforementioned polycrystalline silicon thin film forming method.
이때, 다결정 실리콘 박막이 형성된 기판을 사용하여 태양전지를 제조할 수 있다.In this case, the solar cell may be manufactured using the substrate on which the polycrystalline silicon thin film is formed.
또한, 다결정 실리콘 박막이 형성된 기판을 사용하여 트랜지스터를 제조할 수 있다.In addition, a transistor can be manufactured using a substrate on which a polycrystalline silicon thin film is formed.
이상에서 설명한 바와 같이 본 발명에 의하면, 플라즈마 화학 기상 증착(PECVD) 방법을 통해 산화실리콘층(SiOx)을 금속층 상부에 증착하는 과정에서 공급되는 혼합가스(SiH4+N2O)에 포함된 산소원자에 의해 발생되는 산소 플라즈마에 의해 금속층 상부에 산화물층이 자연스럽게 생성되며, 이는 산화실리콘층 증착단계에서 산화실리콘이 형성되는 동안 산화물층이 자연스럽게 생성되기에 다결정 실리콘 박막을 형성하는데 있어서 형성 과정이 간소화될 수 있으며, 혼합가스(SiH4+NO2)를 사용함으로 고가의 사일렌(SiH4) 가스의 사용량을 줄일 수 있으며, 독성의 사일렌 가스를 무독성의 아산화규소(N2O)로 혼합하여 사용함으로 사일렌 가스의 독성을 저감하는 장치가 필요가 없기 때문에 그 제조비용이 절감될 수 있는 효과가 있다.According to the present invention as described above, contained in the mixed gas (SiH 4 + N 2 O) to be supplied in the course of using the plasma chemical vapor deposition (PECVD) method depositing a silicon layer (SiO x) oxidizing the metal layer upper portion The oxide layer is naturally formed on the metal layer by the oxygen plasma generated by the oxygen atom, which is a process of forming the polycrystalline silicon thin film because the oxide layer is naturally formed during the formation of the silicon oxide in the silicon oxide layer deposition step. It can be simplified, and the use of mixed gas (SiH 4 + NO 2 ) can reduce the use of expensive silen (SiH 4 ) gas, and mix the toxic silica gas with non-toxic silicon dioxide (N 2 O) It is possible to reduce the manufacturing cost because there is no need to use the device to reduce the toxicity of the xylene gas by using.
아울러, 본 발명의 다결정 실리콘 박막 형성 방법으로 다결정 실리콘 박막이 형성된 기판을 이용하여 제조되는 태양전지나 트랜지스터의 제조비용 또한 절감할 수 있는 효과가 있다.In addition, the polycrystalline silicon thin film forming method of the present invention can also reduce the manufacturing cost of a solar cell or a transistor manufactured using a substrate on which a polycrystalline silicon thin film is formed.
도1은 본 발명의 일 실시예에 따른 다결정 실리콘 박막 형성 방법을 도시한 흐름도이다.1 is a flowchart illustrating a method of forming a polycrystalline silicon thin film according to an embodiment of the present invention.
도2는 본 발명의 일 실시예에 따른 다결정 실리콘 박막 형성 방법을 개략적으로 도시한 개략도이다.2 is a schematic diagram schematically showing a method of forming a polycrystalline silicon thin film according to an embodiment of the present invention.
도3은 본 발명의 일 실시예에 따른 다결정 실리콘 박막을 형성하기 위하여 금속층, 산화물층, 산화실리콘층이 증착된 기판을 개략적으로 도시한 개략도이다.3 is a schematic diagram illustrating a substrate on which a metal layer, an oxide layer, and a silicon oxide layer are deposited to form a polycrystalline silicon thin film according to an embodiment of the present invention.
도4(a)는 550℃에서 5시간 동안 어닐링 한 후 EDX (energy dispersive x-ray spectroscopy) 측정을 위한 SiO1 .45(220nm)/Al (60nm)/글래스로 이루어진 샘플의 단면 TEM(transmission electron microscope) 이미지이다. 도시된 I, II, III, 및 IV는 층을 식별하기 위한 식별기호이다. 도4(b), 도4(c) 및 도4(d)는 각각 Si, O, Al 원자의 EDX(energy dispersive x-ray spectroscopy) 맵핑 분포를 나타낸 것이다. 도4(e)는 도4(a)에 도시된 라인을 따라 EDX 라인 스캐닝에 의해 결정된 Si, O, Al 원자의 위치 분포를 나타낸 것이다.4 (a) is then annealed at 550 ℃ for 5 hours, EDX (energy dispersive x-ray spectroscopy ) SiO 1 .45 for measurement (220nm) / Al (60nm) / glass cross-section of the sample TEM (transmission electron consisting of microscope image. I, II, III, and IV shown are identifiers for identifying layers. 4 (b), 4 (c) and 4 (d) show an energy dispersive x-ray spectroscopy (EDX) mapping distribution of Si, O and Al atoms, respectively. FIG. 4 (e) shows the positional distribution of Si, O, and Al atoms determined by EDX line scanning along the line shown in FIG. 4 (a).
도5(a)는 550℃에서 5시간 동안 어닐링 한 후 SiO1 .45(220nm)/Al (60nm)/글래스로 이루어진 샘플의 광학 현미경 이미지(optical microscopic image)이다. 붉은 점과 표식들은 라만(Raman) 측정지점을 나타낸 것이다. 도5(b)는 도5(a)에 도시된 다른 지점들에서 측정된 라만스펙트럼(Raman spectra)을 나타낸 것이다.It is also 5 (a) is then annealed at 550 ℃ for 5 hours, an optical microscope image of a sample consisting of SiO 1 .45 (220nm) / Al (60nm) / glass (optical microscopic image). Red dots and markers indicate Raman measurement points. FIG. 5 (b) shows Raman spectra measured at different points shown in FIG. 5 (a).
도6은 550℃에서 5시간 동안 어닐링 한 후 SiO1 .45(220nm)/Al (60nm)/글래스로 이루어진 샘플의 XRD 스펙트럼(x-ray diffraction spectrum)을 나타낸 것이다.6 is then annealed at 550 ℃ for 5 hours it shows the SiO 1 .45 (220nm) / Al (60nm) / sample of the XRD spectrum (x-ray diffraction spectrum) consisting of the glass.
본 발명의 바람직한 실시 예에 대하여 첨부된 도면을 참조하여 더 구체적으로 설명하되, 이미 주지되어진 기술적 부분에 대해서는 설명의 간결함을 위해 생략하거나 압축하기로 한다.Preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings, but the well-known technical parts will be omitted or compressed for brevity of description.
도1은 본 발명의 일 실시예에 따른 다결정 실리콘 박막 형성 방법을 도시한 흐름도이며, 도2는 본 발명의 일 실시예에 따른 다결정 실리콘 박막 형성 방법을 개략적으로 도시한 개략도이고, 도3은 본 발명의 일 실시예에 따른 다결정 실리콘 박막을 형성하기 위하여 금속층, 산화물층, 산화실리콘층이 증착된 기판을 개략적으로 도시한 개략도이다.1 is a flowchart illustrating a method of forming a polycrystalline silicon thin film according to an embodiment of the present invention, and FIG. 2 is a schematic view illustrating a method of forming a polycrystalline silicon thin film according to an embodiment of the present invention, and FIG. A schematic diagram schematically illustrating a substrate on which a metal layer, an oxide layer, and a silicon oxide layer are deposited to form a polycrystalline silicon thin film according to an embodiment of the present invention.
도1 내지 도3을 참조하면, 본 발명의 일 실시예에 따른 산화실리콘 박막을 이용한 다결정 실리콘 박막 형성 방법은 금속층 증착단계(S100), 산화실리콘층 증착단계(S200) 및 어닐링 단계(S300)를 포함할 수 있다.1 to 3, the polycrystalline silicon thin film forming method using a silicon oxide thin film according to an embodiment of the present invention is a metal layer deposition step (S100), silicon oxide layer deposition step (S200) and annealing step (S300) It may include.
금속층 증착단계(S100)는 기판(110) 상에 금속층(120)을 증착하는 단계이다.The metal layer deposition step S100 is a step of depositing the metal layer 120 on the substrate 110.
이때, 금속층(120)은 다결정 실리콘 박막을 형성하기 위한 촉매로 작용할 수 있다.In this case, the metal layer 120 may act as a catalyst for forming the polycrystalline silicon thin film.
그리고, 본 발명의 일 실시예에 따른 다결정 실리콘 박막 형성 방법에서 금속층(120)은 알루미늄(Aluminum; Al)으로 이루어질 수 있다.In the method of forming a polycrystalline silicon thin film according to an embodiment of the present invention, the metal layer 120 may be made of aluminum (Al).
또한, 금속층(120)의 증착은 실온에서 열 증착법(thermal vaperation method)을 통해 수행될 수 있으나 이에 한정되지 않는다.In addition, the deposition of the metal layer 120 may be performed by a thermal vapeation method at room temperature, but is not limited thereto.
그리고, 금속층(120)은 60nm 정도의 두께를 가질 수 있다. The metal layer 120 may have a thickness of about 60 nm.
또한, 기판(110)은 글래스기판이 사용될 수 있으며, 기판(110)으로 글래스기판이 사용되는 경우, 그 예로서 코닝(corning)사 No. 7059 글래스기판이 사용될 수 있다. In addition, a glass substrate may be used as the substrate 110, and when the glass substrate is used as the substrate 110, a Corning No. 7059 glass substrates may be used.
그리고, 금속층 증착단계(S100) 이전에 완충층 증착단계(미도시)가 선행될 수 있으나, 완충층(SiO2)은 유리(glass)와 같은 성분이므로 완충층 증착단계(미도시)는 생략할 수 있다.The buffer layer deposition step (not shown) may be preceded by the metal layer deposition step S100, but the buffer layer deposition step (not shown) may be omitted since the buffer layer SiO 2 is a component such as glass.
산화실리콘층 증착단계(S200)는 상술한 금속층 형성단계(S100)에서 기판(110) 상에 증착된 금속층(120) 상에 산화실리콘층(140)을 증착하는 단계이다.Silicon oxide layer deposition step (S200) is a step of depositing the silicon oxide layer 140 on the metal layer 120 deposited on the substrate 110 in the above-described metal layer forming step (S100).
여기서, 산화실리콘층 증착단계(S200)는 PECVD 방법을 이용하여 형성될 수 있다.Here, the silicon oxide layer deposition step (S200) may be formed using a PECVD method.
먼저, 산화실리콘층 증착단계(S200)는 상술한 금속층 증착단계(S100)에서 금속층(110)이 코팅된 기판을 진공 형성이 가능한 PECVD 반응기 내에 위치시키고, PECVD 반응기 내에 혼합가스를 공급한다.First, the silicon oxide layer deposition step (S200) is located in the above-described metal layer deposition step (S100) the substrate coated with the metal layer 110 in a PECVD reactor capable of vacuum formation, and supplies a mixed gas in the PECVD reactor.
그리고, PECVD 반응기 내에서 플라즈마를 발생시키는 전극에 의해 혼합가스는 이온화되며, 이온화된 혼합가스는 PECVD 반응기 내에 위치한 금속층이 증착된 기판 상에 도달하여 산화실리콘층(140)을 증착한다.In addition, the mixed gas is ionized by the electrode generating the plasma in the PECVD reactor, and the ionized mixed gas reaches the substrate on which the metal layer located in the PECVD reactor is deposited to deposit the silicon oxide layer 140.
이때, 산화실리콘층(140)은 220nm 정도의 두께를 가질 수 있다.In this case, the silicon oxide layer 140 may have a thickness of about 220 nm.
여기서, 혼합가스는 질소로 희석된 5 % 사일렌(SiH4) 및 아산화질소(N2O)로 이루어질 수 있으며, 두 가스의 혼합비율에 따라 x값이 상이한 SiOx(0<x<2) 즉,산화실리콘층(140)을 형성할 수 있다.Here, the mixed gas may be made of 5% xylene (SiH 4 ) and nitrous oxide (N 2 O) diluted with nitrogen, and SiO x (0 <x <2) having different x values depending on the mixing ratio of the two gases. That is, the silicon oxide layer 140 may be formed.
이때, 혼합가스는 고가의 사일렌(SiH4) 가스를 아산화질소(N2O)로 혼합하여 사용함으로써 소량의 사일렌(SiH4) 가스가 사용되어 다결정 실리콘 박막 형성의 제조 비용이 절감될 수 있다.In this case, a small amount of xylene (SiH 4 ) gas may be used by mixing expensive xylene (SiH 4 ) gas with nitrous oxide (N 2 O) to reduce the manufacturing cost of polycrystalline silicon thin film formation. have.
또한, 독성 물질인 사일렌(SiH4) 가스를 무독성인 아산화질소(N2O)로 혼합하여 사용함으로써, 사일렌(SiH4) 가스를 단독으로 사용할 경우에 필요하던 독성 저감 장치가 불필요하기에 다결정 실리콘 박막 형성의 제조 비용이 절감될 수 있다.In addition, by using a mixture of toxic silane (SiH 4 ) gas with non-toxic nitrous oxide (N 2 O), the toxic abatement device required when using silane (SiH 4 ) gas alone is unnecessary. The manufacturing cost of polycrystalline silicon thin film formation can be reduced.
이때, 본 발명의 일 실시예에서는 x=1.45인, SiO1 .45에 한해서 설명이 이루어지나 이에 한정되지 않는다.At this time, in the embodiment of the present invention through the description just in the x = 1.45, SiO 1 .45 done, but not limited thereto.
그리고, PECVD 방법을 수행하는 동안 기판(110)의 온도는 200 ℃ 내지 400 ℃로 유지될 수 있고, 바람직하게는 약 300℃ 일 수 있다.In addition, the temperature of the substrate 110 may be maintained at 200 ° C. to 400 ° C., preferably about 300 ° C., during the PECVD method.
또한, 산화실리콘층(140)은 잉여 Si를 포함하는 산화물 즉, SiOx (0<x<2)인 Si 풍부(rich) 산화물인 것이 바람직하다.In addition, the silicon oxide layer 140 is preferably an oxide containing excess Si, that is, a Si rich oxide having SiO x (0 <x <2).
그리고, 이온화된 혼합가스가 산화실리콘 박막층(150)을 증착하는 동안 이와 동시에 PECVD 반응기 내에서 아산화질소(N2O)의 이온화로 발생한 플라즈마 상태의 산소이온은 기판 상에 증착된 금속층(120) 즉, 알루미늄(Al)과 반응할 수 있다.In addition, while the ionized mixed gas deposits the silicon oxide thin film layer 150, at the same time, oxygen ions in a plasma state generated by ionization of nitrous oxide (N 2 O) in the PECVD reactor are deposited on the metal layer 120, that is, on the substrate. , May react with aluminum (Al).
여기서, Al-O, Si-O 간의 이온 결합 각각의 결합해리 에너지에 차이가 있어 상대적으로 결합에너지가 낮은 Al-O 이온 결합이 우선적으로 발생하며, 이에 알루미늄(Al)이 우선적으로 산화가 이루어지게 된다. Here, there is a difference in the bond dissociation energy of each of the ionic bonds between Al-O and Si-O, so that Al-O ionic bonds having a relatively low binding energy are generated first, so that aluminum (Al) is preferentially oxidized. do.
그렇기에, 알루미늄(Al) 즉, 금속층(120) 상부에는 산화알루미늄(Al2O3) 즉, 산화물층(130)이 형성된다.Therefore, aluminum (Al), that is, aluminum oxide (Al 2 O 3 ), that is, the oxide layer 130 is formed on the metal layer 120.
이를 통해, 산화실리콘층(140)이 증착되는 동안 산화알루미늄이 형성되고, 산화알루미늄(Al2O3)의 상부에 산화실리콘층(140)이 형성될 수 있다.Through this, aluminum oxide may be formed while the silicon oxide layer 140 is deposited, and the silicon oxide layer 140 may be formed on the aluminum oxide (Al 2 O 3 ).
이때, 기존 비정질실리콘을 이용하여 다결정 실리콘 박막층을 형성하는 경우, 산화물층 형성과정이 필연적으로 포함되어야 하였으나, 본 발명은 별도의 산화물층(130) 형성과정 없이 산화실리콘층 증착단계(S200)에서 금속층(120)과 산화실리콘 박막층(150) 사이 계면에 산화물층(130)이 형성될 수 있다.In this case, in the case of forming the polycrystalline silicon thin film layer using the existing amorphous silicon, the oxide layer forming process should be included inevitably, the present invention is a metal layer in the silicon oxide layer deposition step (S200) without forming a separate oxide layer 130 An oxide layer 130 may be formed at an interface between the 120 and the silicon oxide thin film layer 150.
즉, 본 발명의 일 실시예에 따른 다결정 실리콘 박막 형성방법은 하나의 단계, 산화실리콘층 증착단계(S200)에서 산화물층(130)과 산화실리콘층(140)을 형성하는 것이 가능하다.That is, in the polycrystalline silicon thin film forming method according to an embodiment of the present invention, it is possible to form the oxide layer 130 and the silicon oxide layer 140 in one step, the silicon oxide layer deposition step (S200).
어닐링 단계(S300)는 상술한 금속층 증착단계 및 산화실리콘층 증착단계를 통해 금속층(120), 산화실리콘층(140)이 증착된 기판(110) 상에 다결정 실리콘 박막층(220)을 형성하도록 열처리하는 단계이다.Annealing step (S300) is a heat treatment to form a polycrystalline silicon thin film layer 220 on the substrate 110, the metal layer 120, the silicon oxide layer 140 is deposited through the above-described metal layer deposition step and silicon oxide layer deposition step Step.
여기서, 산화실리콘층(140), 금속층(120) 등이 증착된 기판(110)을 고순도 질소(99.999%)를 주변가스로 사용하는 석영관 반응기 내에 위치시키고, Al-Si 합금 계 공융온도(~577℃) 이하의 온도로 열처리 즉, 어닐링(Annealing)한다.Here, the substrate 110 on which the silicon oxide layer 140 and the metal layer 120 are deposited is placed in a quartz tube reactor using high purity nitrogen (99.999%) as an ambient gas, and the Al-Si alloy-based eutectic temperature (~ Heat treatment, that is, annealing, at a temperature of 577 ° C. or less.
이때, 상술한 산화실리콘층 증착단계(S200)에서 산화실리콘층(140)이 증착되면서 형성된 산화물층(130) 즉, 산화알루미늄은 금속층(120)의 금속원자 즉, 알루미늄(Al)이 촉매로 작용하여 산화실리콘층(140)에 확산되는 확산 경로로 작용할 수 있으며, 산화물층(130)은 산화실리콘층(140)과 금속층(120) 간의 층교환에 기여할 수 있다. At this time, in the above-described silicon oxide layer deposition step (S200), the oxide layer 130 formed as the silicon oxide layer 140 is deposited, that is, aluminum oxide, is a metal atom of the metal layer 120, that is, aluminum (Al) acts as a catalyst. As a result, the silicon oxide layer 140 may act as a diffusion path that is diffused into the silicon oxide layer 140, and the oxide layer 130 may contribute to layer exchange between the silicon oxide layer 140 and the metal layer 120.
그리고, 어닐링 단계(S300)에서 가열 속도는 일 예로 5℃/min 으로 일정하게 유지되었으며, 산화실리콘층(140), 금속층(120) 등이 증착된 기판(110)을 500℃ 내지 600℃ 범위 내 온도에서 열처리하였다.And, the heating rate in the annealing step (S300) was maintained at a constant 5 ℃ / min as an example, the substrate 110 on which the silicon oxide layer 140, the metal layer 120 and the like is deposited within the range of 500 ℃ to 600 ℃ Heat treatment at temperature.
이때, 상술한 범위보다 온도가 현저히 낮은 경우, 산화물층(130)을 통한 물질의 확산이 잘 이루어지지 않을 수 있으며, 이와 반대로 상술한 범위보다 온도가 높은 경우, 산화실리콘층(140), 금속층(120) 등이 증착된 기판(110)의 손상을 야기할 수 있다.At this time, when the temperature is significantly lower than the above-described range, the diffusion of the material through the oxide layer 130 may not be performed well, on the contrary, when the temperature is higher than the above-mentioned range, the silicon oxide layer 140, the metal layer ( 120 may cause damage to the deposited substrate 110.
즉, 상술한 범위는 어닐링을 통해 형성되는 다결정 실리콘 박막층(220)의 결정성과 직결될 수 있으며, 본 발명의 일 실시예에서는 550℃에서 5시간동안 열처리한 경우, 형성되는 다결정 실리콘 박막층(220)의 결정성이 우수하였다.That is, the above-described range may be directly connected to the crystallinity of the polycrystalline silicon thin film layer 220 formed through annealing. In an embodiment of the present invention, the polycrystalline silicon thin film layer 220 formed when heat-treated at 550 ° C. for 5 hours is used. The crystallinity of was excellent.
그리고, 냉각 속도 또한 상술한 가열속도와 같게 5℃/min으로 유지될 수 있으며, 산화실리콘층(140), 금속층(120) 등이 증착된 기판(110)의 온도가 100℃ 미만인 경우 석영관 반응기 내에서 꺼내질 수 있다.The cooling rate may also be maintained at 5 ° C./min, as described above, and when the temperature of the substrate 110 on which the silicon oxide layer 140 and the metal layer 120 are deposited is less than 100 ° C., the quartz tube reactor Can be taken out from within.
이때, 도2에 도시된 바와 같이, 기판 상에 산화실리콘층(140), 금속층(120) 등의 다수의 층이 증착된 기판(100)은 어닐링 단계(S300)를 거친 후 기판(210) 상에 다결정 실리콘 박막층(220)이 형성될 수 있다.In this case, as shown in FIG. 2, the substrate 100 having a plurality of layers, such as the silicon oxide layer 140 and the metal layer 120 deposited on the substrate, undergoes an annealing step (S300) and then is formed on the substrate 210. The polycrystalline silicon thin film layer 220 may be formed on the substrate.
이때, 상술한 다결정 실리콘 박막 형성 방법으로 다결정 실리콘 박막이 형성된 기판(200)을 제조할 수 있으며, 이와 같이 다결정 실리콘 박막이 형성된 기판(200)을 사용하여 태양전지, 트랜지스터 등을 제조할 수 있다.In this case, the substrate 200 in which the polycrystalline silicon thin film is formed may be manufactured by the aforementioned polycrystalline silicon thin film forming method, and the solar cell, the transistor, and the like may be manufactured using the substrate 200 in which the polycrystalline silicon thin film is formed.
한편, 도4 내지 도6을 참조하여 상술한 다결정 실리콘 박막의 형성 방법에 의해 형성된 다결정 실리콘 박막의 특성에 대해 설명하고자 한다.Meanwhile, the characteristics of the polycrystalline silicon thin film formed by the method of forming the polycrystalline silicon thin film described above with reference to FIGS. 4 to 6 will be described.
도4(a)는 550℃에서 5시간 동안 어닐링 한 후 EDX (energy dispersive x-ray spectroscopy) 측정을 위한 SiO1 .45(220nm)/Al (60nm)/글래스로 이루어진 샘플의 단면 TEM(transmission electron microscope) 이미지이다. 도시된 I, II, III, 및 IV는 층을 식별하기 위한 식별기호이다. 도4(b), 도4(c) 및 도4(d)는 각각 Si, O, Al 원자의 EDX(energy dispersive x-ray spectroscopy) 맵핑 분포를 나타낸 것이다. 도4(e)는 도4(a)에 도시된 라인을 따라 EDX 라인 스캐닝에 의해 결정된 Si, O, Al 원자의 위치 분포를 나타낸 것이다.4 (a) is then annealed at 550 ℃ for 5 hours, EDX (energy dispersive x-ray spectroscopy ) SiO 1 .45 for measurement (220nm) / Al (60nm) / glass cross-section of the sample TEM (transmission electron consisting of microscope image. I, II, III, and IV shown are identifiers for identifying layers. 4 (b), 4 (c) and 4 (d) show an energy dispersive x-ray spectroscopy (EDX) mapping distribution of Si, O and Al atoms, respectively. FIG. 4 (e) shows the positional distribution of Si, O, and Al atoms determined by EDX line scanning along the line shown in FIG. 4 (a).
도4(a)는 어닐링 이후의 4층 구조를 명확하게 보여주며, 도시된 I, II, III, 및 IV는 층을 식별하기 위한 식별기호이다.Fig. 4 (a) clearly shows the four-layer structure after annealing, wherein I, II, III, and IV shown are identification symbols for identifying the layers.
도4(b) 내지 도4(d)에 도시된 바와 같이, Si 원자의 경우, 전체영역에 분포하지만 II층에 더 많이 분포함을 보여주며, II층에는 O 원자가 거의 분포하지 않지만, II를 제외한 다른 층에는 O가 관찰되었다.As shown in Figs. 4 (b) to 4 (d), it is shown that Si atoms are distributed throughout the entire region but more distributed in the II layer, and O atoms are hardly distributed in the II layer. O was observed in other layers.
이는, 도4(e)에 도시된 결과에 의해 추가적으로 확인이 가능하다.This can be further confirmed by the result shown in FIG.
이때, II층의 Si 원자가 상술한 어닐링 단계(S300)에서 수행되는 열처리에 의해 유도되었음을 알 수 있으며, EDX 맵핑과 라인 스캐닝 결과 II층이 더 이상 금속층(120)이 아님을 보여준다.At this time, it can be seen that the Si atoms of the II layer is induced by the heat treatment performed in the annealing step (S300) described above, and shows that the II layer is no longer the metal layer 120 as a result of EDX mapping and line scanning.
여기서, Al 원자의 경우에는 주로 I층과 II층 사이 계면에 분포함을 보여주며, 이러한 결과는 Al원자가 Al층으로부터 Si상을 가진 II층으로 확산 이동하는 것에 기인한다.Here, Al atoms are mainly distributed at the interface between the I layer and the II layer. This result is due to the diffusion of Al atoms from the Al layer to the II layer having the Si phase.
참고로, 본 발명의 일 실시예에 따른 다결정 실리콘 박막 형성방법의 실험조건에서는 I층이 확인되지만, 어닐링 시간을 증가시키는 등 어닐링 조건을 변경함으로써, I층은 결정화되어 다결정 실리콘 박막을 형성할 수 있다.For reference, in the experimental conditions of the polycrystalline silicon thin film forming method according to an embodiment of the present invention, the I layer is confirmed, but by changing the annealing conditions such as increasing the annealing time, the I layer can be crystallized to form the polycrystalline silicon thin film. have.
도5(a)은 550℃에서 5시간 동안 어닐링 한 후 SiO1 .45(220nm)/Al (60nm)/글래스로 이루어진 샘플의 광학 현미경 이미지(optical microscopic image)이다. 붉은 점과 표식들은 라만(Raman) 측정지점을 나타낸 것이다. 도5(b)은 도5(a)에 도시된 다른 지점들에서 측정된 라만스펙트럼(Raman spectra)을 나타낸 것이다.Is also 5 (a) is then annealed at 550 ℃ for 5 hours SiO 1 .45 (220nm) / Al (60nm) / an optical microscope image (optical microscopic image) of the sample made of a glass. Red dots and markers indicate Raman measurement points. FIG. 5 (b) shows Raman spectra measured at different points shown in FIG. 5 (a).
여기서, 도5(a)은 마이크로 라만 분광기(micro-Raman spectrometer)에 부착된 빌트인 광학 현미경을 사용하여 촬영하였으며, 도8(a)는 결정성 및 입자의 결정 방위에 따라 상이한 색상을 나타낸다.Here, Figure 5 (a) was taken using a built-in optical microscope attached to a micro-Raman spectrometer, Figure 8 (a) shows a different color depending on the crystallinity and the crystal orientation of the particles.
또한, 도5(b)은 도5(a)에 a 내지 f로 표시된 각각 상이한 위치에서 측정한 것이며, 도5(b)에 도시된 바와 같이, 측정위치에 관계없이, 결정질 실리콘의 특성이라 할 수 있는 520cm- 1 부근에 피크가 있는 대칭형 스펙트럼이 확인되었다.In addition, Fig. 5 (b) is measured at different positions indicated by a to f in Fig. 5 (a), and as shown in Fig. 5 (b), regardless of the measurement position, the characteristics of crystalline silicon can be said. 520cm that - the symmetrical spectrum with a peak in the vicinity of one was confirmed.
이는, 도4(a)에 도시된 II층이 전체 영역에서 완전히 결정화되었음을 의미한다.This means that the layer II shown in Fig. 4A is completely crystallized in the entire region.
도6은 550℃에서 5시간 동안 어닐링 한 후 SiO1 .45(220nm)/Al (60nm)/글래스로 이루어진 샘플의 XRD 스펙트럼(x-ray diffraction spectrum)을 나타낸 것이다.6 is then annealed at 550 ℃ for 5 hours it shows the SiO 1 .45 (220nm) / Al (60nm) / sample of the XRD spectrum (x-ray diffraction spectrum) consisting of the glass.
상기 데이터에서 몇몇 특징적인 피크를 보여주며, 이때, 2θ = 28.4°의 회절 각에서 위치하는 가장 큰 피크와 2θ = 47.4°, 56.3°, 및 76.6°에서 작은 피크들이 관찰되고, 이는, 각각 실리콘 결정의 (111), (220), (311), (331) 면에서의 회절 피크 값과 일치함을 보인다.The data show some characteristic peaks, where the largest peak located at a diffraction angle of 2θ = 28.4 ° and small peaks at 2θ = 47.4 °, 56.3 °, and 76.6 ° are observed, respectively It is shown that it is consistent with the diffraction peak values at (111), (220), (311), and (331) planes.
또한, 상술한 데이터는 생성된 다결정 실리콘이 (111) 방향으로 우선적인 배향성을 가지는 것을 의미하며, 도7에 도시된 결과와도 일치함을 보인다.In addition, the above-mentioned data means that the produced polycrystalline silicon has preferential orientation in the (111) direction, and is consistent with the result shown in FIG.
이때, 2θ = 45.8° 및 67.1°에서 관찰된 추가 피크는 각각 γ-Al2O3 결정의 (400) 및 (440)면에 해당한다.At this time, additional peaks observed at 2θ = 45.8 ° and 67.1 ° correspond to the (400) and (440) planes of the γ-Al 2 O 3 crystals, respectively.
여기서, γ-Al2O3 상과 관련된 회절 피크가 나타난 것은 SiOx로 이루어진 산화실리콘층(140)과 알루미늄으로 이루이진 금속층(120)에서 알루미늄과 산소 사이의 반응에 의한 것이다.Here, the diffraction peaks related to the γ-Al 2 O 3 phase are due to the reaction between aluminum and oxygen in the silicon oxide layer 140 made of SiOx and the metal layer 120 made of aluminum.
이때, 다결정 실리콘 박막의 형성은 일반적으로 알루미늄 유도 층 교환(Al induced layer exchange; ALILE)에 의해 진행될 수 있으며, 본 발명의 일 실시예에 따른 다결정 실리콘 박막 형성 방법에서 산화실리콘층 증착단계(S200)에서 생성되는 산화물층(130) 즉, Al2O3는 산화실리콘층(140)과 금속층(120) 사이 계면에 생성되어 금속층(120)으로 확산되는 Si 원자의 확산 경로로 작용한다.In this case, the formation of the polycrystalline silicon thin film may be generally performed by Al induced layer exchange (ALILE), and the silicon oxide layer deposition step (S200) in the polycrystalline silicon thin film formation method according to an embodiment of the present invention. The oxide layer 130 generated, i.e., Al 2 O 3, is formed at the interface between the silicon oxide layer 140 and the metal layer 120 to serve as a diffusion path of Si atoms diffused into the metal layer 120.
여기서, 상술한 구조의 열처리 즉, 어닐링 단계(S300)를 수행하는 경우, 금속층(120)의 Al 원자가 산화실리콘층(140)으로 확산되고, 산화실리콘층(140)의 Si-O 결합은 해리되어 새로운 Al2O3와 자유 Si 원자를 만들게 된다.Here, when performing the heat treatment, that is, the annealing step (S300) of the above-described structure, Al atoms of the metal layer 120 is diffused into the silicon oxide layer 140, the Si-O bond of the silicon oxide layer 140 is dissociated New Al 2 O 3 and free Si atoms are created.
이때, Al 원자에 의해 생성된 Si 원자와 산화실리콘층(140)에 존재하는 기존의 과잉 Si 원자는 산화물층(130)을 가로질러 금속층(120)으로 확산되어 Si 결정핵을 생성하고, 후속적으로, 우선적인 (111) 배향을 가진 다결정 실리콘 입자들이 성장한다.At this time, the Si atoms generated by the Al atoms and the existing excess Si atoms present in the silicon oxide layer 140 diffuse across the oxide layer 130 to the metal layer 120 to generate Si crystal nuclei, and subsequently As a result, polycrystalline silicon particles with a preferential (111) orientation grow.
이 경우, (111) 방향으로 배향된 Si 원자를 유도하는 γ-Al2O3 층이 우선적으로 형성되어 산화실리콘층(140)과 다결정 실리콘 박막층(220) 사이의 계면에 위치한다.In this case, the γ-Al 2 O 3 layer which induces Si atoms oriented in the (111) direction is preferentially formed and positioned at the interface between the silicon oxide layer 140 and the polycrystalline silicon thin film layer 220.
이는, 도4에 나타난 데이터에 의해 뒷받침될 수 있으며, Al원자는 주로 도4(a)에서 산화실리콘층(130)에 해당하는 I층과 다결정 실리콘 박막층(220)에 해당하는 II층 사이 계면에 분포함을 확인할 수 있다.This may be supported by the data shown in FIG. 4, where Al atoms are mainly present at the interface between the I layer corresponding to the silicon oxide layer 130 and the II layer corresponding to the polycrystalline silicon thin film layer 220 in FIG. You can see the distribution.
결국, 본 발명은, 플라즈마 화학 기상 증착(PECVD) 방법을 통해 산화실리콘층(SiOx)을 금속층 상부에 증착하는 과정에서 공급되는 혼합가스(SiH4+N2O)에 포함된 산소원자에 의해 발생되는 산소 플라즈마에 의해 금속층 상부에 산화물층이 자연스럽게 생성되며, 이는 산화실리콘층 증착단계에서 산화실리콘이 형성되는 동안 산화물층이 자연스럽게 생성되기에 다결정 실리콘 박막을 형성하는데 있어서 형성 과정이 간소화될 수 있으며, 혼합가스(SiH4+NO2)를 사용함으로 고가의 사일렌(SiH4) 가스의 사용량을 줄일 수 있으며, 독성의 사일렌 가스를 무독성의 아산화규소(N2O)로 혼합하여 사용함으로 사일렌 가스의 독성을 저감하는 장치가 필요가 없기 때문에 그 제조비용이 절감될 수 있는 다결정 실리콘 박막 형성 방법을 제공할 수 있다.After all, the present invention, by the oxygen atom contained in the mixed gas (SiH 4 + N 2 O) supplied in the process of depositing the silicon oxide layer (SiO x ) on the metal layer by the plasma chemical vapor deposition (PECVD) method The oxide layer is naturally generated on the metal layer by the generated oxygen plasma, which can simplify the formation process in forming the polycrystalline silicon thin film because the oxide layer is naturally formed during the formation of the silicon oxide in the silicon oxide layer deposition step. By using the mixed gas (SiH 4 + NO 2 ), it is possible to reduce the use of expensive silica (SiH 4 ) gas, and by using toxic xylene gas mixed with non-toxic silicon oxide (N 2 O) Since there is no need for a device that reduces the toxicity of the benzene gas, it is possible to provide a polycrystalline silicon thin film forming method which can reduce the manufacturing cost thereof.
위에서 설명한 바와 같이 본 발명에 대한 구체적인 설명은 첨부된 도면을 참조한 실시 예에 의해서 이루어졌지만, 상술한 실시 예는 본 발명의 바람직한 예를 들어 설명하였을 뿐이기 때문에, 본 발명이 상기의 실시 예에만 국한되는 것으로 이해되어져서는 아니 되며, 본 발명의 권리범위는 후술하는 청구범위 및 그 균등개념으로 이해되어져야 할 것이다.As described above, the detailed description of the present invention has been made by the embodiments with reference to the accompanying drawings. However, since the above-described embodiments have only been described with reference to preferred embodiments of the present invention, the present invention is limited to the above embodiments. It should not be understood that the scope of the present invention is to be understood by the claims and equivalent concepts described below.
<부호의 설명><Description of the code>
100 : 다수의 층이 증착된 기판100: substrate on which multiple layers are deposited
110 : 기판110: substrate
120 : 금속층120: metal layer
130 : 산화물층 130: oxide layer
140 : 산화실리콘층 140: silicon oxide layer
200 : 다결정 실리콘 박막이 형성된 기판200: substrate on which the polycrystalline silicon thin film is formed
210 : 기판210: substrate
220 : 다결정 실리콘 박막층220: polycrystalline silicon thin film layer

Claims (10)

  1. 다결정 실리콘 박막을 형성하기 위한 촉매로 작용하는 금속을 기판 상에 증착하는 금속층 증착단계;Depositing a metal layer on a substrate, the metal serving as a catalyst for forming a polycrystalline silicon thin film;
    상기 금속층 증착단계에서 증착된 금속층 상에 산화실리콘층을 증착하는 산화실리콘층 증착단계; 및A silicon oxide layer deposition step of depositing a silicon oxide layer on the metal layer deposited in the metal layer deposition step; And
    상기 금속층 증착단계 및 상기 산화실리콘층 증착단계를 통해 상기 금속층 및 산화실리콘층이 증착된 기판 상에 다결정 실리콘 박막층이 형성되도록 열처리하는 어닐링 단계;를 포함하는 것을 특징으로 하는And annealing the heat treatment such that a polycrystalline silicon thin film layer is formed on the substrate on which the metal layer and the silicon oxide layer are deposited through the metal layer deposition step and the silicon oxide layer deposition step.
    다결정 실리콘 박막 형성 방법.Polycrystalline Silicon Thin Film Formation Method.
  2. 제1항에 있어서, The method of claim 1,
    상기 금속층 증착단계에서, 상기 금속층은 알루미늄(Al)인 것을 특징으로 하는In the metal layer deposition step, the metal layer is characterized in that the aluminum (Al).
    다결정 실리콘 박막 형성 방법.Polycrystalline Silicon Thin Film Formation Method.
  3. 제2항에 있어서,The method of claim 2,
    상기 산화실리콘층 증착단계는, 플라즈마 화학기상증착(plasma enhanced chemical vapor deposition ;PECVD, 이하 ‘PECVD’라 칭함) 방법을 사용하는 것을 특징으로 하는The silicon oxide layer deposition step is characterized by using a plasma enhanced chemical vapor deposition (PECVD, hereinafter referred to as "PECVD") method
    다결정 실리콘 박막 형성 방법.Polycrystalline Silicon Thin Film Formation Method.
  4. 제3항에 있어서,The method of claim 3,
    상기 산화실리콘층 증착단계는, 상기 금속층 증착단계에서 상기 금속층이 증착된 기판을 PECVD 반응기 내에 위치시키고, 상기 PECVD 반응기 내에 혼합가스를 공급하여 상기 금속층 상에 산화실리콘층을 증착하며,In the silicon oxide layer deposition step, placing the substrate on which the metal layer is deposited in the metal layer deposition step in a PECVD reactor, and supplying a mixed gas in the PECVD reactor to deposit a silicon oxide layer on the metal layer,
    상기 혼합가스는 사일렌(SiH4) 및 아산화질소(N2O)를 포함하고,The mixed gas includes xylene (SiH 4 ) and nitrous oxide (N 2 O),
    상기 산화실리콘층 증착단계에서 상기 산화실리콘층을 증착하는 동안 상기 금속층이 상기 혼합가스에 포함된 산소 원자에 의해 발생하는 산소 플라즈마에 노출되어 상기 금속층과 상기 산화실리콘층 사이 계면에 산화물층이 형성되는 것을 특징으로 하는During the deposition of the silicon oxide layer in the silicon oxide layer deposition step, the metal layer is exposed to an oxygen plasma generated by oxygen atoms included in the mixed gas to form an oxide layer at an interface between the metal layer and the silicon oxide layer. Characterized by
    다결정 실리콘 박막 형성 방법.Polycrystalline Silicon Thin Film Formation Method.
  5. 제4항에 있어서, The method of claim 4, wherein
    상기 산화실리콘층 증착단계에서, 상기 산화실리콘층은 SiOx인 Si 풍부 산화물(Si-rich oxide)이고, 여기서, 0<x<2인 것을 특징으로 하는In the silicon oxide layer deposition step, the silicon oxide layer is a SiO x in Si-rich oxide (Si-rich oxide), wherein, characterized in that 0 <x <2
    다결정 실리콘 박막 형성 방법.Polycrystalline Silicon Thin Film Formation Method.
  6. 제2항에 있어서,The method of claim 2,
    상기 어닐링 단계는, Al-Si 합금 계 공융온도 범위 이하의 온도에서 어닐링(Annealing)하는 것을 특징으로 하는 The annealing step, characterized in that the annealing (annealing) at a temperature below the Al-Si alloy-based eutectic temperature range
    다결정 실리콘 박막 형성 방법.Polycrystalline Silicon Thin Film Formation Method.
  7. 제6항에 있어서,The method of claim 6,
    상기 어닐링 단계는, 500℃ 내지 600℃ 범위 내 온도에서 어닐링하는 것을 특징으로 하는 The annealing step is characterized in that the annealing at a temperature in the range of 500 ℃ to 600 ℃.
    다결정 실리콘 박막 형성 방법.Polycrystalline Silicon Thin Film Formation Method.
  8. 제1항 내지 제7항 중 어느 한 항에 다결정 실리콘 박막 형성 방법으로 다결정 실리콘 박막이 형성된 기판.The board | substrate with which the polycrystalline silicon thin film was formed in any one of Claims 1-7 by the polycrystalline silicon thin film formation method.
  9. 제8항에 따른 다결정 실리콘 박막이 형성된 기판을 사용하여 제조된 태양전지.A solar cell manufactured using a substrate on which the polycrystalline silicon thin film according to claim 8 is formed.
  10. 제8항에 따른 다결정 실리콘 박막이 형성된 기판을 사용하여 제조된 트랜지스터.A transistor manufactured using a substrate on which the polycrystalline silicon thin film according to claim 8 is formed.
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US20110189841A1 (en) * 2006-03-23 2011-08-04 Board Of Trustees Of The University Of Arkansas Fabrication of large grain polycrystalline silicon film by nano aluminum-induced crystallization of amorphous silicon
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