WO2018139704A1 - Procédé de formation de film mince de silicium polycristallin - Google Patents

Procédé de formation de film mince de silicium polycristallin Download PDF

Info

Publication number
WO2018139704A1
WO2018139704A1 PCT/KR2017/002623 KR2017002623W WO2018139704A1 WO 2018139704 A1 WO2018139704 A1 WO 2018139704A1 KR 2017002623 W KR2017002623 W KR 2017002623W WO 2018139704 A1 WO2018139704 A1 WO 2018139704A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
oxide layer
polycrystalline silicon
metal layer
silicon thin
Prior art date
Application number
PCT/KR2017/002623
Other languages
English (en)
Korean (ko)
Inventor
윤종환
Original Assignee
강원대학교산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강원대학교산학협력단 filed Critical 강원대학교산학협력단
Publication of WO2018139704A1 publication Critical patent/WO2018139704A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Definitions

  • the present invention relates to a method of forming a polycrystalline silicon thin film.
  • Silicon has been widely applied as a semiconductor device in electronic devices because of its economic advantages of raw materials and easy integration with existing devices.
  • polycrystalline silicon thin films have a contact resistance with a metal and thermoelectric photoelectric properties. Due to the characteristics of photoelectronic properties and high conversion efficiency, application possibilities are emerging for manufacturing devices such as solar cells and transistors.
  • Korean Patent Publication No. 10-1011806 (filed date: April 30, 2009, published date: January 24, 2011) is given below.
  • Technology has been proposed to form a polycrystalline silicon thin film using amorphous silicon.
  • the prior art uses a metal induced crystallization method (MIC) to induce crystallization of amorphous silicon by coating a metal catalyst, that is, a metal layer on the amorphous silicon and then heat treatment.
  • MIC metal induced crystallization method
  • MIC metal induction crystallization method
  • a double layer composed of an aluminum layer and an amorphous silicon layer deposited on the substrate is annealed at a temperature below the Al-Si alloy-based eutectic temperature ( ⁇ 557 ° C.), where amorphous Si atoms separated from the silicon layer diffuse into the aluminum layer across the oxide layer located at the interface between the aluminum layer and the amorphous silicon layer, and then Si nucleation occurs in the Al layer.
  • a problem of this process is that the oxide layer formed on the aluminum layer, that is, the difficulty of controlling the formation of the aluminum oxide layer and the high cost of manufacturing the amorphous silicon layer are involved.
  • the layer exchange between the amorphous silicon layer and the metal layer is not performed, so that the crystallization of the amorphous silicon is not performed smoothly.
  • prior art requires forming an oxide layer separately from depositing a metal layer and an amorphous silicon layer on a substrate in order to achieve a layer exchange between the metal layer and the amorphous silicon layer in forming a polycrystalline silicon thin film. It had to be included.
  • An object of the present invention is to provide a method of forming a polycrystalline silicon thin film in which the formation process is simplified by replacing amorphous silicon and solving the above problems.
  • a method of forming a polycrystalline silicon thin film includes depositing a metal layer on a substrate, which serves as a catalyst for forming the polycrystalline silicon thin film; A silicon oxide layer deposition step of depositing a silicon oxide layer on the metal layer deposited in the metal layer deposition step; And annealing to heat-treat the polycrystalline silicon thin film layer to be formed on the substrate on which the metal layer and the silicon oxide layer are deposited through the metal layer deposition step and the silicon oxide layer deposition step.
  • the metal layer may be aluminum (Al).
  • the silicon oxide layer deposition step may use a plasma enhanced chemical vapor deposition (PECVD, "PECVD”) method.
  • PECVD plasma enhanced chemical vapor deposition
  • the silicon oxide layer deposition step by placing the substrate on which the metal layer is deposited in the metal layer deposition step in a PECVD reactor, and supplying a mixed gas in the PECVD reactor to deposit a silicon oxide layer on the metal layer, the mixing
  • the gas may include xylene (SiH 4 ) and nitrous oxide (N 2 O).
  • the metal layer is exposed to an oxygen plasma generated by oxygen atoms included in the mixed gas such that an oxide layer is formed at an interface between the metal layer and the silicon oxide layer. Can be formed.
  • the silicon oxide layer is a Si-rich oxide (Si-rich oxide) is SiO x , where 0 ⁇ x ⁇ 2.
  • the annealing step may be annealed at a temperature below the Al-Si alloy eutectic temperature range.
  • the annealing step may be annealed at a temperature within the range of 500 °C to 600 °C.
  • the substrate on which the polycrystalline silicon thin film is formed may be manufactured by the aforementioned polycrystalline silicon thin film forming method.
  • the solar cell may be manufactured using the substrate on which the polycrystalline silicon thin film is formed.
  • a transistor can be manufactured using a substrate on which a polycrystalline silicon thin film is formed.
  • the mixed gas (SiH 4 + N 2 O) to be supplied in the course of using the plasma chemical vapor deposition (PECVD) method depositing a silicon layer (SiO x) oxidizing the metal layer upper portion
  • the oxide layer is naturally formed on the metal layer by the oxygen plasma generated by the oxygen atom, which is a process of forming the polycrystalline silicon thin film because the oxide layer is naturally formed during the formation of the silicon oxide in the silicon oxide layer deposition step.
  • the polycrystalline silicon thin film forming method of the present invention can also reduce the manufacturing cost of a solar cell or a transistor manufactured using a substrate on which a polycrystalline silicon thin film is formed.
  • FIG. 1 is a flowchart illustrating a method of forming a polycrystalline silicon thin film according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram schematically showing a method of forming a polycrystalline silicon thin film according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram illustrating a substrate on which a metal layer, an oxide layer, and a silicon oxide layer are deposited to form a polycrystalline silicon thin film according to an embodiment of the present invention.
  • 4 (a) is then annealed at 550 °C for 5 hours, EDX (energy dispersive x-ray spectroscopy ) SiO 1 .45 for measurement (220nm) / Al (60nm) / glass cross-section of the sample TEM (transmission electron consisting of microscope image. I, II, III, and IV shown are identifiers for identifying layers.
  • 4 (b), 4 (c) and 4 (d) show an energy dispersive x-ray spectroscopy (EDX) mapping distribution of Si, O and Al atoms, respectively.
  • FIG. 4 (e) shows the positional distribution of Si, O, and Al atoms determined by EDX line scanning along the line shown in FIG. 4 (a).
  • FIG. 5 (a) is then annealed at 550 °C for 5 hours, an optical microscope image of a sample consisting of SiO 1 .45 (220nm) / Al (60nm) / glass (optical microscopic image). Red dots and markers indicate Raman measurement points.
  • FIG. 5 (b) shows Raman spectra measured at different points shown in FIG. 5 (a).
  • FIG. 1 is a flowchart illustrating a method of forming a polycrystalline silicon thin film according to an embodiment of the present invention
  • FIG. 2 is a schematic view illustrating a method of forming a polycrystalline silicon thin film according to an embodiment of the present invention
  • the polycrystalline silicon thin film forming method using a silicon oxide thin film according to an embodiment of the present invention is a metal layer deposition step (S100), silicon oxide layer deposition step (S200) and annealing step (S300) It may include.
  • the metal layer deposition step S100 is a step of depositing the metal layer 120 on the substrate 110.
  • the metal layer 120 may act as a catalyst for forming the polycrystalline silicon thin film.
  • the metal layer 120 may be made of aluminum (Al).
  • the deposition of the metal layer 120 may be performed by a thermal vapeation method at room temperature, but is not limited thereto.
  • the metal layer 120 may have a thickness of about 60 nm.
  • a glass substrate may be used as the substrate 110, and when the glass substrate is used as the substrate 110, a Corning No. 7059 glass substrates may be used.
  • the buffer layer deposition step (not shown) may be preceded by the metal layer deposition step S100, but the buffer layer deposition step (not shown) may be omitted since the buffer layer SiO 2 is a component such as glass.
  • Silicon oxide layer deposition step (S200) is a step of depositing the silicon oxide layer 140 on the metal layer 120 deposited on the substrate 110 in the above-described metal layer forming step (S100).
  • the silicon oxide layer deposition step (S200) may be formed using a PECVD method.
  • the silicon oxide layer deposition step (S200) is located in the above-described metal layer deposition step (S100) the substrate coated with the metal layer 110 in a PECVD reactor capable of vacuum formation, and supplies a mixed gas in the PECVD reactor.
  • the mixed gas is ionized by the electrode generating the plasma in the PECVD reactor, and the ionized mixed gas reaches the substrate on which the metal layer located in the PECVD reactor is deposited to deposit the silicon oxide layer 140.
  • the silicon oxide layer 140 may have a thickness of about 220 nm.
  • the mixed gas may be made of 5% xylene (SiH 4 ) and nitrous oxide (N 2 O) diluted with nitrogen, and SiO x (0 ⁇ x ⁇ 2) having different x values depending on the mixing ratio of the two gases. That is, the silicon oxide layer 140 may be formed.
  • xylene (SiH 4 ) gas may be used by mixing expensive xylene (SiH 4 ) gas with nitrous oxide (N 2 O) to reduce the manufacturing cost of polycrystalline silicon thin film formation.
  • SiO 1 .45 done, but not limited thereto.
  • the temperature of the substrate 110 may be maintained at 200 ° C. to 400 ° C., preferably about 300 ° C., during the PECVD method.
  • the silicon oxide layer 140 is preferably an oxide containing excess Si, that is, a Si rich oxide having SiO x (0 ⁇ x ⁇ 2).
  • oxygen ions in a plasma state generated by ionization of nitrous oxide (N 2 O) in the PECVD reactor are deposited on the metal layer 120, that is, on the substrate. , May react with aluminum (Al).
  • aluminum (Al), that is, aluminum oxide (Al 2 O 3 ), that is, the oxide layer 130 is formed on the metal layer 120.
  • aluminum oxide may be formed while the silicon oxide layer 140 is deposited, and the silicon oxide layer 140 may be formed on the aluminum oxide (Al 2 O 3 ).
  • the present invention is a metal layer in the silicon oxide layer deposition step (S200) without forming a separate oxide layer 130
  • An oxide layer 130 may be formed at an interface between the 120 and the silicon oxide thin film layer 150.
  • Annealing step (S300) is a heat treatment to form a polycrystalline silicon thin film layer 220 on the substrate 110, the metal layer 120, the silicon oxide layer 140 is deposited through the above-described metal layer deposition step and silicon oxide layer deposition step Step.
  • the substrate 110 on which the silicon oxide layer 140 and the metal layer 120 are deposited is placed in a quartz tube reactor using high purity nitrogen (99.999%) as an ambient gas, and the Al-Si alloy-based eutectic temperature ( ⁇ Heat treatment, that is, annealing, at a temperature of 577 ° C. or less.
  • ⁇ Heat treatment that is, annealing, at a temperature of 577 ° C. or less.
  • the oxide layer 130 formed as the silicon oxide layer 140 is deposited, that is, aluminum oxide, is a metal atom of the metal layer 120, that is, aluminum (Al) acts as a catalyst.
  • the silicon oxide layer 140 may act as a diffusion path that is diffused into the silicon oxide layer 140, and the oxide layer 130 may contribute to layer exchange between the silicon oxide layer 140 and the metal layer 120.
  • the heating rate in the annealing step (S300) was maintained at a constant 5 °C / min as an example, the substrate 110 on which the silicon oxide layer 140, the metal layer 120 and the like is deposited within the range of 500 °C to 600 °C Heat treatment at temperature.
  • the diffusion of the material through the oxide layer 130 may not be performed well, on the contrary, when the temperature is higher than the above-mentioned range, the silicon oxide layer 140, the metal layer ( 120 may cause damage to the deposited substrate 110.
  • the above-described range may be directly connected to the crystallinity of the polycrystalline silicon thin film layer 220 formed through annealing.
  • the polycrystalline silicon thin film layer 220 formed when heat-treated at 550 ° C. for 5 hours is used.
  • the crystallinity of was excellent.
  • the cooling rate may also be maintained at 5 ° C./min, as described above, and when the temperature of the substrate 110 on which the silicon oxide layer 140 and the metal layer 120 are deposited is less than 100 ° C., the quartz tube reactor Can be taken out from within.
  • the polycrystalline silicon thin film layer 220 may be formed on the substrate.
  • the substrate 200 in which the polycrystalline silicon thin film is formed may be manufactured by the aforementioned polycrystalline silicon thin film forming method, and the solar cell, the transistor, and the like may be manufactured using the substrate 200 in which the polycrystalline silicon thin film is formed.
  • 4 (a) is then annealed at 550 °C for 5 hours, EDX (energy dispersive x-ray spectroscopy ) SiO 1 .45 for measurement (220nm) / Al (60nm) / glass cross-section of the sample TEM (transmission electron consisting of microscope image. I, II, III, and IV shown are identifiers for identifying layers.
  • 4 (b), 4 (c) and 4 (d) show an energy dispersive x-ray spectroscopy (EDX) mapping distribution of Si, O and Al atoms, respectively.
  • FIG. 4 (e) shows the positional distribution of Si, O, and Al atoms determined by EDX line scanning along the line shown in FIG. 4 (a).
  • Fig. 4 (a) clearly shows the four-layer structure after annealing, wherein I, II, III, and IV shown are identification symbols for identifying the layers.
  • the Si atoms of the II layer is induced by the heat treatment performed in the annealing step (S300) described above, and shows that the II layer is no longer the metal layer 120 as a result of EDX mapping and line scanning.
  • Al atoms are mainly distributed at the interface between the I layer and the II layer. This result is due to the diffusion of Al atoms from the Al layer to the II layer having the Si phase.
  • the I layer is confirmed, but by changing the annealing conditions such as increasing the annealing time, the I layer can be crystallized to form the polycrystalline silicon thin film. have.
  • Is also 5 (a) is then annealed at 550 °C for 5 hours SiO 1 .45 (220nm) / Al (60nm) / an optical microscope image (optical microscopic image) of the sample made of a glass. Red dots and markers indicate Raman measurement points.
  • FIG. 5 (b) shows Raman spectra measured at different points shown in FIG. 5 (a).
  • Figure 5 (a) was taken using a built-in optical microscope attached to a micro-Raman spectrometer
  • Figure 8 (a) shows a different color depending on the crystallinity and the crystal orientation of the particles.
  • Fig. 5 (b) is measured at different positions indicated by a to f in Fig. 5 (a), and as shown in Fig. 5 (b), regardless of the measurement position, the characteristics of crystalline silicon can be said. 520cm that - the symmetrical spectrum with a peak in the vicinity of one was confirmed.
  • the above-mentioned data means that the produced polycrystalline silicon has preferential orientation in the (111) direction, and is consistent with the result shown in FIG.
  • the diffraction peaks related to the ⁇ -Al 2 O 3 phase are due to the reaction between aluminum and oxygen in the silicon oxide layer 140 made of SiOx and the metal layer 120 made of aluminum.
  • the formation of the polycrystalline silicon thin film may be generally performed by Al induced layer exchange (ALILE), and the silicon oxide layer deposition step (S200) in the polycrystalline silicon thin film formation method according to an embodiment of the present invention.
  • the oxide layer 130 generated, i.e., Al 2 O 3 is formed at the interface between the silicon oxide layer 140 and the metal layer 120 to serve as a diffusion path of Si atoms diffused into the metal layer 120.
  • the Si atoms generated by the Al atoms and the existing excess Si atoms present in the silicon oxide layer 140 diffuse across the oxide layer 130 to the metal layer 120 to generate Si crystal nuclei, and subsequently As a result, polycrystalline silicon particles with a preferential (111) orientation grow.
  • the ⁇ -Al 2 O 3 layer which induces Si atoms oriented in the (111) direction is preferentially formed and positioned at the interface between the silicon oxide layer 140 and the polycrystalline silicon thin film layer 220.
  • the present invention by the oxygen atom contained in the mixed gas (SiH 4 + N 2 O) supplied in the process of depositing the silicon oxide layer (SiO x ) on the metal layer by the plasma chemical vapor deposition (PECVD) method
  • the oxide layer is naturally generated on the metal layer by the generated oxygen plasma, which can simplify the formation process in forming the polycrystalline silicon thin film because the oxide layer is naturally formed during the formation of the silicon oxide in the silicon oxide layer deposition step.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Photovoltaic Devices (AREA)

Abstract

La présente invention concerne un procédé de formation d'un film mince de silicium polycristallin, le procédé comprenant : une étape de dépôt de couche métallique consistant à déposer, sur un substrat, un métal servant de catalyseur pour former un film mince de silicium polycristallin; une étape de dépôt de couche d'oxyde de silicium consistant à déposer une couche d'oxyde de silicium sur la couche métallique déposée dans l'étape de dépôt de couche métallique; et une étape de recuit consistant à effectuer un traitement thermique de manière à former une couche de film mince de silicium polycristallin sur le substrat sur lequel la couche métallique et la couche d'oxyde de silicium ont été déposées par l'étape de dépôt de couche métallique et l'étape de dépôt de couche d'oxyde de silicium.
PCT/KR2017/002623 2017-01-25 2017-03-10 Procédé de formation de film mince de silicium polycristallin WO2018139704A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2017-0011764 2017-01-25
KR1020170011764A KR101919086B1 (ko) 2017-01-25 2017-01-25 다결정 실리콘 박막 형성 방법

Publications (1)

Publication Number Publication Date
WO2018139704A1 true WO2018139704A1 (fr) 2018-08-02

Family

ID=62977991

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2017/002623 WO2018139704A1 (fr) 2017-01-25 2017-03-10 Procédé de formation de film mince de silicium polycristallin

Country Status (2)

Country Link
KR (1) KR101919086B1 (fr)
WO (1) WO2018139704A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102708283B1 (ko) 2019-07-01 2024-09-20 주식회사 엘지화학 실리콘 웨이퍼 제조 방법
KR102601668B1 (ko) 2019-07-01 2023-11-10 주식회사 엘지화학 실리콘 웨이퍼 제조 방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040051075A (ko) * 2002-12-11 2004-06-18 엘지.필립스 엘시디 주식회사 다결정 실리콘의 형성 방법
KR20100100187A (ko) * 2009-03-05 2010-09-15 삼성모바일디스플레이주식회사 다결정 실리콘층의 제조방법
KR100994236B1 (ko) * 2009-05-22 2010-11-12 노코드 주식회사 다결정 실리콘 박막의 제조방법
US20110189841A1 (en) * 2006-03-23 2011-08-04 Board Of Trustees Of The University Of Arkansas Fabrication of large grain polycrystalline silicon film by nano aluminum-induced crystallization of amorphous silicon
KR101057147B1 (ko) * 2010-03-23 2011-08-16 노코드 주식회사 다결정 실리콘 박막의 제조방법

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4105811B2 (ja) * 1998-09-30 2008-06-25 京セラ株式会社 多結晶シリコン膜の形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040051075A (ko) * 2002-12-11 2004-06-18 엘지.필립스 엘시디 주식회사 다결정 실리콘의 형성 방법
US20110189841A1 (en) * 2006-03-23 2011-08-04 Board Of Trustees Of The University Of Arkansas Fabrication of large grain polycrystalline silicon film by nano aluminum-induced crystallization of amorphous silicon
KR20100100187A (ko) * 2009-03-05 2010-09-15 삼성모바일디스플레이주식회사 다결정 실리콘층의 제조방법
KR100994236B1 (ko) * 2009-05-22 2010-11-12 노코드 주식회사 다결정 실리콘 박막의 제조방법
KR101057147B1 (ko) * 2010-03-23 2011-08-16 노코드 주식회사 다결정 실리콘 박막의 제조방법

Also Published As

Publication number Publication date
KR20180087595A (ko) 2018-08-02
KR101919086B1 (ko) 2018-11-16

Similar Documents

Publication Publication Date Title
WO2019103500A1 (fr) Composition pour déposer un film mince contenant du silicium et procédé de production d'un film mince contenant du silicium l'utilisant
WO2012018210A2 (fr) Procédé permettant de déposer un film mince de manière cyclique
WO2016122081A1 (fr) Procédé de fabrication de couche mince de chalcogénure de métal
WO2019221583A1 (fr) Aln lamellaire, procédé pour la fabrication de celui-ci et nanofeuille d'aln exfoliée à partir de celui-ci
WO2021096326A1 (fr) Procédé de formation de film mince à l'aide d'un matériau de protection de surface
WO2015105337A1 (fr) Nouveau dérivé trisilyl amine, procédé pour le préparer et couche mince contenant du silicium l'utilisant
WO2018139704A1 (fr) Procédé de formation de film mince de silicium polycristallin
WO2010134691A2 (fr) Procédé de fabrication de couche mince à base de silicium polycristallin
WO2017082695A2 (fr) Film mince de métal-carbure-oxyde comprenant du carbone, un oxyde et du métal, et procédé de fabrication associé
WO2014084557A1 (fr) Composés de précurseur de silicium et procédé de dépôt de film mince contenant du silicium l'utilisant
WO2017122985A1 (fr) Procédé de préparation d'une couche mince d'oxyde, couche mince d'oxyde et dispositif électronique ainsi fabriqué
WO2018094806A1 (fr) Procédé de fabrication d'un revêtement antireflet microstructuré ou nanostructuré, et dispositif d'affichage
WO2021141324A1 (fr) Procédé de formation de film mince à l'aide d'un matériau de protection de surface
WO2018186535A1 (fr) Procédé de préparation d'un matériau bidimensionnel à l'aide d'un traitement de surface par inhibiteur d'adsorption
WO2022075687A1 (fr) Verre résistant au plasma et son procédé de fabrication
WO2017188546A1 (fr) Procédé de dépôt de film mince
WO2019100427A1 (fr) Procédé de fabrication de substrat de réseau souple, et substrat de réseau souple
WO2014209030A1 (fr) Procédé pour la fabrication de graphène utilisant un élément couvercle et procédé pour la fabrication d'élément électronique comprenant celui-ci
WO2024117712A1 (fr) Dispositif à semi-conducteurs et son procédé de fabrication
WO2014073892A1 (fr) Procédé de fabrication de couche mince contenant du silicium
WO2022250343A1 (fr) Procédé de fabrication de cuivre revêtu de silicium, cuivre anti-oxydation revêtu de silicium l'utilisant, et dispositif semi-conducteur l'utilisant
WO2024014766A1 (fr) Procédé de fabrication d'un film mince de dichalcogénure de métal de transition ayant une structure hiérarchique tridimensionnelle hautement uniforme
WO2022034987A1 (fr) Procédé de fabrication de pile solaire à couche mince de pérovskite
WO2010030068A1 (fr) Procédé de transition de phase de matériau amorphe
WO2023075277A1 (fr) Procédé de fabrication d'une couche mince à l'aide d'une couche de graphène à surface fonctionnalisée et couche mince fabriquée par ce procédé

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17894578

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17894578

Country of ref document: EP

Kind code of ref document: A1