KR20040051075A - Methode Of Forming Polycrystalline Silicon - Google Patents

Abstract

PURPOSE: A method for forming polycrystalline silicon is provided to reduce process time and fabrication cost, and improve the surface characteristics for a gate isolating layer by forming an amorphous silicon layer on a catalyst metal layer and simultaneously carrying out a crystallization on the amorphous silicon layer. CONSTITUTION: A catalyst metal layer(230) is formed on a substrate(210). An amorphous silicon layer is deposited on the catalyst metal layer and simultaneously the amorphous silicon layer is transformed into a polycrystalline silicon layer(220a) by crystallization on the amorphous silicon layer. Preferably, the depositing and crystallizing process are carried out by using a PECVD(Plasma Enhanced Chemical Vapor Deposition) apparatus or an LPCVD(Low Pressure Chemical Vapor Deposition) apparatus at the temperature of 550-600 °C.

Description

Method of Forming Polycrystalline Silicon

The present invention relates to a liquid crystal display device, and more particularly, to a method of forming a polycrystalline silicon film used as an active layer of a thin film transistor for a liquid crystal display device.

In the current flat panel display (FPD) field, an active matrix liquid crystal display (AMLCD) is the mainstream. In an active matrix liquid crystal display device, a thin film transistor (TFT) is used as a switching device to change the transmittance of a pixel by adjusting a voltage applied to a liquid crystal of one pixel.

Such thin film transistors are mainly formed using hydrogenated amorphous silicon (hereinafter, abbreviated as amorphous silicon), which is called an amorphous silicon thin film transistor (amorphous silicon TFT). Amorphous silicon thin film transistor is easy to manufacture a large area, high productivity, and can be deposited at a low substrate temperature of 350 ℃ or less has the advantage of using a low-cost insulating substrate.

However, because amorphous silicon has disordered atomic arrangements, weak Si-Si bonds and dangling bonds exist, and thus they become metastable when irradiated with light or applied with electric fields. This problem is emerging. In particular, amorphous silicon has a problem in that its properties are deteriorated by irradiation of light, and its electrical characteristics (field effect mobility: 0.1-1.0 cm 2 / V · s) and reliability are poor, making it difficult to use in driving circuits.

Therefore, the amorphous silicon thin film transistor is used only as a switching element of the pixel and the driving circuit is mounted by connecting an insulating substrate and a printed circuit board (PCB) by using an integrated circuit (Tape Carrier Package) driving IC (TCP). As a result, the driving IC and the mounting cost take a large part of the cost.

In addition, when the resolution of the liquid crystal panel for a liquid crystal display device is increased, the pad pitch outside the substrate connecting the gate wiring and the data wiring of the thin film transistor substrate with the TCP becomes short, and the TCP bonding itself becomes difficult.

However, since polycrystalline silicon has much higher field effect mobility than amorphous silicon, a driving circuit can be made on a substrate, thereby reducing driving IC cost and simplifying mounting.

In addition, polycrystalline silicon has a higher field effect mobility than amorphous silicon, and is advantageous as a switching device of a high resolution panel. The polycrystalline silicon may be applied to a display in which a lot of light is emitted due to less light current than amorphous silicon.

The structure of such a polycrystalline silicon TFT is briefly described with reference to the drawings.

1 is a schematic cross-sectional view showing the structure of a conventional polycrystalline silicon thin film transistor.

As shown in FIG. 1, a buffer layer 20 is formed on the substrate 10, and an active layer 30 made of polycrystalline silicon is formed on the buffer layer 20. The active layer 30 is divided into the source and drain regions 30a and 30b and the channel region 30c by a subsequent process. A gate insulating layer 40 is formed on the active layer 30, and a gate 50 corresponding to the active layer 30 is formed on the gate insulating layer 40. An interlayer insulator 60 including source and drain contact holes 62a and 62b is formed on the gate 50, and the source and drain contact holes 62a and 62b are formed on the interlayer insulating film 60. Source and drain electrodes 70a and 70b are formed to be connected to the source and drain regions 30a and 30b, respectively.

It is very important to form an active layer made of polysilicon in such a polycrystalline silicon thin film transistor. Generally, in order to form a polycrystalline silicon thin film, a plasma enhanced chemical vapor deposition (PECVD) method or a low pressure vapor deposition method is used. Vapor Deposition: LPCVD method is used to deposit pure amorphous silicon (intrinsic amorphous silicon), and then crystallize it again.

These crystallization methods can be classified into three categories as follows.

First, the solid phase crystallization (SPC) method is a method of forming polycrystalline silicon by heat-treating amorphous silicon for a long time at a high temperature.

Second, metal induced crystallization (MIC) method is a method of forming a polycrystalline silicon by depositing a metal on amorphous silicon, a large-area glass substrate can be used.

Third, the laser annealing method is a method of forming polycrystalline silicon by applying a laser to an amorphous silicon thin film.

The first method, the solid phase crystallization method, forms a buffer layer with a predetermined thickness to prevent diffusion of impurities on a quartz substrate that can withstand high temperatures of 600 ° C. or higher, and deposits amorphous silicon on the buffer layer. After that, a method of obtaining polycrystalline silicon by heat treatment at a high temperature for a long time in a furnace, as described above, the solid phase crystallization is performed for a long time at a high temperature, so that a desired polycrystalline silicon phase cannot be obtained, and grain growth direction is irregular. When applied to the thin film transistor, the gate insulating film to be connected to the polycrystalline silicon grows irregularly, and thus the breakdown voltage of the device is lowered. The grain size of the polycrystalline silicon is severely uneven so that the electrical characteristics of the device are poor. In addition to lowering the cost, there is a problem of using an expensive quartz substrate.

The second method, metal-induced crystallization, can form polycrystalline silicon using a low-cost, large-area glass substrate. However, since metal residues are more likely to be present in a network inside the polycrystalline silicon, film quality reliability is improved. Cannot be guaranteed.

The third method, the laser heat treatment method, is the most widely studied method of forming polycrystalline silicon, and supplies the laser energy instantaneously (tens of hundreds to hundreds of nanoseconds) to a substrate on which amorphous silicon is deposited to make the amorphous silicon melted. It is a method of forming polycrystalline silicon by cooling.

However, since polycrystalline silicon crystallized by the laser heat treatment crystallization method has a problem of inferiority in uniformity, technical space remains to be applied to a large-area substrate.

Therefore, a new application of the MIC method has been proposed. Field-enhanced metal-induced crystallization (Field Enhanced MIC: FE-), which can lower the crystallization time and the temperature required for crystallization by applying a direct current high voltage to the metal-treated thin film, has been proposed. MIC) method.

This field applied metal induction crystallization method will be described in detail with reference to the accompanying drawings.

2A to 2C are schematic cross-sectional views illustrating a conventional field application metal induced crystallization method.

As shown in FIG. 2A, an amorphous silicon layer 120 is formed on the substrate 110. The amorphous silicon layer 120 is formed using a PECVD apparatus or an LPCVD apparatus.

As shown in FIG. 2B, the catalyst metal layer 130 is formed on the amorphous silicon layer 120. The catalytic metal layer 130 serves as a catalyst in the crystallization step by subsequent heat treatment and electric field application.

As shown in FIG. 2C, electrodes 140a and 140b are formed at both ends of the catalyst metal layer 130, and the catalyst metal layer 130 and the amorphous silicon layer 120 (120 in FIG. 2B) are formed through the electrodes 140a and 140b. Apply voltage to At the same time, by heating the substrate 110 including the amorphous silicon layer (120 in FIG. 2B) by a heating device (not shown), the amorphous silicon layer (120 in FIG. 2B) is crystallized to become the polycrystalline silicon layer 120a. In general, a furnace is used as a heating device.

In such crystallization of amorphous silicon, the metal atoms of the catalytic metal layer serve as crystallization nuclei of amorphous silicon, and the electric field by the applied voltage promotes the role of these metal atoms, thereby increasing the crystallization rate and lowering the crystallization temperature.

However, such a conventional field application metal induced crystallization method has a separate step of heating the substrate including the amorphous silicon layer in addition to the amorphous silicon layer forming step and the catalyst metal layer forming step, thereby increasing the processing time and reducing productivity and manufacturing cost There is a problem that increases. In addition, when the catalyst metal layer remains after crystallization, a problem may occur that the interface property between the gate insulating film and the active layer is degraded.

In order to improve the above-mentioned problems, in the present invention, by forming a catalyst metal layer on the substrate, and forming amorphous silicon on the substrate and simultaneously crystallization, the process time is shortened to reduce the manufacturing cost and interface characteristics with the gate insulating film It is an object of the present invention to provide a method for forming polycrystalline silicon which improves the amount of silicon.

1 is a schematic cross-sectional view showing the structure of a conventional polycrystalline silicon thin film transistor.

2a to 2c are schematic cross-sectional views illustrating a conventional field applied metal induced crystallization method.

3A-3B are schematic cross-sectional views illustrating a method of crystallizing amorphous silicon according to the present invention.

<Description of Symbols for Major Parts of Drawings>

10, 110, 210: substrate 20: buffer layer

30: active layer 40: gate insulating film

50 gate electrode 60 interlayer insulating film

62a: source electrode 62b: drain electrode

120, 220: amorphous silicon layer 120a, 220a: polycrystalline silicon layer

130, 230: catalyst metal layer

In order to achieve the above object, the present invention comprises the steps of forming a catalyst metal layer on the substrate; It provides a method of forming polycrystalline silicon comprising the step of simultaneously crystallizing an amorphous silicon layer on the catalyst metal layer.

The step of depositing and simultaneously crystallizing the amorphous silicon layer is performed using a plasma vapor deposition (PECVD) device or an atmospheric pressure vapor deposition (LPCVD) device at a temperature between 550 ° C. and 600 ° C., and the thickness of the amorphous silicon layer is 300 ° C. Between 800Å.

The catalyst metal layer may be formed of one of nickel (Ni), cobalt (Co), and lead (Pb) using one of a sputter, an e-beam evaporator, or an ion implanter. It is formed, the thickness of the catalyst metal layer is 10 kPa or less.

The method may further include forming a buffer layer between the substrate and the catalyst metal layer. The buffer layer may form a double layer of SiO ₂ / SiNx at a thickness of 3000 kPa and 1000 kPa, respectively.

On the other hand, the present invention comprises the steps of forming a buffer layer on the substrate; Forming a catalyst metal layer on the buffer layer; Depositing an amorphous silicon layer on the catalyst metal layer and simultaneously crystallizing to form a polycrystalline silicon layer; Etching the polycrystalline silicon layer to form an active layer; Forming a gate insulating film on the active layer; Forming a gate corresponding to the active layer on the gate insulating layer; Implanting ions into the active layer using the gate as an ion implantation mask to form source and drain regions; Forming an interlayer insulating film on the gate; A method of forming a polycrystalline silicon thin film transistor including forming a source and a drain electrode connected to a source and a drain region, respectively, is formed on the interlayer insulating layer.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

3A to 3B are schematic cross-sectional views illustrating a method of crystallizing amorphous silicon according to the present invention.

As shown in FIG. 3A, the catalyst metal layer 230 is formed on the substrate 210. The catalytic metal layer 230 may be formed of one of nickel (Ni), cobalt (Co), and lead (Pb) using a sputter, an e-beam evaporator, or an ion implanter. It may be formed at about 100 ° C. or less, and has a thickness of about 1 to 2 atomic layers of about 10 GPa or less. This catalytic metal layer 230 serves as a crystallization catalyst in the subsequent deposition and crystallization steps of the amorphous silicon layer.

Although not shown, a buffer layer may be formed between the substrate 210 and the catalyst metal layer 230 to block impurities that may flow from the substrate 210, wherein the buffer layer may be formed of a SiO ₂ / SiNx bilayer. Preferably, the thickness can be formed to about 3000 kPa and 1000 kPa, respectively.

As illustrated in FIG. 3B, an amorphous silicon layer (not shown) is deposited on the catalyst metal layer 230 and simultaneously crystallized to form the polycrystalline silicon layer 220a. The polycrystalline silicon layer 220a may be formed using a plasma vapor deposition (PECVD) or atmospheric vapor deposition (LPCVD), the process temperature is 600 ℃ or less, preferably 550 ℃ to 600 ℃. At this time, the reaction gas is SiH ₄ (Si ₂ H ₆ ): H ₂ (N ₂ ) = 200sccm: 500sccm. The thickness of the polycrystalline silicon layer 220a is preferably 300 kPa to 800 kPa.

As such, since the polycrystalline silicon layer 220a is formed at the same time as the deposition of the amorphous silicon layer, a separate heat treatment process is not required.

In addition, when the thin film transistor fabrication process is performed, the polycrystalline silicon layer 220a is used as an active layer and a gate insulating film is formed on the polycrystalline silicon layer 220a. The catalyst metal layer 230 is disposed below the polycrystalline silicon layer 220a. Since it is formed, it does not affect the interface characteristics between the polycrystalline silicon layer 220a used as the active layer and the gate insulating film, thereby improving the electrical characteristics of the thin film transistor.

The method for forming polycrystalline silicon according to the present invention is not limited to the above embodiments, and various changes and modifications are possible by one of ordinary skill in the art without departing from the spirit of the present invention. It is apparent that such changes and modifications belong to the present invention through the appended claims.

As described above, in the method of forming the polycrystalline silicon according to the present invention, since a separate heat treatment step is not required, the process time can be shortened, thereby reducing the manufacturing cost and improving the process yield since defects that may occur in the heat treatment process can be excluded. You can. In addition, since the interface property between the active layer and the gate insulating film is improved, the electrical properties of the polycrystalline silicon thin film transistor may be improved.

Claims (11)

Forming a catalyst metal layer on the substrate; Simultaneously depositing an amorphous silicon layer on the catalyst metal layer and crystallizing the same Polycrystalline silicon formation method comprising a. The method of claim 1, And simultaneously crystallizing the amorphous silicon layer, wherein the crystallization is performed at a temperature between 550 ° C and 600 ° C. The method of claim 2, And simultaneously crystallizing the amorphous silicon layer using a plasma vapor deposition (PECVD) device or an atmospheric pressure vapor deposition (LPCVD) device. The method of claim 3, wherein Wherein the thickness of the amorphous silicon layer is between 300 kPa and 800 kPa. The method of claim 1, The catalyst metal layer is a method of forming polycrystalline silicon, characterized in that formed using one of nickel (Ni), cobalt (Co), lead (Pb). The method of claim 5, wherein And the thickness of the catalyst metal layer is 10 kPa or less. The method of claim 6, The catalyst metal layer is formed using a sputter, an e-beam evaporator, or an ion implanter. The method of claim 1, Forming a buffer layer between the substrate and the catalyst metal layer. The method of claim 8, The buffer layer is a method for forming polycrystalline silicon, characterized in that the double layer of SiO ₂ / SiNx. The method of claim 9, Uicheung SiO ₂ and the thickness of the SiNx layer on the buffer layer are each 3000Å, the method of forming the polycrystalline silicon, characterized in that the 1000Å. Forming a buffer layer over the substrate; Forming a catalyst metal layer on the buffer layer; Depositing an amorphous silicon layer over the catalyst metal layer and simultaneously crystallizing to form a polycrystalline silicon layer; Etching the polycrystalline silicon layer to form an active layer; Forming a gate insulating film on the active layer; Forming a gate corresponding to the active layer on the gate insulating layer; Implanting ions into the active layer using the gate as an ion implantation mask to form source and drain regions; Forming an interlayer insulating film on the gate; Forming a source and a drain electrode connected to the source and drain regions, respectively, on the interlayer insulating layer; Method of forming a polycrystalline silicon thin film transistor comprising a.