KR100652060B1 - poly-Si layer, method for crystallizing to the same and method for fabricating TFT array substrate by using the said - Google Patents

Abstract

The present invention provides a polysilicon layer and its crystallization method to form a uniform and low quality micro silicon layer by periodically depositing a thin layer of amorphous silicon layer several times and then hydrogenating it, and manufacturing a liquid crystal display device using the same. The polysilicon layer according to the present invention comprises an amorphous silicon layer formed on a substrate and composed of a plurality of unit layers and having a porous interface between the unit layers, and hydrogen diffused from the surface of the amorphous silicon layer. And crystallized seeds formed by reacting at the porous interface, and a plurality of crystal grains crystallized about the crystallized seeds by hydrogen diffused from the surface of the amorphous silicon layer.

Hydrogen Plasma, Micro Silicon Layer, Void Defects

Description

Polysilicon layer and its crystallization method and manufacturing method of liquid crystal display device using the same {poly-Si layer, method for crystallizing to the same and method for fabricating TFT array substrate by using the said}

1 is a process cross-sectional view showing a crystallization process according to the prior art.

Figure 2 is an SEM surface observation of the microsilicon layer for explaining the problems caused by the prior art.

Figure 3a to 3b is a cross-sectional view showing a crystallization process according to another prior art.

Figure 4 is an SEM surface observation of the microsilicon layer for explaining another conventional problem.

5a to 5c is a cross-sectional view showing a crystallization process according to the present invention.

6A to 6C are SEM surface observation diagrams of the microsilicon layer according to the hydrogenation time.

7 is a graph showing the crystallization volume fraction and grain size according to the hydrogenation time.

8A to 8F are process cross-sectional views of a TFT array substrate according to the present invention.

9 is a graph showing drain current versus gate voltage at different hydrogenation times.

10A to 10C are graphs showing the values of Ion, Ioff, and μ, respectively, according to the hydrogenation time.

* Explanation of symbols for the main parts of the drawings

11,211 insulation board 12 gate electrode

13: gate insulating film 14,213: amorphous silicon layer

24 semiconductor layer 15 data wiring

15a, 15b: source / drain electrodes 16: protective film

17 pixel electrode 18 contact hole

213a: unit layer 215: grain

217: Crystallized Seed

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polysilicon crystallization method. The present invention relates to a polysilicon layer, a crystallization method thereof, and a method of manufacturing a liquid crystal display device using the same, to form a microsilicon layer having a low void defect.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELDs), and vacuum fluorescence (VFDs) have been developed. Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as the substitute for CRT (Cathode Ray Tube) for mobile image display device because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention has been developed in a variety of monitors, such as television and computer for receiving and displaying broadcast signals.

A general liquid crystal display device may be broadly divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel has a predetermined space and is bonded to the color filter array substrate and the thin film transistor array substrate. And a liquid crystal layer injected between the two substrates.

In this case, the thin film transistor array substrate includes a plurality of gate lines arranged in one direction at a predetermined interval, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, and each of the gate lines and data. A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing lines, and a plurality of thin film transistors (TFTs) that are switched by signals of the gate lines to transfer signals of the data lines to each pixel electrode. Film Transistor) is provided.

Here, the thin film transistor uses an active layer made of amorphous silicon (amorphous silicon: a-Si) and an active layer made of polysilicon (micro silicon: μc-Si) having a crystalline phase, depending on which silicon is used as the active layer. Can be classified as using.

The active layer made of microsilicon has a carrier mobility of about 10 to 100 times higher than that of an active layer made of amorphous silicon, and thus can be a driving circuit on a substrate, which is advantageous as a switching element of a high resolution panel.

Accordingly, liquid crystal display devices using microsilicon as the active layer have been recognized as a technology for realizing next generation high performance intelligent display systems.

In this case, the micro silicon layer may be formed by directly depositing polycrystalline silicon or by depositing amorphous silicon and then crystallizing it into polycrystal.

The former method is LPCVD (Low Pressure Chemical Vapor Deposition) to be deposited at a high temperature of 550 ° C. or higher, and plasma deposited using SiF ₄ / SiH ₄ / H ₂ mixed gas at 400 ° C. or lower. PECVD (Plasma Enhanced Chemical Vapor Deposition).

On the other hand, the latter method is a solid phase crystallization method (SPC method: Solid Phase Crystallization), which crystallizes by depositing amorphous silicon on a glass substrate and heat treatment at a high temperature for a long time, and an excimer that is instantaneously crystallized by applying an excimer laser while heating to 250 ℃ Laser annealing (ELA: Eximer Laser Annealing), metal induced crystallization (CVD) that induces crystallization by depositing metal on top of the amorphous silicon layer, and amorphous silicon divided into several zones SLS method to investigate and crystallize.

Hereinafter, a method of forming a microsilicon layer will be described in detail with reference to the accompanying drawings.

1 is a process cross-sectional view showing a crystallization process according to the prior art, Figure 2 is a SEM surface observation of the microsilicon layer for explaining the problem according to the prior art.

3A and 3B are cross-sectional views showing another crystallization process according to the prior art, and FIG. 4 is an SEM surface observation diagram of a microsilicon layer for explaining another conventional problem.

First, in the case of directly depositing micro silicon (μc-Si) as a single layer, as shown in FIG. 1, the base film 113 is formed of silicon nitride (SiNx) or silicon oxide (SiOx) on the substrate 111. It forms and deposits a micro silicon by diluting a ratio of silane gas (SiH ₄ ) and hydrogen gas (H ₂ ), which are deposition gases, to 1:60 to 1: 300. At this time, the deposition temperature is a high temperature of 250 ~ 300 ℃, the deposition RF power is 300 ~ 1000W.

However, in this case, hydrogen atoms of the base film 113 thermally activated at a high temperature of 250 to 300 ° C. react with hydrogen radicals, which are deposition gases, to generate hydrogen gas (H ₂ ), and thus voids inside the microsilicon layer 114. Void-like defects 118 are formed. These void defects 118 serve to increase defect density and lower crystallinity (see FIG. 2).

As such, the method of directly depositing micro silicon has a mobility (μ) of 0.05 to 0.2 cm ² due to ion damage caused by high RF power during deposition and void defects caused by the base film and hydrogen gas reaction. Will be lowered to / Vs.

Meanwhile, in the method of polycrystallizing amorphous silicon using the growth seed layer, first, as shown in FIG. 3A, the amorphous silicon is deposited to the seed generation layer 152 to a thickness of 20 GPa and subjected to hydrogenation for 10 to 30 seconds. To form the crystallization seed 153. Thereafter, as shown in FIG. 3B, amorphous silicon is again deposited on the seed generation layer 152 on which the crystallization seed 153 is formed to a thickness of 200 to 300 GPa, and the surface of the amorphous silicon layer 154 is 10 to 40 minutes. During the hydrogenation treatment.

However, in this case, the thickness of the amorphous silicon layer 154 is so thick that a diffusion path of hydrogen is formed during the hydrogenation process, resulting in an increase in stress during crystal growth from the growth seed layer 152. As a result, even after 15 minutes of hydrogenation, low crystallinity (Xc) of less than 20% appears, and mobility (μ) is low as 0.2 ~ 0.4 cm ² / Vs.

Therefore, the present invention is a polysilicon layer and a crystallization method for forming a uniform, low defect quality microsilicon layer by periodically depositing a thin thickness of amorphous silicon layer several times and then hydrogenating instead of the conventional crystallization method. The purpose is to provide.

In addition, the present invention provides a method for manufacturing a liquid crystal display device for improving the electrical properties such as mobility of the device, sub-threshold voltage, etc. by forming a high quality micro silicon layer having few void defects as a semiconductor layer. There is another purpose.

Polysilicon layer according to the present invention for achieving the above object is formed on a substrate consisting of a plurality of unit layers and having a porous interface between the unit layer and the diffusion from the surface of the amorphous silicon layer And a crystallization seed formed by reacting hydrogen at the porous interface, and a plurality of crystal grains crystallized about the crystallization seed by hydrogen diffused from the surface of the amorphous silicon layer.

In addition, the polysilicon layer crystallization method comprises the steps of periodically repeating the deposition and non-deposition of amorphous silicon on the substrate, and hydrogenated the amorphous silicon layer to form and grow a crystallized seed crystal silicon to polysilicon Characterized in that it comprises a step of crystallization.

Meanwhile, a method of manufacturing a liquid crystal display device using the polysilicon crystallization method includes forming a gate wiring and a gate electrode on a substrate, forming a gate insulating film on the entire surface including the gate wiring, and forming a gate insulating film on the gate insulating film. Periodically repeating deposition and non-deposition of amorphous silicon, hydrogenating the amorphous silicon layer to form and growing a crystallization seed to crystallize amorphous silicon to polysilicon, and patterning the polysilicon to a semiconductor layer Forming a layer; forming a data line crossing the gate line; and forming a source / drain electrode stacked on the semiconductor layer; forming a passivation layer on the entire surface including the data line; and penetrating the passivation layer. To form a pixel electrode in contact with the drain electrode. Characterized in that made.

Hereinafter, a polysilicon layer according to the present invention, a crystallization method thereof, and a method of manufacturing a liquid crystal display device using the same will be described in detail with reference to the accompanying drawings.

5A to 5C are cross-sectional views illustrating a crystallization process according to the present invention, and FIGS. 6A to 6C are SEM surface views of microsilicon layers according to hydrogenation time, and FIG. 7 is a crystallization volume fraction according to hydrogenation time. And graphs showing grain size.

As shown in FIG. 5C, the polysilicon layer according to the present invention includes an amorphous silicon layer 213 formed on the insulating substrate 211 and formed of a plurality of unit layers 213a and having a porous interface between the unit layers. The crystallized seed 217 is formed by crystallization seed 217 formed by reaction of hydrogen diffused from the surface of the amorphous silicon layer 213 at the porous interface and hydrogen diffused from the surface of the amorphous silicon layer 213. It characterized in that it comprises a plurality of crystal grains 215 crystallized around.

Specifically, hydrogen is diffused from the surface of the amorphous silicon layer 213 to the porous interface between the unit layers to form a crystallization seed 217 at the interface between the unit layers, and the crystallized seed 217 thus formed is hydrogen diffusion. This further causes the crystallization seed to grow in the lower layer. In this manner, a microsilicon layer composed of high quality grains can be obtained.

Referring to the crystallization process of the polysilicon layer, first, as shown in FIG. 5A, the unit layer 213a of amorphous silicon (a-Si) is formed on the insulating substrate 211 by chemical vapor deposition (CVD). It deposits in thickness of -20Å. In this case, silane gas (SiH ₄ ) and hydrogen gas (H ₂ ) are used as the deposition gas. The ratio is 1:10 or less, and the deposition RF power is 100 to 300W.

Next, the RF power is turned off to stop the deposition of amorphous silicon, and after a predetermined time passes, the RF power is turned on again to 100 to 300 W to deposit a unit layer of amorphous silicon. At this time, the RF power is periodically turned on / off so that the unit layer of amorphous silicon is intermittently deposited under the same deposition conditions.

As shown in FIG. 5B, after repeatedly depositing amorphous silicon about 10 to 15 times, as shown in FIG. 5C, a hydrogenation process using hydrogen gas (H ₂ ) is performed to form the amorphous silicon layer 213. Crystallize. In the hydrogenation process, the RF power is 300 to 1000 W, and the process is performed for 10 to 40 minutes.

As described above, when the amorphous silicon is intermittently deposited about 10 to 15 times and then hydrogenated, the hydrogen diffused on the surface of the amorphous silicon layer 213 is allowed to have sufficient time and hydrogen at the porous intermittent surface of the interface of the unit layer 213a. Thereby forming a crystallization seed, which then undergoes crystallization growth.

This reaction will occur sequentially from the surface of the amorphous silicon layer 213 on the diffusion path of hydrogen gas, as shown in FIG. 5C, and can form relatively dense and uniform grains, and the reaction is also stable.

6A to 6C are SEM surface observation diagrams showing the crystallization phenomenon according to the hydrogenation time, FIG. 6A is a photographic view before the hydrogenation treatment, FIG. 6B is a photographic view of the hydrogenation treatment for 5 minutes, and FIG. The photograph shows the hydrogenation treatment for 15 minutes. In this way, it can be confirmed that the longer the hydrogenation treatment time, the larger the grain size.

7 is a graph showing the crystallization volume fraction and grain size when the hydrogenation treatment is performed after the deposition of amorphous silicon a plurality of times intermittently, the curve at the top of the graph shows the volume fraction of the crystals according to the hydrogenation time (Xc: amorphous). The volume ratio of polysilicon to the volume of silicon) shows that as the hydrogenation time increases, the numerical value increases, indicating that the volume fraction of microsilicon increases.

In addition, the curve at the bottom of the graph shows the size of the grains according to the hydrogenation time, and it can be seen that the grain size increases when the hydrogenation treatment is performed for 10 minutes or more.

Hereinafter, a method of manufacturing a TFT array substrate using the crystallization method according to the present invention will be described in detail.

8A to 8F are process cross-sectional views of a TFT array substrate according to the present invention, and FIG. 9 is a graph showing drain current with respect to gate voltage at different hydrogenation processing times, and FIGS. 10A to 10C are hydrogenation processing times. Are graphs showing the values of Ion, Ioff, and μ, respectively.

First, as shown in FIG. 8A, a low-resistance metal layer such as copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), and chromium (Cr) on the insulating substrate 11. To form a gate wiring (not shown) and a gate electrode 12 by depositing and patterning the same by a photolithography process, and inorganic materials such as silicon nitride (SiNx) and silicon oxide (SiOx) on the entire surface including the gate electrode 12. An insulating material is deposited by PECVD to form a gate insulating film 13.

Then, amorphous silicon (a-Si, 14) is deposited thereon in a thin thickness of about 10 to 20 kPa by chemical vapor deposition (CVD). In this case, silane gas (SiH ₄ ) and hydrogen gas (H ₂ ) are used as the deposition gas. The ratio is 1:10 or less, and the deposition RF power is 100 to 300W.

Next, the RF power is turned off to stop the deposition of amorphous silicon, and after a predetermined time passes, the RF power is turned on again to 100 to 300W to deposit amorphous silicon. At this time, the on / off of the RF power is set to be periodically replaced so that the amorphous silicon is intermittently deposited under the same deposition conditions.

As such, when the deposition process and the deposition process of amorphous silicon are repeated about 10 to 15 times, as shown in FIG. 8B, the amorphous silicon layer 14 is formed of several unit layers, The interface becomes a porous intermittent surface. Thereafter, hydrogen is diffused to the porous intermittent surface to form a crystallized seed.

Subsequently, as shown in FIG. 8C, the amorphous silicon layer 14 is hydrogenated to cure. In the hydrogenation process, the RF power is 300 to 1000 W, and the process is performed for 10 to 40 minutes.

As described above, when the amorphous silicon is intermittently deposited about 10 to 15 times and then hydrogenated, the hydrogen diffused on the surface of the amorphous silicon layer 14 is allowed to react with sufficient time and hydrogen in the intermittent surface of the porosity of the interface between the amorphous silicon layers. Crystallization seeds are formed and then crystallized to grow. This reaction will occur sequentially from the surface of the amorphous silicon layer 14 on the diffusion path of hydrogen gas, and can form relatively dense and uniform grains, and the reaction is also stable.

Subsequently, as shown in FIG. 8D, the crystallized polysilicon layer is patterned by a photoetch process to form a semiconductor layer 24. The semiconductor layer 24 is formed on the gate insulating layer 13 on the gate electrode 12.

 Next, as shown in FIG. 8E, copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), chromium (Cr), and the like on the entire surface including the semiconductor layer 24. The data line 15 and the source / drain electrodes 15a and 15b are formed by depositing a low resistance metal layer and patterning the photoresist pattern.

Thus, the data line 15 is formed to vertically cross the gate line to define a pixel, and the source / drain electrodes 15a and 15b are formed on the semiconductor layer 24 to form the gate electrode 12, A thin film transistor stacked with the gate insulating film 13, the semiconductor layer 24, and the source / drain electrodes 15a and 15b is configured.

Subsequently, a protective film 16 is formed by applying an organic insulating material such as benzocyclobutene (BCB) or acrylic resin (acryl resin) on the entire surface including the data line 15, and a part of the drain electrode 15b is exposed. The protective film 16 is patterned to form the contact hole 18.

Finally, as shown in FIG. 8F, indium tin oxide (ITO) or indium zinc oxide (IZO), etc. are deposited and patterned on the entire surface including the passivation layer 16 to form the drain electrode through the contact hole 18. The pixel electrode 17 is formed in the pixel region so as to contact 15b.

As described above, a polysilicon thin film transistor array substrate is completed, and when the color filter array substrate including the color filter layer is bonded to the thin film transistor array substrate and a liquid crystal layer is formed between the two substrates, the liquid crystal display device becomes a liquid crystal display device.

As shown in FIG. 9, the device manufactured as described above may improve values of mobility and sub-threshold voltage according to the hydrogenation time. Specifically, when the gate voltage Vg was 10 V, the value of the drain current Id in the case of 15 minutes was higher in the curve graph than in the case of 5 minutes of the hydrogenation treatment. The linear graph is the result of calculating the result of the drain current by the square root, and the slope in the case of 15 minutes was larger than that in the case of five minutes of hydrogenation treatment. At this time, since the slope is inversely proportional to the S-factor representing the sub-threshold voltage, it can be seen that the sub-threshold voltage increases when the hydrogenation is performed for 15 minutes.

These results indicate that the effects of hydrogen diffusion, crystallization, and defect passivation increased with the hydrogenation time, which can be judged as improvement of device performance.

Meanwhile, through FIGS. 10A to 10C, after forming a plurality of unit layers under an amorphous silicon deposition condition, a hydrogenated device (the present invention) and a growth seed layer are formed, and thick amorphous silicon is deposited thereon, followed by hydrogenation. The performance difference of the device (prior art) can be examined, and the performance improvement of the device manufactured by the present invention can be confirmed.

Specifically, Figure 10a shows the value of Ion according to the hydrogenation time, it can be seen that the Ion value in the present invention using an amorphous silicon layer consisting of a plurality of unit layers than in the prior art using the seed layer. Here, Ion represents the drain current Id when the gate voltage is 20V.

In addition, Figure 10b shows the value of Ioff according to the hydrogenation time, there is no problem in the application of the device if Ioff is less than 1.E- ¹¹ , the prior art using a seed layer, as well as consisting of a plurality of unit layers It can be seen that the Ioff value in the present invention using an amorphous silicon layer is also less than 1.E- ¹¹ . Here, Ioff represents the drain current Id when the gate voltage is -5V.

Finally, Figure 10c shows the value of μ (mobility) according to the hydrogenation time, μ value in the present invention using an amorphous silicon layer consisting of a plurality of unit layers than in the prior art using the seed layer You can see high.

As such, it can be seen that the crystallization method according to the present invention is superior in electrical characteristics such as mobility and sub-threshold voltage to the crystallization method according to the prior art. This is because hydrogen diffuses and reacts along the porous interface between the unit layers, thereby exhibiting a hydrogen annealing effect more efficiently.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

That is, in the detailed description of the present invention, the embodiment has been described with reference to a liquid crystal display device having a polysilicon thin film transistor. However, the present invention is not limited thereto and may be applied to a semiconductor device, a display device, or the like having a polysilicon thin film transistor.

The polysilicon layer and the crystallization method thereof according to the present invention as described above, and the manufacturing method of the liquid crystal display device using the same have the following effects.

First, in the case of forming a microsilicon layer, when the amorphous silicon is intermittently deposited about 10 to 15 times and then hydrogenated, hydrogen diffused from the surface of the amorphous silicon layer is sufficient for an intermittent surface of porosity at the interface between the amorphous silicon layers. And crystallization seeds with hydrogen, followed by crystallization growth.                     

Therefore, it is possible to overcome the disadvantages of the high defect rate and the low crystallization rate by the conventional single deposition method of micro silicon, and to obtain a high quality micro silicon layer with few defects.

Second, the device having the microsilicon layer formed by the present invention as a semiconductor layer has improved electrical characteristics such as mobility and sub-threshold voltage.

Claims (17)

An amorphous silicon layer formed on the substrate and having a plurality of unit layers and having a porous interface between the unit layers; A crystallized seed formed between the unit layer and the unit layer by reacting hydrogen diffused from the surface of the amorphous silicon layer at the porous interface; And a plurality of crystal grains crystallized about the crystallization seed by hydrogen diffused from the surface of the amorphous silicon layer. The method of claim 1, The interlayer porous interface is polysilicon layer, characterized in that formed by the non-deposition process of the amorphous silicon layer. The method of claim 1, The polysilicon layer, characterized in that the unit layer has a thickness of 10 ~ 20Å. The method of claim 1, The amorphous silicon layer is a polysilicon layer, characterized in that consisting of 10 to 15 unit layers. Repeatedly depositing and depositing amorphous silicon on the substrate a plurality of times to form an amorphous silicon layer composed of a plurality of unit layers; And hydrogenating the amorphous silicon layer to form a crystallization seed between the unit layer and the unit layer and growing the same to crystallize the amorphous silicon into polysilicon. The method of claim 5, Polycrystalline silicon crystallization method characterized in that for depositing the amorphous silicon once, a thickness of 10 ~ 20Å. The method of claim 5, Polycrystalline crystallization method, characterized in that for repeating the deposition and amorphous deposition of amorphous silicon on the substrate 10 to 15 times. The method of claim 5, The deposition of the amorphous silicon polysilicon crystallization method characterized in that the silane gas (SiH ₄ ) and hydrogen gas (H ₂ ) is diluted to a ratio of 1:10 or less, and the deposition RF power is 100 ~ 300W. The method of claim 5, Polysilicon crystallization method characterized in that the RF power is turned off when the amorphous silicon is not deposited. The method of claim 5, The hydrogenation treatment is a polysilicon crystallization method, characterized in that performed for 10 to 40 minutes under RF of 300 ~ 1000W. The method of claim 5, Prior to depositing the amorphous silicon, further comprising forming a buffer layer on the insulating substrate. Forming a gate wiring and a gate electrode on the substrate; Forming a gate insulating film on the entire surface including the gate wiring; Repeatedly depositing and depositing amorphous silicon a plurality of times on the gate insulating film to form an amorphous silicon layer composed of a plurality of unit layers; Hydroprocessing the amorphous silicon to form a crystallization seed between the unit layer and the unit layer and growing it to crystallize the amorphous silicon into polysilicon; Patterning the polysilicon to form a semiconductor layer; Forming a data line crossing the gate line and a source / drain electrode stacked on the semiconductor layer; Forming a protective film on the entire surface including the data line; And forming a pixel electrode penetrating through the passivation layer to be in contact with the drain electrode. The method of claim 12, A method of manufacturing a liquid crystal display device, characterized in that the deposition of the amorphous silicon once, the thickness of 10 ~ 20Å. The method of claim 12, And repeatedly performing deposition and non-deposition of amorphous silicon on the substrate 10 to 15 times. The method of claim 12, The deposition of the amorphous silicon is performed by diluting silane gas (SiH ₄ ) and hydrogen gas (H ₂ ) at a ratio of 1:10 or less, and depositing RF power at 100 to 300 W. . The method of claim 12, The method of manufacturing a liquid crystal display device, characterized in that the RF power is turned off when the amorphous silicon is not deposited. The method of claim 12, The hydrogenation process is a method of manufacturing a liquid crystal display device, characterized in that performed for 10 to 40 minutes under an RF of 300 ~ 1000W.

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