KR20070095043A - The manufacturing method of the display device - Google Patents

Abstract

A method for manufacturing a display device is provided to manufacture a thin film transistor having a multi crystal silicon layer of a large and uniform crystal grain size. A method for manufacturing a display device includes the steps of: forming a gate electrode wiring(111) on a substrate(100); forming an insulation film(120) on an upper part of the gate electrode wiring(111); forming an amorphous silicon layer(130) on an upper part of the insulation film(120); and applying a current on the gate electrode wiring(111), and crystallizing the amorphous silicon layer(130); and forming a current applying unit exposed to the outside by etching a part of the amorphous silicon layer(130) and the insulation film(120). The gate electrode wiring(111) have at least one of Cr, Al, and Mo.

Description

Manufacturing method of display device {THE MANUFACTURING METHOD OF THE DISPLAY DEVICE}

1 is a schematic block diagram of a display device according to an exemplary embodiment.

2 to 10 are cross-sectional views of each method of manufacturing a display device according to an exemplary embodiment.

<Explanation of symbols for main parts of the drawings>

10: pixel portion of display device 20: gate driving circuit portion

30: data driving circuit section 100: substrate

110: metal for the gate electrode 111: gate electrode wiring

112: current applying unit 120: gate insulating film

130: amorphous silicon layer 131: polycrystalline silicon layer

132 impurity doped region 133 channel layer

140: photoresist for impurity doping 150: metal for data electrode 151: data electrode wiring 160: passivation layer

170: pixel electrode

200: laser beam

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a display device, and more particularly, to a method of manufacturing a display device using polycrystalline silicon capable of stably growing crystal grains of polycrystalline silicon on a display element substrate.

In general, a thin film transistor (TFT) is used in a display device such as a liquid crystal display (LCD) or an organic luminescent display device (OLED) having a matrix array. Used as a switching element to apply the desired video signal

The most common thin film transistor used in a display device such as a liquid crystal display (LCD) or an organic light emitting display (OLED) is used as a semiconductor layer made of amorphous silicon. The amorphous silicon thin film transistor has a mobility of about 0.5 to 1 cm 2 / Vsec, and thus may be used as a switching element of a liquid crystal display, but the mobility is small, such as a liquid crystal display (LCD) or an organic light emitting diode display ( It is not suitable for forming a drive circuit of a display device such as an OLED) on a substrate. For this reason, instead of forming a driving circuit on a substrate, a separate driving IC (Intergrated Chip) must be attached to a display device using amorphous silicon, which can not simplify the process, resulting in lower productivity and higher product cost. have.

In order to solve the above problems, a display device using a polycrystalline silicon thin film transistor using polycrystalline silicon having an electron mobility of about 20 to 150 cm 2 / Vsec as a semiconductor layer as a switching element and a driving circuit has been developed.

Currently, a method of crystallizing a polycrystalline silicon thin film on a glass substrate having a low melting point is largely a technique of crystallizing by irradiating an amorphous silicon layer with a laser, and depositing a metal element that promotes crystallization on the amorphous silicon layer, and then applying polycrystalline to heat. There is a technique of forming a silicon thin film.

In order to ensure sufficient growth of grains and uniformity of grains, which are important for improving the properties of polycrystalline silicon thin film transistors, the cooling rate becomes an important process element until the amorphous silicon layer is melted, cooled, and then recrystallized to form polycrystalline silicon. . In other words, if the molten silicon layer is cooled too quickly, a large number of crystal nuclei are generated, resulting in a problem of small grain size.

In particular, this problem occurs in a thin film transistor device having a bottom gate structure in which the gate electrode is located under the semiconductor layer, and the heat required for melting and recrystallization of the amorphous silicon layer is required to remove the gate electrode wiring under the silicon layer. Because it is lost through.

For this reason, the bottom gate polycrystalline thin film transistor has a smaller grain size than the top gate polycrystalline thin film transistor, and thus does not have sufficient electron mobility to directly mount the driving circuit onto the substrate. there is a problem.

Accordingly, an aspect of the present invention provides a method of manufacturing a display device using a thin film transistor including a polycrystalline silicon layer having a large crystal grain size and excellent uniformity.

According to an aspect of the present invention, a method of manufacturing a display device includes forming a gate electrode wiring on a substrate, forming an insulating film on the gate electrode wiring, and amorphous silicon on the insulating film. Forming a layer and crystallizing the amorphous silicon layer while flowing a current through the gate electrode wiring.

The gate electrode wirings may include at least one of Cr, Al, and Mo.

After forming the amorphous silicon layer, etching the amorphous silicon layer and a portion of the insulating layer to form a current applying unit exposed to the outside.

In this case, the current applying unit is connected to the gate electrode wiring connected in parallel with each other.

The process of crystallizing the amorphous silicon layer is characterized by using a pulsed laser having an energy density capable of completely melting the amorphous silicon layer.

Alternatively, the process of crystallizing the amorphous silicon layer is characterized in that the use of heat. In this case, the amorphous silicon layer includes a metal element for promoting crystallization.

The method may further include separating the gate electrode wirings connected in parallel after crystallizing the amorphous silicon layer using a laser or heat. In this case, the gate electrode wirings may be separated from each other using a laser.

In another embodiment, a method of manufacturing a display device includes forming a gate electrode wiring on a substrate, forming an insulating film on the gate electrode wiring, and forming an amorphous silicon layer on the insulating film. And etching a portion of the amorphous silicon layer and the insulating layer to form a current applying unit exposed to the outside, and crystallizing the amorphous silicon layer while flowing a current through the gate electrode wiring.

In this case, unlike the current applying unit according to an embodiment of the present invention, the current applying unit is connected to a plurality of gate electrode wires electrically separated from each other.

The process of crystallizing the amorphous silicon layer is the same as the embodiment of the present invention using an energy density and pulsed laser capable of completely melting the amorphous silicon layer or the process of crystallizing the amorphous silicon layer is heat It is characterized by using. In this case, the amorphous silicon layer includes a metal element for promoting crystallization.

Specific details of other embodiments are included in the detailed description and drawings.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments described below, but can be implemented in various forms, and only the embodiments of the present invention to complete the disclosure of the present invention, the general knowledge in the art to which the present invention belongs It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular forms also include the plural unless specifically stated otherwise in the phrases. As used herein, “comprise” and / or “comprising” refers to one or more other components, steps, operations, and / or elements of the mentioned components, steps, operations, and / or elements. It does not exclude existence or addition. Also referred to herein as “top”, “top”, “top” or “bottom”, “bottom” of a layer or film includes intervening another layer or film. In addition, as used herein, "overlapping" indicates a shape in which the lower structure and the upper structure have a common center and overlap each other, and includes a case where another structure is interposed between the lower structure and the upper structure, and the upper structure and the lower structure. Any one of the structures is meant to completely overlap the other structure. Hereinafter, a thin film transistor and a manufacturing method according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 10.

Referring to FIG. 1, a display device according to an exemplary embodiment will be described. 1 is a schematic block diagram of a display device according to an exemplary embodiment. As illustrated in FIG. 1, the image display panel includes a pixel unit 10, a gate driver 20, and a data driver 30.

The pixel portion 10 includes a plurality of pixels connected to the plurality of gate electrode wirings G1 to Gn and the plurality of data electrode wirings D1 to Dn, and each pixel includes a plurality of gate electrode wirings G1 to Gn. ) And a switching element M connected to the plurality of data electrode wires D1 to Dn, and a liquid crystal capacitor Clc or a storage capacitor Cst connected thereto.

The plurality of gate electrode wirings G1 to Gn formed in the row direction transmit a scan signal to the switching element M, and the plurality of data electrode wirings D1 to Dn formed in the column direction are the switching element M. To the gray level voltage corresponding to the image signal. The switching element M is a three terminal element, the control terminal is connected to the gate electrode wirings G1 to Gn, the input terminal is connected to the data electrode wirings D1 to Dn, and the output terminal is the liquid crystal capacitor Clc. ) Or one terminal of the storage capacitor (Cst). The liquid crystal capacitor Clc is connected between the output terminal of the switching element M and the common electrode, and the storage capacitor Cst is connected between the output terminal of the switching element M and the common electrode (independent wiring) or a switching element. It can be connected (shear gate method) between the output terminal of M and the gate electrode wirings G1 to Gn directly above.

The gate driver 20 is connected to the plurality of gate electrode wires G1 to Gn to provide a scan signal for activating the switching element M to the plurality of gate electrode wires G1 to Gn, and the data driver 30 The gray voltage corresponding to the image signal is transmitted to the switching element M by being connected to the plurality of data electrode wires D1 to Dn.

In this case, a MOS transistor is used as the switching element M. The MOS transistor may be implemented as a thin film transistor having polycrystalline silicon as a channel region. In addition, the gate driver 20 and the data driver 30 may also be configured as MOS transistors. The MOS transistors may be implemented as thin film transistors having polycrystalline silicon as a channel region.

The image display panel illustrated in FIG. 1 may be used as a lower substrate of a liquid crystal display using liquid crystal or an organic light emitting display using an organic light emitting element that emits light. In addition, the switching element M may use polycrystalline silicon according to the manufacturing method provided by the present invention as a semiconductor layer.

Hereinafter, a method of manufacturing a display device according to an exemplary embodiment and another exemplary embodiment will be described in detail with reference to FIGS. 2 to 10.

2 to 5A and 6 to 10 illustrate a method of manufacturing a display device according to an exemplary embodiment.

First, as shown in FIG. 2, the gate electrode metal 110 is deposited on the substrate 100. The gate electrode metal 110 should be made of a material having good adhesion to the substrate 100 and having low resistance, and sputtering a metal for the gate electrode including at least one of Cr, Al, and Mo. It can be formed using.

Thereafter, a photoresist (PR) is deposited on the gate electrode metal 110. The photoresist PR is classified into a positive photoresist in which a portion exposed by light is patterned and a negative photoresist in which a portion not exposed by light is patterned.

In the display device according to an exemplary embodiment, a positive photoresist is deposited on the gate electrode metal 110, and the photoresist PR may be formed by light passing through an open mask. ) Is subjected to an exposure step of patterning the desired shape. In addition, a wet etching method using an etching solution capable of etching the gate electrode metal 110 using the patterned photoresist PR, or a dry etching method using plasma is used. As shown in FIGS. 3 and 5A, the gate electrode wiring 111 and the current applying unit 112 are formed.

Both ends of the gate electrode wiring 111 of the display device according to the exemplary embodiment are connected in parallel to each other. In addition, the current applying unit 112 for applying a current to the gate electrode wiring is formed of the same metal as the gate electrode wiring 111 and is connected to the gate electrode wiring 111 connected in parallel. Through this, the same current may be applied to the gate electrode wiring 111 through one current applying unit 112. In addition, the current applying unit 112 should be formed at at least one end of the gate electrode wiring 111. In order to apply a separate scan signal for each gate electrode wiring 111 line, the current applying unit 112 and the parallel connection unit are electrically separated from the gate electrode wiring 111 after crystallization of the amorphous silicon layer 130. This is essential. Therefore, in order to form a wider screen display area, the current applying unit 112 and the parallel connection unit are preferably formed on the non-display area of the screen.

After the gate electrode wiring 111 and the current applying unit 112 are formed, the gate insulating layer 120 and the amorphous silicon layer 130 are deposited as shown in FIG. 4.

The gate insulating layer 120 may form silicon oxide or silicon nitride using chemical vapor deposition (CVD).

Thereafter, as illustrated in FIG. 5A, the gate insulating layer 120 and the amorphous silicon layer 130 are etched to expose the current applying unit 112 to the outside. The gate insulating layer 120 and the amorphous silicon layer 130 may use a dry etching method.

As shown in FIG. 6, the amorphous silicon layer 130 is crystallized by flowing a current through the current applying unit 112 to the gate electrode wiring 111.

When a current flows through the current applying unit 112, a constant resistance heat is generated in the gate electrode wiring 111 as shown in Equation 1 below.

Calories (Q) = 0.24 (cal) * Current (i) ² * Resistance (R) * Time (T)

The resistance heat can be easily adjusted by changing the amount of current applied to heat the gate electrode wiring 111 to a desired temperature.

The gate electrode wiring 111 heated by the resistive heat reduces the amount of heat loss required to crystallize the amorphous silicon layer 130 to secure a cooling rate at which a polycrystalline silicon layer having a sufficient size of grains can be grown.

Crystallization of the amorphous silicon layer 130 is largely performed by the method using the laser beam 200 and depositing a metal element that promotes crystallization on the entire surface or part of the amorphous silicon layer 130 and then applying a single amount of heat to crystallize it. There is a way.

The crystallization method using the electron laser beam 200 is crystallized into a polycrystalline silicon layer through melting and resolidification of some or all regions of the amorphous silicon layer 130. The laser beam 200 uses a pulse-type laser that oscillates according to a predetermined frequency, and mainly uses fluoro krypton (KrF), fluoro xenon (XeF), and xenon chloride (XeCl) as laser sources.

Recently, a method of manufacturing a thin film transistor using a polycrystalline silicon layer having excellent grain size and uniformity using a laser having energy capable of melting all regions of the amorphous silicon layer has been generalized.

Next, a method of crystallizing by applying the latter heat is performed by directly contacting a metal promoting crystallization on the amorphous silicon layer and then applying heat to use the phase shift induced by the metal and the amorphous silicon layer. It is a method of forming a polycrystalline silicon layer. Nickel (Ni) is generally used as a metal for promoting the crystallization.

After crystallizing the amorphous silicon layer 130 to phase change to the polycrystalline silicon layer 131, as shown in FIG. 7, the current applying unit 112 and the gate electrode wiring 111 connected in parallel are electrically disconnected. I need to make it work. If the gate electrode wirings 111 are not disconnected from each other, the scan signal for turning on the thin film transistor for each gate electrode wiring cannot be applied. The disconnection operation uses a laser, ultrasonic waves, etc. that can generate high energy.

After disconnection of the gate electrode wiring 111, dopant ions are doped into portions of the polycrystalline silicon layer 131 to be the source / drain regions 132 as shown in FIG. 8.

First, an impurity doping photoresist 140 is formed on the polycrystalline silicon layer 131, and then an impurity doping photoresist having an opening corresponding to the source / drain region 132 forming portion of the polycrystalline silicon layer 131 is formed. 140 is formed.

The impurity doped region 132 is then formed by doping impurity ions into the source / drain region 132 through the opening. In this case, the thin film transistor TFT is classified into an N-type thin film transistor in which electrons are majority carriers and a P-type thin film transistor in which holes are majority carriers. The N-type thin film transistor is a source of the polycrystalline silicon layer of any one of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) or bismuth (Bi) corresponding to Group 5 on the periodic table Doping to / drain region 132. In contrast, the P-type thin film transistor includes one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Ta) corresponding to Group 3 on the periodic table of the polycrystalline silicon. Dop into the source / drain regions 132 of the layer. The impurity doping may be performed by an ion shower method and an ion implantation method.

Thereafter, after removing the impurity doping photoresist 140, the upper portion of the polycrystalline silicon layer 131 including the source / drain region 132 and the channel layer 133 formed by the impurity doping, as shown in FIG. 9. The metal 150 for the data electrode is deposited on.

After depositing a positive photoresist (Positive PR) on the metal 150 for the data electrode, the photo over the TFT channel formation region using a slit mask or two-tone mask The photoresist PR is patterned so that the height of the resist PR is lower than the height of the photoresist PR on the region where the data electrode wiring 151 is formed.

Subsequently, the polycrystalline silicon layer 131 and the data electrode metal 150 are simultaneously etched using the photoresist PR to etch the data electrode wiring (not shown), the source / drain electrode 151 and the thin film transistor. A polycrystalline silicon layer pattern including the channel layer 133 is formed. In this case, both end portions of the polycrystalline silicon layer pattern including the channel layer 133 and both end portions of the source / drain electrode 151 may have cross sections that coincide with each other.

After performing an etch back process of removing the photoresist pattern on the channel layer 133, an etching process of removing the metal for the data electrode remaining on the channel layer 133 is performed. The thin film transistor TFT is formed.

Alternatively, the polycrystalline silicon 131 and the source / drain region 151 may be formed of different masks. First, a source / drain region 151 is formed in the polycrystalline silicon layer 131, and then the polycrystalline silicon layer 131 is patterned into a desired shape. Thereafter, the metal 150 for the data electrode is deposited on the patterned polycrystalline silicon layer 131. Thereafter, the photoresist PR is applied on the data electrode metal 150, and then the source / drain electrodes 151 are formed using the opened mask.

After the patterning of the polycrystalline silicon layer 131 including the source / drain region 132 and the channel layer 133 and the source / drain electrode 151 are formed, a passivation layer (or a passivation layer) is formed on the TFT. 160 is deposited by chemical vapor deposition (CVD). The passivation layer 160 may be formed of silicon nitride (SiNx). A contact hole is formed to expose a portion of the source / drain electrode 151 to the outside.

Thereafter, a pixel electrode 170 is formed on the passivation layer 160 and electrically connected to the source / drain electrode 151 through the contact hole. The pixel electrode 170 may be formed of indium tin oxide (ITO) or indium zinc oxide (IZO).

After the lower substrate including the thin film transistor TFT formed by the above-described manufacturing method is bonded to the lower substrate, the upper substrate including the color filter and the common electrode corresponding to the pixel electrode 170 is bonded to the lower substrate. The liquid crystal display device may further include a process of interposing a liquid crystal between the upper substrate and the lower substrate.

The method may further include depositing an organic light emitting material that emits itself when an external current is applied to an upper portion of a lower substrate including the thin film transistor (TFT) formed by the above-described manufacturing method. It can be used in the manufacturing process.

Hereinafter, a method of manufacturing a display device according to another exemplary embodiment of the present disclosure will be described. A display device according to another exemplary embodiment of the present invention is manufactured by the manufacturing method illustrated in FIGS. 2 to 4, 5b, and 6 to 10.

First, as shown in FIGS. 2 to 4, the gate electrode wiring 111 is formed on the substrate 100 in the same manner as the method of manufacturing the display device according to the exemplary embodiment.

In the gate electrode wiring 111 according to another embodiment of the present invention, each gate electrode wiring 111 is formed to be electrically separated from each other, as shown in FIG. 5B, and the current applying unit 112 is electrically connected to each other. It is formed by being connected to the separated gate electrode wiring 111.

The gate electrode wiring 111 and the current applying unit 112 according to another embodiment of the present invention are electrically separated from each other, so that the current can be applied to each gate electrode wiring 111 and the current applying unit 112. A current applying device should be used. In addition, the current applying unit 112 is formed at at least one end of the gate electrode wiring 111 in the same manner as the current applying unit according to an embodiment of the present invention, and the current is applied to widen the screen display area. The unit 112 is preferably formed on the non-display area of the screen.

After the gate insulating layer 120 and the amorphous silicon layer 130 are formed on the gate electrode wiring 111, the gate insulating layer 120 is exposed so that the current applying unit 112 is exposed to the outside as shown in FIG. 5B. And the amorphous silicon layer 130 is etched.

Thereafter, as shown in FIG. 6, the amorphous silicon layer 130 is crystallized by flowing a current through the current applying unit 112 to the gate electrode wiring 111. The crystallization method is based on the method of irradiating the laser to the amorphous silicon layer 130 or the method of applying heat to the amorphous silicon layer containing a metal to promote crystallization in the same manner as the manufacturing method of the display device according to an embodiment of the present invention. .

After the crystallization process, as shown in FIG. 7, a process of electrically disconnecting the gate electrode wiring 111 and the current applying unit 112 is performed.

Thereafter, as shown in FIG. 8, the polycrystalline silicon layer 131 is doped with impurities according to a desired carrier type to form a source / drain region 132. After depositing the metal 150 for the data electrode on the polycrystalline silicon layer 131 including the source / drain region 132 doped with impurities and the channel region 133 not doped with impurities, the polycrystalline silicon is deposited. The layer 131 and the data electrode metal 150 are patterned with the same mask to form a thin film transistor TFT. Alternatively, the polycrystalline silicon layer 131 and the source / drain electrode 151 including the source / drain region 132 and the channel layer 133 may be formed using different masks in the same manner as in the exemplary embodiment of the present invention. have. Thereafter, the passivation layer 160 and the pixel electrode 170 electrically connected to any one of the source / drain electrodes 151 are formed.

The lower substrate including the thin film transistor according to another embodiment of the present invention described above is one side of the display device such as a liquid crystal display (LCD) or an organic light emitting display (OLED), as in the embodiment of the present invention. Can be used.

As described above, the thin film transistor including the polycrystalline silicon layer having a large crystal grain size and good uniformity may be manufactured by the method of manufacturing the display device according to the exemplary embodiments and the other embodiments.

Claims (15)

Forming a gate electrode wiring on the substrate; Forming an insulating film on the gate electrode wiring; Forming an amorphous silicon layer on the insulating film; And A method of manufacturing a display device, wherein the amorphous silicon layer is crystallized while a current flows through the gate electrode wiring. The method of claim 1, And the gate electrode wirings include at least one of Cr, Al, and Mo. The method of claim 1, After forming the amorphous silicon layer And etching a portion of the amorphous silicon layer and the insulating layer to form a current applying unit exposed to the outside. The method of claim 3, wherein And the current applying unit is connected to the gate electrode wires connected in parallel to each other. The method of claim 4, wherein And crystallizing the amorphous silicon layer using a laser. The method of claim 5, And the laser has an energy density capable of completely melting the amorphous silicon layer and is pulsed. The method of claim 4, wherein And crystallizing the amorphous silicon layer using heat. The method of claim 7, wherein The crystallized silicon layer further comprises a metal element for promoting crystallization. The method of claim 6 or 8, After crystallizing the amorphous silicon layer And separating the gate electrode wires connected in parallel to each other. The method of claim 9, The method of manufacturing a display device, wherein the gate electrode wirings are separated from each other using a laser. The method of claim 3, wherein And the current applying unit is connected to a plurality of gate electrode wires electrically separated from each other. The method of claim 11, And crystallizing the amorphous silicon layer using a laser. The method of claim 12, And the laser has an energy density capable of completely melting the amorphous silicon layer and is pulsed. The method of claim 11, And crystallizing the amorphous silicon layer using heat. The method of claim 14, The crystallized silicon layer further comprises a metal element for promoting crystallization.

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