KR101338104B1 - Method of fabricating tft array substrate - Google Patents

Abstract

The present invention discloses a method for manufacturing a thin film transistor array substrate. The disclosed method of the present invention forms a silicon layer having grain and grain boundaries on an insulating substrate, and forms a mask having at least one or more slit patterns of equal spacing and grain size on a substrate having the silicon layer, The silicon layer is etched using a mask to form an active pattern, and the mask is etched to expose the grain boundary of the active pattern on the remaining mask surface, and the grain boundary of the active pattern is etched and planarized. Removing the remaining mask. According to the above configuration, the present invention has the advantage of improving the uniformity of the panel as well as the operating characteristics of the thin film transistor.

Description

Thin film transistor array substrate manufacturing method {METHOD OF FABRICATING TFT ARRAY SUBSTRATE}

1 is a plan view showing a typical thin film transistor array substrate.

FIG. 2A to FIG. 2D are cross-sectional views of processes according to the cutting line taken along the line II ′ of FIG. 1.

3 is a plan view showing a thin film transistor array substrate according to the present invention;

4A to 4E are cross-sectional views of processes according to the cutting line taken along the line II-II ′ of FIG. 2.

5 is a plan view of the mask of FIG. 4B.

The present invention relates to a method of manufacturing a thin film transistor array substrate, and more particularly, to a method of manufacturing a thin film transistor array substrate having an active pattern formed of polysilicon.

Recently, with the rapid development of the information society, there is a need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption, among which a liquid crystal display has a resolution, It is excellent in color display and image quality, and is actively applied to notebooks and desktop monitors.

The liquid crystal display device includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal layer interposed between the color filter substrate and the array substrate. The liquid crystal display having such a configuration displays an image by driving a liquid crystal layer having optical anisotropy by an electric field generated by applying a voltage to the common electrode and the pixel electrode.

1 is a plan view illustrating a general thin film transistor array substrate.

As shown in FIG. 1, a gate wiring 120 and a data wiring 130 are arranged to be orthogonal to each other in the array substrate 100 for a liquid crystal display device, and a pixel is formed between the gate wiring 120 and the data wiring 130. The area P is defined. The thin film transistor T is positioned at the intersection of the gate line 120 and the data line 130. At one end of each of the gate and data lines 120 and 130, a gate pad G and a data pad D for transmitting an electrical signal to the gate and data lines 120 and 130 are positioned. The gate pad G transmits a scan signal to the gate line 120, and the data pad G transmits an image signal to the data line 130.

The thin film transistor T is connected to the gate line 120 to receive a scanning signal and receives a scanning signal, and a source electrode connected to the data line 130 to receive a video signal. 132 and the drain electrode 134 spaced apart from the source electrode 132 by a predetermined interval. An active pattern 127 is positioned between the gate electrode 122 and the source and drain electrodes 132 and 134.

A pixel electrode 136 connected to the drain electrode 134 is formed in the pixel region P through the contact hole 147, and the pixel electrode 136 is a neighboring gate wiring to which a previous scan signal is transmitted. Extending toward 120.

The array substrate 100 for a liquid crystal display device as described above is formed by a thin film deposition and patterning process. For example, in order to form the active pattern 127, first, a silicon layer is deposited, and the active layer is formed by patterning the silicon layer using a predetermined mask.

In the array substrate 100 for the liquid crystal display device, the active pattern 127 may be formed to have various line widths according to a necessary use in other parts besides the thin film transistor. The active pattern 127 may serve as a conductive channel through which electrons flow. The active pattern 127 may be cadmium cerenide (CdSe), hydrogenated amorphous silicon (a-Si: H), poly crystalline silicon (poly-Si), or the like. When the amorphous silicon is used as the active pattern, the amorphous silicon may be conveniently manufactured in a low temperature treatment system having a maximum deposition temperature of about 350 ° C. In practice, however, low electron mobility (<2 cm2 / Vsec) in amorphous silicon acts as a barrier to switching characteristics of thin film transistors, and also drives circuitry and thin films that control thin film transistors at high speed. Makes the integration of transistors difficult. On the other hand, when the polysilicon is used as the active pattern, the polysilicon thin film transistor is suitable for an active matrix liquid crystal display because it has a response speed several times faster than amorphous silicon as a switching element. In addition, the polysilicon thin film transistor has an advantage of having a high field effect mobility of about 20 to 550 cm 2 / Vsec, as compared to the amorphous-thin film transistor which is widely used. Here, the field effect mobility determines the switching speed of the thin film transistor, and polysilicon is several times faster than amorphous silicon. This difference is due to the fact that polysilicon is composed of several grains and has fewer defects than amorphous silicon. Accordingly, the polysilicon is expected to be a device capable of integrating a driving circuit as well as switching for a next generation liquid crystal display device having a large area screen.

Crystallization of such polysilicon includes a solid phase crystallization (SPC) method, a metal induced crystallization (MIC) method, an excimer laser annealing method, and the like. Among these, the SPC method is a solid phase crystal method, which crystallizes amorphous silicon at a high temperature (600 degrees). In this method, since crystallization takes place in the solid phase, there are many defects in the grains, resulting in poor crystallinity. Polysilicon crystallized through the above method can obtain good grains as the liquid silicon is cooled from the silicon seed at the initial stage of crystallization, and the silicon crystal growth is lateral growth. Large grains can be obtained.

In general, if the silicon seed spacing is larger than the maximum growth distance of silicon grain, the silicon crystal that grows laterally around the silicon seed is grown to the maximum and then nucleated by super-cooling in the remaining liquid phase. This happens and small grains are formed. However, if the seed spacing is less than the maximum growth distance, lateral growth occurs around the seed, and each grain forms grain boundaries, forming a large grain of poly-silicon (poly-Si) thin film. As described above, the crystal grains must be uniformly arranged while forming a boundary of large silicon on the substrate to obtain a thin film transistor (TFT) device having excellent performance. Thus, the silicon seed distribution is less than the maximum crystal growth distance, but should be arranged uniformly at the largest possible spacing.

2A through 2D are cross-sectional views illustrating a cutting plane taken along line II of FIG. 1, and illustrate a method of manufacturing a thin film transistor array substrate according to the related art, in which the crystallized silicon layer is applied as an active pattern.

As shown in FIG. 2A, the gate electrode 122 is formed on the array substrate 100. The array substrate 100 may be an insulating substrate and may be a transparent substrate such as glass.

As shown in FIG. 2B, the gate insulating layer 124 and the silicon layer 126 are sequentially formed on the substrate having the gate electrode 122. The silicon layer 126 may be a crystallized silicon layer, such as the SPC method described above. When the silicon layer is formed to have a thickness of 500 ns, the grain boundary may have a height of 500 ns from the surface. That is, since the silicon layer 126 includes a plurality of grains in the film and grain boundaries formed around the grains, the surface may be rough. In particular, the surface roughness of the silicon layer 126 may be deteriorated at the grain boundary portion. A predetermined mask 150 is formed on the substrate having the silicon layer 126. The mask 150 may be a photoresist pattern.

As shown in FIG. 2C, the silicon layer is etched using the mask 150 to form the active pattern 127.

As shown in FIG. 2D, the mask is removed. Next, source / drain electrodes 132 and 134 are formed on the substrate having the active pattern 127. The passivation layer 146 is formed on the substrate having the source / drain electrodes 132 and 134. The protective layer is etched to form a contact hole 147 exposing the drain electrode 134. A transparent conductive film is formed on the substrate having the contact hole 147. The transparent conductive layer is etched to form a pixel electrode 136 electrically connected to the drain electrode 134 through the contact arc 147.

In general, what influences the operating characteristics of the switching element is related to the mobility of the active pattern constituting the switching element. In other words, if the mobility of the active pattern is fast, the operation characteristic of the switching element is good, whereas if the mobility of the active pattern is slow, the operation characteristic of the switching element is poor.

However, in this prior art, polysilicon crystallized by the SLS method has an advantage that it can be formed by increasing the width of the grain, while there are many defects on the surface during the crystallization process. The defect is formed by melting the amorphous silicon and then blocking the laser beam, and the heat present in the silicon is released through the array substrate, which is an insulating substrate. As such, silicon starts to crystallize by the cooling process, and in particular, crystals close to the surface are abnormally grown by sudden cooling. Polysilicon having such a surface state is subjected to a process of laminating a protective film later. At this time, by depositing a protective film on the polysilicon active pattern having a plurality of defects, a trap level for electrons is generated by mismatches occurring at the interface between the active pattern and the protective film. For this reason, the mobility of electrons flowing through the surface of the polysilicon active pattern is remarkably lowered, and there are many limitations on the operation characteristics of the device.

The switching speed of the thin film transistor including the polysilicon active pattern crystallized by the SLS method is about twice as fast as that of a general polysilicon thin film transistor, but it is necessary to further improve the speed.

Accordingly, an object of the present invention is to provide a method for manufacturing a thin film transistor array substrate which can improve the operating characteristics of the thin film transistor by removing the grain boundary of the silicon layer to obtain an active pattern having a flat surface.

In order to achieve the above object, the present invention provides a method for manufacturing a thin film transistor array substrate. The method includes forming a silicon layer having grain and grain boundaries on an insulating substrate, forming a mask having at least one slit pattern at the same spacing as the grain size on the substrate having the silicon layer, and using the mask. Etching the silicon layer to form an active pattern, and etching the mask to expose the grain boundary of the active pattern on the remaining mask surface, and to planarize by etching the grain boundary of the active pattern. Removing the mask.

The silicon layer is preferably formed by a solid phase crystallization process.

It is preferable that the said silicon layer is a polycrystalline silicon layer.

The slit pattern of the mask is preferably patterned in the same form as the grain boundary.

Patterning the silicon layer preferably proceeds to a dry etching process.

The planarization of the surface of the active pattern is preferably performed by a dry etching process.

After removing the remaining mask, a source / drain electrode is formed on the substrate from which the mask is removed, a protective film is formed on a substrate having the source / drain electrode, and the protective film is etched to expose the drain electrode. The method may further include forming a contact hole and covering the contact hole on the passivation layer to form a pixel electrode electrically connected to the drain electrode.

(Example)

Hereinafter, a method of manufacturing a thin film transistor array substrate according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view illustrating a thin film transistor array substrate according to the present invention.

As shown in FIG. 3, the gate wiring 220 and the data wiring 230 are arranged orthogonal to the array substrate 200 for the liquid crystal display device. The pixel region P is defined between the gate line 220 and the data line 230. The thin film transistor T1 is positioned at the intersection of the gate line 220 and the data line 230. The gate pad G1 and the data pad D1 are positioned at one end of each of the gate wiring 220 and the data wiring 220 and 230. The gate pad G1 and the data pad D1 serve to transfer electrical signals to the gate and data lines 220 and 230.

The thin film transistor T1 is connected to the gate line 220 to receive a scanning signal and receives a scanning signal, and a source electrode connected to the data line 230 to receive a video signal. 232 and the drain electrode 234 spaced apart from the source electrode 232 by a predetermined interval are arranged, respectively. An active pattern 227 is interposed between the gate electrode 222 and the source and drain electrodes 232 and 234.

The pixel electrode 236 is connected to the drain electrode 234 through the contact hole 247. The pixel electrode 236 extends toward the neighboring gate line 220 to which the previous scan signal is transmitted.

4A through 4E are cross-sectional views illustrating a cutting plane taken along line II-II ′ of FIG. 2. Referring to FIGS. 4A through 4E, a method of manufacturing a thin film transistor array substrate of a liquid crystal display device having the above configuration will be described. do.

As shown in FIG. 4A, the gate electrode 222 is formed on the array substrate 200. The array substrate 200 may be a transparent insulating substrate such as glass. The gate electrode metal film may be one or more selected from a group of conductive metals including aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), and the like. The gate electrode metal film may be formed by a sputtering method.

As shown in FIG. 4B, the gate insulating layer 224 and the silicon layer 226 are sequentially formed on the substrate having the gate electrode 222. The gate insulating layer 224 may be a silicon oxide layer. The silicon layer 226 may be a crystallized silicon layer such as the SPC method described above. Since the silicon layer 126 includes a plurality of grains G and grain boundaries D formed around the grains G, the surface may be rough. For example, when the silicon layer is formed to have a thickness of 500 ns, the grain boundary may have a height of 500 ns from the surface. Thus, the surface roughness of the silicon layer 226 may be poor at the grain boundary (D). A predetermined mask 250 is formed on the substrate having the silicon layer 226. The mask 250 may be a photoresist pattern. As illustrated in FIG. 5, the mask 250 may be patterned to have slit patterns S at the same interval as the grain G size. The mask 250 may be obtained by applying a slit mask to expose the focus to zero. The slit patterns S have the same shape as the grain boundary D and may be patterned in a wave shape. Thus, the mask 250 may have the same surface roughness as the silicon layer 226. In FIG. 5, reference numeral A denotes an interval between the slit patterns S. Referring to FIG.

As shown in FIG. 4C, the silicon layer is first etched using the mask to form an active pattern 227. The first etching process may be a dry etching process. Then, the mask is ashed. As a result, the grain boundaries D of the active pattern are exposed from the surface of the mask 251 remaining after the ashing. Hereinafter, a mask remaining after ashing will be referred to as a mask pattern 251 to distinguish it from the mask.

As shown in FIG. 4D, the active pattern surface is planarized. That is, the grain boundaries are removed by second etching the active pattern 227 exposed from the surface of the mask pattern 251.

As shown in FIG. 4E, the mask pattern is removed. Subsequently, a source electrode 232 and a drain electrode 234 spaced apart from the source electrode 232 are formed on the substrate resultant. As the metal film for forming the source electrode 232 and the drain electrode 234, a material having a different etching selectivity from that of the gate electrode metal film may be used. The metal film for forming the source electrode 232 and the drain electrode 234 may be one or more selected from the group of conductive metals including molybdenum (Mo) or molybdenum alloy. The metal film for forming the source electrode 232 and the drain electrode 234 may be formed by vapor deposition or sputtering. Next, a passivation layer 246 is formed on the substrate having the source electrode 232 and the drain electrode 234. As the passivation layer 246, a transparent organic insulating material or an insulating material may be used. The passivation layer 246 is patterned to form a contact hole 247 exposing the drain electrode 234. A transparent conductive film is formed on the substrate having the contact hole 247. The transparent conductive layer is patterned to form a pixel electrode 236 electrically connected to the drain electrode 234 through the contact hole 247.

In the present invention, by removing the grain boundary to planarize the surface of the active pattern, it is possible to prevent the generation of electron trap levels due to mismatches occurring at the interface between the active pattern and the protective film formed in a subsequent step. Therefore, it is possible to prevent the mobility of electrons flowing through the surface of the polysilicon active pattern to improve the operation characteristics of the device.

Meanwhile, in the present invention, the bottom gate structure has been described as an example, but the present invention is not limited thereto and may be applied to the top gate structure. The top gate structure, unlike the bottom gate structure, has a gate electrode disposed thereon. In order to form the top gate structure, a buffer insulating film is first formed on a substrate, and then an active layer is formed by depositing and crystallizing a silicon layer thereon. Subsequently, a gate insulating film and a gate electrode are formed in sequence.

According to the present invention, an active pattern having a flat surface can be obtained by removing the grain boundary of the silicon layer. As a result, not only the operation characteristics of the thin film transistor but also the uniformity of the panel can be improved.

Claims (7)

Forming a silicon layer having grain and grain boundaries on the insulating substrate through crystallization; Forming a photoresist film on the silicon layer and applying a slit mask to expose the focus to zero to form a photoresist pattern having a wavy surface with a shape corresponding to the grains and grain boundaries; Etching the silicon layer using the photoresist pattern as a mask to form an active pattern; Ashing the photoresist pattern until the grain boundaries are exposed so that the photoresist pattern remains on the grain; Planarizing the active pattern by etching the grain boundaries exposed between the remaining photoresist patterns; And Removing the remaining photoresist pattern remaining on the active pattern Thin film transistor array substrate manufacturing method comprising a. The method of claim 1, wherein the silicon layer is formed by a solid crystallization process. The method of claim 1, wherein the silicon layer is a polycrystalline silicon layer. The method of claim 1, wherein the photoresist pattern is patterned in the same form as the grain boundary. The method of claim 1, wherein the patterning of the silicon layer is performed by a dry etching process. The method of claim 1, wherein the planarization of the active pattern is performed by a dry etching process. The method of claim 1, wherein after the removing of the photoresist pattern, Forming a source / drain electrode on the substrate from which the photoresist pattern is removed; Forming a protective film on the substrate having the source / drain electrodes, Etching the passivation layer to form a contact hole exposing the drain electrode, And forming a pixel electrode electrically covering the contact hole on the passivation layer, the pixel electrode electrically connected to the drain electrode.

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