KR100595315B1 - method for crystalling amorphous layer and method for forming TFT using it - Google Patents

Abstract

The present invention relates to a crystallization method of amorphous silicon having coarse grains and a method of forming a thin film transistor using the same by raising the temperature by the electrical resistance heating method during the laser crystallization and proceeding crystallization of the amorphous silicon at a high temperature. Forming an amorphous silicon layer on the substrate, heating the amorphous silicon layer to a predetermined temperature by an electrical resistance heating method, and crystallizing the amorphous silicon layer heated to the predetermined temperature by irradiating a laser. It features.

Amorphous silicon, polycrystalline silicon, excimer laser, electric resistance heating method

Description

Crystallization method of amorphous silicon and method of forming thin film transistor using same {method for crystalling amorphous layer and method for forming TFT using it}

1 is a plan view showing a general liquid crystal display device

2A to 2D are cross-sectional views showing a conventional method for crystallizing amorphous silicon.

3A to 3D are cross-sectional views illustrating a method of crystallizing amorphous silicon according to the present invention.

4A to 4E are cross-sectional views illustrating a method of forming a thin film transistor according to a first embodiment of the present invention.

5A through 5D are cross-sectional views illustrating a method of forming a thin film transistor according to a second embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

31: insulating substrate 32: buffer layer

33 amorphous silicon layer 34 electrode

35 polycrystalline silicon layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method of crystallizing amorphous silicon suitable for improving the characteristics and reliability of a device, and a method of forming a thin film transistor using the same.

In general, a thin film transistor is composed of a multilayer and divided into a semiconductor layer, an insulating layer, a protective layer, and an electrode layer.

Each element of the thin film transistor will be described in more detail as follows.

First, amorphous silicon, polysilicon, or the like is used as the semiconductor layer.

In addition, a silicon nitride film (SiN _X ), a silicon oxide film (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), tantalum oxide (TaO _X ), or the like may be used as the insulating layer.

In addition, a transparent organic insulating material or an insulating material is used as the passivation layer.

In addition, a metal conductive material such as aluminum (Al), chromium (Cr), molybdenum (Mo) is generally used as the electrode layer.

The materials according to each of these elements are deposited using a deposition apparatus, i.e., a sputtering apparatus, a chemical vapor deposition (CVD) apparatus, and then lithography. Each element is formed.

The semiconductor layer of each component layer configured as described above serves as a conducting channel through which electrons flow, and the electrode layer is composed of a source electrode, a drain electrode, and a gate electrode, wherein the source electrode is a means for applying a signal voltage to the semiconductor layer. do.

In addition, the source electrode serves as a means for emitting a signal voltage to the drain electrode through the semiconductor layer.

The gate electrode serves as a means for switching the flow of current from the source electrode to the drain electrode.

Therefore, the thin film transistor is used as a switching element and is applied as a switching element for an active matrix liquid crystal display device (AMLCD).

The active matrix liquid crystal display device can be successfully constructed by using a thin film transistor in which cadmium serenide (CdSe), hydrogenated amorphous silicon (a-Si: H), and poly-Si are used as semiconductor layers. .

As described above, amorphous silicon of the material used as the semiconductor layer of the thin film transistor is simple to process and can be processed at low temperature, and is already used for manufacturing a large area device such as a solar cell.

In addition, the manufacturing process of the device using the amorphous silicon is convenient because the maximum temperature can be performed alone in a low temperature processing system of about 350 ℃.

In practice, however, low electron mobility (less than about 2 cm 2 / Vsec) in amorphous silicon acts as a barrier to the operating characteristics of switching of thin film transistors, and also drives circuitry to control thin film transistors at high speed. ) And thin film transistors are difficult to integrate.

On the other hand, a thin film transistor using polysilicon as a semiconductor layer is suitable for an active matrix liquid crystal display device.

The polysilicon thin film transistor requires a new processing step, but instead has a response speed several times faster than that of amorphous silicon as a switching element in an active matrix liquid crystal display device.

In addition, the biggest advantage of the poly-silicon thin film transistor is that it has a high field effect mobility of about 20 ~ 550cm2 / Vsec.

Here, the field effect mobility determines the switching speed of the thin film transistor, and polysilicon is several times faster than amorphous silicon.

This difference is due to the fact that polysilicon is composed of several grains and has fewer defects than amorphous silicon.

Therefore, it is expected to be a device capable of integrating a driving circuit as well as a switching device for a next-generation liquid crystal display device having a large area screen by depositing amorphous silicon and crystallizing it to form polysilicon.

Crystallization methods of amorphous silicon for obtaining such polysilicon include SPC method, MIC method, excimer laser annealing method and the like.

The solid phase crystallization (SPC) method is a solid phase crystal method, and is a method of crystallizing amorphous silicon at a high temperature (600 ° C. or more).

In this method, since crystallization takes place in a solid phase, crystal grains are poor due to many defects (micro-twins, dislocations) in the crystal grains. In order to compensate for this, a high temperature (over 1000 ° C) thermal oxide film is used as a gate insulating film. Therefore, there is a disadvantage that must use a high-priced material such as crystals that can withstand more than 1000 ℃.

The metal induced crystallization (MIC) method is a metal induction crystallization method, which is a method of crystallizing a metal by applying heat by depositing a metal on amorphous silicon. At this time, the metal serves to lower the enthalpy of the amorphous silicon to be crystallized.

Therefore, low temperature process treatment of about 500 ° C. is possible, but the surface condition is not good, and the electrical properties are degraded by the metal. In addition, since this method is also solid phase crystallization, there are many defects in the grains.

Polysilicon crystallized by the above-described methods can obtain a good grain (grain) as the liquid silicon is cooled from the silicon seed (Silicon seed) in the early stage of crystallization.

Such silicon crystal growth can obtain large grains in lateral growth.

If the spacing of each silicon seed is larger than the maximum growth distance of silicon grain, the silicon crystal that grows laterally around the silicon seed grows up to the maximum and the nucleation is generated by super-cooling in the remaining liquid phase. Get up and make a small grain.

However, if the seed spacing is smaller than the maximum growth distance, lateral growth occurs around the seed to form grain boundaries, with each grain forming a large grain of poly-Si.

As described above, crystals of large silicon must be uniformly arranged on the substrate while forming grain boundaries to obtain a thin film transistor (TFT) device having excellent performance.

1 is a plan view illustrating a general liquid crystal display device.

As shown in FIG. 1, a plurality of gate lines 11 are arranged in one direction at regular intervals to define the pixel region P on the lower substrate 10, and are perpendicular to the gate lines 11. The plurality of data lines 12 are arranged at regular intervals in the direction.

Each pixel region P defined by crossing the gate line 11 and the data line 12 is switched by a pixel electrode 16 formed in a matrix form and a signal of the gate line 11, A plurality of thin film transistors for transmitting a signal of the data line 12 to the pixel electrodes 16 are formed.

Here, the thin film transistor is formed on the gate electrode 13 protruding from the gate line 11, the gate insulating film (not shown) formed on the front surface, and the gate insulating film above the gate electrode 13. And a source electrode 15a formed to protrude from the data line 12, and a drain electrode 15b formed at regular intervals on the source electrode 15a. .

The drain electrode 15b is electrically connected to the pixel electrode 16 through the contact hole 17.

Meanwhile, the lower substrate 10 configured as described above has a predetermined space and is bonded to the upper substrate (not shown).

In this case, the upper substrate has an opening corresponding to the pixel region P formed in the lower substrate 10, and serves as a light blocking layer, and a red / green / color for implementing color. In addition to the blue (R / G / B) color filter layer and the pixel electrode (reflection electrode) 16, a common electrode for driving a liquid crystal is included.

The lower and upper substrates 10 and 10 have a predetermined space by a spacer and liquid crystal is injected between two substrates bonded by a seal material having a liquid crystal injection hole.

Hereinafter, with reference to the accompanying drawings, a conventional method for crystallizing amorphous silicon is as follows.

2A to 2D are cross-sectional views illustrating a conventional method for crystallizing amorphous silicon.

As shown in FIG. 2A, a PECVD layer is formed on the insulating substrate 21 using a silicon oxide film (SiO ₂ ) or the like, and a PECVD layer using silane gas on the buffer layer 22. Amorphous Silicon is deposited using a method such as (Plasma Enhanced Chemical Vapor Deposition) or sputtering to form an amorphous silicon layer 23.

As shown in FIG. 2B, an annealing process is performed on the insulating substrate 21 on which the amorphous silicon layer 23 is deposited at a temperature of 400 to 500 ° C. to perform a dehydrogenation process.

In this case, the dehydrogenation process is performed to prevent films ablation during laser annealing.

As shown in FIG. 2C, a polycrystalline silicon layer is formed by irradiating the dehydrated amorphous silicon layer 23 with an excimer laser 25 having a specific wavelength in front of the dehydrogenated amorphous silicon layer 23. To form (24).

Here, the excimer laser 25 is irradiated while scanning in the direction of the arrow from one side of the polycrystalline silicon layer 24.

At this time, the amorphous silicon layer 23 is instantaneously melted and solidified, and the crystallization reaction proceeds rapidly. That is, the process window is very narrow because two reactions, nucleation reactions and grain growth, are performed by heating instantaneously at about 1000 ° C. at room temperature (25 ° C.).

As shown in Fig. 2D, the size of the crystal grains of the polycrystalline silicon layer 24 subjected to the crystallization process by the excimer laser is usually very small, on the order of several thousand angstroms.

In the crystallization method of amorphous silicon using the conventional excimer laser as described above, the amorphous silicon in the solid state is instantaneously melted by a high-energy (300 mJ / cm 2 or more) laser to make the liquid crystal state, and then the crystalline silicon by the instant cooling action. The phenomenon of phase transformation is applied.

However, in the conventional method of crystallizing amorphous silicon as described above, there are the following problems.

That is, however, localization of the process occurs within a few tens of ns hours at a temperature of 25 to 1000 ° C., resulting in a reduction of the process window due to thermal shock of the glass substrate or rapid quenching during cooling. After processing, the final grain size is as small as about 3000 mm 3.

The present invention has been made to solve the above problems, the crystallization method of amorphous silicon having coarse grains by increasing the temperature by the electrical resistance heating method at the time of laser crystallization and crystallization of amorphous silicon at a high temperature and a thin film using the same It is an object of the present invention to provide a method for forming a transistor.

In accordance with an aspect of the present invention, there is provided a method of crystallizing amorphous silicon, the method comprising: forming an amorphous silicon layer on an insulating substrate, heating the amorphous silicon layer to a predetermined temperature by an electric resistance heating method, and It characterized in that it comprises a step of crystallizing the amorphous silicon layer heated to a temperature of the laser irradiation.

In addition, the method for forming a thin film transistor according to the present invention for achieving the above object is to form an amorphous silicon layer on an insulating substrate, the amorphous silicon layer is heated to a predetermined temperature by an electrical resistance heating method and the heated Irradiating a laser to an amorphous silicon layer to form a polycrystalline silicon layer, patterning the polycrystalline silicon layer to form an active layer, forming a gate insulating film on an entire surface of the insulating substrate including the active layer, and gate insulation Forming a gate electrode on the film, forming a source / drain region in the active layers on both sides of the gate electrode, and forming an interlayer insulating layer having contact holes to expose a predetermined portion of the source / drain region on the insulating substrate. Forming a connection with the source / drain region through the contact hole; It characterized by yirueojim including the step of forming a source electrode and a drain electrode.

Hereinafter, with reference to the accompanying drawings will be described in detail the crystallization method of amorphous silicon according to the present invention and a method of forming a thin film transistor using the same.

3A to 3D are cross-sectional views illustrating a method of crystallizing amorphous silicon according to the present invention.

As shown in FIG. 3A, an insulating material such as a silicon oxide film (SiO ₂ ) is deposited on the insulating substrate 31 to form a buffer layer 32.

Here, the buffer layer 32 prevents impurities of the insulating substrate 31 from diffusing into the amorphous silicon layer formed later.

Meanwhile, the silicon oxide film used as the buffer layer 32 is formed by contacting oxygen (O ₂ ) or water vapor at a high temperature of 300 to 500 ° C.

Subsequently, amorphous silicon (Amorphous Silicon) is used at 300 to 400 ° C. using a method such as Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure CVD (LPCVD), or sputtering using silane gas on the buffer layer 32. E) is deposited to form an amorphous silicon layer 33.

Here, the buffer layer 32 is formed to have a thickness of about 3000 GPa, and the amorphous silicon layer 33 is formed to have a thickness of about 500 GPa.

As shown in FIG. 3B, the insulating substrate 31 on which the amorphous silicon layer 33 is formed is annealed at a temperature of 400 to 500 ° C. to perform a dehydrogenation process.

In this case, the dehydrogenation process is performed to prevent films ablation during laser annealing.

As shown in FIG. 3C, the electrodes 34 are formed at both ends of the amorphous silicon layer 33 on which the dehydrogenation is performed, and the electric resistance heating method is applied to the electrodes 34 to supply DC or AC power. The amorphous silicon layer 33 is selectively heated.

At this time, the amorphous silicon layer 33 is crystallized by irradiating an amorphous silicon layer 33 with an excimer laser 30 while heating the amorphous silicon layer 33 by an electric resistance heating method. (35) is formed.

In the present invention, the amorphous silicon layer 33 is crystallized by irradiating the excimer laser 30 while the amorphous silicon layer 33 is heated by an electric resistance heating method.

That is, the electrode 34 is formed at both ends of the amorphous silicon layer 33, and the electrode 34 is heated to a temperature of 300 to 500 ° C. in advance by an electric resistance heating method. By scanning the excimer laser 30 from one side to the other side, the grain size may be increased by lowering the melting and solidification rate of the amorphous silicon layer 33.

Here, the surface temperature of the amorphous silicon layer 33 is maintained at a temperature of about 300 ~ 500 ℃ by the electrical resistance heating method.

As shown in FIG. 3D, the crystal grain size of the polycrystalline silicon layer 35 crystallized by excimer laser irradiation while the amorphous silicon layer 33 is heated by an electrical resistance method is several times larger than that of a conventional 3000 micron. It becomes bigger.

4A to 4E are cross-sectional views illustrating a method of forming a thin film transistor according to a first embodiment of the present invention.

As shown in FIG. 4A, an insulating material such as silicon oxide (SiO ₂ ) is deposited on the transparent insulating substrate 31 to form a buffer layer 32, and an amorphous silicon layer 33 on the buffer layer 32. To form.

Here, the amorphous silicon layer 33 may be formed on the buffer layer 32 using a method such as plasma enhanced chemical vapor deposition (PECVD), low pressure CVD (LPCVD), sputtering, etc. using silane gas. It is formed by depositing amorphous silicon (Amorphous Silicon) at 400 ℃.

Subsequently, after forming the electrodes 34 at both ends of the amorphous silicon layer 33, power is applied to the electrode 34 so that the amorphous silicon layer 33 maintains a temperature of about 300 to 500 ° C.

As shown in FIG. 4B, an excimer laser is irradiated to the amorphous silicon layer 33 heated to the predetermined temperature to crystallize the amorphous silicon layer 33 to form a polycrystalline silicon layer 35.

As shown in FIG. 4C, the crystallized polycrystalline silicon layer 35 is selectively removed through a photo and etching process to form an active layer 36 having an island shape.

As shown in FIG. 4D, a gate insulating film 37 is formed on the entire surface of the insulating substrate 31 including the active layer 36, and a metal film is formed on the gate insulating film 37.

Here, the gate insulating film 37 is formed by depositing silicon oxide or silicon nitride by CVD (Chemical Vapor Deposition) method, the metal film is aluminum (Al), aluminum alloy (AlNd), chromium (Cr), tungsten Conductive metal films such as (W) and molybdenum (Mo) are formed by evaporation by sputtering.

Subsequently, the metal layer is selectively removed through a photo and etching process to form a gate wiring (not shown) and a gate electrode 38 on the gate insulating layer 37.

The n-type or p-type impurity ions are selectively implanted into the entire surface of the insulating substrate 31 by using the gate electrode 38 as a mask, and the source / electrode 36 is formed on the active layer 36 on both sides of the gate electrode 38. The drain region 39 is formed.

As shown in FIG. 4E, a thermal annealing process using thermal energy such as a laser is performed on the entire surface of the insulating substrate 31 to activate each ion region formed in the active layer 36.

Next, an interlayer insulating film 40 is formed on the entire surface of the insulating substrate 31 including the gate electrode 38, and the interlayer insulating film 40 is exposed to expose the source / drain regions 39 through photo and etching processes. Is selectively removed to form a contact hole.

Here, the interlayer insulating film 39 is formed of an inorganic insulating material such as silicon nitride or silicon oxide or an organic insulating material having a low dielectric constant such as acrylic organic compound, Teflon, BCB, cytosol or PFCB.

Subsequently, a metal film is deposited on the entire surface of the insulating substrate 31 including the contact hole, and is connected to the data line (not shown) and the source / drain region 39 crossing the gate line through a photo and etching process. The source / drain electrodes 41 are formed.

 Here, the metal film is a metal of aluminum (Al), copper (Cu), tungsten (W), chromium (Cr), molybdenum (Mo), titanium (Ti) or tantalum (Ta), or molybdenum of MoW, MoTa or MoNb. An alloy (Mo alloy) and the like are formed by depositing by CVD or sputtering.

5A through 5D are cross-sectional views illustrating a method of forming a thin film transistor according to a second embodiment of the present invention.

As shown in FIG. 5A, the sputtering method is selected from a metal made of Al, Al-Pd, Al-Si, Al-Si-Ti, Al-Si-Cu, Al alloy, or the like on the transparent glass substrate 41. Thereby depositing a metal film at a thickness of 200 to 4000 kPa.

Subsequently, the metal film is selectively etched through a photo and etching process to form a gate electrode 42 on the glass substrate 41.

Here, when the gate electrode 42 is a metal capable of anodizing, the gate electrode 42 may be anodized to prevent hillock.

As shown in FIG. 5B, a gate insulating film 43 made of a silicon nitride film or a silicon oxide film is formed on the entire surface of the glass substrate 41 including the gate electrode 42.

Subsequently, an amorphous silicon layer is formed on the gate insulating layer 43.

The amorphous silicon layer is heated to a temperature of 300 to 500 ° C. by an electric resistance heating method, and an excimer laser is irradiated to the heated amorphous silicon layer to form a polycrystalline silicon layer 44.

As shown in FIG. 5C, the polycrystalline silicon layer 44 is selectively removed through a photo and etching process to form an active layer 45.

Here, the active layer 45 is formed to cover the gate electrode 42 to correspond to the gate electrode 42.

As shown in FIG. 5D, an ohmic contact layer 46 and a metal film are sequentially formed on the entire surface of the insulating substrate 41 including the active layer 45.

Subsequently, the metal layer and the ohmic contact layer 46 are selectively removed through a photo and etching process to form an electrically separated source electrode 47 and a drain electrode 48.

In the above-described process, the active layer 45, the source electrode 47, and the drain electrode 48 are performed using separate masks, but may be formed through one mask.

That is, an ohmic contact layer and a metal film are sequentially deposited on the polycrystalline silicon layer, a photoresist is applied on the metal film, and then a photoresist pattern is formed by an exposure and development process using a mask (half-tone mask). In this case, the mask (half-tone mask) is composed of a blocking region that completely blocks the light, a transmission region through which light is transmitted, and a slit region where only a predetermined amount of light is irradiated.

Therefore, the developed photoresist pattern is formed to have a different thickness.

Subsequently, the metal layer, the ohmic contact layer, and the polycrystalline silicon layer are removed by wet or dry etching using the photoresist pattern as a mask to form an active layer.

The photoresist pattern is ashed to remove a portion having a relatively thin thickness among the photoresist patterns.

In this case, the photoresist pattern is thinner as a whole.

Next, the metal layer and the ohmic contact layer corresponding to the channel region of the thin film transistor are etched using the ashed photoresist pattern as a mask to form a source electrode and a drain electrode, and then the remaining photoresist pattern is removed. .

In addition, after the insulating film is deposited on the entire surface of the thin film transistor formed in accordance with the present invention, a contact hole is formed to expose a predetermined portion of the surface of the drain electrode through a photo and etching process, and a transparent metal film is formed on the entire surface of the substrate including the contact hole. The liquid crystal display device may be formed by forming a pixel electrode connected to the drain electrode through the contact hole by selectively removing the substrate after deposition.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

As described above, the method of crystallizing amorphous silicon and the method of forming a thin film transistor using the same according to the present invention have the following effects.

First, polycrystalline silicon having coarse grains can be formed by irradiating and crystallizing an excimer laser in a state in which amorphous silicon is heated to a constant temperature through an electrical resistance heating method, and stability of the laser annealing process can be greatly improved.

Second, the characteristics and reliability of the TFT device using the polycrystalline silicon thin film can be improved.

Claims (17)

Forming an amorphous silicon layer on the insulating substrate; Forming electrodes at both ends of the amorphous silicon layer; Heating the amorphous silicon layer by applying power to the electrode by an electric resistance heating method; And crystallizing the amorphous silicon layer by irradiating a laser with the amorphous silicon layer heated to a predetermined temperature. The method of claim 1, wherein the predetermined temperature is 300 to 500 ° C. 6. The method of claim 1, wherein the laser is an excimer laser. 2. The method of claim 1, further comprising the step of performing a dehydrogenation process on the amorphous silicon layer before heating the amorphous silicon layer. 5. The method of claim 4, wherein the dehydration step is carried out at 400 ~ 500 ℃. The method of claim 1, further comprising forming a buffer layer between the insulating substrate and the amorphous silicon layer. 7. The method of claim 6, wherein the buffer layer is a silicon oxide film. delete 2. The method of claim 1, wherein the power source is an alternating current or direct current power source. The method of claim 1, wherein the laser is irradiated while scanning from one side to the other side. Forming an amorphous silicon layer on the insulating substrate; Electrodes are formed at both ends of the amorphous silicon layer, and a power is applied to the electrodes by an electric resistance heating method to form a polycrystalline silicon layer by irradiating a laser to the amorphous silicon layer while heating the amorphous silicon layer to a predetermined temperature. Doing; Patterning the polycrystalline silicon layer to form an active layer; Forming a gate insulating film on an entire surface of the insulating substrate including the active layer; Forming a gate electrode on the gate insulating film; Forming a source / drain region in the active layers on both sides of the gate electrode; Forming an interlayer insulating film having contact holes on the insulating substrate such that the source / drain regions are partially exposed on the surface thereof; And forming a source electrode and a drain electrode connected to the source / drain region through the contact hole. The method of claim 11, wherein the predetermined temperature is 300 to 500 ° C. 13. The method of claim 11, further comprising performing a dehydrogenation process on the amorphous silicon layer before heating the amorphous silicon layer. The method of claim 13, wherein the dehydration step is performed at 400 ° C. to 500 ° C. 15. 12. The method of claim 11, further comprising forming a buffer layer between the insulating substrate and the amorphous silicon layer. 12. The method of claim 11, wherein the gate electrode is one of conductive metal films such as aluminum, aluminum alloy, chromium, tungsten, and molybdenum. The method of claim 11, wherein the interlayer insulating film is formed of any one of an inorganic insulating material such as silicon nitride or silicon oxide or an organic insulating material having a low dielectric constant such as acrylic organic compound, Teflon, BCB, cytosol or PFCB. Method of forming a thin film transistor.

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