KR100325629B1 - Polysilicon-thin film transistor element and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a switching device in which the semiconductor layer is formed of polysilicon, and more particularly, to a thin film transistor in which the microstructure of the polysilicon surface is planarized.

The thin film transistor etches and recrystallizes a grain boundary of silicon crystal constituting the polysilicon forming the semiconductor layer by a predetermined method to planarize the fine surface of the semiconductor layer, thereby causing an interface mismatch at the interface between the semiconductor layer and the insulating layer. By eliminating the trapping level of electrons, the improved operation characteristics of the device can be obtained, and the short-circuit of the device due to the electrical breakdown of the insulating layer, which can be caused by the surface of the uneven semiconductor layer, can be prevented. It can increase the effect.

Description

Polysilicon-thin film transistor element and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching device having a semiconductor layer. More specifically, the present invention relates to a thin film transistor having a semiconductor layer having a flat microsurface.

In general, the thin film transistor is composed of a multilayer and is divided into a semiconductor layer, an insulating layer, a protective layer, and an electrode layer.

Each element of the thin film transistor will be described in more detail. Amorphous silicon or polysilicon may be used as an active layer, and a silicon nitride film (SiN) may be used as an insulation layer. _X ), silicon oxide film (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), tantalum oxide (TaO _X ), etc. are used, and a transparent organic material or an insulating material is used as a passivation layer, and an electrode layer is used. As a layer), metal conductive materials such as aluminum (Al), chromium (Cr), and molybdenum (Mo) are generally used.

The materials according to each of these elements are deposited using a deposition apparatus, i.e., a sputtering apparatus, a chemical vapor deposition (CVD) apparatus, etc., and then subjected to lithography. Each element is formed.

The semiconductor layer of each component layer configured as described above serves as a conductive channel through which electrons flow, and the electrode layer is composed of a source electrode, a drain electrode, and a gate electrode, and the drain electrode serves as a means for applying a signal voltage to the semiconductor layer. .

In addition, the source electrode is a means for emitting a current flowing in the semiconductor layer to the peripheral portion by the signal voltage.

The gate electrode serves as a means for switching the flow of current flowing from the drain electrode through the semiconductor layer to the source electrode.

Accordingly, the thin film transistor can be used as a switching element and is applied as a switching element for an active matrix liquid crystal disply device (AMLCD).

The active matrix liquid crystal display device uses a thin film transistor in which cadmium serenide (CdSe), hydrogenated amorphous silicon (a-Si: H), and poly crystallin silicon (poly-Si) are used as a semiconductor layer. Successful configuration is possible.

As described above, amorphous silicon is a material used as a semiconductor layer of a thin film transistor, and thus, since the process is simple and can be processed at low temperature, it is already used for manufacturing a large area device such as a solar cell.

In addition, the manufacturing process of the device using amorphous silicon is convenient because the maximum temperature can be performed alone in a low temperature processing system of about 350 ℃.

However, in practice, low electron mobility (<2 cm2 / Vsec) in amorphous silicon acts as a disturbing factor in the operating characteristics of amorphous silicon, and also drives circuit elements that control thin film transistors at high speed. circuitry) and makes the integration of thin film transistors difficult.

On the other hand, a thin film transistor using polysilicon as a semiconductor layer is suitable for an active matrix liquid crystal display device.

A thin film transistor made of polysilicon requires a new processing step, but instead has a response speed several times faster than amorphous silicon as a switching element in an active matrix liquid crystal display device.

In addition, the greatest advantage of polysilicon over the widely used amorphous-thin film transistor is that it has a high field effect mobility of about 50 ~ 150 cm 2 / Vsec.

Field effect mobility determines the switching speed of thin film transistors and is about 200 times faster than amorphous silicon.

This difference is due to the fact that polysilicon is microcrystalline and has fewer defects than amorphous silicon.

Therefore, polysilicon is expected as an optimal material for switching means for the next generation liquid crystal display device having a large area screen.

Crystallization of such polysilicon includes SPC method, MIC method, excimer laser annealing method, etc. In more detail, SPC (Solid phase crystallization) method is a method of crystallizing amorphous silicon at high temperature, but the film quality is excellent. If the substrate is selected due to high temperature processing, there is a disadvantage that a high price material such as a crystal that can withstand above 1000 ° C must be used.

In addition, MIC (Metal induced crystallization) method is a method of crystallizing by applying a heat by depositing a predetermined metal on the amorphous silicon, the metal serves to lower the enthalpy of the amorphous silicon to be crystallized.

Therefore, low temperature process treatment of about 500 ° C. is possible, but the surface condition is not good and it is not a method widely used due to the deterioration of properties due to metal.

As another method, there is a method using a laser, which is excellent in terms of price competitiveness because low-temperature processing can be used and a low-cost glass substrate can be used.

In particular, the thin film transistor manufactured by the excimer laser annealing method can have a moving speed of 100 cm 2 / Vsec or more, so that the device has good operating characteristics.

The polysilicon crystallized by the above-described methods is a result of the continuous formation of silicon crystals composed of grain and gray boundaries starting from the formation of silicon seeds at the initial stage of crystallization. Such silicon crystals have lateral growth around silicon seeds.

If the spacing of each silicon seed is greater than the maximum growth distance of silicon grain, the silicon crystals that grow laterally around the silicon seed will exist without the grain boundaries of each crystal being in contact with each other.

As described above, the state in which the fine silicon crystals are not formed in continuous contact with each other on the substrate is electrically isolated and thus cannot function as an element.

Therefore, as shown in Figs. 1A to 1C, the silicon seed distribution must be somewhat dense.

As shown, when the grains 13 of silicon, which are laterally grown around the silicon seed 11, grow to some extent, each grain 13 and the boundary 15 of the grains are in contact with each other and continuously. Will grow.

2A to 2C are cross-sectional views illustrating a manufacturing process of a film transistor in which a conventional semiconductor layer is formed of polysilicon, and a coplanar thin film transistor will be described as an example.

One of an insulating material of a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN _X ), and an aluminum oxide film (Al ₂ O ₃ ) is selected and deposited on the substrate 21 to form a thin insulating layer.

The insulating layer acts as a buffer between the substrate and the semiconductor layer to be formed later, thereby preventing warpage and the like, which may occur due to non-uniform contact between the substrate and the semiconductor layer.

As illustrated in FIG. 2A, after depositing the insulating layer (not shown), amorphous silicon including hydrogen is deposited to form a semiconductor layer 23.

In this case, the semiconductor layer 23 of the thin film transistor used as the switching element is generally formed of polysilicon by recrystallization of amorphous silicon (hereinafter referred to as 'amorphous silicon'), thereby forming the semiconductor layer 23. You lose.

After depositing the amorphous silicon, the amorphous silicon is crystallized into polysilicon through predetermined steps and methods to recrystallize the amorphous silicon into polysilicon.

As shown in FIG. 1C, the polysilicon is a result of successively forming a plurality of silicon crystals composed of grains 13 and grain boundaries 15.

As described above, after forming the semiconductor layer 23 and patterning it again in an island form, as shown in FIG. 2B, n + amorphous silicon is used to lower the contact resistance between the semiconductor layer 23 and the conductive film to be formed later. Alternatively, p + amorphous silicon is deposited and patterned to form an ohmic contact layer (not shown).

After forming the ohmic contact layer (not shown), the ohmic contact layer is formed by depositing and patterning a conductive metal such as aluminum (Al), tungsten (W), molybdenum (Mo), nickel (Ni), and tantalum (Ta). The source electrode 25a and the drain electrode 25b are formed so as to overlap the plane (not shown) and correspond to each other at predetermined intervals.

After the source electrode 25a and the drain electrode 25b are formed, the semiconductor layer 23 exposed between the source / drain electrodes 25a and 25b and the source electrode 25a and the drain electrode 25b. The insulating layer 27 is formed by selecting and depositing one of insulating materials of a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN _X ), and an aluminum oxide film (AlO ₂ ).

After the insulating layer 27 is formed, conductive metals such as aluminum (Al), tungsten (W), molybdenum (Mo), nickel (Ni), and tantalum (Ta) are deposited and patterned as shown in FIG. 2C. The gate electrode 29 is formed on the semiconductor layer 23 exposed between the source electrode 25a and the drain electrode 25b.

Meanwhile, FIG. 3 illustrates an interface between the semiconductor layer 23 in which amorphous silicon is crystallized from polysilicon and the insulating layer 27 as described above.

As a result, the grain boundary 26 is formed so as to rise upwardly compared to the grain 24 growing flat, and thus the grain boundary 26 compared to the flat grain 24 in the semiconductor layer 23 formed of polysilicon. The finely protruded shape of the trap becomes a trap level that impedes the flow of electrons, resulting in a loss of current in the semiconductor layer, and if the insulating layer 27 is deposited on the semiconductor layer 23 of this type, The thickness of the insulating layer 27 formed is not constant.

Therefore, a thinly deposited portion of the insulating film will easily cause breakdown even at a small current value, and as a result, a short occurs in the device and causes the device to be destroyed.

In addition, when the insulating layer 27 is thinly grown, the pointed portions of the polysilicon crystals do not deposit an insulating material, and in this situation, electric current of the device can be easily predicted if current flows.

As shown in the drawing, the conventional technique is insulated to a thickness more than necessary to prevent breakdown due to the grain boundary 26 of the polysilicon in the process of depositing an insulating layer on the semiconductor layer 23 made of polysilicon. The layers 27 were stacked up.

However, the conventional method can prevent the failure of the device due to breakdown, but the problem of trapping electrons by grain boundaries, planarization between the insulating layer and the semiconductor layer, and deterioration of the operation characteristics of the device due to the thick stacked insulating layer This remains a problem.

Accordingly, an object of the present invention is to planarize an interface between a semiconductor layer and an insulating layer, thereby reducing the thickness of the insulating layer and eliminating trap levels for electrons flowing through the semiconductor layer, thereby improving the operation characteristics and reliability of the device.

1a to 1c is a plan view showing the growth process of grain,

2A to 2C are cross-sectional views illustrating a manufacturing process of a conventional thin film transistor,

3 is a partial view showing A of FIG. 2C,

4 is a partial cross-sectional view of a thin film transistor,

5A is a top view of a polysilicon surface,

5B is a cross-sectional view of the polysilicon surface,

Figure 6a is a plan view showing the etching state of the surface of the polysilicon according to the present invention,

6B is a cross-sectional view illustrating an etching state of a polysilicon surface according to the present invention;

6C is a cross-sectional view of planarized polysilicon in accordance with the present invention;

7 is a complete process cross-sectional view of a thin film transistor.

<Description of the symbols for the main parts of the drawings>

119: grain boundary 123: junction of each boundary

113: semiconductor layer

In order to achieve the above object, another thin film transistor according to the present invention comprises the steps of forming an insulating layer by thinly depositing an insulating material on the substrate; Depositing amorphous silicon on the insulating layer to form a semiconductor layer; Removing a hydrogen of amorphous silicon forming the semiconductor layer by a predetermined method; Forming the hydrogen-depleted amorphous silicon into polysilicon as a result of the continuous growth of silicon crystals composed of grains and grain boundaries using a predetermined crystallization method; Forming the polysilicon layer and etching a portion of the silicon crystal composed of grains and grain boundaries in contact with a predetermined nicking solution; Melting the surface of the grain etched by the grain boundary portion to fill the etched grain boundary portion evenly and recrystallization to planarize the surface of the semiconductor layer; Patterning the semiconductor layer having the planarized surface to form an island shape; Forming an ohmic contact layer by depositing an over-doped semiconducting material on the island-shaped semiconductor layer and patterning the doped semiconductive material so as to correspond to each other at a predetermined interval; Depositing a conductive metal on the ohmic contact layer and forming a source electrode and a drain electrode so as to correspond to each other at a predetermined interval; Forming an insulating layer by depositing an insulating material on the semiconductor layer exposed at predetermined intervals between the source electrode and the drain electrode and the source electrode and the drain electrode; Depositing a conductive metal on the insulating layer and patterning the conductive metal to form a gate electrode; The present invention provides a method of manufacturing a protective layer by depositing an insulating material on the gate electrode.

Preferably, the method of recrystallizing the amorphous silicon is characterized in that one of the excimer laser, argon laser, ion beam method.

Preferably, the nicking solution is characterized in that hydrofluoric acid and chromic acid are diluted in a predetermined ratio.

Preferably, the grain size is characterized in that 3000 ~ 4000 mm 3.

In addition, a switching device manufacturing method according to a feature of the present invention is a continuous silicon crystal composed of grain and grain boundary in a thin film transistor type photosensitive sensor including a gate electrode, a source electrode, a drain electrode, and a polysilicon-semiconductor layer. Growing to crystallize into polysilicon; Etching the grain boundary portions in which the silicon crystals are in contact with each other; And melting the surface of each grain etched by the grain boundary portion to fill the etched grain boundary portion evenly and to recrystallize to planarize the surface.

As described above, when the semiconductor layer, which is an active layer of the thin film transistor, is formed, the operation of planarizing the fine surface of the semiconductor layer made of polysilicon removes the trap state generated at the interface between the insulating layer and the semiconductor layer, thereby conducting electrons. Can improve the characteristics.

In addition, since the flatness of the semiconductor surface allows the insulating layer to be deposited thinner than before, the operation characteristics of the device may be improved.

In addition, it is possible to prevent the failure of the device due to the insulation breakdown caused by the irregular surface can increase the yield of the product.

Hereinafter, an embodiment of a method of manufacturing a thin film transistor type photosensitive device according to the present invention will be described in detail with reference to the accompanying drawings.

Example

The thin film transistor according to the present invention forms a semiconductor layer with polysilicon, and selectively etches the grain boundary portion of the silicon crystal constituting the polysilicon and anneals the polysilicon layer where the grain boundary is etched to flatten the surface. do.

In more detail, the thin film transistor according to the present invention first forms an insulating layer (not shown) on the substrate 111 with a predetermined insulating material.

The insulating layer serves as a buffer between the substrate 111 and the conductive film to be formed later.

It prevents warping and the like which may occur due to non-uniform contact between the substrate and the semiconductor layer.

As shown in FIG. 4, amorphous silicon is deposited on the insulating layer (not shown) to form a semiconductor layer 113.

After the semiconductor layer 113 is formed, prior to recrystallization from polysilicon, a dehydrogenation process for removing hydrogen contained in the amorphous silicon should be performed.

When annealing amorphous silicon that has not undergone dehydrogenation, hydrogen flies during the annealing reaction and hydrogen flies remain voids, causing deterioration of the electrical characteristics of the device.

Therefore, a dehydrogenation process that blows off hydrogen in advance before annealing is required, wherein dehydrogenation is performed at a predetermined temperature using an electric furnace or a laser.

As described above, after the dehydrogenation of amorphous silicon is completed, amorphous silicon is recrystallized by means of an excimer laser, an argon laser, an ion beam method, and the like. Polysilicon crystals consist of a continuous formation of numerous silicon crystals composed of grain and grain boundaries.

At this time, the grain size can be controlled by means of crystallizing amorphous silicon into polysilicon.

For example, in the laser annealing method, which is one of the crystallization means, grain growth can be controlled by the shape and energy density of the laser beam, the temperature of the substrate, and the cooling rate.

In general, excimer lasers have shown that a relatively good silicon crystal can be obtained at an energy density of 240 ~ 330mJ / ㎠.

More specifically, the relationship between grain size and energy density can be explained by crystal grain size divided into three regions according to energy density.

That is, a low energy density regime-partial melting regime, a near complete melting regime-super lateral growth regime, and a high energy density region (High energy density rgime-Compelete melting regime), the state of the silicon surface in the low energy density region is a state in which the melting depth is less than the silicon thickness, the contact growth of grain occurs competitively, mainly the longitudinal axis growth, grain Is a region where the size of grain is very small and the grain diameter is smaller than the film thickness of the semiconductor layer.

The near complete melting regime is a state in which the silicon film of the semiconductor layer is almost completely melted, and the silicon crystals have a preferential direction in the [111] direction and are laterally grown. It can be said that the state just before.

Thirdly, in the high energy density regime, quenching leads to ice crystal formation and solid growth, low grain size due to low substrate temperature, and amorphousness in thin films.

As a result, grain size is independent of temperature at high energy densities.

Therefore, the size of the grain can be controlled to some extent in consideration of the energy density and cooling speed of the laser beam.

As shown in 5a, the dehydrogenated amorphous silicon is formed of a uniform silicon crystal composed of grain 117 and grain boundary 119.

The portions 123 in which the grain boundaries 119 of the silicon crystal contact each other are formed in a shape 119 that collides with each other as shown in FIG. 5B.

This microdefect on the semiconductor surface acts as a trapping level for electrons as described above, which causes current loss in the semiconductor layer, and when the insulating layer is formed later, the insulating material does not evenly accumulate on the semiconductor layer. The thickness of is not uniform. If a current flows in a thinly deposited portion, insulation breakdown of the device occurs through this portion, and electrical defects of the thin film transistor may cause point defects in the liquid crystal display device.

Therefore, in order to remove the defect as described above, the junction 123 of the pointed grain boundary 119 is etched to a predetermined width and height using one of the etching solutions shown in [Table 1]. give.

TABLE 1

Nickname Solution Chemical formula Application field Sirtle HF: Cr ₂ O ₃ (1: 1) Application to materials with a {111} orientation. Dash HF: HNO ₃ : acetic acid (1: 3: 10) Most suitable for p-type materials, but can be used for n-type and p-type substrates with {111} and {100} orientations. Secco HF: K ₂ Cr ₂ O ₇ (2: 1) HF: Cr ₂ O ₃ (2: 1) It is a general quenching solution, and is particularly suitable for materials having a {100} aromaticity. Schilmel HF: HNO ₃ (155: 1) Application to p type materials. Jenkins HF: HNO ₃ : CrO ₃ : Cu (No ₃ ) ₂ : 3 H ₂ 0: Acetic acid: H ₂ O (2: 1: 1: (2g): 2: 2) Generally applicable

Among those shown in Table 1, in the present embodiment, an etching solution in which hydrofluoric acid (HF) and chromic acid (Cr ₂ O ₃ ) are diluted at a predetermined ratio is used.

As mentioned above, the reason for selectively etching the grain boundary is that the grain boundary contains a lot of impurities and has a lower density than the grains that grow densely as impurities are pushed to the surface of the crystal during the crystallization of silicon. It is easier to etch than grain.

FIG. 6A is a partial plan view of a silicon crystal in which grain boundaries 119 (see FIG. 5) are etched as described above, and FIG. 6B is a cross-sectional view of the polysilicon semiconductor layer in which grain boundaries are etched.

As shown, the portions 123 etched between the grains 119 and the grains are etched to have a uniform width and depth.

As described above, after the junction portion 123 of each grain boundary is etched, the semiconductor layer is flattened by melting the grain by using an excimer laser, an argon laser, an ion beam method, etc. to fill the etched portion and simultaneously recrystallization. Can form.

Therefore, as the surface tension increases, the surface of the grain may recrystallize to a relatively flat surface state when annealing.

Such a case can be proved by the expression of surface tension, internal energy, free energy, and surface area as follows.

In more detail, the force required to spread the generated liquid on the grain surface, and the surface tension γ to maintain the surface of the liquid is the reversible work W _r required to increase the surface of the liquid by the unit area. Is defined by].

[Equation 1]

dwr = γdA ---- (1)

At this time, dA is the derivative value per unit area of the surface of the liquid.

By defining the conditions under which this reversible surface work is done, the surface tension can be related to other thermodynamic properties in the liquid state.

In other words, when changing from one equilibrium state to another equilibrium state, the change of the internal energy E or the free energy G of Gibbs is expressed as follows according to the first and second laws of thermodynamics of [Equation 2].

[Formula 2]

---- (2)

dG = -SdT + VdP + γdA + Σμidni ---- (3)

Therefore, the surface tension γ may be defined as shown in Equation 3 with respect to the internal energy E and the free energy G.

[Equation 3]

γe () S, V, ni = () P, T, ni ---- (4)

In this case, the subscripts indicate independent variables to be maintained if the surface area is slightly increased.

As can be seen from the above equation, the smaller the surface area, the higher the surface tension under the condition that free energy and internal energy are constant.

Therefore, in the present embodiment by the above-described formula, in order to obtain a relatively flat surface state when recrystallizing polysilicon, it is preferable that the grain is melted as small as possible.

The grain size according to the present embodiment is about 3000 to 4000 3000, and this value is smaller than that of general polysilicon grains, and when the grain boundary is reannealed, the grains are melted and melted. It is an approximate size that the silicon can fill the etched portion and fill the etched portion flat and recrystallize flat.

As shown in FIG. 6C, after the semiconductor layer 113 having a flat surface is formed, the semiconductor layer 113 is patterned into islands, and as shown in FIG. 7, aluminum (Al) and nickel (Ni) are formed on the island-like semiconductor layer. And doped conductive metal ions such as molybdenum (Mo) and tungsten (W) to form source and drain regions 115a and 115b.

After the source and drain regions 115a and 115b are formed, the exposed semiconductor layer 113 between the source and drain regions 115a and 115b and the source and drain regions 115a and 115b. The insulating layer 125 is formed by selecting and depositing one of insulating materials, such as a silicon nitride film (SiN _x ), a silicon oxide film (SiO ₂ ), and an aluminum oxide film (A ₂ IO ₃ ).

After the insulating layer 125 is formed, a conductive metal is deposited and patterned on the insulating layer 125, and then the upper portion of the semiconductor layer 113 exposed between the source region 133a and the drain region 133b is insulated. The gate electrode 127 is formed on the layer 125.

After the gate electrode 127 is formed, the insulating layer 125 and the gate electrode 127 are simultaneously patterned and etched to have a predetermined length.

The gate electrode 127 is a conductive metal such as aluminum (Al), tantalum (Ta), molybdenum (Mo), tungsten (W), nickel (Ni), aluminum alloy, molybdenum-tungsten alloy (Mo-W), or the like. Select one of the deposition and patterning to form.

After forming the gate electrode 127, a protective layer 129 is formed on the gate electrode 119 by using an insulating material.

After forming the passivation layer 129, contact holes 131a and 131b are formed at both sides of the passivation layer 129, but are formed up to the drain region 115a and the top of the source region 115b.

After the contact holes 131a and 131b are formed, a conductive metal is deposited and patterned on the protective layer 127 on which the contact holes 131a and 131b are formed, and the source electrode 133a is formed to correspond to a predetermined interval. The drain electrode 133b is formed, and the source electrode 133a and the drain electrode 133b are formed on both sides of the semiconductor layer 113 through the contact holes 131a and 131b. It is electrically connected to the drain region 115b.

As described above, in the present embodiment, a method of manufacturing a coplanar thin film transistor, which is one of the structures for forming a thin film transistor, has been described as an example. However, a source electrode and a drain electrode are formed on a substrate to correspond to a predetermined interval, and continuously The same method can be used to planarize the polysilicon of the semiconductor layer by using the same method for a staggered type thin film transistor in which a semiconductor layer, an insulating layer, a gate electrode, and a protection layer are formed. In addition to the thin film transistor, polysilicon is used as the semiconductor layer, and the polysilicon layer and the insulating layer are continuously formed, and the present invention can be applied to a switching device in which a conductive channel is formed at the interface between the semiconductor layer and the insulating layer.

Accordingly, various modifications may be made without departing from the spirit of the invention, and the modified embodiments may be clearly understood by the appended claims that belong to the scope of the present rights.

In the thin film transistor using polysilicon as a semiconductor layer, the semiconductor layer formed of polysilicon is formed by etching and re-annealing a portion of the grain boundary forming a silicon crystal so as to rise sharply compared to the flat grains of the grains and grain boundaries. By planarizing the micro surface, it is possible to prevent trapping of electrons which may be caused by the grain boundary as described above, or short circuit of the device due to breakdown of the insulating layer. There is an effect of improving the yield.

Claims (8)

Depositing amorphous silicon on the substrate to form a semiconductor layer; Forming the amorphous silicon into a polysilicon layer comprising grains and grain boundaries using a crystallization method; Etching the grain boundary portion of the polysilicon layer using an etching solution; The grain boundary portion melts the etched grain and recrystallizes the etched grain boundary portion to fill the etched grain boundary portion to planarize the surface of the semiconductor layer; Patterning the planarized semiconductor layer to form an island; Ion-doped the semiconductor layer formed in the island shape to form a source region and a drain region, respectively; Depositing a conductive metal on the semiconductor layer through an insulating film and patterning the conductive metal in a predetermined pattern to form a gate electrode; And a source electrode and a drain electrode connected to the source and drain regions formed by the ion doping, respectively. The method of claim 1, The amorphous silicon is a thin film transistor manufacturing method containing hydrogen. The method of claim 1, Thin-film transistor manufacturing method further comprises a dehydrogenation process in the crystallization step of the polysilicon. The method of claim 1, The method of recrystallizing the amorphous silicon is a thin film transistor manufacturing method of the excimer laser, argon laser, ion beam method. The method of claim 1, The etching solution is a thin film transistor manufacturing method of diluting one of a circle, a dash, a saco, a chermel, Jenkinson The method of claim 1, The grain size is a thin film transistor manufacturing method of 1000 ~ 10000Å. A field effect transistor comprising a polysilicon-semiconductor layer, Depositing amorphous silicon on an insulating substrate; Crystallizing the amorphous silicon with polysilicon consisting of grain and grain boundaries; Etching the grain boundary portions of the polysilicon surface on which silicon crystals are in contact with each other; The step of flattening the surface of the polysilicon by recrystallizing the grain boundary by melting the etched grain and flatten the etched portion Field effect transistor manufacturing method comprising a. Depositing amorphous silicon on the substrate; Crystallizing the amorphous silicon with polysilicon consisting of grain and grain boundaries; Etching the grain boundary portions in which the silicon crystals are in contact with each other; Flattening the surface of the polysilicon by dissolving each grain etched by the grain boundary portion and recrystallizing the etched boundary portion. Planarization method of the polysilicon surface comprising a.