KR101043788B1 - Fabricating Of A Polycrystalline silicon layer and Fabricating Of A Thin film transistor comprising the same - Google Patents

Abstract

The present invention comprises the steps of providing a substrate; Forming an amorphous silicon film on the substrate; Forming a conductive layer on the amorphous silicon film; A method of manufacturing a polycrystalline silicon film, and a method of manufacturing a thin film transistor comprising the same, include crystallizing the amorphous silicon film by applying an electric field to the conductive layer.

Accordingly, the present invention includes a method of manufacturing a polycrystalline silicon film that can prevent arc generation due to dielectric breakdown of the insulating layer due to the potential difference between the amorphous silicon layer and the conductive layer, and can simplify the crystallization process, and includes the same. It is effective to provide a method for manufacturing a thin film transistor.

Joule heat, arc, crystallization

Description

Manufacturing method of polycrystalline silicon film and manufacturing method of thin film transistor including same {Fabricating Of A Polycrystalline silicon layer and Fabricating Of A Thin film transistor comprising the same}

The present invention relates to a method of manufacturing a polycrystalline silicon film and a method of manufacturing a thin film transistor including the same, and more particularly, to a method of manufacturing a thin film transistor capable of preventing the arc generation due to dielectric breakdown of the insulating layer.

Recently, research and development on an active matrix flat panel display device using a thin film transistor have been actively performed among various technologies for manufacturing a flat panel display device. Conventionally, a semiconductor layer of a thin film transistor is formed of amorphous silicon. However, in general, amorphous silicon has a disadvantage in that the mobility and aperture ratio of electrons, which are charge carriers, are low and incompatible with CMOS processes.

On the other hand, the polycrystalline silicon thin film element can form a driving circuit on the substrate like a pixel TFT-array necessary for writing an image signal to a pixel, which was not possible with an amorphous silicon TFT. Therefore, in the polycrystalline silicon thin film element, the connection between the plurality of terminals and the driver IC becomes unnecessary, thereby increasing productivity and reliability and reducing the thickness of the panel. In addition, in the polycrystalline silicon TFT process, since the microfabrication technology of silicon LSI can be used as it is, a microstructure can be formed in wiring etc. Therefore, since there is no pitch constraint on the TAB mounting of the driver IC seen in the amorphous silicon TFT, pixel reduction is easy and a large number of pixels can be realized at a small angle of view. Compared with the thin film transistor using amorphous silicon, the thin film transistor using polycrystalline silicon in the semiconductor layer has advantages in that the size of the semiconductor layer is determined by the high switching capability and the self-matching, so that the device size and the CMOS can be reduced. For this reason, polycrystalline silicon thin film transistors are used as pixel switching elements such as active matrix flat panel display devices (eg, liquid crystal displays and organic light emitting display devices). It is emerging as a major element for the practical use of the.

There are two methods for manufacturing such polycrystalline silicon TFTs: a method of manufacturing at a high temperature condition and a technology of manufacturing at a low temperature condition. In order to form at a high temperature condition, an expensive material such as quartz must be used as a substrate, which is not suitable for large area. . Therefore, studies have been actively conducted on a method for producing a large amount of amorphous silicon thin film from polycrystalline silicon under low temperature conditions.

Such low-temperature polycrystalline silicon may be formed by solid phase crystallization (SPC), metal induced crystallization (MIC), metal induced side crystallization (MILC), or excimer laser. Crystallization (ELC: Excimer Laser Crystallization) method.

Although the SPC method can obtain uniform crystallization using low-cost equipment, it requires a high crystallization temperature and a long time, so it is impossible to use a substrate having a relatively low heat deformation temperature such as a glass substrate, and the productivity is low. Have. In the case of the SPC method, annealing is performed on an amorphous silicon thin film for about 1 to 24 hours at a temperature of 600 to 700 ° C. to allow crystallization. In addition, in the case of the polycrystalline silicon produced by the SPC method, it is accompanied with twin-growth during the solid phase transformation from the amorphous phase to the crystal phase, and thus contains a large number of crystal lattice defects in the formed grains. These factors serve to reduce the mobility and increase the threshold voltage of electrons and holes of the manufactured polycrystalline silicon TFT.

The MIC method has the advantage that amorphous silicon is brought into contact with a specific metal so that its crystallization is performed at a temperature much lower than the crystallization temperature by the SPC method. Metals that enable the MIC method include Ni, Pd, Ti, Al, Ag, Au, Co, Cu, Fe, Mn, and the like, and these metals react with amorphous silicon to form eutectic or silicide phases. (silicide phase) is formed to promote low temperature crystallization. However, application of the MIC method to the actual process of polycrystalline silicon TFT fabrication causes serious contamination of the metal in the channel.

The MILC method is an application technique of the MIC method, which forms a gate electrode instead of depositing a metal on a channel, and then deposits a thin layer of metal on a source and a drain in a self-aligned structure to induce metal induced crystallization. The technique then induces lateral crystallization towards the channel. Ni and Pd are the most commonly used metals in the MILC method. Polycrystalline silicon prepared by the MILC method is known to exhibit high leakage current characteristics, despite excellent crystallinity and high field effect mobility compared to the SPC method. In other words, the metal contamination problem is reduced compared to the MIC method, but it is still not completely solved. On the other hand, a field-directed directional crystallization (FALC) is an improved method of the MILC method. Compared with the MILC method, FALC method has a faster crystallization rate and anisotropy in the crystallization direction, but it also does not completely solve the problem of metal contamination.

The crystallization methods such as the MIC method, the MILC method, and the FALC method are effective in lowering the crystallization temperature compared to the SPC method, but the crystallization time is still long, and all of them have in common that the crystallization is induced by the metal. Therefore, it is not free in that it is a problem of metal contamination. On the other hand, the recently developed ELC method makes it possible to produce a polycrystalline silicon thin film on a glass substrate in a low temperature process while solving the problem of metal contamination. The amorphous silicon thin film deposited by LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition) has a very high absorption coefficient for the ultraviolet region (λ = 308 nm), which is the wavelength of the excimer laser. Melt the amorphous silicon thin film easily in density. When the amorphous silicon thin film is crystallized by an excimer laser, the process of melting and solidification is accompanied in a very short time. In this respect, the ELC method is not a low temperature process in the strict sense. However, the ELC process undergoes crystallization by very fast melting and solidification in the local melt zone, which is greatly affected by the excimer laser, resulting in extremely short time (in tens of nano-sec units) without damaging the substrate. Polycrystalline silicon can be produced. That is, when the laser is irradiated on the amorphous silicon of the base material consisting of a glass substrate / insulating layer / amorphous silicon thin film in a very short time, only the amorphous silicon thin film is selectively heated, and crystallization is performed without damaging the glass substrate located below. In addition, in the case of the polycrystalline silicon produced during the phase transformation from the liquid phase to the solid phase, there is an advantage that the crystal structure in the crystal grains and the crystal defects in the crystal grains can be significantly reduced than that of the polycrystalline silicon produced through the solid phase crystallization, ELC Polycrystalline silicon produced by the process is superior to the results of other crystallization methods.

Nevertheless, ELC law has some significant drawbacks. For example, problems in the laser system that the irradiation amount of the laser beam itself is nonuniform, problems in the laser process that the processing area of the laser energy density to obtain coarse grains are extremely limited, and shot marks in large areas It has the problem of remaining. These two factors cause non-uniformity of grain size of the polycrystalline silicon thin film constituting the active layer of the polycrystalline silicon TFT. In addition, polycrystalline silicon produced with a phase transformation from the liquid phase to the solid phase is accompanied by volume expansion, so that a severe protrusion phenomenon occurs toward the surface from the point where the grain boundary is made. This phenomenon also directly affects the gate insulating layer, which is a subsequent process, such as reducing breakdown voltage and hot carrier stress caused by uneven flatness of the polycrystalline silicon / gate insulating layer interface. It has a serious impact on reliability.

Recently, a sequential lateral solidification (SLS) method has been developed to solve the instability of the ELC method described above, and has succeeded in stabilizing the process area of the laser energy density, but still does not solve the phenomenon of shot marks and protrusion toward the surface. In addition, in view of the current trend of rapidly developing flat panel display industry, there is still a problem of using a laser in the crystallization process of a substrate having a size of 1 m x 1 m or more, which will need mass production sooner or later. Moreover, since the equipment for the execution of the ELC method and the SLS method is very expensive, there is a problem that the initial investment and maintenance costs are high.

Therefore, the advantages of the laser crystallization method, i.e., because the process is performed in a short time, it does not damage the underlying substrate, and it is possible to produce very good grains with almost no defects due to high temperature phase transformation. In addition, there is a need for a method of crystallizing an amorphous silicon thin film that can solve the disadvantages of such laser crystallization method, that is, the irradiation non-uniformity and process limitation due to the local process and the problem of using expensive equipment. In particular, active matrix organic light emitting diodes (EL), which are recently attracting much attention in the application of next-generation flat panel displays, are TFT-LCDs, while voltage-driven, but current-driven systems. Grain size uniformity is a very important factor. Therefore, the reality of the flat panel display industry is that the low-temperature crystallization method using the ELC method or the SLS method using a laser hits the limit. Considering this fact, there is a great need for a new technology for producing a high quality polycrystalline silicon thin film by low temperature crystallization using a laserless method.

In order to solve this problem of the prior art, the inventors of the present invention, in Korean Patent Application No. 2004-37952, preheat the silicon thin film at a temperature range where the substrate is not deformed during the process to generate an intrinsic carrier therein. By lowering the resistance to Joule heating, the present invention first proposed a method of crystallization by applying Joule heating by the movement of the carrier by directly applying an electric field to the preheated silicon thin film. This method is very innovative in that it can produce high quality polycrystalline silicon thin film in a short time at relatively low temperature.

In addition, the inventors of the present invention, in Korean Patent Application No. 2005-73076, form an amorphous silicon thin film after forming an ITO layer and an insulating layer, respectively, on an insulating layer on a transparent substrate, and apply an electric field to the ITO layer. By inducing Joule heating, high heat is generated, which results in better crystallization and dopant activation and thermal oxide film at a lower temperature than conventionally, preferably at room temperature, in a very short time without damaging the substrate. We present a method to achieve process and crystal lattice defect healing.

However, due to the potential difference between the amorphous silicon layer and the conductive layer, arc generation due to dielectric breakdown of the insulating layer has been a problem, and a method for effectively preventing the process and simplifying the process is needed.

The present invention provides a method of manufacturing a polycrystalline silicon film capable of effectively preventing arc generation due to dielectric breakdown of the insulating layer due to the potential difference between the amorphous silicon layer and the conductive layer, and simplifying the crystallization process, and manufacturing a thin film transistor including the same. The purpose is to provide a method.

The present invention comprises the steps of forming an amorphous silicon film on top of the substrate; Forming a conductive layer on the amorphous silicon film; And crystallizing the amorphous silicon film by applying an electric field to the conductive layer.

In addition, the present invention comprises the steps of providing a substrate; Forming an amorphous silicon film on the substrate; Forming a conductive layer on the amorphous silicon film; It provides a method for manufacturing a thin film transistor comprising the step of crystallizing the amorphous silicon film by applying an electric field to the conductive layer.

In addition, the present invention comprises the steps of removing the conductive layer; And etching the upper portion of the crystallized silicon film to a predetermined thickness, and a method of manufacturing a thin film transistor including the same.

The present invention also provides a method of manufacturing a polycrystalline silicon film and a method of manufacturing a thin film transistor having the same, wherein the thickness of etching the upper portion of the crystallized silicon film is 100 kW to 500 kW.

The present invention also provides a method of manufacturing a polycrystalline silicon film and a method of manufacturing a thin film transistor having the same, wherein the amorphous silicon film and the conductive layer are in direct contact.

According to the present invention, a method of manufacturing a polycrystalline silicon film that can prevent the occurrence of arc due to dielectric breakdown of the insulating layer due to the potential difference between the amorphous silicon layer and the conductive layer, and can simplify the crystallization process, and includes the same It is effective to provide a method for manufacturing a thin film transistor.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention. In addition, in the drawings, the length, thickness, etc. of layers and regions may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 is a cross-sectional view for explaining a crystallization method by common joule heating.

Referring to FIG. 1, the first insulating layer 11, the amorphous silicon (a-Si) film 12, the second insulating layer 13, and the conductive layer 14 are sequentially formed on the substrate 10. By applying an electric field to the conductive layer 14 to induce Joule heating, high heat is generated to crystallize the amorphous silicon film 12 by the high heat.

The material of the substrate 10 is not particularly limited, and for example, a transparent substrate material such as glass, quartz, plastic, or the like is possible, and in terms of economical efficiency, glass is more preferable.

The first insulating layer 11 is used to prevent elution of an alkali material in some materials inside the substrate 10, for example, a glass substrate, which may be generated in a later process. Oxide (SiO ₂ ) and silicon nitride are formed by evaporation, but the thickness is generally about 2000-5000 Pa, but is not limited thereto. The first insulating layer 11 may be omitted, and the method of the present invention may be applied to such a structure, so the scope of the present invention should be interpreted as including such a structure.

Subsequently, an amorphous silicon film 12 is formed on the first insulating layer 11, and a second insulating layer 13 is formed on the amorphous silicon film 12.

The second insulating layer 13 may serve to prevent the subsequent amorphous silicon film 12 from being contaminated by the conductive layer 14 and to insulate the TFT device during the heat treatment process. The second insulating layer 13 may be formed of the same material as the first insulating layer 11.

Subsequently, a conductive layer 14 is formed on the second insulating layer 13. The conductive layer 14 may be formed of a transparent conductive thin film or a metal thin film.

Next, an electric field is applied to the conductive layer 14. When an electric field is applied to the conductive layer 14, the amorphous silicon film 12 is crystallized by Joule heating.

However, in the case where the amorphous silicon film 12 is crystallized into a polycrystalline silicon layer, the amorphous silicon film 12 and the conductive layer 14 and the second insulating film 13 interposed therebetween may use a capacitor. In this case, when the generated potential difference exceeds the dielectric breakdown voltage of the second insulating layer 13, current may flow through the second insulating layer 13 to generate an arc.

2A to 2D are cross-sectional views illustrating a process of manufacturing a thin film transistor according to a first embodiment of the present invention.

First, referring to FIG. 2A, a first insulating layer 31, an amorphous silicon (a-Si) film 32, and a conductive layer 33 are sequentially formed on the substrate 30, and the conductive layer 33 is formed. ) By applying an electric field to induce Joule heating, high heat is generated, and the amorphous silicon film 32 is crystallized by the high heat.

Specifically, the first insulating layer 31 is formed on a substrate 30 made of glass, stainless steel, plastic, or the like in a single layer or a plurality of layers using an insulating film such as a silicon oxide film or a silicon nitride film. In this case, the first insulating layer 31 serves to prevent the diffusion of moisture or impurities generated from the substrate 30 or to control the heat transfer rate during crystallization so that the amorphous silicon layer can be crystallized well. do.

Subsequently, an amorphous silicon (a-Si) film 32 is formed on the first insulating layer 31.

The amorphous silicon (a-Si) film 32 is formed by, for example, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, PECVD (plasma enhanced chemical vapor deposition), sputtering, vacuum evaporation, or the like. And preferably PECVD method. The amorphous silicon (a-Si) film 32 may be formed to a thickness of 400 to 2000 microns.

Subsequently, a conductive layer 33 is formed on the amorphous silicon (a-Si) film 32.

The conductive layer 33 may be formed of a transparent conductive thin film or a metal thin film. Preferably, the conductive layer 33 is formed of a metal thin film having a melting point of 1100 ° C. or more. In order to crystallize the amorphous silicon film 12 for a very short time of about 0.1 to 300 microseconds, high temperature of 1100 ° C. or more may be applied to the amorphous silicon film 32 at an instant. In order to prevent breakage of the conductive layer 33 at such a high temperature, the conductive layer 33 is preferably formed of a metal thin film having a melting point of 1100 ° C. or more. Examples of the metal having a melting point of 1100 ° C. or more include molybdenum (Mo), titanium (Ti), chromium (Cr), or molybdenum tungsten (MoW).

The conductive layer 33 may be formed by a method such as sputtering or evaporation, and may be formed at 500 kPa to 3000 kPa. But it is not limited to that.

Next, an electric field is applied to the conductive layer 33. When an electric field is applied to the conductive layer 33, the amorphous silicon film 32 is crystallized by Joule heating.

The application of the electric field to the conductive layer 33 is performed by applying energy of a power density that can generate by Joule heating a high heat sufficient to induce crystallization of the amorphous silicon film 32. Since the application of the electric field is determined by various factors such as the resistance, length, and thickness of the conductive layer 33, it is difficult to be specified, but about 100 W / cm ² to 1,000,000 W / cm ² , preferably 1000 W / cm ² to 100,000 W / cm ² .

In this case, the applied current may be DC or AC, and the application time of the electric field may be 1 / 10,000,000 to 1 second, and preferably 1 / 100,000 to 1/10 second. The application of this electric field can be repeated several times in regular or irregular units.

It is preferable to apply the electric field to the conductive layer 33 to the extent that high heat of 1100 ° C. or more occurs. When the crystallization is performed at a high temperature of less than 1100 ° C., crystallization may not be completed by applying a single electric field for a short time of about 1 / 1,000,000 to 1 second. Then, the electric field application process must be repeated several times. In this case, in order to prevent the occurrence of non-uniformity due to accumulated heat, it is necessary to leave the electric field application for several seconds after the electric field application is completed once. As a result, the total process time for crystallization can reach several minutes.

However, when the crystallization is performed at a high temperature of 1100 ° C. or higher, crystallization may be completed by one electric field application, and the time required for one electric field application is very short, such as several hundreds of microseconds. Therefore, when the crystallization is performed at a high temperature of 1100 ° C. or more, the total process time for crystallization can be significantly reduced. In addition, crystallization may be improved by crystallizing a single electric field in a short process time at a high temperature.

Therefore, as described above, in order to ensure stability of the conductive layer 33 at a high temperature of 1100 ° C. or more, the conductive layer 33 is preferably formed of a metal thin film having a melting point of 1100 ° C. or more.

Meanwhile, before applying an electric field to the conductive layer 33, the substrate 30 on which the components 31, 32, and 33 are formed may be preheated to an appropriate temperature range. The appropriate temperature range refers to a temperature range in which the substrate 30 is not damaged throughout the process, and is preferably a range lower than the heat deformation temperature of the substrate 30. The preheating method is not particularly limited, and for example, a method of putting in a general heat treatment furnace, a method of irradiating radiant heat such as a lamp, or the like may be used.

In addition, before applying an electric field to the conductive layer 33, the amorphous silicon film 32 may be doped with n-type or p-type impurities, and a heat treatment process for activating the doped impurities may be performed. Alternatively, after applying the electric field to the conductive layer 33 to form the amorphous silicon film 32 as a Joule heating polycrystalline silicon film, the polycrystalline silicon film may be doped with n-type or p-type impurities, and the doped impurities The heat treatment process for activating may be performed. At this time, phosphorus (P) is preferable as the n-type impurity, and boron (B) is preferable as the p-type impurity.

As described above, in the thin film transistor according to the first embodiment of the present invention, the first insulating layer 31, the amorphous silicon (a-Si) film 32, and the conductive layer 33 are sequentially formed on the substrate 30. A high heat is generated by applying an electric field to the conductive layer 33 to induce Joule heating to crystallize the amorphous silicon film 32 by the high heat.

That is, in the thin film transistor according to the first embodiment of the present invention, the conductive layer 33 is formed on the amorphous silicon (a-Si) film 32 to perform crystallization.

In the crystallization of a thin film transistor having a general structure, an insulating layer was formed on an amorphous silicon (a-Si) film, and after forming a conductive layer on the insulating layer, crystallization was performed by applying an electric field to the conductive layer.

For this reason, in a thin film transistor having a general structure, the amorphous silicon film, the conductive layer, and the insulating film interposed therebetween form a capacitor. When the potential difference exceeds the dielectric breakdown voltage of the insulating film, The current flows through the insulating film to generate an arc. However, in the present invention, since a conductive layer is formed on the amorphous silicon (a-Si) film without crystallization, crystallization is performed, and thus, no capacitor is formed. It is possible to fundamentally prevent the arc generated by the dielectric breakdown voltage of the insulating film.

In addition, in a thin film transistor having a general structure, since a separate insulating film is formed between the amorphous silicon (a-Si) film and the conductive layer, it is formed by a separate manufacturing process, and the insulating film is formed in a separate process in a later step. However, in the present invention, since the process of forming and removing the insulating film is unnecessary, the manufacturing process can be simplified.

2B, the conductive layer 33 is removed. In addition, in the present invention, after removing the conductive layer 33, the upper portion of the crystallized silicon film is partially etched to form the polycrystalline silicon film 32 '.

That is, as described above, in the present invention, the arc generated by the dielectric breakdown voltage of the insulating film is fundamentally prevented and conductively formed on the amorphous silicon (a-Si) film without forming an insulating layer to simplify the manufacturing process. A layer is formed to crystallize. In this case, the upper region of the amorphous silicon film is contaminated by the conductive layer directly contacting the amorphous silicon (a-Si) film.

For this reason, eventually, the upper region of the crystallized silicon film is contaminated by the conductive layer, and accordingly, in the present invention, it is preferable to remove the upper region of the contaminated silicon film to a predetermined thickness.

In this case, it is preferable that the thickness of etching the upper portion of the crystallized silicon film is 100 kPa to 500 kPa. If the etching thickness is less than 100 kPa, there is a problem in that the region contaminated by the conductive layer remains in the crystallized silicon film. When the thickness of the etching exceeds 500 kPa, the surface roughness of the silicon film is increased, resulting in poor device characteristics of the thin film transistor.

However, in order for the polycrystalline silicon layer to function effectively as a semiconductor layer of the thin film transistor, it is preferable that the thickness of the partially etched polycrystalline silicon film 32 ′ is 500 Å or more.

2C, the semiconductor layer 35 is formed by patterning the partially etched polycrystalline silicon film 32 ′. In addition, a gate insulating layer 36 is formed on the semiconductor layer 35, wherein the gate insulating layer 36 may be a silicon oxide layer, a silicon nitride layer, or a double layer thereof.

Subsequently, a single layer of an aluminum alloy such as aluminum (Al) or aluminum-neodymium (Al-Nd) on the gate insulating layer 36, or multiple aluminum alloys are laminated on a chromium (Cr) or molybdenum (Mo) alloy. The gate electrode metal layer (not shown) is formed on the layer, and the gate electrode metal layer is etched by the photolithography process to form the gate electrode 37 in a portion corresponding to the channel region of the semiconductor layer 35.

Next, an interlayer insulating film 38 is formed over the entire substrate including the gate electrode 37. The interlayer insulating layer 38 may be a silicon nitride film, a silicon oxide film, or a multilayer thereof.

Subsequently, the interlayer insulating layer 38 and the gate insulating layer 36 are etched to form a contact hole 39 exposing a predetermined region of a source / drain region of the semiconductor layer 35.

2D, source / drain electrodes 39a and 39b connected to the source / drain regions of the semiconductor layer 35 are formed on the interlayer insulating layer 38 through the contact hole 39.

Thus, the thin film transistor according to the first embodiment of the present invention can be manufactured.

3A to 3C are cross-sectional views illustrating a process of manufacturing a thin film transistor according to a second embodiment of the present invention.

The process of manufacturing the thin film transistor according to the second embodiment of the present invention may be the same as the process of manufacturing the thin film transistor according to the first embodiment of the present invention except for the following.

Referring to FIG. 3A, a buffer layer 51 is formed on the substrate 50. The gate electrode 52 is formed on the buffer layer 51. Subsequently, a gate insulating layer 53 is formed on the entire surface of the substrate 50 including the gate electrode.

Subsequently, an amorphous silicon film 54 and a conductive layer 55 are sequentially formed on the gate insulating film 53. Subsequently, an electric field is applied to the conductive layer 55 to form the amorphous silicon film 54 as a Joule heating polycrystalline silicon film.

As described above, in the thin film transistor according to the second embodiment of the present invention, the conductive layer 55 is formed on the amorphous silicon film 54 to perform crystallization.

As a result, in the present invention, since the conductive layer is formed on the amorphous silicon (a-Si) film without crystallization, crystallization is performed, no capacitor is formed, and therefore, an arc generated by the dielectric breakdown voltage of the insulating film. Can be prevented at the source.

In addition, in the present invention, a process for forming and removing such an insulating film is unnecessary, so that the manufacturing process can be simplified.

5B, the conductive layer 55 is removed. In addition, in the present invention, after removing the conductive layer 55, the upper portion of the crystallized silicon film is partially etched to form the polycrystalline silicon film 54 '.

That is, as in the first embodiment of the present invention, in the second embodiment of the present invention, the upper region of the amorphous silicon film is contaminated by the direct contact of the conductive layer with the amorphous silicon (a-Si) film. It is preferable to remove the upper region of the film, and in this case, the thickness of etching the upper portion of the crystallized silicon film is preferably 100 kPa to 500 kPa.

In addition, in order for the polycrystalline silicon layer to function effectively as a semiconductor layer of the thin film transistor, it is preferable that the thickness of the partially etched polycrystalline silicon film 54 'is 500 Å or more.

Next, referring to FIG. 3C, the partially etched polycrystalline silicon film 54 ′ is patterned to form a semiconductor layer 57.

Subsequently, an ohmic contact material film and a source / drain conductive film are sequentially stacked on the semiconductor layer 57, and the stacked source / drain conductive film and the ohmic contact material film are patterned in order to sequentially source / drain electrodes 59a and 59b and ohmic. An ohmic contact layer 58 is formed. The ohmic contact layer 58 may be an amorphous silicon film doped with an impurity, and the ohmic contact layer 58 may not be formed when an impurity is doped into the semiconductor layer 57.

Thus, the thin film transistor according to the second embodiment of the present invention can be manufactured.

Although the present invention has been shown and described with reference to preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

1 is a cross-sectional view for explaining a crystallization method by common joule heating;

2A to 2D are cross-sectional views illustrating a process of manufacturing a thin film transistor according to a first embodiment of the present invention;

3A to 3C are cross-sectional views illustrating a process of manufacturing a thin film transistor according to a second embodiment of the present invention.

Claims (20)

Forming an amorphous silicon film on the substrate; Forming a conductive layer having a thickness of 500 mV to 3000 mV on the amorphous silicon film; And Applying an electric field to the conductive layer to crystallize the amorphous silicon film at a temperature of 1100 ° C. or higher. The method of claim 1, Removing the conductive layer; And And etching the upper portion of the crystallized silicon film to a predetermined thickness. The method of claim 2, The thickness of etching the upper portion of the crystallized silicon film is a method of producing a polycrystalline silicon film, characterized in that 100 ~ 500Å. The method of claim 1, And the amorphous silicon film and the conductive layer are in direct contact with each other. Providing a substrate; Forming an amorphous silicon film on the substrate; Forming a conductive layer having a thickness of 500 mV to 3000 mV on the amorphous silicon film; And applying an electric field to the conductive layer to crystallize the amorphous silicon film at a temperature of 1100 ° C. or higher. The method of claim 5, And the amorphous silicon film and the conductive layer are in direct contact with each other. The method of claim 5, Removing the conductive layer; And And etching the upper portion of the crystallized silicon film to a predetermined thickness. The method of claim 7, wherein The thickness of etching the upper portion of the crystallized silicon film is a method of manufacturing a thin film transistor, characterized in that 100 to 500Å. The method of claim 7, wherein And forming a semiconductor layer by patterning the crystallized silicon film etched to a predetermined thickness. The method of claim 9, Forming a gate insulating film on the semiconductor layer; Forming a gate electrode on the gate insulating film; Forming an interlayer insulating film on the gate electrode; And And forming a source / drain electrode electrically connected to the source / drain regions of the semiconductor layer on the interlayer insulating layer. The method of claim 5, Forming an amorphous silicon film on the substrate Forming a buffer layer on the substrate; Forming a gate electrode on the buffer layer; Forming a gate insulating film on an entire surface of the substrate including the gate electrode; And And forming an amorphous silicon film on the gate insulating film. The method of claim 11, After applying an electric field to the conductive layer to crystallize the amorphous silicon film, Removing the conductive layer; And And etching the upper portion of the crystallized silicon film to a predetermined thickness. 13. The method of claim 12, The thickness of etching the upper portion of the crystallized silicon film is a method of manufacturing a thin film transistor, characterized in that 100 to 500Å. 13. The method of claim 12, And patterning the crystallized silicon film etched to a predetermined thickness to form a semiconductor layer. The method of claim 14, Sequentially stacking an ohmic contact material film and a source / drain conductive film on the semiconductor layer; And And patterning the stacked source / drain conductive layer and the ohmic contact material layer to form a source / drain electrode and an ohmic contact layer. delete The method of claim 5, The conductive layer comprises molybdenum (Mo), titanium (Ti), chromium (Cr) or molybdenum (MoW) manufacturing method of a thin film transistor. The method of claim 5, The conductive layer is a manufacturing method of a thin film transistor, characterized in that the melting point is more than 1100 ℃. The method of claim 5, And doping an n-type or p-type impurity into the amorphous silicon film before applying an electric field to the conductive layer. The method of claim 5, And applying doping an n-type or p-type impurity to the crystallized silicon film after applying an electric field to the conductive layer.

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