WO2018133407A1 - 一种i/o时刻表及制作方法及输出方法及应用其的设备 - Google Patents

一种i/o时刻表及制作方法及输出方法及应用其的设备 Download PDF

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Publication number
WO2018133407A1
WO2018133407A1 PCT/CN2017/098230 CN2017098230W WO2018133407A1 WO 2018133407 A1 WO2018133407 A1 WO 2018133407A1 CN 2017098230 W CN2017098230 W CN 2017098230W WO 2018133407 A1 WO2018133407 A1 WO 2018133407A1
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time
output
timing
timetable
time segment
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PCT/CN2017/098230
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English (en)
French (fr)
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钱利斌
尤丽英
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钱利斌
尤丽英
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Publication of WO2018133407A1 publication Critical patent/WO2018133407A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels

Definitions

  • the invention relates to an I/O timetable, a manufacturing method thereof, an output method and a device using the same, and belongs to the technical field of inverter control.
  • a multi-level inverter refers to an inverter in which the number of levels in the output voltage waveform of the inverter is equal to or greater than 3, such as a three-level inverter, a five-level inverter, and a seven-level inverter. And so on.
  • main circuit structures can be divided into two main categories: one is a clamped half-bridge structure, and the other is Cascaded structure.
  • PWM Pulse Width Modulation
  • the PWM control method of multi-level inverter is closely related to its circuit structure and working characteristics. Different circuit structures and their working characteristics use different PWM control circuits.
  • the multi-level inverter Compared with the two-level inverter, the multi-level inverter adds some new auxiliary circuits to the circuit structure, making the circuit more complicated, more demanding, and more control targets.
  • the technical problem to be solved by the present invention is to provide an I/O timetable with various application modes, a manufacturing method, an output method, and a device for applying the same.
  • An I/O timetable comprising two or more time segments of an ordered record, the time segment comprising an I/O level parameter and one or a set of I/O time parameters;
  • the I/O level parameter is used to record a level state of each I/O pin that controls the inverter circuit
  • the I/O time parameter is used to record a length of time during which the respective I/O pins of the inverter circuit are continuously in a corresponding level state of the I/O level parameter or time data at which the time length can be calculated.
  • the I/O time parameter can be recorded using a length timing method, that is, using a length of time.
  • the I/O time parameter may use an endpoint timing mode, ie, a start time time and/or a stop time time of a time segment.
  • the endpoint timing mode includes the following types:
  • Endpoint method incremental timing mode the time data of the start time of the time segment is smaller than the time segment
  • Endpoint decrement timing the time data of the start time of the time segment is greater than the time segment
  • the endpoint method reduces the timing mode: only the time data of one endpoint of the time segment is recorded, and the time data of the other endpoint of the time segment is the time data set by the system or the time shared by the time segment set by the system. data.
  • the type of storage manner of the I/O schedule includes storing time segments adopting the same timing mode and storing time segments using multiple timing modes.
  • two or more I/O timetables may be combined to form an I/O schedule, and a composite I/O schedule may include control waveforms of independent modulated and/or non-independent modulated output voltage combinations.
  • An I/O schedule creation method includes the following steps:
  • S1 determining a length of time of one period of the I/O schedule, then dividing the one period into a plurality of the time segments and determining an output level and the I/O time parameter in each of the time segments, And determining a timing unit of the time segment;
  • S2 determining a relationship between a level state of an output voltage of the inverter circuit and a level state of an I/O pin controlled thereto;
  • S3 Establish an association between the I/O time parameter of each of the time segments and the I/O level parameter, and store the I/O timetable.
  • An I/O schedule creation method includes the following steps:
  • S1 determining an output level of the plurality of time segments and the I/O time parameter, and then combining the plurality of time segments in order, and determining a timing unit of the time segment;
  • S2 determining a relationship between a level state of an output voltage of the inverter circuit and a level state of an I/O pin controlled thereto;
  • S3 Establish an association between the I/O time parameter of each of the time segments and the I/O level parameter, and store the I/O timetable.
  • the type of output level comprises: a continuous output level and a continuous combination of output levels; each of said time segments can only correspond to one continuous output level or a continuous output level combination.
  • the storage I/O schedule is stored according to an I/O schedule storage mode and a time segment timing manner
  • the type of the I/O schedule storage manner includes the time segment and the storage using the same timing manner.
  • Storing a time segment using a plurality of timing modes, the type of the time segment timing mode includes: the length timing mode, the endpoint method incremental timing mode, the endpoint method decrement timing mode, and the endpoint method reduced timing mode .
  • the time segment omits the time data set by the storage system and/or omits the time data shared by the time segments set by the storage system when stored in the end point method.
  • An I/O timetable output method includes the following steps:
  • Q1 Specify a time segment of an I/O schedule as a time segment to be output
  • Q2 Set the timing unit of the timing unit to be the same as the timing unit of the time segment to be output, set the timing mode of the timing unit to be the same as the output timing mode of the time segment to be output, and set the initial timing of the timing unit and the start output of the time segment to be output. The same time value;
  • the timing unit performs timing in the timing mode and the timing unit, and outputs an I/O level parameter of the time segment to be output;
  • Q4 The level of the I/O pin that is used to output the I/O level parameter remains unchanged until the time segment being output is timed out;
  • Step Q5 Repeat steps Q2-Q4 to output the next to-be-output time segment obtained by the sequence of the I/O timetable and the I/O timetable output mode specified by the step Q1, and then repeat Execute once Steps Q2-Q4 are used to output the next to-be-output time segment obtained according to the order of the I/O timetable and the I/O timetable output mode of the time segment to be output obtained in the second time, and sequentially output the time segment.
  • step Q2 further comprises the following types of operations:
  • timing unit of the timing unit and the timing unit of the time segment to be output are already the same, omitting the timing unit of the timing unit and the timing unit of the time segment to be output are the same,
  • An I/O timetable output method includes the following steps:
  • Q1 Specify a time segment of an I/O schedule as a time segment to be output
  • Q2 designating a timing unit to time the time segment to be output, setting the timing unit of the timing unit to be the same as the timing unit of the time segment to be output, and setting the timing mode of the timing unit to be consistent with the output timing mode of the time segment to be outputted. Setting an initial timing time of the timing unit and a start output time value of the time segment to be outputted are the same;
  • the timing unit performs timing in the timing mode and the timing unit, and outputs an I/O level parameter of the time segment to be output;
  • Q4 The level of the I/O pin that is used to output the I/O level parameter remains unchanged until the time segment being output is timed out;
  • Step Q5 Repeat steps Q2-Q4 to output the next to-be-output time segment obtained by the sequence of the I/O timetable and the I/O timetable output mode specified by the step Q1, and then repeat Performing a step Q2-Q4 for outputting the next to-be-output time segment obtained according to the order of the I/O time table and the I/O time table output mode of the time segment to be output obtained according to the second time, and sequentially outputting the time segment.
  • step Q2 further comprises the following types of operations:
  • the types of output timing modes of the time segments include an incremental timing mode and a decreasing timing mode.
  • the types of the I/O timetable output manners include:
  • Clockwise output mode output time segments according to the order of time segments in the I/O timetable
  • Counterclockwise output mode output time segments in reverse order of time segments in the I/O timetable
  • the time segment is output in the order agreed upon when the I/O schedule is created.
  • the initial timing of setting the timing unit further includes the following types of setting:
  • each initial value is assigned once;
  • each initial value is assigned once;
  • the method further includes a nested output mode: outputting the I/O schedule in a nested loop manner, outputting a time segment of the I/O schedule in an inner loop, and outputting an I/O schedule in an outer loop.
  • a nested output mode outputting the I/O schedule in a nested loop manner, outputting a time segment of the I/O schedule in an inner loop, and outputting an I/O schedule in an outer loop.
  • a device that uses the above I/O schedule and I/O schedule output method.
  • an I/O schedule creation method is also included.
  • an online calculation function is further included: a new I/O schedule is newly established while outputting the I/O schedule as a control waveform.
  • the invention has the beneficial effects that the application mode is various and the complex control can be completed, especially in the multi-level frequency converter.
  • the patent can be used to replace a large number of analog circuits; Multi-level drive technology for high-voltage inverters can be ported to low-voltage inverters.
  • the invention also has the following application prospects:
  • Figure 1 is a flow chart of an embodiment of the present invention
  • Figure 2 is a waveform diagram of an embodiment of the present invention.
  • Figure 3 is a waveform diagram of one embodiment of the present invention.
  • Figure 4 is a circuit diagram of an embodiment of the present invention.
  • Figure 5 is a schematic view of an embodiment of the present invention.
  • Figure 6 is a schematic view of an embodiment of the present invention.
  • Figure 7 is a schematic view of an embodiment of the present invention.
  • FIG. 8 is a flow chart of a method for outputting an I/O timetable according to the present invention.
  • Figure 9 is a circuit diagram of an embodiment of the present invention.
  • Figure 10 is a schematic view of an embodiment of the present invention.
  • Figure 11 is a waveform diagram of an embodiment of the present invention.
  • Figure 12 is a schematic view of an embodiment of the present invention.
  • Figure 13 is a waveform diagram of an embodiment of the present invention.
  • Figure 14 is a circuit diagram of an embodiment of the present invention.
  • Figure 15 is a schematic view of an embodiment of the present invention.
  • Figure 16 is a waveform diagram of an embodiment of the present invention.
  • Figure 17 is a schematic view of an embodiment of the present invention.
  • Figure 18 is a waveform diagram of an embodiment of the present invention.
  • Figure 19 is a circuit diagram of an embodiment of the present invention.
  • Figure 20 is a schematic illustration of one embodiment of the present invention.
  • Figure 21 is a waveform diagram of one embodiment of the present invention.
  • An I/O timetable includes two or more time segments recorded in sequence, the time segment including an I/O level parameter and one or a set of I/O time parameters, wherein Table 1 shows the I/O timetables that are clocked using the endpoint timing:
  • the I/O level parameter is used to record the level state of the two I/O pins P1.1 and P1.0 of the control inverter circuit.
  • the level of the I/O pin is The state adopts 1 and 0 respectively to indicate a high and low state;
  • the I/O time parameter is used to record two I/O pins P1.1 and P1.0 of the control inverter circuit at the I/O level parameter.
  • the time data of the two endpoints of the corresponding continuous state of the level state can be calculated by simple subtraction.
  • the inverter circuit of the present invention is Refers to the inverter main circuit, or the inverter main circuit and its auxiliary circuits.
  • the ordered recording refers to recording a time segment according to the order of outputting the time segments in the forward direction or the order of outputting the time segments in the reverse direction, and may also refer to the recording of the time segments in the order agreed with the output method of the I/O time table.
  • Table 2 is an I/O time table using a length timing method for recording two I/O pins P1.1 and P1.0 of the control inverter circuit at the I/O power The time-length data of the continuous duration of the level state corresponding to the level parameter.
  • Time slice 1 1806 1 Time segment 2 1571 0 0 Time slice 3 1806 1 0
  • the endpoint timing mode includes the following types:
  • Endpoint method incremental timing mode as shown in Table 1, the time data of the start time of the time segment is smaller than the time data of the termination time of the time segment;
  • End point method decrement timing mode the time data of the start time of the time segment is greater than the time data of the end time of the time segment, that is, the size of the time end point in Table 1 is reversed;
  • the endpoint method reduces the timing mode: only the time data of one endpoint of the time segment is recorded, and the time data of the other endpoint of the time segment is the time data set by the system or the time data shared by the time segment set by the system, Table 1 As shown, any two adjacent time segments, the start time of the latter time segment and the end time of the previous time segment are equal, then the two equal time data only need to store one of them, and the first The start time of each time segment is 0, and the I/O time table shown in Table 1 is reduced to become the I/O time table shown in Table 3.
  • Table 3 is an I/O schedule that uses the endpoint method to streamline timing.
  • two or more I/O timetables can synthesize an I/O schedule, and the synthesized I/O schedule first needs to expand the I/O schedule, and the extended I/O schedule is A time segment in the order of the time segments of the I/O schedule is added in front of or behind the I/O schedule.
  • the period of the two I/O timetables is extended to at least the time length of the least common multiple of the two I/O timetable periods; the I/O timetable The period refers to the length of time of the I/O schedule, which is the cumulative sum of the lengths of all time segments in the I/O schedule; if two I/O schedules have the same period, the I/O schedule cannot be extended.
  • the time period (time node or time length) of the two extended I/O timetables are respectively projected onto the same time axis; in the overlapping area of the two I/O timetables, 2 I
  • the time node of the /O time table is re-segmented to form a new time segment, each time segment containing level parameters from corresponding time segments of two I/O time tables; the first time node of two I/O time tables It may be coincident or offset; the time length of the least common multiple of the overlap region is taken as one period of the synthesized I/O schedule.
  • a composite I/O schedule may include a control waveform of an output voltage combination of independent modulation and/or non-independent modulation.
  • the output voltage combination refers to an output voltage of 2 or more phases, as shown in FIG. 2, two phases.
  • the modulation process of the output voltage is independent of each other.
  • the types of storage methods of the I/O schedule include storing time segments using the same timing mode and storing time segments using a plurality of timing modes.
  • the time segment in which the same timing mode is stored means that the time segment stored in the I/O timetable adopts a timing mode.
  • each time segment in the I/O timetable adopts the endpoint method to increase the timing mode.
  • the storage of time segments using multiple timing methods means that the time segments stored in the I/O timetable adopt different timing methods, as shown in Table 4. In the first four time segments in Table 4, the endpoint method is used to increase the timing mode. The next four time segments use the endpoint method to count down.
  • Time slice 6 6048 4477 0 0
  • Time slice 7 4477 2671 0 1
  • Time segment 8 2671 0 0 0
  • the time segment timing mode includes: the length timing mode, the endpoint method incremental timing mode, the endpoint method decreasing timing mode, and the endpoint method reduced timing mode, that is, a time segment may adopt a length timing manner or Endpoint method incremental timing mode or endpoint method decrement timing method or endpoint method streamlined timing mode.
  • An I/O schedule creation method includes the following steps:
  • FIG. 3 A specific example is shown in Figure 3.
  • a sinusoidal signal wave with a period of 15708 microseconds. Take a complete sinusoidal signal wave period as the length of time of an I/O timetable.
  • a method of sinusoidal signal wave and triangular carrier comparison is employed to divide time segments.
  • the sine wave is larger than the triangular wave, the output voltage is E; the sine wave is smaller than the triangular wave, and the output voltage is zero.
  • the sine wave is smaller than the triangular wave, the output voltage is -E; the sine wave is larger than the triangular wave, and the output voltage is zero.
  • the output voltage u AB has three output levels: +E, 0, and -E. These three levels are distributed over 8 time segments, so a period is divided into at least 8 time segments. .
  • Table 5 is a comparison table of the I/O time parameters and the level state relationship of the output voltage u AB listed in the "length method" of Fig. 3, and the timing unit is 1 microsecond.
  • the single-phase sinusoidal signal wave shown in Figure 3 if pulse width modulation is used, the inverter circuit shown in Figure 4 is controlled.
  • the preferred carrier ratio is 15-30. This value can be used to divide other SPWM controls. Waveform reference.
  • S2 determining the relationship between the level state of the output voltage of the inverter circuit and the level state of the I/O pin controlled thereto; that is, determining the level or level combination of each output of the inverter circuit to be used for output a level state or a level combination state corresponding to all I/O pins for controlling the inverter circuit to output the level or level combination;
  • FIG. 4 An example of a single-phase full-bridge inverter circuit is provided. Other inverter circuits can be implemented by referring to it. As shown in FIG. 4, the relationship between the level state of the output voltage u AB and the state of each inverter tube is as shown in Table 6. . S1 and S4 are turned on, S2 and S3 are turned off, then u AB is E; S1, S2, S3, and S4 are off, then u AB is 0; S1 and S4 are off, and S2 and S3 are on, then u AB is -E.
  • Table 7 shows the relationship between the level state of each I/O pin of the inverter circuit (that is, the I/O level parameter in this design) and the state of the inverter tube of the single-phase full-bridge inverter circuit.
  • Table 6 the relationship between the level state of the output voltage u AB and the state of the inverter tube is obtained, and the relationship between the I/O level parameter and the state of the inverter tube is obtained according to Table 7, so that the level state of the output voltage u AB can be obtained.
  • Table 8 is a table of the relationship between the level state of the output voltage u AB and the I/O level parameter.
  • Table 8 shows the relationship between the level state of the output voltage u AB and the I/O level parameters.
  • S3 Establish an association between the I/O time parameter of each of the time segments and the I/O level parameter, and store the I/O timetable.
  • the I/O time parameter is associated with the level state of the output voltage u AB
  • the level state of the output voltage u AB is associated with the I/O level parameter
  • Level parameters are associated. Each time segment can only have one continuous output level or output level combination. Similarly, each time segment can only have one I/O level parameter.
  • the relationship table between the I/O time parameter and the I/O level parameter shown in Table 9 is called an I/O time table.
  • the type of output level comprises: a continuous output level and a continuous combination of output levels; each of said time segments can only correspond to one continuous output level or a continuous output. Level combination.
  • the storage I/O schedule may be stored according to an I/O schedule storage mode and a time segment timing manner, and the type of the I/O schedule storage manner includes the storage using the same timing.
  • the type of the time segment timing mode includes: the length timing mode, the endpoint method incremental timing mode, the endpoint method decrement timing mode, and
  • the endpoint method is a streamlined timing method.
  • the I/O timetable shown in Table 9 stores time segments in the same timing mode, which uses the endpoint method to increment the timing mode;
  • the I/O timetable shown in Table 4 stores the time in multiple timing modes. Fragment, the time segment adopts the endpoint method incremental timing mode and the endpoint method decrement timing mode; the specific method is selected according to actual needs.
  • the time data set by the storage system is omitted and/or the time data shared by the time segment set by the storage system is omitted.
  • Table 9 The I/O schedule shown in Table 9 is reduced to become the I/O schedule shown in Table 10.
  • Table 10 is an I/O schedule that uses the same endpoint method to streamline timing.
  • Table 10 shows the use of the same endpoint method to streamline timing I/O timetables.
  • the output voltage is E/2
  • the DC voltage can be used to output the equivalent E/2 DC voltage when the interval output level is E and the output level is equal to 0, and the time for outputting E or 0 is 1000.
  • Microseconds thus obtaining 2 I/O time parameters and time segments determined by the output level. If two sets of the above time segments are combined in order, the I/O time parameters and outputs shown in Table 11 can be obtained.
  • the voltage level state relationship table of the voltage, the timing unit is 1 microsecond.
  • the type of output level comprises: a continuous output level and a continuous combination of output levels; each of said time segments can only correspond to one continuous output level or a continuous output. Level combination.
  • the storage I/O schedule may be stored according to an I/O schedule storage mode and a time segment timing manner, and the type of the I/O schedule storage manner includes the storage using the same timing.
  • the type of the time segment timing mode includes: the length timing mode, the endpoint method incremental timing mode, the endpoint method decrement timing mode, and
  • the endpoint method is a streamlined timing method.
  • the time data set by the storage system is omitted and/or the time data shared by the time segment set by the storage system is omitted.
  • the equivalent value of the output voltage is changed by changing the length of the corresponding output slice to change the pulse width ratio of the corresponding output level.
  • the waveform of the output voltage is changed by changing the pulse width of each output level by proportionally changing the length of time of each time segment.
  • An I/O timetable output method includes the following steps:
  • Q1 Specify the time segment of an I/O timetable as the time segment to be output; therefore, it is flexible to select the time segment of any time segment as the first output to meet different needs;
  • the timing unit of the timing unit is the same as the timing unit of the time segment to be output, set the timing mode of the timing unit to be the same as the output timing mode of the time segment to be output, and set the initial timing of the timing unit and the start output of the time segment to be output.
  • the time value is the same;
  • the timing unit is a schematic description, which may be a timed software program, or a timed hardware, or a combination of timed software and hardware, which can be selected according to needs;
  • the chronograph time can be not less than the chronograph time of the time segment, and can be timed for a plurality of time segments; the I/O timetable output method in the embodiment has only one timing unit for time segment counting.
  • an output time segment (time segment 1) of the I/O time table shown in Table 4 is outputted in an incremental timing manner, and the time unit of the time parameter of the time segment to be outputted is 1 microsecond, so the timing of the timing unit is set.
  • the unit is 1 microsecond;
  • the output timing mode of the output time segment is the incremental timing mode, so the timing mode of setting the timing unit is the incremental timing mode;
  • the output timing mode of the output time segment is the incremental timing mode, then the start time of the time segment The time is 0, so the timing of setting the timing unit is 0;
  • the time segment is used to reduce the time segment of the time mode, and only the time data of one end point of the time segment is recorded, and the time data of the other end point of the time segment is the time data set by the system or the time shared by the time segment set by the system. Data, so it is necessary to obtain time data that is omitted for storage according to the production method.
  • the time segment of the length method is used to output the time segment, which is processed by the time segment of the end point method, and the time length data is used as the time data of one end point of the time segment, and the time data of the other end point is 0 or other Data selected as needed;
  • the timing unit performs timing in the timing mode and the timing unit, and outputs an I/O level parameter of a time segment to be outputted; the output I/O level parameter refers to an I/O level parameter. Values are output from each corresponding I/O pin.
  • Q4 The level of the I/O pin that is used to output the I/O level parameter remains unchanged until the time segment being output is timed out;
  • the time segment being output refers to the time segment of the level state immediately after the I/O level parameter is output and is being held by each corresponding I/O pin; the output to be output is output in step Q3.
  • the I/O level parameter of the time segment, the time segment to be output is converted into the time segment being output;
  • the time data of one end of the time segment is assigned to the timing unit, and when the time of the timing unit reaches the time of the other end of the time segment, the time segment is timed out.
  • step Q5 Repeat steps Q2-Q4 to output the next to-be-output time segment obtained by the sequence of the I/O timetable and the I/O timetable output mode specified by the step Q1, and then repeat Performing a step Q2-Q4 for outputting the next to-be-output time segment obtained according to the order of the I/O time table and the I/O time table output mode of the time segment to be output obtained according to the second time, and sequentially outputting the time segment. .
  • the time segment to be output is obtained for the first time in step Q1, and the steps Q2-Q4 are performed once, and the time segment to be output specified in step Q1 is outputted, if step Q1 is specified.
  • the time segment 1 is the time segment to be output, and the I/O time table output mode is the clockwise output mode, then the second time segment to be outputted is the time segment 2, and the third time segment to be output is the time segment. 3, ... and so on; if step Q1 specifies that time segment 1 is the time segment to be output, but the I/O time table output mode is counterclockwise output mode, the second time segment to be outputted is time segment 8, The time slice to be output obtained for the third time is time segment 7, ... and so on. In actual use, it is possible to confirm whether to stop the output I/O timetable during the output of the I/O timetable, and continue to output after confirming that it does not stop.
  • step Q2 also includes the following types of operations:
  • timing unit of the timing unit and the timing unit of the time segment to be output have been the same, omitting the timing unit of the timing unit and the timing unit of the time segment to be output are the same;
  • timing mode of the timing unit and the output timing mode of the time segment to be output have been consistent, the timing mode of omitting the setting of the timing unit is consistent with the output timing mode of the time segment to be outputted;
  • the types of output timing modes of the time segments include an incremental timing mode and a decreasing timing mode
  • the incremental timing mode refers to counting the I/O time parameter with a small time data of the time segment to the I/O time parameter with a large time data; the decrement timing method refers to comparing the time data from the time data. Large I/O time parameters are clocked to I/O time parameters with small time data.
  • the size of the I/O time parameter can be determined by addition and subtraction, and then an I/O time parameter is used as the start time of the time segment and another I/O time parameter is used as the time segment output timing mode.
  • the time segment is used to reduce the time segment of the time mode, and only the time data of one end point of the time segment is recorded, and the time data of the other end point of the time segment is the time data set by the system or the time shared by the time segment set by the system.
  • the data can be obtained according to the production method, and the time segment that is omitted for storage can also be timed by using the incremental timing method or the decreasing timing method.
  • the time segment using the length timing method imitating the time segment using the endpoint method to streamline the timing
  • the time length data is used as the time data of one of the end points of the time segment, and the time data of the other end point is 0 or other data selected according to the need, so the time segment using the length timing mode can also adopt the incremental timing mode or the decrement timing.
  • the I/O schedule output manner includes:
  • Clockwise output mode output time segments according to the order of time segments in the I/O timetable, and the output sequence of the time segments is as shown in FIG. 5;
  • Counterclockwise output mode output time segments according to the reverse order of time segments in the I/O timetable, and the output sequence of the time segments is as shown in FIG. 6;
  • the time segment is output in the order agreed upon when the I/O schedule is created, for example, when the I/O schedule is created and the I/O schedule output method is agreed: the order of the output time segments is 1, 3, 5, 2, 4, 6..., then the order of the I/O timetable output method output time segments is 1, 3, 5, 2, 4, 6, ....
  • the initial timing of setting the timing unit further includes the following types of settings:
  • each initial value is assigned once; that is, the initial timing of each time segment is set, and each time segment timing time is mutually Independent, as shown in Figure 7;
  • each initial value is assigned once; an I/O timetable output cycle refers to the I/O time. a process in which all time segments in the table are outputted once; in the process of outputting the I/O timetable, any two adjacent time segments starting from the fixed time segment are temporally continuous, so After the initial time value of the fixed time segment is assigned, the remaining time segments of the output I/O time table need not be assigned an initial value, and the time duration of the two time segments refers to the end output time of the time segment of the previous output and after The output time of an output time segment is equal; if there are consecutive time segments, but not all consecutive, the time segments that are not continuous with the time segment of the previous output need to be assigned initial values.
  • the initial value is assigned once, and the subsequent output time segment does not need to be assigned an initial value.
  • This method is applicable to the I/O timetable in which all time segments are time-finding; in the output I/O In the process of the timetable, all time segments adopt the same output timing mode, and any adjacent two time segments starting from a fixed time segment are temporally continuous; time parameters of the I/O timetable are performed.
  • the accumulation or subtraction operation that is, the time length of an I/O schedule period is added or subtracted from the time parameter of the time segment when the output of a time segment is completed.
  • the timing time of the timing unit is set to 0 at the beginning of the time segment 1, and the output time segment 2-8 is not assigned the initial value, but one output is output each time.
  • the time parameter of the time segment is added with 15708 (the length of time of an I/O timetable period) as the time parameter of the next output of the time segment.
  • the method further includes a nested output mode: as shown in FIG. 8, outputting the I/O schedule in a nested loop manner, and outputting a time segment of the I/O schedule in an inner loop, Cyclic output I/O timetable, both can run simultaneously in parallel, thus saving program space and good versatility.
  • a nested output mode as shown in FIG. 8, outputting the I/O schedule in a nested loop manner, and outputting a time segment of the I/O schedule in an inner loop, Cyclic output I/O timetable, both can run simultaneously in parallel, thus saving program space and good versatility.
  • the preferred way is: when storing the I/O timetable, all time segments adopt the same timing unit and the same timing mode, and all time segments in the endpoint method are continuous in time; in the output I/O All time segments use the same output timing method for the timetable.
  • An I/O timetable output method includes the following steps:
  • Q1 Specify the time segment of an I/O timetable as the time segment to be output; therefore, it is flexible to select the time segment of any time segment as the first output to meet different needs;
  • Q2 designating a timing unit to time the time segment to be output, setting the timing unit of the timing unit to be the same as the timing unit of the time segment to be output, and setting the timing mode of the timing unit to be consistent with the output timing mode of the time segment to be outputted.
  • the initial timing time of the timing unit is set to be the same as the start output time value of the time segment to be outputted; the timetable of the timing unit is not less than the time of the time segment, and the time segments of the time segment can be timed; there are several timing units for the time. Fragment timing, so specify a timing unit to time the time segment to be output. For example, different timing units have different timing units, which can respectively time different time segments of the timing unit. Different timing units have different timing modes, which can be separately Timing of time segments with different output timing modes, ... can be selected as needed.
  • the timing unit performs timing in the timing mode and the timing unit, and outputs an I/O level parameter of the time segment to be output.
  • Q4 The level of the I/O pin that is used to output the I/O level parameter remains unchanged until the time segment being output is timed out;
  • Step Q5 Repeat steps Q2-Q4 to output the next to-be-output time segment obtained by the sequence of the I/O timetable and the I/O timetable output mode specified by the step Q1, and then repeat Performing a step Q2-Q4 for outputting the next to-be-output time segment obtained according to the order of the I/O time table and the I/O time table output mode of the time segment to be output obtained according to the second time, and sequentially outputting the time segment. .
  • step Q2 also includes the following types of operations:
  • the types of output timing modes of the time segments include an incremental timing mode and a decreasing timing mode.
  • the I/O schedule output manner includes:
  • Clockwise output mode output time segments according to the order of time segments in the I/O timetable
  • Counterclockwise output mode output time segments in reverse order of time segments in the I/O timetable
  • the time segment is output in the order agreed upon when the I/O schedule is created.
  • the initial timing of setting the timing unit further includes the following types of settings:
  • each initial value is assigned once;
  • each initial value is assigned once;
  • the method further includes a nested output mode: outputting the I/O schedule in a nested loop manner, outputting a time segment of the I/O schedule, and outputting an I/O schedule. .
  • This embodiment provides a specific application example of controlling a three-phase two-level half-bridge inverter circuit using the SPWM mode.
  • the circuit shown in FIG. 9 is a three-phase two-level half-bridge inverter circuit, and three half-bridges are respectively used.
  • the dotted line indicates that S1, S2, S3, S4, S5 and S6 are inverter tubes, D1, D2, D3, D4, D5 and D6 are freewheeling tubes, u AO is the voltage of terminal A relative to the O terminal, u BO is The voltage at the B terminal relative to the O terminal, u CO is the voltage at the C terminal relative to the O terminal. E is the DC supply voltage, and O is the midpoint voltage of E.
  • FIG. 9 there are six inverter tubes, and six I/O pins are used to control six inverter tubes.
  • Figure 10 shows the control relationship of the I/O pin to the inverter tube of the inverter circuit. When the I/O pin outputs a high level, the corresponding controlled inverter tube is turned on, when the I/O pin output is low. The corresponding controlled inverter tube is cut off at the level.
  • Fig. 11 there are three sinusoidal signal waves of the same period, and a complete sine wave period is taken as the length of time of one cycle.
  • a method of comparing a sinusoidal signal wave with a triangular carrier is used to divide the time segments.
  • the output voltage In the portion where the sine wave is larger than the triangular wave, the output voltage is E/2; in the portion where the sine wave is smaller than the triangular wave, the output voltage is -E/2.
  • Table 13 is a relationship table of the relationship between the I/O time parameter of one cycle and the level state of the output voltage combination according to the I/O time table listed in Fig. 11, and the timing unit is 1 microsecond.
  • the output mode of the I/O time table adopts a clockwise output mode, and the output mode of the time segment adopts a decrement time mode.
  • Q1 Specify time segment 1 as the time segment to be output; flexiblely select the time segment of any time segment as the first output;
  • the timing unit performs timing in the timing mode and the timing unit, and outputs an I/O level parameter of the time segment to be output; and outputs the I/O level parameter from P1.5-P1.0;
  • Q4 The level state of the I/O pin for outputting the I/O level parameter is kept unchanged until the time segment is timed out; in this embodiment, the timing of the timing unit is waited for by the decreasing timing mode.
  • the time parameters of the I/O timetable shown in Table 15 are also changed accordingly, and the output time of the corresponding level output by the inverter circuit shown in FIG. 9 is also It will change, thus affecting the pulse width ratio of each level state of the output voltage, so the effective value of the output voltage can be changed by the I/O time table.
  • the period of the I/O timetable shown in Table 15 also changes accordingly, and the period of the output voltage of the inverter circuit shown in FIG. 9 also changes accordingly, so The period of the output voltage is changed by the I/O timetable.
  • Figure 12 shows a SVPWM mode vector diagram using vector synthesis. This method divides the circumference into small segments and alternates them with adjacent voltage vectors so that the resultant vector is equivalent to the chord of the arc. To approximate this small arc, so that it continues to switch to form a regular polygon that approximates a circle.
  • the circle drawn with a dotted line in Figure 12 represents a circular rotating magnetic field.
  • the circumference is equally divided into six small segments, each of which is outputted by a 7-segment method, and the time segments having the same output voltage vector and adjacent time segments are combined to obtain 36 time segments.
  • Figure 13 is a waveform diagram of the output voltage of the vector diagram shown in Figure 12.
  • Table 16 is the time of one cycle listed according to Figure 13.
  • a comparison table of the relationship between the level parameter and the output voltage level, the following table is Table 16:
  • the magnetic flux trace circle is equally divided into several small segments (multiples of 6), and the preferred number of segments is 12-30.
  • Table 17 is a comparison table of the state of the inverter tube and the state of the I/O pin level corresponding to the eight voltage vectors.
  • the time parameters of the I/O timetable shown in Table 18 are also changed accordingly, and the output time of the corresponding voltage vector outputted by the inverter circuit shown in FIG. It will also change, thus affecting the ratio of the output time of each voltage vector, so the effective value of the output output voltage can be changed by the I/O timetable.
  • the period of the I/O timetable shown in Table 18 also changes accordingly, and the period of the output voltage of the inverter circuit shown in FIG. 9 also changes accordingly,
  • the period of the output output voltage can be changed by the I/O time table.
  • three diode-clamped three-level inverter units are each marked with a dashed box.
  • S1, S2, S3, and S4 are inverter tubes
  • D1 and D2 are clamp diodes
  • D3, D4, D5, and D6 are freewheeling diodes.
  • each element functions as the inverter unit.
  • the A terminal, the B terminal, and the C terminal are output terminals of three inverter circuits, respectively, and output voltages U AO , U BO , and U CO .
  • E is the DC supply voltage applied to the three half-bridge inverter circuits.
  • C1 and C2 are DC voltage dividing capacitors.
  • the inverter tubes S1 and S3, S2 and S4, S5 and S7, S6 and S8, S9 and S11, S10 and S12 operate in a complementary state to constitute six pairs of complementary inverter tubes.
  • the control of 12 inverter tubes is realized by 6 I/O pins, that is, each I/O pin controls a pair of complementary inverter tubes.
  • Figure 15 shows the control relationship of the I/O pin to the inverter tube of the inverter circuit. When P1.5 outputs a high level, S1 is turned on and S3 is turned off. When P1.5 outputs a low level, S1 is turned off. S3 is turned on, and the control methods of the remaining I/O pins are the same.
  • a method of comparing sinusoidal signal waves with in-phase stacked triangular carriers is used to divide time segments.
  • the sine wave is larger than the triangular wave, the output voltage is E; the sine wave is smaller than the triangular wave, and the output voltage is zero.
  • the sine wave is smaller than the triangular wave, the output voltage is -E; the sine wave is larger than the triangular wave, and the output voltage is zero.
  • a relationship table between the I/O time parameter of one cycle of the I/O timetable and the level state of the output voltage combination can be listed, as shown in Table 19 below, and the timing unit is 1 micro. second.
  • Table 20 is a table of the relationship between the level state of the output voltage of the inverter circuit, the state of the inverter tube, and the I/O level parameter.
  • a specific application example of the three-phase diode clamp three-level half-bridge inverter circuit shown in Fig. 14 is controlled by the SVPWM mode using the vector synthesis method.
  • Figure 17 shows a three-level three-phase vector diagram of SVPWM mode using vector synthesis. This method divides the circumference into small segments and alternates them by three voltage vectors surrounding the reference phasor. Vector equivalent The chord of the arc, to approximate this small arc, so that it continues to switch to form a regular polygon that approximates a circle.
  • the circle drawn with a dotted line represents a circular rotating magnetic field, taking a complete circular rotating magnetic field cycle as a cycle. Length of time.
  • FIG. 18 is a waveform diagram of the output voltage of the vector diagram shown in FIG.
  • a comparison table of the relationship between the I/O time parameter of one cycle of the I/O timetable and the level state of the output voltage combination is shown in FIG. 18, as shown in Table 22 below, and the timing unit is 1 microsecond:
  • the embodiment provides a specific implementation manner of using the SPWM mode control for the three-phase 2H bridge cascade inverter circuit in the cascade inverter circuit, and other cascade inverter circuits can be implemented by referring to this embodiment, and the specific circuit is as shown in FIG. 19 .
  • three 2H bridge cascade inverter circuits are respectively marked with a broken line frame.
  • S1 to S8 are inverter tubes, and D1 to D8 are freewheeling diodes.
  • S1 to S24 are inverter tubes.
  • the A terminal, the B terminal, and the C terminal are output terminals of three 2H bridge cascades, respectively.
  • E is the DC power supply voltage applied to the three 2H bridge cascade inverter circuits, and the two DC power supplies are independent of each other.
  • Figure 20 shows the control relationship between I/O pins and inverter tubes. When the I/O pin outputs a high level, the corresponding controlled inverter tube is turned on. When the I/O pin outputs a low level, the corresponding controlled inverter tube is turned off.
  • the three-phase 2H bridge cascade circuit waveform has three sinusoidal signal waves of the same period, and takes a complete sine wave period as the length of one cycle.
  • a comparison table of the relationship between the I/O time parameter of one cycle of the I/O time table and the level state of the output voltage combination is shown in FIG. 21, see Table 25 below, and the timing unit is 1 microsecond:
  • negative 0 is an abbreviation for the reverse bypass output 0 level
  • positive 0 is an abbreviation for the forward bypass output 0 level.
  • the invention has the beneficial effects that the application mode is various, and the complicated control can be completed, especially in the multi-level frequency converter.
  • the patent can replace a large number of analog circuits; Multi-level drive technology for high-voltage inverters can be ported to low-voltage inverters.
  • An inverter device wherein the inverter device adopts the above I/O timetable and an I/O timetable output method, and the inverter device may include: an inverter power supply, a frequency converter, an inverter, and the like, which require inverter control
  • the device in which the inverter and the frequency converter are applied more, provides an embodiment of the inverter, and all the inverter devices used fall within the protection scope of the present invention.
  • an I/O schedule creation method is also included.
  • an online calculation function is further included: while the I/O schedule is output as a control waveform, a new I/O schedule is newly established, and efficiency is improved, and continuous output can be realized.
  • the communication function further comprises: a protocol for communicating with an external device, which can receive commands and data of the external device, and is convenient for transmission of control commands with other controllers or lower machinery, and can adopt various existing connection buses and protocols. According to the specific needs, the choice is not made.
  • the I/O timetable of the present invention and the output method thereof use the I/O level parameter to control the level state of the I/O pin, and then control the conduction state of the inverter tube through the level state of the I/O pin.
  • the I/O time parameter is used to control the length of time that the I/O pin is continuously in the corresponding level state, thereby controlling the length of time that the inverter tube continues for a corresponding state continuously, so the method of the present invention is suitable for control adoption.
  • Inverter circuit that turns on and off the inverter.
  • the method of the present invention can be used to control the equivalent output voltage of the inverter circuit to output different control modes
  • the method of the present invention can be used to control the output voltage of the inverter circuit to output different frequencies;
  • the output voltage of different effective values or the flux linkage of different amplitudes is used as a reference, and the method of the invention can be used to control the equivalent output voltage of the inverter circuit to output different effective values;
  • the invention also has the following application prospects:
  • An air compressor runs all day, the load conditions vary from day to day, and the air compressor starts and stops frequently, and I want to carry out the transformation.
  • Inverter design Set several levels according to the output power of the air compressor. The highest level of output power is higher than the maximum load of the air compressor. The lowest level of output power is lower than the minimum load of the air compressor. Levels are preferred I/O timetables;
  • the air compressor Under actual working conditions, use the air compressor to test several I/O timetables, collect the energy consumption indicators of each I/O timetable that meets the set requirements, and select the I/ with the lowest energy consumption index.
  • the O timetable is a preferred I/O timetable; the output requirement is that the output power of the air compressor is within a certain level range; the same method is used for other output power levels to optimize the I/O timetable.
  • the I/O timetable with the output power higher is switched; if the I/O time is being output If the output power corresponding to the table is higher than the current load and exceeds the set time, the I/O schedule with the output power lower is switched.
  • a machine requires five types of motor output and five types of torque for each speed
  • Inverter design Stores I/O timetables corresponding to five types of speeds, and each speed stores an I/O timetable corresponding to five types of torques. When outputting, the I/O timetable is specified according to the speed and torque requirements.
  • the requirement of a certain equipment for the motor is that the range of the speed change is large and the load variation range is large.
  • Inverter design scheme 1 store a large number of I / O timetables, corresponding to different speeds and loads.
  • Inverter design scheme 2 Using the I/O timetable calculation method, using high-performance computing chips for real-time computing.
  • Inverter design scheme 3 The inverter device is used as an output platform, and an I/O timetable is produced by means of an external computing device.
  • the inverter device receives an externally input I/O timetable, and then outputs the output method.
  • Inverter design Adopt quantitative control to control both speed and running time. Slowly accelerate at the beginning of the start. After reaching a certain speed, it will remain unchanged, and slowly decelerate after reaching a certain time. According to the above analysis, several corresponding I/O timetables are created in the order of output speed, and the output time or output quantity of each I/O timetable is specified, and the output I/O is output in order and corresponding time. Timetable.
  • the motor speed can be estimated by theoretical value or empirical value. If the motor speed exceeds the reasonable range, there is an abnormality. If the I/O timetable has been output for some time, the motor can be inferred. The number of revolutions. Taking the electric vehicle in motion as an example, if the actual speed does not reach the reasonable speed that the output I/O timetable should have, it can be judged that the vehicle has an abnormality.
  • a device requires three motors to operate together, and one or more of the motors are operated at the same time.
  • Inverter design I/O timetable superposition method is used to prepare I/O timetables for each motor. When outputting, the I/O timetable of the motor to be run is superimposed and then output superimposed. After the I / O timetable.
  • the I/O time table and its output method are used to control the multi-level inverter circuit and use I/O time
  • the table controls the 2-level inverter circuit method as well, and the control is convenient.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.

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Abstract

一种I/O时刻表、制作方法及输出方法及应用其的设备，I/O时刻表包括两个或两个以上有序记录的时间片段，时间片段包含一个I/O电平参数和一个或者一组I/O时间参数；I/O电平参数用于记录控制逆变电路的各个I/O引脚的电平状态；I/O时间参数用于记录控制逆变电路的时间数据，使用方便，改变I/O时刻表即可改变控制波形，通过改变控制波形可以改变控制方式，也可以改变输出频率，可以应用SPWM、SVPWM和直流PWM的控制，通用性好，应用其方法的设备可以实现一机多种方式的控制，可以应用于单相、两相、三相及三相以上的控制，可以应用于两电平和多电平的控制，有利于制作标准化元件。

Description

一种I/O时刻表及制作方法及输出方法及应用其的设备 技术领域
本发明涉及一种I/O时刻表及制作方法及输出方法及应用其的设备，属于逆变控制技术领域。
背景技术
当代的逆变技术，有两种研究方向，一种是两电平研究方向，另一种是多电平研究方向。多电平逆变器是指这种逆变器输出电压波形中的电平数等于或大于3的逆变器，如三电平逆变器、五电平逆变器和七电平逆变器等。
现在已经形成了几种典型的多电平逆变器主电路的结构形式，这些主电路结构形式从原理上可以分为两大类：一类是钳位式半桥结构形式，另一类是级联式结构形式。
多电平逆变器的PWM(Pulse Width Modulation)控制法主要有三类：即载波调制法、消除特定谐波法和空间电压相量调制法。
多电平逆变器的PWM控制法是和其电路结构与工作特点密切相关的，不同的电路结构及其工作特点，就用不同的PWM控制电路。
和两电平逆变器相比，多电平逆变器在电路结构上增加了一些新的辅助电路，使电路更复杂、要求更严格、控制目标更多。
发明内容
本发明要解决的技术问题是：为克服上述问题，提供一种应用方式多样的I/O时刻表及制作方法及输出方法及应用其的设备。
本发明解决其技术问题所采用的技术方案是：
一种I/O时刻表，包括两个或两个以上有序记录的时间片段，所述时间片段包含一个I/O电平参数和一个或者一组I/O时间参数；
所述I/O电平参数用于记录控制逆变电路的各个I/O引脚的电平状态；
所述I/O时间参数用于记录控制逆变电路的各个I/O引脚在所述I/O电平参数相应的电平状态连续持续的时间长度或可计算所述时间长度的时间数据。
优选地，所述I/O时间参数可使用长度计时方式，即采用时间长度来记录。
优选地，所述I/O时间参数可使用端点计时方式，即记录时间片段的开始时刻时间和/或终止时刻时间。
优选地，所述端点计时方式包括以下类型：
端点法递增计时方式：时间片段的开始时刻的时间数据小于该时间片段的
终止时刻的时间数据；
端点法递减计时方式：时间片段的开始时刻的时间数据大于该时间片段的
终止时刻的时间数据；
端点法精简计时方式：只记录时间片段的一个端点的时间数据，而该时间片段的另外一个端点的时间数据是系统设定的时间数据或者是系统设定的时间片段共用的时间 数据。
优选地，所述I/O时刻表的存储方式的种类包括存储采用同一种计时方式的时间片段和存储采用多种计时方式的时间片段。
优选地，2个或者2个以上I/O时刻表可合成一个I/O时刻表，一个合成的I/O时刻表中可包括独立调制和/或非独立调制的输出电压组合的控制波形。
一种I/O时刻表制作方法，包括以下步骤：
S1：确定I/O时刻表的一个周期的时间长度，然后把所述一个周期划分为若干个所述时间片段并确定每个所述时间片段内的输出电平和所述I/O时间参数，并确定所述时间片段的计时单位；
S2：确定逆变电路的输出电压的电平状态和对其控制的I/O引脚的电平状态的关系；
S3：建立每个所述时间片段的所述I/O时间参数和所述I/O电平参数的关联，存储所述I/O时刻表。
一种I/O时刻表制作方法，包括以下步骤：
S1：确定若干个所述时间片段的输出电平和所述I/O时间参数，然后把所述若干个时间片段按次序组合，并确定所述时间片段的计时单位；
S2：确定逆变电路的输出电压的电平状态和对其控制的I/O引脚的电平状态的关系；
S3：建立每个所述时间片段的所述I/O时间参数和所述I/O电平参数的关联，存储所述I/O时刻表。
优选地，所述输出电平的种类包括：连续的输出电平和连续的输出电平组合；每一个所述时间片段只能对应一种连续的输出电平或者一种连续的输出电平组合。
优选地，存储I/O时刻表可按照I/O时刻表存储方式和时间片段计时方式存储，所述I/O时刻表存储方式的种类包括所述存储采用同一种计时方式的时间片段和所述存储采用多种计时方式的时间片段，所述时间片段计时方式的种类包括：所述长度计时方式、所述端点法递增计时方式、所述端点法递减计时方式和所述端点法精简计时方式。
优选地，所述时间片段在采用端点法精简计时方式存储时，省略存储系统设定的时间数据和/或省略存储系统设定的时间片段共用的时间数据。
一种I/O时刻表输出方法，包括以下步骤：
Q1：指定一个I/O时刻表的时间片段为待输出时间片段；
Q2：设置计时单元的计时单位和待输出时间片段的计时单位相同，设置计时单元的计时方式和待输出时间片段的输出计时方式一致，设置计时单元的初始计时时间和待输出时间片段的开始输出时间数值相同；
Q3：所述计时单元以所述计时方式和所述计时单位进行计时，并输出待输出时间片段的I/O电平参数；
Q4：保持用于输出I/O电平参数的I/O引脚的电平状态不变，直到正在输出的时间片段被计时完毕；
Q5：重复执行一次步骤Q2-Q4，用于输出依据步骤Q1指定的待输出时间片段在I/O时刻表的次序和I/O时刻表输出方式得到的下一次待输出时间片段，然后再重复执行一次 步骤Q2-Q4，用于输出依据第2次得到的待输出时间片段在I/O时刻表的次序和I/O时刻表输出方式得到的下一次待输出时间片段，依次类推输出时间片段。
优选地，步骤Q2还包括以下类型的操作：
(1)如果计时单元的计时单位和待输出时间片段的计时单位已经相同，省略设置所述计时单元的计时单位和待输出时间片段的计时单位相同，
(2)如果计时单元的计时方式和待输出时间片段的输出计时方式已经一致，省略设置所述计时单元的计时方式和待输出时间片段的输出计时方式一致，
(3)如果计时单元的当前计时时间和待输出时间片段的开始输出时间已经数值相等，省略设置所述计时单元的初始计时时间和待输出时间片段的开始输出时间数值相同；
一种I/O时刻表输出方法，包括以下步骤：
Q1：指定一个I/O时刻表的时间片段为待输出时间片段；
Q2：指定一个计时单元为待输出时间片段计时，设置所述计时单元的计时单位和待输出时间片段的计时单位相同，设置所述计时单元的计时方式和待输出时间片段的输出计时方式一致，设置所述计时单元的初始计时时间和待输出时间片段的开始输出时间数值相同；
Q3：所述计时单元以所述计时方式和所述计时单位进行计时，并输出待输出时间片段的I/O电平参数；
Q4：保持用于输出I/O电平参数的I/O引脚的电平状态不变，直到正在输出的时间片段被计时完毕；
Q5：重复执行一次步骤Q2-Q4，用于输出依据步骤Q1指定的待输出时间片段在I/O时刻表的次序和I/O时刻表输出方式得到的下一次待输出时间片段，然后再重复执行一次步骤Q2-Q4，用于输出依据第2次得到的待输出时间片段在I/O时刻表的次序和I/O时刻表输出方式得到的下一次待输出时间片段，依次类推输出时间片段。
优选地，步骤Q2还包括以下类型的操作：
(1)如果待输出时间片段和其上一个输出的时间片段使用同一个计时单元，省略指定一个计时单元为待输出时间片段计时，
(2)如果所述计时单元的计时单位和待输出时间片段的计时单位已经相同，省略设置所述计时单元的计时单位和待输出时间片段的计时单位相同，
(3)如果所述计时单元的计时方式和待输出时间片段的输出计时方式已经一致，省略设置所述计时单元的计时方式和待输出时间片段的输出计时方式一致，
(4)如果所述计时单元的当前计时时间和待输出时间片段的开始输出时间已经数值相等，省略设置所述计时单元的初始计时时间和待输出时间片段的开始输出时间数值相同；
优选地，所述时间片段的输出计时方式的种类包括递增计时方式和递减计时方式。
优选地，所述I/O时刻表输出方式的种类包括：
顺时针输出方式：按时间片段在I/O时刻表中的排列次序输出时间片段；
逆时针输出方式：按时间片段在I/O时刻表中的逆向排列次序输出时间片段；
和制作I/O时刻表时约定的次序输出时间片段。
优选地，设置计时单元的初始计时时间还包括以下种类设置方式：
(1)在每个I/O时刻表输出周期的每个时间片段的开始时刻，各赋初值1次；
(2)在每个I/O时刻表输出周期中的1个或多个固定的时间片段的开始时刻，各赋初值1次；
(3)在循环输出I/O时刻表的开始时刻赋初值1次；
优选地，还包括嵌套输出方式：以嵌套循环方式输出所述I/O时刻表，内循环输出所述I/O时刻表的时间片段，外循环输出I/O时刻表。
一种设备，所述设备采用以上I/O时刻表和I/O时刻表输出方法。
优选地，还包括I/O时刻表制作方法。
优选地，还包括在线计算功能：一边将所述I/O时刻表输出为控制波形，一边重新建立新的I/O时刻表。
优选地，还包括以下种类的操作方式：
S1、输出指定的I/O时刻表；
S2、在输出过程中切换输出I/O时刻表；
S3、输出I/O时刻表计时、输出I/O时刻表计次、输出时间片段计次；
S4、定量输出I/O时刻表。
本发明的有益效果是：应用方式多样，可以完成复杂的控制，特别是应用于多电平变频器中，在没有专用驱动芯片的情况下，使用本专利可以替代大量的模拟电路；把原本多用于高压变频器的多电平驱动技术，可以移植到低压变频器。
本发明还具有以下应用前景：
1.应用优选的I/O时刻表；
2.变频和转矩控制应用；
3.用作输出平台；
4.定量输出控制；
5.和检测元件配合，实时掌握设备的运行情况；
6.同时控制多个目标；
7.有利于多电平控制技术的推广。
附图说明
下面结合附图和实施例对本发明进一步说明。
图1是本发明一个实施例的流程图；
图2是本发明一个实施例的波形图；
图3是本发明一个实施例的波形图；
图4是本发明一个实施例的电路图；
图5是本发明一个实施例的示意图；
图6是本发明一个实施例的示意图；
图7是本发明一个实施例的示意图；
图8是本发明所述I/O时刻表输出方法的流程图；
图9是本发明一个实施例的电路图；
图10是本发明一个实施例的示意图；
图11是本发明一个实施例的波形图；
图12是本发明一个实施例的示意图；
图13是本发明一个实施例的波形图；
图14是本发明一个实施例的电路图；
图15是本发明一个实施例的示意图；
图16是本发明一个实施例的波形图；
图17是本发明一个实施例的示意图；
图18是本发明一个实施例的波形图；
图19是本发明一个实施例的电路图；
图20是本发明一个实施例的示意图；
图21是本发明一个实施例的波形图。
具体实施方式
现在结合附图对本发明作进一步详细的说明。这些附图均为简化的示意图，仅以示意方式说明本发明的基本结构，因此其仅显示与本发明有关的构成，本发明如图1-21所示。
实施例1
本发明所述一种I/O时刻表，包括两个或两个以上有序记录的时间片段，所述时间片段包含一个I/O电平参数和一个或者一组I/O时间参数，其中表1为使用端点计时方式计时的I/O时刻表：
Figure PCTCN2017098230-appb-000001
表1
其中所述I/O电平参数用于记录控制逆变电路的2个I/O引脚P1.1和P1.0的电平状态，在本实施例中，I/O引脚的电平状态采用1和0分别表示高低电平状态；所述I/O时间参数用于记录控制逆变电路的2个I/O引脚P1.1和P1.0在所述I/O电平参数相应的电平状态连续持续时间的两个端点的时间数据，可通过简单的减法算出时间长度，例如表1中时间片段1的时间长度就是1806-0＝1806；本发明所述逆变电路是指逆变主电路，或者是逆变主电路及其辅助电路。所述有序记录，是指根据正向输出时间片段的次序或者逆向输出时间片段的次序进行记录时间片段，还可以是指和I/O时刻表输出方法约定的次序进行记录时间片段。
表2是采用长度计时方式的I/O时刻表，所述I/O时间参数用于记录控制逆变电路的2个I/O引脚P1.1和P1.0在所述I/O电平参数相应的电平状态连续持续时间的时间长度数据。
Figure PCTCN2017098230-appb-000002
时间片段1 1806 1 0
时间片段2 1571 0 0
时间片段3 1806 1 0
表2
实施例2
在实施例1所述I/O时刻表的基础上，所述端点计时方式包括以下类型：
端点法递增计时方式：如表1中所示，时间片段的开始时刻的时间数据小于该时间片段的终止时刻的时间数据；
端点法递减计时方式：时间片段的开始时刻的时间数据大于该时间片段的终止时刻的时间数据，即将表1中的时间端点的大小颠倒过来；
端点法精简计时方式：只记录时间片段的一个端点的时间数据，而该时间片段的另外一个端点的时间数据是系统设定的时间数据或者是系统设定的时间片段共用的时间数据，表1所示，任意相邻的两个时间片段，后一个时间片段的开始时刻时间和前一个时间片段的终止时刻时间相等，则这两个相等的时间数据只需存储其中的一个，并且约定第一个时间片段的开始时刻时间为0，表1所示的I/O时刻表经过精简后变成表3所示的I/O时刻表。表3是采用端点法精简计时的I/O时刻表。
Figure PCTCN2017098230-appb-000003
表3
在优选的实施方式中，2个或者2个以上I/O时刻表可合成一个I/O时刻表，合成I/O时刻表先要扩展I/O时刻表，扩展I/O时刻表就是在该I/O时刻表的前面或者后面依次添加按该I/O时刻表的时间片段的排列顺序的时间片段。以合成2个I/O时刻表为例进行说明：分别把两个I/O时刻表的周期至少扩展到这两个I/O时刻表周期的最小公倍数的时间长度；I/O时刻表的周期是指I/O时刻表的时间长度，是I/O时刻表中所有时间片段的时间长度的累加和；如两个I/O时刻表具有相同的周期，可以不扩展I/O时刻表的周期；把这两个扩展后的I/O时刻表的时间数据(时间节点或者时间长度)分别投射到同一个时间轴上；在2个I/O时刻表的重叠区域，被2个I/O时刻表的时间节点重新分割形成新的时间片段，每个时间片段包含来自两个I/O时刻表的对应时间片段的电平参数；两个I/O时刻表的第一个时间节点可以重合，也可以有偏移；取重叠区域至少1倍所述最小公倍数的时间长度作为合成后的I/O时刻表的一个周期。
一个合成的I/O时刻表中可包括独立调制和/或非独立调制的输出电压组合的控制波形，输出电压组合是指2相或者2相以上的输出电压，如图2所示，两相输出电压的调制过程相互独立。
所述I/O时刻表的存储方式的种类包括存储采用同一种计时方式的时间片段和存储采用多种计时方式的时间片段。存储采用同一种计时方式的时间片段是指I/O时刻表存储的时间片段采用一种计时方式，如表1所示，I/O时刻表中每个时间片段都采用了端点法递增计时方式；存储采用多种计时方式的时间片段是指I/O时刻表存储的时间片段采用了不同的计时方式，如表4所示，在表4中前4个时间片段使用了端点法递增计时方式而后4个时间片段使用了端点法递减计时方式。
Figure PCTCN2017098230-appb-000004
时间片段6 6048 4477 0 0
时间片段7 4477 2671 0 1
时间片段8 2671 0 0 0
表4
所述时间片段计时方式的种类包括：所述长度计时方式、所述端点法递增计时方式、所述端点法递减计时方式和所述端点法精简计时方式，即一个时间片段可以采用长度计时方式或者端点法递增计时方式或者端点法递减计时方式或者端点法精简计时方式。
实施例3
一种I/O时刻表制作方法，如图1所示，包括以下步骤：
S1、确定I/O时刻表的一个周期的时间长度，然后根据输出电压的波形质量要求把所述一个周期划分为若干个所述时间片段并确定每个所述时间片段内的输出电平和所述I/O时间参数，并确定所述时间片段的计时单位；每一个时间片段只能有一种连续的输出电平或者输出电平组合，对于只有一相输出电压的情况下，每一个时间片段内输出电压只能有一种连续的输出电平，对于有2相或2相以上输出电压的情况下，每一个时间片段只能有一种连续的输出电平组合，输出电平组合是指2相或2相以上输出电压的电平状态；
具体一个例子如图3中，有一个周期为15708微秒的正弦信号波，取一个完整的正弦信号波周期作为一个I/O时刻表的时间长度，
在图3中所示，采用了正弦信号波和三角载波比较的方法来划分时间片段。
在正弦信号波的正半周，正弦波大于三角波的部分，输出电压为E；正弦波小于三角波的部分，输出电压为0。
在正弦信号波的负半周，正弦波小于三角波的部分，输出电压为-E；正弦波大于三角波的部分，输出电压为0。
在一个完整的正弦信号波周期中，输出电压uAB有3种输出电平：+E、0和-E，这3个电平分布在8时间片段内，因此一个周期至少分成8个时间片段。
表5是根据图3的“长度法”列出的I/O时间参数和输出电压uAB的电平状态关系对照表，计时单位为1微秒。
Figure PCTCN2017098230-appb-000005
表5
在实际使用中，图3所示的单相正弦信号波，如果采用脉宽调制方式，控制图4所示的逆变电路，优选的载波比是15-30，此数值可供分割其他SPWM控制波形参考。
S2：确定逆变电路的输出电压的电平状态和对其控制的I/O引脚的电平状态的关系；即确定逆变电路输出每一种将用于输出的电平或者电平组合时，用于控制逆变电路输出所述电平或者电平组合的所有I/O引脚所对应的电平状态或者电平组合状态；
提供一个单相全桥逆变电路的例子，其他逆变电路可参照其实施，如图4中所示，输出电压uAB的电平状态和各个逆变管的状态的关系如表6所示。S1和S4导通、S2和S3截止，则uAB为E；S1、S2、S3和S4截止，则uAB为0；S1和S4截止、S2和S3导通，则uAB为-E。
Figure PCTCN2017098230-appb-000006
表6输出电压uAB的电平状态和逆变管状态的关系对照表
对图4的电路分析可知，在实现uAB的三种输出电平的情况下，S1和S4工作相同，S2和S3工作相同，因此只要用2个I/O引脚即可实现对4个逆变管的控制。
控制逆变电路的各个I/O引脚的电平状态(即为本设计中的I/O电平参数)和单相全桥逆变电路的逆变管状态的关系如表7所示。用P1.1控制S1和S4，P1.1＝1时S1和S4导通，P1.1＝0时S1和S4截止；用P1.0控制S2和S3，P1.0＝1时S2和S3导通，P1.0＝0时S2和S3截止。
Figure PCTCN2017098230-appb-000007
表7I/O电平参数和逆变管状态的关系对照表
根据表6得到输出电压uAB的电平状态和逆变管状态的关系，根据表7得到I/O电平参数和逆变管状态的关系，因此可以得到输出电压uAB的电平状态和I/O电平参数的关系。表8是输出电压uAB的电平状态和I/O电平参数的关系对照表。P1.1＝1和P1.0＝0时，则uAB为E；P1.1＝0和P1.0＝0时，则uAB为0；P1.1＝0和P1.0＝1时，则uAB为-E。
Figure PCTCN2017098230-appb-000008
表8输出电压uAB的电平状态和I/O电平参数的关系对照表
S3：建立每个所述时间片段的所述I/O时间参数和所述I/O电平参数的关联，存储所述I/O时刻表。
根据以上分析，I/O时间参数和输出电压uAB的电平状态相关联，输出电压uAB的电平状态又和I/O电平参数相关联，则I/O时间参数和I/O电平参数相关联。每一个时间片段只能有一种连续的输出电平或者输出电平组合，同理每一个时间片段只能有一个I/O电平参数。
根据表5得到I/O时间参数和输出电压uAB的电平状态的关系，根据表8得到输出电压uAB的电平状态和I/O电平参数的关系，得到I/O时间参数和I/O电平参数的关系，见表9：
Figure PCTCN2017098230-appb-000009
表9
在本设计中，表9所示的I/O时间参数和I/O电平参数的关系表称为I/O时刻表。
在优选的实施方式中，所述输出电平的种类包括：连续的输出电平和连续的输出电平组合；每一个所述时间片段只能对应一种连续的输出电平或者一种连续的输出电平组合。
在优选的实施方式中，所述存储I/O时刻表可按照I/O时刻表存储方式和时间片段计时方式存储，所述I/O时刻表存储方式的种类包括所述存储采用同一种计时方式的时间片段和所述存储采用多种计时方式的时间片段；所述时间片段计时方式的种类包括：所述长度计时方式、所述端点法递增计时方式、所述端点法递减计时方式和所述端点法精简计时方式。例如表9所示的I/O时刻表存储采用同一种计时方式的时间片段，所述时间片段采用端点法递增计时方式；表4所示的I/O时刻表存储采用多种计时方式的时间片段，所述时间片段采用端点法递增计时方式和端点法递减计时方式；具体选择哪种方式根据实际的需求进行选择。
在优选的实施方式中，所述时间片段在采用端点法精简计时方式存储时，省略存储系统设定的时间数据和/或省略存储系统设定的时间片段共用的时间数据。
对照表9所示的I/O时刻表经过精简后变成表10所示的I/O时刻表。表10是采用同一种端点法精简计时的I/O时刻表。
Figure PCTCN2017098230-appb-000010
表10为采用同一种端点法精简计时I/O时刻表
实施例4
本实施例中提供一个使用直流PWM模式控制单相全桥逆变电路的具体的应用实例，该单相全桥逆变电路仍采用图4中的电路，因此逆变管状态同上述实施例3中论述一致，直接以上述为基础制作I/O时刻表。
1、确定若干个所述时间片段的输出电平和所述I/O时间参数，然后把所述若干个时间片段按次序组合，并确定所述时间片段的计时单位；以输出电压为E/2的直流电压为例，通过分析可知间隔输出电平为E的时间和输出电平为0的时间相等就能输出等效E/2的直流电压，并规定每次输出E或者0的时间为1000微秒，因此得到2个I/O时间参数和输出电平确定的时间片段，若把2组上述时间片段按次序组合在一起，则可以得到表11所示的的I/O时间参数和输出电压的电平状态关系对照表，计时单位为1微秒。
Figure PCTCN2017098230-appb-000011
表11
2、确定逆变电路的输出电压的电平状态和对其控制的I/O引脚的电平状态的关系；该步骤同实施例3中步骤相同；
3、建立每个所述时间片段的所述I/O时间参数和所述I/O电平参数的关联，存储所述I/O时刻表，根据表11得到I/O时间参数和输出电压的电平状态的关系，根据实施例3中分析的表8得到输出电压的电平状态和I/O电平参数的关系，因此可以得到I/O时间参数和I/O电平参数的关系，见下表12：
Figure PCTCN2017098230-appb-000012
表12
在优选的实施方式中，所述输出电平的种类包括：连续的输出电平和连续的输出电平组合；每一个所述时间片段只能对应一种连续的输出电平或者一种连续的输出电平组合。
在优选的实施方式中，所述存储I/O时刻表可按照I/O时刻表存储方式和时间片段计时方式存储，所述I/O时刻表存储方式的种类包括所述存储采用同一种计时方式的时间片段和所述存储采用多种计时方式的时间片段；所述时间片段计时方式的种类包括：所述长度计时方式、所述端点法递增计时方式、所述端点法递减计时方式和所述端点法精简计时方式。
在优选的实施方式中，所述时间片段在采用端点法精简计时方式存储时，省略存储系统设定的时间数据和/或省略存储系统设定的时间片段共用的时间数据。
采用I/O时刻表方式控制逆变电路输出直流电压应用小结
通过改变相应时间片段的时间长度来改变相应输出电平的脉宽比例，从而改变输出电压的等效值。
通过按比例改变各个时间片段的时间长度来改变各个输出电平的脉冲宽度，从而改变输出电压的波形。
实施例5
一种I/O时刻表输出方法，包括以下步骤：
Q1：指定一个I/O时刻表的时间片段为待输出时间片段；因此可灵活选择任意时间片段为第一个输出的时间片段，以满足不同需求；
Q2：设置计时单元的计时单位和待输出时间片段的计时单位相同，设置计时单元的计时方式和待输出时间片段的输出计时方式一致，设置计时单元的初始计时时间和待输出时间片段的开始输出时间数值相同；所述计时单元是示意说明，可以是可计时的软件程序，也可以是可计时的硬件，还可以是可计时的软件和硬件的结合体，可根据需要进行选择；计时单元的可计时时间不小于时间片段的计时时间，可为多个时间片段计时；本实施例所述I/O时刻表输出方法仅有一个为时间片段计时的计时单元。
以递增计时方式输出表4所示的I/O时刻表的一个待输出时间片段(时间片段1)为例，待输出时间片段的时间参数的计时单位是1微秒，因此设置计时单元的计时单位为1微秒；待输出时间片段的输出计时方式是递增计时方式，因此设置计时单元的计时方式是递增计时方式；待输出时间片段的输出计时方式是递增计时方式，则时间片段的开始时刻时间为0，因此设置计时单元的计时时间为0；
采用端点法精简计时方式的时间片段，只记录时间片段的一个端点的时间数据，而该时间片段的另外一个端点的时间数据是系统设定的时间数据或者是系统设定的时间片段共用的时间数据，因此需要根据制作方法获取被省略存储的时间数据。
输出采用长度法计时方式的时间片段，仿效采用端点法精简计时的时间片段来处理，把时间长度数据作为所述时间片段的其中一个端点的时间数据，另一个端点的时间数据是0或者是其他根据需要选择的数据；
Q3：所述计时单元以所述计时方式和所述计时单位进行计时，并输出待输出时间片段的I/O电平参数；输出I/O电平参数是指把I/O电平参数的值从各个对应的I/O引脚输出。
Q4：保持用于输出I/O电平参数的I/O引脚的电平状态不变，直到正在输出的时间片段被计时完毕；
正在输出的时间片段是指刚被输出I/O电平参数并正在被各个对应的I/O引脚保持输出I/O电平参数后的电平状态的时间片段；在步骤Q3输出待输出时间片段的I/O电平参数，待输出时间片段就转变为正在输出的时间片段；
在步骤Q2把时间片段的一个端点的时间数据赋值给计时单元，当计时单元的计时时间到达所述时间片段的另一个端点的时间时，所述时间片段被计时完毕。
Q5：重复执行一次步骤Q2-Q4，用于输出依据步骤Q1指定的待输出时间片段在I/O时刻表的次序和I/O时刻表输出方式得到的下一次待输出时间片段，然后再重复执行一次步骤Q2-Q4，用于输出依据第2次得到的待输出时间片段在I/O时刻表的次序和I/O时刻表输出方式得到的下一次待输出时间片段，依次类推输出时间片段。以输出表4所示的I/O时刻表为例，在步骤Q1第1次得到待输出时间片段，执行一次步骤Q2-Q4，则步骤Q1指定的待输出时间片段完成输出，如果步骤Q1指定时间片段1为待输出时间片段，且I/O时刻表输出方式是顺时针输出方式，则第2次得到的待输出时间片段是时间片段2，第3次得到的待输出时间片段是时间片段3，……依此类推；如果步骤Q1指定时间片段1为待输出时间片段，但I/O时刻表输出方式是逆时针输出方式，则第2次得到的待输出时间片段是时间片段8，第3次得到的待输出时间片段是时间片段7，……依此类推。在实际使用中，在输出I/O时刻表的过程中可采用确认是否停止输出I/O时刻表，经过确认不停止，则继续输出。
在优选的实施方式中，步骤Q2还包括以下类型的操作：
(1)如果计时单元的计时单位和待输出时间片段的计时单位已经相同，省略设置所述计时单元的计时单位和待输出时间片段的计时单位相同；
(2)如果计时单元的计时方式和待输出时间片段的输出计时方式已经一致，省略设置所述计时单元的计时方式和待输出时间片段的输出计时方式一致；
(3)如果计时单元的当前计时时间和待输出时间片段的开始输出时间已经数值相等，省略设置所述计时单元的初始计时时间和待输出时间片段的开始输出时间数值相同；
在优选的实施方式中，所述时间片段的输出计时方式的种类包括递增计时方式和递减计时方式；
对于端点法计时的时间片段，递增计时方式是指从时间片段的时间数据较小的I/O时间参数向时间数据较大的I/O时间参数进行计时；递减计时方式是指从时间数据较大的I/O时间参数向时间数据较小的I/O时间参数进行计时。
可以通过加减法运算来判断I/O时间参数的大小，然后根据时间片段输出计时方式把一个I/O时间参数作为所述时间片段的开始时刻时间而把另一个I/O时间参数作为所述时间片段的终止时刻时间；在实际使用中，在制作I/O时刻表时所有的时间片段采用和输出方法约定的计时方式，则可省略判断I/O时间参数大小的步骤。
采用端点法精简计时方式的时间片段，只记录时间片段的一个端点的时间数据，而该时间片段的另外一个端点的时间数据是系统设定的时间数据或者是系统设定的时间片段共用的时间数据，可以根据制作方法获取被省略存储的时间数据，因此采用端点法精简计时方式的时间片段也可采用递增计时方式或者递减计时方式进行计时；
采用长度计时方式的时间片段，仿效采用端点法精简计时的时间片段来处理，把 时间长度数据作为所述时间片段的其中一个端点的时间数据，另一个端点的时间数据是0或者是其他根据需要选择的数据，因此采用长度计时方式的时间片段也可采用递增计时方式或者递减计时方式进行计时；
在优选的实施方式中，所述I/O时刻表输出方式包括：
顺时针输出方式：按时间片段在I/O时刻表中的排列次序输出时间片段，时间片段的输出顺序如图5所示；
逆时针输出方式：按时间片段在I/O时刻表中的逆向排列次序输出时间片段，时间片段的输出顺序如图6所示；
和制作I/O时刻表时约定的次序输出时间片段，例如在制作I/O时刻表时和I/O时刻表输出方法约定：输出时间片段的次序是1、3、5、2、4、6……，则I/O时刻表输出方法输出时间片段的次序是1、3、5、2、4、6……。
在优选的实施方式中，设置计时单元的初始计时时间还包括以下种类设置方式：
(1)在每个I/O时刻表输出周期的每个时间片段的开始时刻，各赋初值1次；即每个时间片段的开始时刻设置一次初始计时时间，每个时间片段计时时间相互独立，如图7中所示；
(2)在每个I/O时刻表输出周期中的1个或多个固定的时间片段的开始时刻，各赋初值1次；一个I/O时刻表输出周期是指把I/O时刻表中的所有时间片段各输出一次的过程；在输出I/O时刻表的过程中，从所述固定的时间片段开始的任意相邻的两个时间片段都是时间上连续的，因此在所述固定的时间片段赋初值后，输出I/O时刻表的其余时间片段都不需要赋初值，所述两个时间片段时间上连续是指前一个输出的时间片段的终止输出时间和后一个输出的时间片段的开始输出时间相等；如果存在连续的时间片段，但并非全部连续，则和上一个输出的时间片段不连续的时间片段都需要赋初值。
(3)在循环输出I/O时刻表的开始时刻赋初值1次；
在循环输出I/O时刻表的开始时刻赋初值1次，后续输出时间片段不需赋初值，此方法适用于所有时间片段采用端点法计时的I/O时刻表；在输出I/O时刻表的过程中，所有时间片段采用相同的输出计时方式，并且从一个固定的时间片段开始的任意相邻的两个时间片段都是时间上连续的；对I/O时刻表的时间参数进行累加或者累减操作，即当一个时间片段输出完成后，对所述时间片段的时间参数加上或者减去一个I/O时刻表周期的时间长度。以递增计时方式输出表9所示I/O时刻表为例，在时间片段1的开始时刻设置计时单元的计时时间为0，输出时间片段2-8都不赋初值，但每次输出一个时间片段后，该时间片段的时间参数都加上15708(一个I/O时刻表周期的时间长度)作为该时间片段下一次输出的时间参数。
在优选的实施方式中，还包括嵌套输出方式：如图8中所示，以嵌套循环方式输出所述I/O时刻表，内循环输出所述I/O时刻表的时间片段，外循环输出I/O时刻表，两者可以并行同时运行，因此节省程序空间，通用性好。
在实际使用中，优选的方式是：在存储I/O时刻表时所有时间片段采用相同的计时单位和相同的计时方式，采用端点法计时方式的所有时间片段时间上连续；在输出I/O时刻表时所有时间片段使用相同的输出计时方式。
实施例6
一种I/O时刻表输出方法，包括以下步骤：
Q1：指定一个I/O时刻表的时间片段为待输出时间片段；因此可灵活选择任意时间片段为第一个输出的时间片段，以满足不同需求；
Q2：指定一个计时单元为待输出时间片段计时，设置所述计时单元的计时单位和待输出时间片段的计时单位相同，设置所述计时单元的计时方式和待输出时间片段的输出计时方式一致，设置所述计时单元的初始计时时间和待输出时间片段的开始输出时间数值相同；计时单元的可计时时间不小于时间片段的计时时间，可为多个时间片段计时；有若干个计时单元为时间片段计时，因此指定一个计时单元为待输出时间片段计时，例如：不同的计时单元有不同的计时单位，可分别为计时单位不同的时间片段计时，不同的计时单元有不同的计时方式，可分别为输出计时方式不同的时间片段计时，……可根据需要进行选择。
Q3：所述计时单元以所述计时方式和所述计时单位进行计时，并输出待输出时间片段的I/O电平参数。
Q4：保持用于输出I/O电平参数的I/O引脚的电平状态不变，直到正在输出的时间片段被计时完毕；
Q5：重复执行一次步骤Q2-Q4，用于输出依据步骤Q1指定的待输出时间片段在I/O时刻表的次序和I/O时刻表输出方式得到的下一次待输出时间片段，然后再重复执行一次步骤Q2-Q4，用于输出依据第2次得到的待输出时间片段在I/O时刻表的次序和I/O时刻表输出方式得到的下一次待输出时间片段，依次类推输出时间片段。在实际使用中，在输出I/O时刻表的过程中可采用确认是否停止输出I/O时刻表，经过确认不停止，则继续输出。
在优选的实施方式中，步骤Q2还包括以下类型的操作：
(1)如果待输出时间片段和其上一个输出的时间片段使用同一个计时单元，省略指定一个计时单元为待输出时间片段计时，
(2)如果所述计时单元的计时单位和待输出时间片段的计时单位已经相同，省略设置所述计时单元的计时单位和待输出时间片段的计时单位相同，
(3)如果所述计时单元的计时方式和待输出时间片段的输出计时方式已经一致，省略设置所述计时单元的计时方式和待输出时间片段的输出计时方式一致，
(4)如果所述计时单元的当前计时时间和待输出时间片段的开始输出时间已经数值相等，省略设置所述计时单元的初始计时时间和待输出时间片段的开始输出时间数值相同。
在优选的实施方式中，所述时间片段的输出计时方式的种类包括递增计时方式和递减计时方式。
在优选的实施方式中，所述I/O时刻表输出方式包括：
顺时针输出方式：按时间片段在I/O时刻表中的排列次序输出时间片段；
逆时针输出方式：按时间片段在I/O时刻表中的逆向排列次序输出时间片段；
和制作I/O时刻表时约定的次序输出时间片段。
在优选的实施方式中，设置计时单元的初始计时时间还包括以下种类设置方式：
(1)在每个I/O时刻表输出周期的每个时间片段的开始时刻，各赋初值1次；
(2)在每个I/O时刻表输出周期中的1个或多个固定的时间片段的开始时刻，各赋初值1次；
(3)在循环输出I/O时刻表的开始时刻赋初值1次；
在优选的实施方式中，还包括嵌套输出方式：以嵌套循环方式输出所述I/O时刻表，内循环输出所述I/O时刻表的时间片段，外循环输出I/O时刻表。
实施例7
本实施提供一个使用SPWM模式控制三相两电平半桥逆变电路的具体的应用实例，如图9所示的电路，是三相两电平半桥逆变电路，3个半桥分别用虚线框标出，S1、S2、S3、S4、S5和S6是逆变管，D1、D2、D3、D4、D5和D6是续流管，uAO是A端相对O端的电压，uBO是B端相对O端的电压，uCO是C端相对O端的电压。E是的直流电源电压，O是E的中点电压。在图9所示的电路中有6个逆变管，使用6个I/O引脚实现对6个逆变管的控制。图10所示是I/O引脚对逆变电路的逆变管的控制关系，当I/O引脚输出高电平时对应的被控逆变管导通，当I/O引脚输出低电平时对应的被控逆变管截止。
1、确定I/O时刻表的一个周期的时间长度，然后把所述一个周期划分为若干个所述时间片段并确定每个所述时间片段内的输出电平和所述I/O时间参数，并确定所述时间片段的计时单位；
在图11中，有3个周期相同的正弦信号波，取一个完整的正弦波周期作为一个周期的时间长度。在本实施例中，采用了正弦信号波和三角载波比较的方法来划分时间片段。
在正弦波大于三角波的部分，输出电压为E/2；在正弦波小于三角波的部分，输出电压为-E/2。
表13是根据图11列出的I/O时刻表的一个周期的I/O时间参数和输出电压组合的电平状态的关系对照表，计时单位是1微秒。
Figure PCTCN2017098230-appb-000013
表13
2、确定逆变电路的输出电压的电平状态和对其控制的I/O引脚的电平状态的关系；
半桥一电路分析：
①S1导通、S2关断，则uAO输出电压为E/2。
②S2导通、S1关断，则uAO输出电压为-E/2。
半桥二和半桥三原理同半桥一，因此可得出下表：
Figure PCTCN2017098230-appb-000014
-E/2 关 开 0 1 -E/2 关 开 0 1 -E/2 关 开 0 1
表14
注明：“开”表示逆变管导通；“关”表示逆变管截止。在其他表格中含义相同。
3、建立每个所述时间片段的所述I/O时间参数和所述I/O电平参数的关联，存储所述I/O时刻表，根据表13得到I/O时间参数和输出电压组合的电平状态的关系，根据表14得到输出电压组合的电平状态和I/O电平参数的关系，因此可以得到I/O时间参数和I/O电平参数的关系，详见表15，本时刻表中采用的是长度计时方式：
Figure PCTCN2017098230-appb-000015
表15
根据表15的I/O时刻表，提供一个该I/O时刻表的具体的输出应用实例，I/O时刻表的输出方式采用顺时针输出方式，时间片段的输出方式采用递减计时方式。
Q1：指定时间片段1为待输出时间片段；可灵活选择任意时间片段为第一个输出的时间片段；
Q2：在第一次输出待输出时间片段时，设置计时单元的计时单位为1微秒，设置计时单元的计时方式为递减计时方式，设置计时单元的计时时间为281(时间片段1的I/O时间参数)；在本实施例中所有的时间片段采用相同的计时单位和相同的输出计时方式，因此从第2次待输出时间片段开始可以省略设置计时单元的计时单位和计时方式，只需要设置计时单元的初始计时时间和待输出时间片段的开始输出时间数值相同；
Q3：所述计时单元以所述计时方式和所述计时单位进行计时，并输出待输出时间片段的I/O电平参数；把I/O电平参数从P1.5-P1.0输出；
Q4：保持用于输出I/O电平参数的I/O引脚的电平状态不变，直到所述时间片段被计时完毕；在本实施例中采用递减的计时方式，等待计时单元的计时时间为0，281-0＝281，即为时间片段1的时间长度，其余时间片原理相同；
Q5：重复执行一次步骤Q2-Q4，输出时间片段2，重复执行一次步骤Q2-Q4，输出时间片段3，……依次类推；在本实施例中，输出时间片段的顺序是：1→2→……→36→1→2→……→36→1→……。
采用SPWM调制方式的小结：
在制作I/O时刻表时，通过改变参考波形的幅值，表15所示I/O时刻表的时间参数也相应改变，则图9所示的逆变电路输出相应电平的输出时间也将改变，从而影响到输出电压的各个电平状态的脉宽比例，因此可以通过I/O时刻表改变输出电压的有效值。
在制作I/O时刻表时，通过改变参考波形的周期，表15所示I/O时刻表的周期也相应改变，则图9所示的逆变电路输出电压的周期也相应改变，因此可以通过I/O时刻表改变输出电压的周期。
实施例8
本实施例中，提供一个使用矢量合成法的SVPWM模式控制三相两电平半桥逆变电路的具体的应用实例，该三相两电平半桥逆变电路仍采用图9中的电路和图10的控制关系，直接以上述为基础制作I/O时刻表。
1、确定I/O时刻表的一个周期的时间长度，然后把所述一个周期划分为若干个所述时间片段并确定每个所述时间片段内的输出电平和所述I/O时间参数，并确定所述时间片段的计时单位；
图12所示，是一个使用矢量合成法的SVPWM模式矢量图，这种方式是将圆周等分为若干小段，用相邻的电压矢量交替切换，使其合成矢量等效这段弧的弦，来近似这一小段弧，这样不断切换下去，形成一个逼近圆形的正多边形，图12中用虚线画的圆代表圆形旋转磁场，
取一个完整的圆形旋转磁场周期作为一个周期的时间长度。在本实施例中，将圆周等分为6个小段，每个小段采用7段法输出，把输出电压矢量相同的且相邻的时间片段合并，得到36个时间片段。
图13是图12所示矢量图的输出电压波形图。表16是根据图13列出的一个周期的时 间参数和输出电压组合的电平状态的关系对照表，下表为表16：
Figure PCTCN2017098230-appb-000016
Figure PCTCN2017098230-appb-000017
在实际使用中，将磁链轨迹圆等分为若干个小段(6的倍数)，优选的分段数为12-30。
2、确定逆变电路的输出电压的电平状态和对其控制的I/O引脚的电平状态的关系；如图12所示，从圆心出发，带有箭头的6根线段，代表6个电压矢量，另外还有2个0向量。表17是8种电压矢量所对应的逆变管状态和I/O引脚电平状态的关系对照表。
Figure PCTCN2017098230-appb-000018
表17
3、建立每个所述时间片段的所述I/O时间参数和所述I/O电平参数的关联，存储所述I/O时刻表，根据表16得到I/O时间参数和输出电压组合的电平状态的关系，根据表17得到输出电压组合的电平状态和I/O电平参数的关系，因此可以得到I/O时间参数和I/O电平参数的关系，建立I/O时刻表见下表18：
Figure PCTCN2017098230-appb-000019
Figure PCTCN2017098230-appb-000020
采用SVPWM调制方式的小结：
在制作I/O时刻表时，通过改变参考磁链的幅值，表18所示I/O时刻表的时间参数也相应改变，则图9所示的逆变电路输出相应电压矢量的输出时间也将改变，从而影响到各个电压矢量的输出时间的比例，因此可以通过I/O时刻表改变输出输出电压的有效值。
在制作I/O时刻表时，通过改变参考磁链的周期，表18所示I/O时刻表的周期也相应改变，则图9所示的逆变电路输出电压的周期也相应改变，因此可以通过I/O时刻表改变输出输出电压的周期。
实施例9
在本实施例中，提供一个使用SPWM模式控制图14中所示的三相二极管钳位三电平半桥逆变电路的具体的应用实例。
在图14中，3个二极管钳位三电平逆变单元分别用虚线框标出。在逆变单元一中，S1、S2、S3、S4是逆变管，D1、D2是钳位二极管，D3、D4、D5、D6是续流二极管。在逆变单元二和逆变单元三中，各元件的作用同逆变单元一。A端、B端、C端分别是3个逆变电路的输出端，输出电压UAO、UBO、UCO。E是加在3个半桥逆变电路上的直流电源电压。C1、C2是直流分压电容。
在图14所示的电路中，逆变管S1和S3、S2和S4、S5和S7、S6和S8、S9和S11、S10和S12工作在互补状态，组成6对互补逆变管。采用6个I/O引脚来实现对12个逆变管的控制，即每一个I/O引脚控制一对互补的逆变管。图15所示是I/O引脚对逆变电路的逆变管的控制关系，其中P1.5输出高电平，则S1导通，S3截止；P1.5输出低电平，则S1截止，S3导通，其余I/O引脚的控制方法相同。
1、确定I/O时刻表的一个周期的时间长度，然后把所述一个周期划分为若干个所 述时间片段并确定每个所述时间片段内的输出电平和所述I/O时间参数，并确定所述时间片段的计时单位；
在如图16所示的三相二极管钳位三电平逆变电路SPWM模式输出波形中，
有3个周期相同的正弦信号波，取一个完整的正弦波周期作为一个周期的时间长度。
在本实施例中，采用了正弦信号波和同相层叠的三角载波比较的方法来划分时间片段。在正弦信号波的正半周，正弦波大于三角波的部分，输出电压为E；正弦波小于三角波的部分，输出电压为0。在正弦信号波的负半周，正弦波小于三角波的部分，输出电压为-E；正弦波大于三角波的部分，输出电压为0。
根据图16的SPWM模式输出波形可列出I/O时刻表的一个周期的I/O时间参数和输出电压组合的电平状态的关系对照表，具体如下表19所示，计时单位是1微秒。
Figure PCTCN2017098230-appb-000021
Figure PCTCN2017098230-appb-000022
表19
2、确定逆变电路的输出电压的电平状态和对其控制的I/O引脚的电平状态的关系；半桥一电路分析：当逆变管S1、S2同时导通时，输出端A对O点的电平为E/2；当逆变管S2、S3同时导通时，输出端A和O相连，A点对O点的电平为0；当逆变管S3、S4同时导通时，输出端A对O点的电平为-E/2。所以图16所示的逆变电路的输出电平数有3种。
半桥二和半桥三的工作原理同半桥一。表20是逆变电路的输出电压的电平状态、逆变管状态、I/O电平参数的关系对照表。
Figure PCTCN2017098230-appb-000023
表20
3、建立每个所述时间片段的所述I/O时间参数和所述I/O电平参数的关联，存储所述I/O时刻表，根据表19得到I/O时间参数和输出电压组合的电平状态的关系，根据表20得到输出电压组合的电平状态和I/O电平参数的关系，因此可以得到I/O时间参数和I/O电平参数的关系，如下表21所示：
Figure PCTCN2017098230-appb-000024
Figure PCTCN2017098230-appb-000025
表21
实施例10
在本实施例中，提供一个使用矢量合成法的SVPWM模式控制图14中所示的三相二极管钳位三电平半桥逆变电路的具体的应用实例。
本实施例中仍采用图14中的电路和图15的控制关系，因此直接以上述论述为基础制作I/O时刻表。
1、确定I/O时刻表的一个周期的时间长度，然后把所述一个周期划分为若干个所述时间片段并确定每个所述时间片段内的输出电平和所述I/O时间参数，并确定所述时间片段的计时单位；
图17所示，是一个使用矢量合成法的SVPWM模式三电平三相矢量图，这种方式是将圆周等分为若干小段，用包围参考相量的三个电压矢量交替切换，使其合成矢量等效这段 弧的弦，来近似这一小段弧，这样不断切换下去，形成一个逼近圆形的正多边形，图中用虚线画的圆代表圆形旋转磁场，取一个完整的圆形旋转磁场周期作为一个周期的时间长度。
在本实施例中，将圆周等分为12个小段，每个小段采用7段法输出，图18是图17所示矢量图的输出电压波形图。
根据图18列出I/O时刻表的一个周期的I/O时间参数和输出电压组合的电平状态的关系对照表，详见下表22，计时单位是1微秒：
Figure PCTCN2017098230-appb-000026
Figure PCTCN2017098230-appb-000027
表22
2、确定逆变电路的输出电压和对其控制的I/O引脚的电平状态的关系；如图17中所示，从圆心出发，并带有箭头的24根线段，代表24个电压矢量，另外还有3个0向量。表23是根据以上27种电压矢量所对应的逆变管状态和I/O电平参数的关系对照表。
Figure PCTCN2017098230-appb-000028
Figure PCTCN2017098230-appb-000029
表23
3、建立每个所述时间片段的所述I/O时间参数和所述I/O电平参数的关联，存储所述I/O时刻表，根据表22得到I/O时间参数和输出电压组合的电平状态的关系，根据表23得到输出电压组合的电平状态和I/O电平参数的关系，因此可以得到I/O时间参数和I/O电平参数的关系，见表24
Figure PCTCN2017098230-appb-000030
Figure PCTCN2017098230-appb-000031
表24
实施例11
本实施例针对级联逆变电路中的三相2H桥级联逆变电路提供一个使用SPWM模式控制的具体实施方式，其他级联逆变电路都可参照本实施例实现，具体电路如图19所示，在图中，3个2H桥级联逆变电路分别用虚线框标出。在2H桥级联1中，S1～S8是逆变管，D1～D8是续流二极管。在2H桥级联2、2H桥级联3中，各元件的作用同2H桥级联1。S1～S24是逆变管。A端、B端、C端分别是3个2H桥级联的输出端。E是加在3个2H桥级联逆变电路上的直流电源电压，两个直流电源相互独立。该电路中有24个逆变管，使用24个I/O引脚实现对24个逆变管的控制，在图20所示是I/O引脚对逆变电路的逆变管的控制关系，当I/O引脚输出高电平时对应的被控逆变管导通，当I/O引脚输出低电平时对应的被控逆变管截止。
1、确定I/O时刻表的一个周期的时间长度，然后把所述一个周期划分为若干个所述时间片段并确定每个所述时间片段内的输出电平和所述I/O时间参数，并确定所述时间片段的计时单位；
在图21所示三角载波移相SPWM模式控制三相2H桥级联电路波形中，有3个周期相同的正弦信号波，取一个完整的正弦波周期作为一个周期的时间长度。
在本实施例中，采用了2组相位不同但频率和幅值相同的反相层叠三角载波分别同3个正弦波比较来划分时间片段，正弦波和三角载波比较的方法和实施例3中论述一致。
根据图21列出I/O时刻表的一个周期的I/O时间参数和输出电压组合的电平状态的关系对照表，见下表25，计时单位是1微秒：
Figure PCTCN2017098230-appb-000032
Figure PCTCN2017098230-appb-000033
表25
在表25中，负0是反向旁路输出0电平的缩写，正0是正向旁路输出0电平的缩写。
2、确定逆变电路的输出电压的电平状态和对其控制的I/O引脚的电平状态的关系；建立逆变电路的输出电压的电平状态、逆变管状态、I/O电平参数的关系对照表，详见下 表26：
Figure PCTCN2017098230-appb-000034
Figure PCTCN2017098230-appb-000035
3、建立每个所述时间片段的所述I/O时间参数和所述I/O电平参数的关联，存储所述I/O时刻表，根据表25得到I/O时间参数和输出电压组合的电平状态的关系，根据表26得到输出电压的电平状态和I/O电平参数的关系，因此可以得到I/O时间参数和I/O电平参数的关系，见表27。
Figure PCTCN2017098230-appb-000036
Figure PCTCN2017098230-appb-000037
Figure PCTCN2017098230-appb-000038
表27I/O时刻表
本发明的有益效果是，应用方式多样，可以完成复杂的控制，特别是应用于多电平变频器中，在没有专用驱动芯片的情况下，使用本专利可以替代大量的模拟电路；把原本多用于高压变频器的多电平驱动技术，可以移植到低压变频器。
实施例12
一种逆变设备，所述逆变设备采用以上I/O时刻表和I/O时刻表输出方法，该逆变设备可包括：逆变电源、变频器、逆变器等需要逆变控制的设备，其中以逆变器、变频器应用较多，提供一个逆变器的实施方式，凡是采用的逆变设备都落入本发明的保护范围。
在优选的实施方式中，还包括I/O时刻表制作方法。
在优选的实施方式中，还包括在线计算功能：一边将所述I/O时刻表输出为控制波形，一边重新建立新的I/O时刻表，提高效率，能够实现连续输出。
还包括以下操作方式：
S1、输出指定的I/O时刻表，在开始或者输出的过程中都可以通过命令进行指定，然后输出；
S2、在输出过程中切换输出I/O时刻表，当具体应用时，可能是多个I/O时刻表同时应用，输出不同的控制波形时，会需要切换不同的I/O时刻表，因此需要根据指令进行切换；
S3、输出I/O时刻表计时、输出I/O时刻表计次、输出时间片段计次；
S4、定量输出I/O时刻表，根据此功能，使用者可以指定定时定量完成的任务，使得控制功能更加多样化。
优选的还包括通讯功能：包含和外部设备进行通讯的协议，可接收外部设备的命令和数据，便于和其他控制器或下位机械进行控制命令的传输，可采用现有的各种连接总线和协议，根据具体需要进行选择，不进行具体限定。
I/O时刻表和及其输出方法应用小结
本发明的I/O时刻表及其输出方法，使用I/O电平参数控制I/O引脚的电平状态，再通过I/O引脚的电平状态控制逆变管的导通和截止，使用I/O时间参数控制I/O引脚在相应的电平状态连续持续的时间长度，从而控制逆变管在相应的状态连续持续的时间长度，因此本发明的方法适用于控制采用逆变管的导通和截止进行逆变的逆变电路。
在制作I/O时刻表时，使用不同的控制方式，就可以利用本发明的方法控制逆变电路输出不同控制方式的等效输出电压；
在制作I/O时刻表时，使用不同频率的输出电压或者使用不同周期的磁链作参考，就可以利用本发明的方法控制逆变电路输出不同频率的等效输出电压；
在制作I/O时刻表时，利用不同有效值的输出电压或者使用不同幅值的磁链作参考，就可以利用本发明的方法控制逆变电路输出不同有效值的等效输出电压；
本发明还具有以下应用前景：
1.应用优选的I/O时刻表：
某空压机全天运行，一天中的负载情况各不相同，空压机频繁启停，想进行改造。
逆变设备设计方案：按空压机输出功率的大小设定若干个等级，最高等级的输出功率高于空压机的最大负载，最低等级的输出功率低于空压机的最小负载，为每个等级优选I/O时刻表；
在实际工作条件下，使用所述空压机测试若干个I/O时刻表，采集每一个输出能满足设定要求的I/O时刻表的能耗指标，挑选一个能耗指标最低的I/O时刻表作为优选的I/O时刻表；输出要求是指空压机的输出功率在某个等级范围；使用同样的方法为其他输出功率等级优选I/O时刻表。
输出时，若正在输出的I/O时刻表所对应的输出功率低于当前负载且超过设定的时间，则切换输出功率高一级的I/O时刻表；若正在输出的I/O时刻表所对应的输出功率高于当前负载且超过设定的时间，则切换输出功率低一级的I/O时刻表。
2.变频和转矩控制应用：
某机器要求电动机输出5种转速及每种转速下输出5种转矩；
逆变设备设计方案：存储对应5种转速的I/O时刻表，且每个转速存储对应5种转矩的I/O时刻表，输出时按转速和转矩要求指定I/O时刻表。
3.用作输出平台：
某设备对电动机的要求是转速变化范围大、负载变化范围大。
逆变设备设计方案一：存储海量的I/O时刻表，分别对应不同的转速和负载。
逆变设备设计方案二：采用I/O时刻表计算方法，采用高性能的运算芯片，进行实时运算。
逆变设备设计方案三：把逆变设备作为输出平台，借助外部运算设备制作I/O时刻表，逆变设备接收外部输入的I/O时刻表，然后使用输出方法进行输出。
4.定量输出控制：
某悬挂车，把一个零件从A位置转移到B位置，要求途中少晃动。
逆变设备设计方案：采用定量控制，对速度和运行时间都进行控制，在启动初期缓慢加速，达到某一速度后维持不变，达到某一时间后缓慢减速。根据上述分析，按输出速度的先后顺序制作若干个对应的I/O时刻表，并指定每一个I/O时刻表的输出时间或者输出数量，输出时按次序和对应指定的时间输出I/O时刻表。
5.和检测元件配合，实时掌握设备的运行情况：
在输出I/O时刻表时，可以以理论值或经验值推测电机的转速，如果电机的转速超出合理范围，则有异常存在，如果已经输出I/O时刻表有一段时间，则可以推测电机的转数。以行进中的电动车辆为例，如果实际速度达不到输出I/O时刻表所应该有的合理的速度，则可判断该车辆有异常存在。
6.同时控制多个目标：
某设备需要3台电动机配合运行，同一时刻运转其中的一台或多台电动机。逆变设备设计方案：采用I/O时刻表叠加方法，分别为每一台电动机准备I/O时刻表；输出时，先把准备运行的电动机的I/O时刻表进行叠加处理，然后输出叠加后的I/O时刻表。
7.有利于多电平控制技术的推广：
如实施例所示，使用I/O时刻表及其输出方法控制多电平逆变电路和使用I/O时刻 表控制2电平逆变电路方法一样，控制方便。
以上述依据本发明的理想实施例为启示，通过上述的说明内容，相关工作人员完全可以在不偏离本项发明技术思想的范围内，进行多样的变更以及修改。本项发明的技术性范围并不局限于说明书上的内容，必须要根据权利要求范围来确定其技术性范围。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。

Claims (23)

  1. 一种I/O时刻表，其特征在于，包括两个或两个以上有序记录的时间片段，所述时间片段包含一个I/O电平参数和一个或者一组I/O时间参数；
    所述I/O电平参数用于记录控制逆变电路的各个I/O引脚的电平状态；
    所述I/O时间参数用于记录控制逆变电路的各个I/O引脚在所述I/O电平参数相应的电平状态连续持续的时间长度或可计算所述时间长度的时间数据。
  2. 如权利要求1所述的I/O时刻表，其特征在于，所述I/O时间参数可使用长度计时方式，即采用时间长度来记录。
  3. 如权利要求1所述的I/O时刻表，其特征在于，所述I/O时间参数可使用端点计时方式，即记录时间片段的开始时刻时间和/或终止时刻时间。
  4. 如权利要求3所述的I/O时刻表，其特征在于，所述端点计时方式包括以下类型：
    端点法递增计时方式：时间片段的开始时刻的时间数据小于该时间片段的终止时刻的时间数据；
    端点法递减计时方式：时间片段的开始时刻的时间数据大于该时间片段的终止时刻的时间数据；
    端点法精简计时方式：只记录时间片段的一个端点的时间数据，而该时间片段的另外一个端点的时间数据是系统设定的时间数据或者是系统设定的时间片段共用的时间数据。
  5. 如权利要求1-4任一项所述的I/O时刻表，其特征在于，所述I/O时刻表的存储方式的种类包括存储采用同一种计时方式的时间片段和存储采用多种计时方式的时间片段。
  6. 如权利要求5所述的I/O时刻表，其特征在于，2个或者2个以上I/O时刻表可合成一个I/O时刻表，一个合成的I/O时刻表中可包括独立调制和/或非独立调制的输出电压组合的控制波形。
  7. 一种I/O时刻表制作方法，其特征在于，包括以下步骤：
    S1：确定I/O时刻表的一个周期的时间长度，然后把所述一个周期划分为若干个所述时间片段并确定每个所述时间片段内的输出电平和所述I/O时间参数，并确定所述时间片段的计时单位；
    S2：确定逆变电路的输出电压的电平状态和对其控制的I/O引脚的电平状态的关系；
    S3：建立每个所述时间片段的所述I/O时间参数和所述I/O电平参数的关联，存储所述I/O时刻表。
  8. 一种I/O时刻表制作方法，其特征在于，包括以下步骤：
    S1：确定若干个所述时间片段的输出电平和所述I/O时间参数，然后把所述若干个时间片段按次序组合，并确定所述时间片段的计时单位；
    S2：确定逆变电路的输出电压的电平状态和对其控制的I/O引脚的电平状态的关系；
    S3：建立每个所述时间片段的所述I/O时间参数和所述I/O电平参数的关联，存储所述I/O时刻表。
  9. 如权利要求7或8所述的I/O时刻表制作方法，其特征在于，所述输出电平的种类包括：连续的输出电平和连续的输出电平组合；每一个所述时间片段只能对应一种连续的输出电平或者一种连续的输出电平组合。
  10. 如权利要求9所述的I/O时刻表制作方法，其特征在于，存储I/O时刻表可按照I/O时刻表存储方式和时间片段计时方式存储，所述I/O时刻表存储方式的种类包括所述存储采 用同一种计时方式的时间片段和所述存储采用多种计时方式的时间片段，所述时间片段计时方式的种类包括：所述长度计时方式、所述端点法递增计时方式、所述端点法递减计时方式和所述端点法精简计时方式。
  11. 如权利要求10所述的I/O时刻表制作方法，其特征在于，所述时间片段在采用端点法精简计时方式存储时，省略存储系统设定的时间数据和/或省略存储系统设定的时间片段共用的时间数据。
  12. 一种I/O时刻表输出方法，其特征在于，包括以下步骤：
    Q1：指定一个I/O时刻表的时间片段为待输出时间片段；
    Q2：设置计时单元的计时单位和待输出时间片段的计时单位相同，设置计时单元的计时方式和待输出时间片段的输出计时方式一致，设置计时单元的初始计时时间和待输出时间片段的开始输出时间数值相同；
    Q3：所述计时单元以所述计时方式和所述计时单位进行计时，并输出待输出时间片段的I/O电平参数；
    Q4：保持用于输出I/O电平参数的I/O引脚的电平状态不变，直到正在输出的时间片段被计时完毕；
    Q5：重复执行一次步骤Q2-Q4，用于输出依据步骤Q1所述待输出时间片段在I/O时刻表的次序和I/O时刻表输出方式得到的下一次待输出时间片段，然后再重复执行一次步骤Q2-Q4，用于输出依据第2次得到的待输出时间片段在I/O时刻表的次序和I/O时刻表输出方式得到的下一次待输出时间片段，依次类推输出时间片段。
  13. 如权利要求12所述的I/O时刻表输出方法，其特征在于，步骤Q2还包括以下类型的操作：
    (1)如果计时单元的计时单位和待输出时间片段的计时单位已经相同，省略设置所述计时单元的计时单位和待输出时间片段的计时单位相同，
    (2)如果计时单元的计时方式和待输出时间片段的输出计时方式已经一致，省略设置所述计时单元的计时方式和待输出时间片段的输出计时方式一致，
    (3)如果计时单元的当前计时时间和待输出时间片段的开始输出时间已经数值相等，省略设置所述计时单元的初始计时时间和待输出时间片段的开始输出时间数值相同。
  14. 一种I/O时刻表输出方法，其特征在于，包括以下步骤：
    Q1：指定一个I/O时刻表的时间片段为待输出时间片段；
    Q2：指定一个计时单元为待输出时间片段计时，设置所述计时单元的计时单位和待输出时间片段的计时单位相同，设置所述计时单元的计时方式和待输出时间片段的输出计时方式一致，设置所述计时单元的初始计时时间和待输出时间片段的开始输出时间数值相同；
    Q3：所述计时单元以所述计时方式和所述计时单位进行计时，并输出待输出时间片段的I/O电平参数；
    Q4：保持用于输出I/O电平参数的I/O引脚的电平状态不变，直到正在输出的时间片段被计时完毕；
    Q5：重复执行一次步骤Q2-Q4，用于输出依据步骤Q1所述待输出时间片段在I/O时刻表的次序和I/O时刻表输出方式得到的下一次待输出时间片段，然后再重复执行一次步骤Q2- Q4，用于输出依据第2次得到的待输出时间片段在I/O时刻表的次序和I/O时刻表输出方式得到的下一次待输出时间片段，依次类推输出时间片段。
  15. 如权利要求14所述的I/O时刻表输出方法，其特征在于，步骤Q2还包括以下类型的操作：
    (1)如果待输出时间片段和其上一个输出的时间片段使用同一个计时单元，省略指定一个计时单元为待输出时间片段计时，
    (2)如果所述计时单元的计时单位和待输出时间片段的计时单位已经相同，省略设置所述计时单元的计时单位和待输出时间片段的计时单位相同，
    (3)如果所述计时单元的计时方式和待输出时间片段的输出计时方式已经一致，省略设置所述计时单元的计时方式和待输出时间片段的输出计时方式一致，
    (4)如果所述计时单元的当前计时时间和待输出时间片段的开始输出时间已经数值相等，省略设置所述计时单元的初始计时时间和待输出时间片段的开始输出时间数值相同。
  16. 如权利要求13或15所述的I/O时刻表输出方法，其特征在于，所述时间片段的输出计时方式的种类包括递增计时方式和递减计时方式。
  17. 如权利要求16所述的I/O时刻表输出方法，其特征在于，所述I/O时刻表输出方式的种类包括：
    顺时针输出方式：按时间片段在I/O时刻表中的排列次序输出时间片段；
    逆时针输出方式：按时间片段在I/O时刻表中的逆向排列次序输出时间片段；
    和制作I/O时刻表时约定的次序输出时间片段。
  18. 如权利要求17所述的I/O时刻表输出方法，其特征在于，设置计时单元的初始计时时间还包括以下种类设置方式：
    (1)在每个I/O时刻表输出周期的每个时间片段的开始时刻，各赋初值1次；
    (2)在每个I/O时刻表输出周期中的1个或多个固定的时间片段的开始时刻，各赋初值1次；
    (3)在循环输出I/O时刻表的开始时刻赋初值1次。
  19. 如权利要求18所述的I/O时刻表输出方法，其特征在于，还包括嵌套输出方式：以嵌套循环方式输出所述I/O时刻表，内循环输出所述I/O时刻表的时间片段，外循环输出I/O时刻表。
  20. 一种设备，其特征在于，所述设备采用以上I/O时刻表和I/O时刻表输出方法。
  21. 如权利要求20所述的设备，其特征在于，还包括I/O时刻表制作方法。
  22. 如权利要求21所述的设备，其特征在于，还包括在线计算功能：一边将所述I/O时刻表输出为控制波形，一边重新建立新的I/O时刻表。
  23. 如权利要求20-22任一项所述的设备，其特征在于，还包括以下种类的操作方式：
    S1、输出指定的I/O时刻表；
    S2、在输出过程中切换输出I/O时刻表；
    S3、输出I/O时刻表计时、输出I/O时刻表计次、输出时间片段计次；
    S4、定量输出I/O时刻表。
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CN106787881A (zh) * 2017-01-18 2017-05-31 钱利斌 一种i/o时刻表及制作方法及输出方法及应用其的设备

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