WO2018133404A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

Info

Publication number
WO2018133404A1
WO2018133404A1 PCT/CN2017/097645 CN2017097645W WO2018133404A1 WO 2018133404 A1 WO2018133404 A1 WO 2018133404A1 CN 2017097645 W CN2017097645 W CN 2017097645W WO 2018133404 A1 WO2018133404 A1 WO 2018133404A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
node
pole
signal
input
Prior art date
Application number
PCT/CN2017/097645
Other languages
English (en)
French (fr)
Inventor
杨盛际
董学
吕敬
陈小川
杨亚锋
赵文卿
张粲
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/757,297 priority Critical patent/US10373558B2/en
Publication of WO2018133404A1 publication Critical patent/WO2018133404A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G09G2310/062—Waveforms for resetting a plurality of scan lines at a time
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G09G2360/145—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen
    • G09G2360/147—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen the originated light output being determined for each pixel
    • G09G2360/148—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen the originated light output being determined for each pixel the light being detected by light detection means within each pixel

Definitions

  • Embodiments of the present disclosure relate to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device.
  • a CMOS (Complementary Metal-Oxide Semiconductor) image sensor can receive external light, convert light into an electrical signal, and output it.
  • CMOS Complementary Metal-Oxide Semiconductor
  • an Active Pixel Sensor (APS) circuit is used in the photoelectric conversion process of a photosensitive device due to a process difference of a Thin Film Transistor (TFT).
  • TFT Thin Film Transistor
  • the resulting end output current is not uniform, and the output current of the source follower thin film transistor is affected by its own threshold voltage, which causes the display picture to be distorted.
  • Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, and a display device.
  • a pixel circuit includes: a reset unit, a charging unit, a compensation unit, and a reading unit;
  • the reset unit is connected to the first signal end, the first voltage end, the second signal end, the first node, the second node, and the third node, and is configured to be configured according to the first signal end and the second signal end
  • An input signal controls potentials of the first node, the second node, and the third node
  • the charging unit is respectively connected to the second signal end and the second node, and configured to control a potential of the second node according to an input signal of the second signal end;
  • the compensation unit is respectively associated with the second node, the first node, the second voltage end, the third node, the fourth node, the third voltage end, the third signal end, the fifth node, and the sixth node Connecting, configured to control potentials of the first node and the third node according to an input signal of the third signal end and a potential of the second node;
  • the reading unit is connected to the first pole of the light emitting device, and the second pole of the light emitting device is grounded; the reading unit is respectively connected to the first voltage end, the fourth signal end, the fourth node, The fifth node and the sixth node are And a read end connection configured to control an output signal of the first pole and the read end of the light emitting device according to an input signal of the fourth signal end.
  • the reset unit includes a fourth transistor, a first transistor, and a seventh transistor;
  • a gate of the fourth transistor is connected to the first signal end, a first pole of the fourth transistor is connected to the first voltage terminal, and a second pole of the fourth transistor is connected to the second node connection;
  • a gate of the first transistor is connected to the second signal end, a first pole of the first transistor is grounded, and a second pole of the first transistor is connected to the first node;
  • the gate of the seventh transistor is connected to the second signal terminal, the first pole of the seventh transistor is grounded, and the second pole of the seventh transistor is connected to the third node.
  • the charging unit is connected to a second pole of the photosensitive device, the first pole of the photosensitive device is grounded, and the photosensitive device comprises a photodiode.
  • the charging unit includes a fifth transistor and a second capacitor
  • a gate of the fifth transistor is connected to the second signal end, a first pole of the fifth transistor is connected to a second pole of the photosensitive device, and a second pole of the fifth transistor is opposite to the first Two-node connection;
  • the first pole of the second capacitor is connected to the second node, and the second pole of the second capacitor is grounded.
  • the compensation unit includes a third transistor, a second transistor, an eighth transistor, a ninth transistor, an eleventh transistor, a first capacitor, and a third capacitor;
  • a gate of the third transistor is connected to the first node, a first pole of the third transistor is connected to the second node, and a second pole of the third transistor is connected to the sixth node;
  • a gate of the second transistor is connected to the third signal terminal, a first pole of the second transistor is connected to the first node, and a second pole of the second transistor is connected to the sixth node ;
  • a gate of the eighth transistor is connected to the third signal end, a first pole of the eighth transistor is connected to the third node, and a second pole of the eighth transistor is connected to the fifth node ;
  • a gate of the ninth transistor is connected to the third node, a first pole of the ninth transistor is connected to the fourth node, and a second pole of the ninth transistor is connected to the fifth node;
  • a gate of the eleventh transistor is connected to the third signal terminal, a first pole of the eleventh transistor is connected to the fourth node, and a second pole of the eleventh transistor is opposite to the first Three voltage terminals are connected;
  • a first pole of the first capacitor is connected to the first node, and a second pole of the first capacitor is connected to the second voltage end;
  • a first pole of the third capacitor is connected to the second voltage terminal, and a second pole of the third capacitor is connected to the third section Point connection.
  • the reading unit includes a tenth transistor, a twelfth transistor, and a sixth transistor;
  • a gate of the tenth transistor is connected to the fourth signal terminal, a first pole of the tenth transistor is connected to the first voltage terminal, and a second pole of the tenth transistor is connected to the fourth node connection;
  • a gate of the twelfth transistor is connected to the fourth signal terminal, a first pole of the twelfth transistor is connected to the fifth node, and a second pole of the twelfth transistor is connected to the light emitting The first pole of the device is connected;
  • the sixth transistor is connected to the fourth signal terminal, the first pole of the sixth transistor is connected to the sixth node, and the second pole of the sixth transistor is connected to the read end.
  • the first to twelfth transistors are all N-type transistors or both are P-type transistors.
  • the present disclosure provides a display device including the pixel circuit of the embodiment of the present disclosure described above.
  • the present disclosure further provides a driving method of a pixel circuit according to an embodiment of the present disclosure, wherein the first voltage terminal is a first level, and the second voltage terminal is a common voltage.
  • the third voltage terminal is a data signal voltage;
  • the driving method of the pixel circuit includes:
  • a second level is input to the first signal end, a second level is input to the second signal end, and a first level is input to the third signal end, to the fourth signal Input the first level;
  • a first level is input to the first signal end, a second level is input to the second signal end, and a first level is input to the third signal end, to the fourth signal Input the first level;
  • a first level is input to the first signal end, a first level is input to the second signal end, and a second level is input to the third signal end, to the fourth signal Input the first level;
  • a second level is input to the first signal end, a first level is input to the second signal end, and a first level is input to the third signal end, to the fourth signal
  • the terminal inputs the second level.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a specific structure of the pixel circuit shown in FIG. 1;
  • FIG. 3 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 4 is an operational timing diagram of a pixel circuit in accordance with an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of current flow in a first stage of a pixel circuit according to the driving method of FIG. 3;
  • FIG. 6 is a schematic diagram of current flow in a second stage of the pixel circuit according to the driving method of FIG. 3;
  • FIG. 7 is a schematic diagram of current flow in a third stage of the pixel circuit according to the driving method of FIG. 3;
  • FIG. 8 is a schematic diagram showing current flow in a fourth stage of the pixel circuit according to the driving method of FIG.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit includes a reset unit 101, a charging unit 102, a compensation unit 103, and a reading unit 104.
  • the charging unit 102 of the pixel circuit is connected to the second electrode of the photosensitive device PD, and the first electrode of the photosensitive device PD is grounded.
  • the reading unit 104 of the pixel circuit is connected to the first pole of the light emitting device OLED, and the second pole of the light emitting device OLED is grounded.
  • the photosensitive device PD comprises a photodiode
  • the light emitting device OLED is an organic electroluminescent device.
  • the reset unit 101 is respectively connected to a first signal end Reset, a first voltage terminal Vdd, a second signal terminal Scan1, a first node A1, a second node A2, and a third node A3.
  • the reset unit 101 is configured to control potentials of the first node A1, the second node A2, and the third node A3 according to the first signal end Reset and an input signal of the second signal end Scan1.
  • the charging unit 102 is connected to the second signal end Scan1 and the second node A2, and the charging unit 102 is configured to control the potential of the second node A2 according to an input signal of the second signal end Scan1. .
  • the compensation unit 103 and the second node A2, the first node A1, the second voltage terminal Vcom, the third node A3, the fourth node A4, the third voltage terminal Vdata, and the third signal terminal Scan2 The fifth node A5 and the sixth node A6 are connected, and the compensation unit 103 is configured to control the first node A1 and the first according to an input signal of the third signal end Scan2 and a potential of the second node A2.
  • the reading unit 104 is respectively connected to the first voltage terminal Vdd, the fourth signal terminal EM, the fourth node A4, the fifth node A5, the sixth node A6, and the read terminal ReadLine.
  • the reading unit 104 is configured to control an output signal of the first pole of the light emitting device OLED and the read end ReadLine according to an input signal of the fourth signal terminal EM.
  • the output current is not uniform due to the difference of the source follower transistor itself, so that the output current is independent of the threshold voltage of the source follower transistor.
  • the driving signal and the scanning signal not only the high-resolution silicon-based display function but also the environmental image monitoring function is provided.
  • FIG. 2 is a schematic diagram of a specific structure of the pixel circuit shown in FIG.
  • the reset unit 101 includes a fourth transistor M4, a first transistor M1, and a seventh transistor N1.
  • a gate of the fourth transistor M4 is connected to the first signal terminal Reset, a first pole of the fourth transistor M4 is connected to the first voltage terminal Vdd, and a second pole of the fourth transistor M4 is The second node A2 is connected.
  • the gate of the first transistor M1 is connected to the second signal terminal Scan1, the first pole of the first transistor M1 is grounded, and the second pole of the first transistor M1 is connected to the first node A1.
  • the gate of the seventh transistor N1 is connected to the second signal terminal Scan1, the first pole of the seventh transistor N1 is grounded, and the second pole of the seventh transistor N1 is connected to the third node A3.
  • the charging unit 102 includes a fifth transistor M5 and a second capacitor C2.
  • a gate of the fifth transistor M5 is connected to the second signal terminal Scan1
  • a first electrode of the fifth transistor M5 is connected to a second electrode of the photosensitive device PD
  • a second electrode of the fifth transistor M5 The pole is connected to the second node A2.
  • the first pole of the second capacitor C2 is connected to the second node A2, and the second pole of the second capacitor C2 is grounded.
  • the compensation unit 103 includes a third transistor M3, a second transistor M2, an eighth transistor N2, a ninth transistor N3, an eleventh transistor N5, a first capacitor C1, and a third capacitor C3.
  • a gate of the third transistor M3 is connected to the first node A1, a first pole of the third transistor M3 is connected to the second node A2, and a second pole of the third transistor M3 is The sixth node A6 is connected.
  • a gate of the second transistor M2 is connected to the third signal terminal Scan2, a first pole of the second transistor M2 is connected to the first node A1, and a second pole of the second transistor M2 is The sixth node A6 is connected.
  • a gate of the eighth transistor N2 is connected to the third signal terminal Scan2, a first pole of the eighth transistor N2 is connected to the third node A3, and a second pole of the eighth transistor N2 is The fifth node A5 is connected.
  • a gate of the ninth transistor N3 is connected to the third node A3, a first pole of the ninth transistor N3 is connected to the fourth node A4, and a second pole of the ninth transistor N3 is The fifth node A5 is connected.
  • a gate of the eleventh transistor N5 is connected to the third signal terminal Scan2, a first pole of the eleventh transistor N5 is connected to the fourth node A4, and a second electrode of the eleventh transistor N5 The pole is connected to the third voltage terminal Vdata.
  • the first pole of the first capacitor C1 is connected to the first node A1, and the second pole of the first capacitor C1 is connected to the second voltage terminal Vcom.
  • the first pole of the third capacitor C3 is connected to the second voltage terminal Vcom, and the second pole of the third capacitor C3 is connected to the third node A3.
  • the reading unit 104 includes a tenth transistor N4, a twelfth transistor N6, and a sixth transistor M6.
  • a gate of the tenth transistor N4 is connected to the fourth signal terminal EM
  • a first pole of the tenth transistor N4 is connected to the first voltage terminal Vdd
  • a second pole of the tenth transistor N4 is The fourth node A4 is connected.
  • a gate of the twelfth transistor N6 is connected to the fourth signal terminal EM, and a first pole of the twelfth transistor N6 Connected to the fifth node A5, the second pole of the twelfth transistor N6 is connected to the first pole of the light emitting device OLED.
  • the sixth transistor M6 is connected to the fourth signal terminal EM
  • the first pole of the sixth transistor M6 is connected to the sixth node A6, and the second pole of the sixth transistor M6 is connected to the reading Side ReadLine connection.
  • the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are switching transistors
  • the third transistor M3 is a source follower transistor
  • the seventh transistor N1, the eighth transistor N2, the tenth transistor N4, the eleventh transistor N5, and the twelfth transistor N6 are switching transistors
  • the ninth transistor N3 is a driving transistor (Driving TFT).
  • the switching transistor, the driving transistor, and the source follower driving transistor used in the embodiments of the present disclosure may be a thin film transistor such as an oxide semiconductor transistor. Since the source and drain of the thin film transistor used herein are symmetrical, the source and the drain thereof can be interchanged. In the disclosed embodiment, one of the source and the drain is referred to as a first pole, and the other of the source and the drain is referred to as a second pole. For convenience of description, all of the thin film transistors in the following examples are P-type thin film transistors whose gate-on voltage is low. Those skilled in the art can understand that the thin film transistor can also be an N-type thin film transistor, and the polarity of the gate control signal can be changed accordingly.
  • a display device including a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit includes a reset unit, a charging unit, a compensation unit, a reading unit, and a light emitting device.
  • the reset unit is configured to control potentials of the first node, the second node, and the third node according to input signals of the first signal end and the second signal end.
  • the charging unit is configured to control the potential of the second node according to the input signal of the second signal end.
  • the compensation unit is configured to control the potentials of the first node and the third node according to the input signal of the third signal terminal and the potential of the second node.
  • the reading unit is configured to control an output signal of the first pole and the reading end of the light emitting device according to the input signal of the fourth signal terminal.
  • FIG. 3 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 4 is a timing chart of operation of a pixel circuit according to an embodiment of the present disclosure.
  • the first voltage terminal Vdd is a high level
  • the second voltage terminal Vcom is a common voltage
  • the third voltage terminal Vdata is a data signal voltage.
  • all of the transistors M1 to M6 and N1 to N6 are P-type transistors whose gate-on voltage is a low voltage.
  • the transistor can also be an N-type transistor, in which case its gate turn-on voltage is a high voltage.
  • the driving method of the pixel circuit according to an embodiment of the present disclosure may include the following steps.
  • step 1001 in the first phase t1, the first signal input signal is low, the input signal of the second signal is low, and the input signal of the third signal is high.
  • the input signal of the fourth signal terminal is at a high level.
  • FIG. 5 is a schematic diagram showing current flow of the pixel circuit in the first stage t1 in the embodiment of FIG. 3.
  • the first phase t1 is a reset phase, and the direction of the arrow in the figure represents the current flow direction.
  • the input signal of the first signal end Reset is a low level
  • the input signal of the second signal end Scan1 is a low level
  • the input signal of the third signal end Scan2 is a high level.
  • the input signal of the fourth signal terminal EM is at a high level.
  • the first transistor M1, the fourth transistor M4, and the fifth transistor M5 are turned on, and the other transistors are turned off.
  • the potential of the first node A1 is reset to Vint, for example, 0V
  • the potential of the second node A2 is Vdd
  • the potential of the third node A3 is reset to 0V
  • the previous voltage signal is reset.
  • step 1002 the second stage t2, the input signal of the first signal end is a high level, the input signal of the second signal end is a low level, and the input signal of the third signal end is a high level, The input signal of the fourth signal terminal is at a high level.
  • FIG. 6 is a schematic diagram showing current flow of the pixel circuit in the second stage t2 in the embodiment of FIG. 3.
  • the second stage t2 is a light-sensing accumulation stage, and an arrow on the photosensitive device PD represents a photoelectric reaction.
  • the input signal of the first signal end Reset is a high level
  • the input signal of the second signal end Scan1 is a low level
  • the input signal of the third signal end Scan2 is a high level.
  • Level, the input signal of the fourth signal terminal EM is at a high level.
  • only the fifth transistor M5 is turned on, and the other transistors are turned off.
  • the photon excitation When the diode PN junction of the photosensitive device PD is irradiated with incident light, the photon excitation generates an electron-hole pair on the PN junction, causing the charge on the PN junction capacitance to recombine, thereby reducing the potential of the second node A2 to Vdata1, wherein Vdata1 is generated directly by the illumination of the diode PN junction.
  • Vdata1 is stored at both ends of the second capacitor C2, thereby preparing for the compensation phase.
  • step 1003 the third stage t3, the input signal of the first signal end is a high level, the input signal of the second signal end is a high level, and the input signal of the third signal end is a low level, The input signal of the fourth signal terminal is at a high level.
  • FIG. 7 is a schematic diagram showing current flow of the pixel circuit in the third stage t3 in the embodiment of FIG. 3.
  • FIG. 7 the third phase t3 is a compensation phase, and the direction of the arrow in the figure represents the current flow direction.
  • the input signal of the first signal end Reset is a high level
  • the input signal of the second signal end Scan1 is a high level
  • the input signal of the third signal end Scan2 is a low level.
  • the input signal of the fourth signal terminal EM is at a high level.
  • the second transistor M2, the third transistor M3, and the fifth transistor M5 are turned on, and the first transistor M1, the fourth transistor M4, and the sixth transistor M6 are turned off.
  • the source follower transistor M3 Since the ground potential of the first node A1 is 0V, the source follower transistor M3 is turned on, and the current flows to the second transistor M2 via the fifth transistor M5 and the third transistor M3, and the first node A1 is charged until the first node is charged.
  • the node A1 is charged until Vdata1-Vmth, and the voltage difference between the gate and source of the third transistor M3 is Vmth.
  • the potential of the first node A1 will be maintained at Vdata1-Vmth.
  • the third voltage of this embodiment The terminal Vdata compensates the ninth transistor N3, compensates the potential of the third node A3 to Vdata2-Vnth, and the voltage difference between the gate and source of the ninth transistor N3 is Vnth.
  • step 1004 the fourth stage t4, the input signal of the first signal end is a low level, the input signal of the second signal end is a high level, and the input signal of the third signal end is a high level, The input signal of the fourth signal terminal is low.
  • FIG. 8 is a schematic diagram showing the current flow of the pixel circuit in the fourth stage t4 in the embodiment of FIG. 3.
  • the fourth stage t4 is a signal acquisition phase, and the direction of the arrow in the figure represents the current flow direction.
  • the input signal of the first signal end Reset is a low level
  • the input signal of the second signal end Scan1 is a high level
  • the input signal of the third signal end Scan2 is a high level.
  • the input signal of the fourth signal terminal EM is low.
  • the source of the third transistor M3 is connected to the voltage Vdd
  • the potential of the second node A2 is Vdd
  • the current flows to the sixth transistor M6 through the fourth transistor M4 and the third transistor M3, and is output by the read terminal Readline. From the saturation current formula of the transistor, you can get:
  • K 1 is the current coefficient of the third transistor M3. It can be seen from the above formula that the operating current I is not affected by the threshold voltage Vmth of the source follower transistor, and is only related to Vdd and Vdata1, wherein Vdata1 is directly generated by the illumination of the diode PN junction, thereby avoiding the process and operation. The drift of the threshold voltage Vmth of the source follower transistor is ensured, and the accuracy of the signal data is ensured.
  • the illuminating current I oled K 2 (Vdd - Vdata2) 2 can be derived, where K 2 is the current coefficient of the driving transistor N3.
  • the light-emission current I oled is not affected by the threshold voltage Vnth of the driving transistor N3, and is only related to the data signal voltage Vdata2 of the driving transistor N3 that is compensated by the third voltage terminal.
  • the process avoids operations and cause the threshold voltage of the driving transistor Vnth drift, so that the threshold voltage of the light emitting Vnth not affect the current I oled, to ensure the normal working of the organic electroluminescent device.
  • the reset unit is configured to control potentials of the first node, the second node, and the third node according to input signals of the first signal end and the second signal end
  • the charging unit is configured to be used according to the second
  • the input signal of the signal end controls the potential of the second node
  • the compensation unit is configured to control the potentials of the first node and the third node according to the input signal of the third signal end and the potential of the second node
  • the reading unit is configured to input according to the fourth signal end
  • the signal controls the output signals of the first pole and the read end of the light emitting device.
  • the technical solution provided by the embodiment compensates for the source follower transistor of the pixel circuit, avoiding the output current being non-uniform due to the difference of the source follower transistor itself, so that the output current is independent of the threshold voltage of the source follower transistor.
  • the embodiment of the present disclosure can not only realize a high-resolution silicon-based display function but also an environmental image monitoring function.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Sustainable Development (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Facsimile Heads (AREA)

Abstract

一种像素电路及其驱动方法、显示装置。像素电路包括复位单元（101）、充电单元（102）、补偿单元（103）、读取单元（104）；复位单元（101）用于根据第一信号端（Reset）和第二信号端（Scan1）的输入信号控制第一节点（A1）、第二节点（A2）以及第三节点（A3）的电位；充电单元（102）用于根据第二信号端（Scan1）的输入信号控制第二节点（A2）的电位；补偿单元（103）用于根据第三信号端（Scan2）的输入信号和第二节点（A2）的电位控制第一节点（A1）和第三节点（A3）的电位；读取单元（104）用于根据第四信号端（EM）的输入信号控制发光器件（OLED）的第一极和读取端（ReadLine）的输出信号。

Description

像素电路及其驱动方法、显示装置
交叉引用
本申请要求于2017年1月18日提交的、申请号为201710035131.7的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开实施例涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示装置。
背景技术
CMOS(Complementary Metal-Oxide Semiconductor，互补性金属氧化物半导体)图像传感器可以接收外界光、将光转换为电信号并输出。作为一种CMOS图像传感器的检测电路，有源式像素传感器(Active Pixel Sensor，简称APS)电路在感光器件的光电转换过程中，由于源极跟随薄膜晶体管(Thin Film Transistor，TFT)自身工艺差异所导致的末端输出电流不均一，源极跟随薄膜晶体管的输出电流会受到其自身的阈值电压的影响，从而使得显示画面失真。
发明内容
本公开实施例提供了一种像素电路及其驱动方法、显示装置。
根据本公开实施例的一个方面，提供了一种像素电路，包括：复位单元、充电单元、补偿单元、读取单元；
所述复位单元与第一信号端、第一电压端、第二信号端、第一节点、第二节点以及第三节点连接，被配置为根据所述第一信号端和所述第二信号端的输入信号控制所述第一节点、所述第二节点以及所述第三节点的电位；
所述充电单元分别与所述第二信号端和所述第二节点连接，被配置为根据所述第二信号端的输入信号控制所述第二节点的电位；
所述补偿单元分别与所述第二节点、所述第一节点、第二电压端、所述第三节点、第四节点、第三电压端、第三信号端、第五节点以及第六节点连接，被配置为根据所述第三信号端的输入信号和所述第二节点的电位控制所述第一节点和所述第三节点的电位；
所述读取单元连接发光器件的第一极，所述发光器件的第二极接地；所述读取单元分别与所述第一电压端、所述第四信号端、所述第四节点、所述第五节点、所述第六节点以 及读取端连接，被配置为根据所述第四信号端的输入信号控制所述发光器件的第一极和所述读取端的输出信号。
例如，所述复位单元包括第四晶体管、第一晶体管以及第七晶体管；
所述第四晶体管的栅极与所述第一信号端连接，所述第四晶体管的第一极与所述第一电压端连接，所述第四晶体管的第二极与所述第二节点连接；
所述第一晶体管的栅极与所述第二信号端连接，所述第一晶体管的第一极接地，所述第一晶体管的第二极与所述第一节点连接；
所述第七晶体管的栅极与所述第二信号端连接，所述第七晶体管的第一极接地，所述第七晶体管的第二极与所述第三节点连接。
例如，所述充电单元连接感光器件的第二极，所述感光器件的第一极接地，所述感光器件包括光电二极管。
例如，所述充电单元包括第五晶体管和第二电容；
所述第五晶体管的栅极与所述第二信号端连接，所述第五晶体管的第一极与所述感光器件的第二极连接，所述第五晶体管的第二极与所述第二节点连接；
所述第二电容的第一极与所述第二节点连接，所述第二电容的第二极接地。
例如，所述补偿单元包括第三晶体管、第二晶体管、第八晶体管、第九晶体管、第十一晶体管、第一电容以及第三电容；
所述第三晶体管的栅极与所述第一节点连接，所述第三晶体管的第一极与所述第二节点连接，所述第三晶体管的第二极与所述第六节点连接；
所述第二晶体管的栅极与所述第三信号端连接，所述第二晶体管的第一极与所述第一节点连接，所述第二晶体管的第二极与所述第六节点连接；
所述第八晶体管的栅极与所述第三信号端连接，所述第八晶体管的第一极与所述第三节点连接，所述第八晶体管的第二极与所述第五节点连接；
所述第九晶体管的栅极与所述第三节点连接，所述第九晶体管的第一极与所述第四节点连接，所述第九晶体管的第二极与所述第五节点连接；
所述第十一晶体管的栅极与所述第三信号端连接，所述第十一晶体管的第一极与所述第四节点连接，所述第十一晶体管的第二极与所述第三电压端连接；
所述第一电容的第一极与所述第一节点连接，所述第一电容的第二极与所述第二电压端连接；
所述第三电容的第一极与所述第二电压端连接，所述第三电容的第二极与所述第三节 点连接。
例如，所述读取单元包括第十晶体管、第十二晶体管以及第六晶体管；
所述第十晶体管的栅极与所述第四信号端连接，所述第十晶体管的第一极与所述第一电压端连接，所述第十晶体管的第二极与所述第四节点连接；
所述第十二晶体管的栅极与所述第四信号端连接，所述第十二晶体管的第一极与所述第五节点连接，所述第十二晶体管的第二极与所述发光器件的第一极连接；
所述第六晶体管与所述第四信号端连接，所述第六晶体管的第一极与所述第六节点连接，所述第六晶体管的第二极与所述读取端连接。
例如，所述第一晶体管至第十二晶体管均为N型晶体管或者均为P型晶体管。
根据本公开实施例的另一方面，本公开提供了一种显示装置，包括上述本公开实施例的像素电路。
根据本公开实施例的另一方面，本公开还提供了一种上述本公开实施例的像素电路的驱动方法，所述第一电压端为第一电平，所述第二电压端为公共电压，所述第三电压端为数据信号电压；
所述像素电路的驱动方法包括：
在第一阶段，向所述第一信号端输入第二电平，向所述第二信号端输入第二电平，向所述第三信号端输入第一电平，向所述第四信号端输入第一电平；
在第二阶段，向所述第一信号端输入第一电平，向所述第二信号端输入第二电平，向所述第三信号端输入第一电平，向所述第四信号端输入第一电平；
在第三阶段，向所述第一信号端输入第一电平，向所述第二信号端输入第一电平，向所述第三信号端输入第二电平，向所述第四信号端输入第一电平；
在第四阶段，向所述第一信号端输入第二电平，向所述第二信号端输入第一电平，向所述第三信号端输入第一电平，向所述第四信号端输入第二电平。
附图说明
图1为根据本公开实施例的一种像素电路的结构示意图；
图2为图1所示像素电路的具体结构示意图；
图3为根据本公开实施例的一种像素电路的驱动方法的流程图；
图4为根据本公开实施例的一种像素电路的工作时序图；
图5为根据图3中驱动方法像素电路在第一阶段的电流流向示意图；
图6为根据图3中驱动方法像素电路在第二阶段的电流流向示意图；
图7为根据图3中驱动方法像素电路在第三阶段的电流流向示意图；以及
图8为根据图3中驱动方法像素电路在第四阶段的电流流向示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开实施例的技术方案，下面结合附图对本公开实施例的像素电路及其驱动方法、显示装置进行详细描述。
图1为根据本公开实施例的一种像素电路的结构示意图。如图1所示，所述像素电路包括复位单元101、充电单元102、补偿单元103、读取单元104。所述像素电路的充电单元102与感光器件PD的第二极连接，所述感光器件PD的第一极接地。所述像素电路的读取单元104连接发光器件OLED的第一极，所述发光器件OLED的第二极接地。
在一个实施例中，所述感光器件PD包括光电二极管，所述发光器件OLED为有机电致发光器件。
参见图1，所述复位单元101分别与第一信号端Reset、第一电压端Vdd、第二信号端Scan1、第一节点A1、第二节点A2以及第三节点A3连接。所述复位单元101用于根据所述第一信号端Reset和所述第二信号端Scan1的输入信号控制所述第一节点A1、所述第二节点A2以及所述第三节点A3的电位。所述充电单元102分别与所述第二信号端Scan1和所述第二节点A2连接，所述充电单元102用于根据所述第二信号端Scan1的输入信号控制所述第二节点A2的电位。所述补偿单元103分别与所述第二节点A2、所述第一节点A1、第二电压端Vcom、所述第三节点A3、第四节点A4、第三电压端Vdata、第三信号端Scan2、第五节点A5以及第六节点A6连接，所述补偿单元103用于根据所述第三信号端Scan2的输入信号和所述第二节点A2的电位控制所述第一节点A1和所述第三节点A3的电位。所述读取单元104分别与所述第一电压端Vdd、所述第四信号端EM、所述第四节点A4、所述第五节点A5、所述第六节点A6以及读取端ReadLine连接，所述读取单元104用于根据所述第四信号端EM的输入信号控制所述发光器件OLED的第一极和所述读取端ReadLine的输出信号。
本公开实施例的技术方案，通过对像素电路的源极跟随晶体管进行补偿，避免了由于源极跟随晶体管自身差异导致的输出电流不均一，使得输出电流与所述源极跟随晶体管的阈值电压无关。另外，根据本公开实施例的技术方案，通过共用驱动信号和扫描信号，不仅满足高分辨率的硅基显示功能，还具备环境影像监测功能。
在本公开的一个实施例中，提供了一种像素电路的具体结构，图2为图1所示像素电路的具体结构示意图。如图2所示，所述复位单元101包括第四晶体管M4、第一晶体管M1以及第七晶体管N1。所述第四晶体管M4的栅极与所述第一信号端Reset连接，所述第四晶体管M4的第一极与所述第一电压端Vdd连接，所述第四晶体管M4的第二极与所述第二节点A2连接。所述第一晶体管M1的栅极与所述第二信号端Scan1连接，所述第一晶体管M1的第一极接地，所述第一晶体管M1的第二极与所述第一节点A1连接。所述第七晶体管N1的栅极与所述第二信号端Scan1连接，所述第七晶体管N1的第一极接地，所述第七晶体管N1的第二极与所述第三节点A3连接。
如图2所示，所述充电单元102包括第五晶体管M5和第二电容C2。所述第五晶体管M5的栅极与所述第二信号端Scan1连接，所述第五晶体管M5的第一极与所述感光器件PD的第二极连接，所述第五晶体管M5的第二极与所述第二节点A2连接。所述第二电容C2的第一极与所述第二节点A2连接，所述第二电容C2的第二极接地。
如图2所示，所述补偿单元103包括第三晶体管M3、第二晶体管M2、第八晶体管N2、第九晶体管N3、第十一晶体管N5、第一电容C1以及第三电容C3。所述第三晶体管M3的栅极与所述第一节点A1连接，所述第三晶体管M3的第一极与所述第二节点A2连接，所述第三晶体管M3的第二极与所述第六节点A6连接。所述第二晶体管M2的栅极与所述第三信号端Scan2连接，所述第二晶体管M2的第一极与所述第一节点A1连接，所述第二晶体管M2的第二极与所述第六节点A6连接。所述第八晶体管N2的栅极与所述第三信号端Scan2连接，所述第八晶体管N2的第一极与所述第三节点A3连接，所述第八晶体管N2的第二极与所述第五节点A5连接。所述第九晶体管N3的栅极与所述第三节点A3连接，所述第九晶体管N3的第一极与所述第四节点A4连接，所述第九晶体管N3的第二极与所述第五节点A5连接。所述第十一晶体管N5的栅极与所述第三信号端Scan2连接，所述第十一晶体管N5的第一极与所述第四节点A4连接，所述第十一晶体管N5的第二极与所述第三电压端Vdata连接。所述第一电容C1的第一极与所述第一节点A1连接，所述第一电容C1的第二极与所述第二电压端Vcom连接。所述第三电容C3的第一极与所述第二电压端Vcom连接，所述第三电容C3的第二极与所述第三节点A3连接。
如图2所示，所述读取单元104包括第十晶体管N4、第十二晶体管N6以及第六晶体管M6。所述第十晶体管N4的栅极与所述第四信号端EM连接，所述第十晶体管N4的第一极与所述第一电压端Vdd连接，所述第十晶体管N4的第二极与所述第四节点A4连接。所述第十二晶体管N6的栅极与所述第四信号端EM连接，所述第十二晶体管N6的第一极 与所述第五节点A5连接，所述第十二晶体管N6的第二极与所述发光器件OLED的第一极连接。所述第六晶体管M6与所述第四信号端EM连接，所述第六晶体管M6的第一极与所述第六节点A6连接，所述第六晶体管M6的第二极与所述读取端ReadLine连接。
根据本公开实施例，第一晶体管M1、第二晶体管M2、第四晶体管M4、第五晶体管M5、第六晶体管M6为开关晶体管(Switching TFT)，第三晶体管M3为源极跟随晶体管。同样的，第七晶体管N1、第八晶体管N2、第十晶体管N4、第十一晶体管N5、第十二晶体管N6为开关晶体管(Switching TFT)，第九晶体管N3为驱动晶体管(Driving TFT)。
本公开实施例中使用的开关晶体管、驱动晶体管和源极跟随驱动晶体管可以是薄膜晶体管，例如氧化物半导体晶体管。由于这里采用的薄膜晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，将源极和漏极中的一个称为第一极，将源极和漏极中的另一个称为第二极。为了便于描述，以下实例中所有薄膜晶体管均为P型薄膜晶体管，其栅极导通电压为低电平。本领域技术人员可以理解，薄膜晶体管也可以是N型薄膜晶体管，相应的改变栅极控制信号的极性即可。
根据本公开实施例的另一方面，提供了一种显示装置，包括根据本公开实施例的像素电路。
根据本公开实施例的显示装置之中，像素电路包括复位单元、充电单元、补偿单元、读取单元以及发光器件。复位单元用于根据第一信号端和第二信号端的输入信号控制第一节点、第二节点以及第三节点的电位。充电单元用于根据第二信号端的输入信号控制第二节点的电位。补偿单元用于根据第三信号端的输入信号和第二节点的电位控制第一节点和第三节点的电位。读取单元用于根据第四信号端的输入信号控制发光器件的第一极和读取端的输出信号。
图3为根据本公开实施例的一种像素电路的驱动方法的流程图，图4为根据本公开实施例一种像素电路的工作时序图。在图3和图4的示例中，所述第一电压端Vdd为高电平，所述第二电压端Vcom为公共电压，所述第三电压端Vdata为数据信号电压。在以下示例中，所有晶体管M1至M6以及N1至N6均为P型晶体管，其栅极导通电压为低电压。本领域技术人员可以理解，晶体管也可以为N型晶体管，此时其栅极导通电压为高电压。
根据本公开实施例的像素电路的驱动方法可以包括以下步骤。
在步骤1001，第一阶段t1，所述第一信号端输入信号为低电平，所述第二信号端的输入信号为低电平，所述第三信号端的输入信号为高电平，所述第四信号端的输入信号为高电平。
图5为图3的实施例中像素电路在第一阶段t1的电流流向示意图。如图5所示，第一阶段t1为复位阶段，图中箭头方向代表电流流向。在第一阶段t1中，所述第一信号端Reset的输入信号为低电平，所述第二信号端Scan1的输入信号为低电平，所述第三信号端Scan2的输入信号为高电平，所述第四信号端EM的输入信号为高电平。此时，第一晶体管M1、第四晶体管M4以及第五晶体管M5导通，其他晶体管关断。此时第一节点A1电势复位为Vint，例如为0V，第二节点A2的电势为Vdd，第三节点A3的电势复位为0V，同时将之前的电压信号进行复位。
在步骤1002，第二阶段t2，所述第一信号端的输入信号为高电平，所述第二信号端的输入信号为低电平，所述第三信号端的输入信号为高电平，所述第四信号端的输入信号为高电平。
图6为图3的实施例中像素电路在第二阶段t2的电流流向示意图。如图6所示，第二阶段t2为光感积累阶段，感光器件PD上的箭头代表光电反应。在第二阶段t2之中，所述第一信号端Reset的输入信号为高电平，所述第二信号端Scan1的输入信号为低电平，所述第三信号端Scan2的输入信号为高电平，所述第四信号端EM的输入信号为高电平。此时，只有第五晶体管M5导通，其他晶体管关断。当感光器件PD的二极管PN结上有入射光照射时，光量子激发在PN结上产生电子空穴对，使得PN结电容上的电荷发生复合，从而将第二节点A2的电势降为Vdata1，其中Vdata1直接由二极管PN结的光照产生。本实施例将Vdata1存储在第二电容C2的两端，从而为补偿阶段做好准备。
在步骤1003，第三阶段t3，所述第一信号端的输入信号为高电平，所述第二信号端的输入信号为高电平，所述第三信号端的输入信号为低电平，所述第四信号端的输入信号为高电平。
图7为图3的实施例中像素电路在第三阶段t3的电流流向示意图。如图7所示，第三阶段t3为补偿阶段，图中箭头方向代表电流流向。在第三阶段t3中，所述第一信号端Reset的输入信号为高电平，所述第二信号端Scan1的输入信号为高电平，所述第三信号端Scan2的输入信号为低电平，所述第四信号端EM的输入信号为高电平。此时，第二晶体管M2、第三晶体管M3、第五晶体管M5导通，第一晶体管M1、第四晶体管M4、第六晶体管M6关断。由于之前第一节点A1接地电位为0V，因此源极跟随晶体管M3导通，电流经由第五晶体管M5和第三晶体管M3流向第二晶体管M2，开始对第一节点A1进行充电，直到将第一节点A1充电至Vdata1-Vmth为止，第三晶体管M3的栅源两极之间的电压差为Vmth。充电完成之后，第一节点A1的电位将一直维持在Vdata1-Vmth。类似地，本实施例第三电压 端Vdata对第九晶体管N3进行补偿，将第三节点A3的电位补偿到Vdata2-Vnth，第九晶体管N3的栅源两极之间的电压差为Vnth。
在步骤1004，第四阶段t4，所述第一信号端的输入信号为低电平，所述第二信号端的输入信号为高电平，所述第三信号端的输入信号为高电平，所述第四信号端的输入信号为低电平。
图8为图3的实施例中像素电路在第四阶段t4的电流流向示意图。如图8所示，第四阶段t4为采集信号阶段，图中箭头方向代表电流流向。在第四阶段t4中，所述第一信号端Reset的输入信号为低电平，所述第二信号端Scan1的输入信号为高电平，所述第三信号端Scan2的输入信号为高电平，所述第四信号端EM的输入信号为低电平。此时，第三晶体管M3的源极接入电压Vdd，第二节点A2的电位为Vdd，电流通过第四晶体管M4和第三晶体管M3流向第六晶体管M6，再由读取端Readline输出。由晶体管的饱和电流公式可以得到：
I＝K1(Vgs-Vmth)2＝K1[Vdd-(Vdata1-Vmth)-Vmth]2＝K1(Vdd-Vdata1)2
其中K1是第三晶体管M3的电流系数。通过上述公式可以看出，此时工作电流I不受源极跟随晶体管的阈值电压Vmth的影响，只与Vdd和Vdata1有关，其中Vdata1直接由二极管PN结的光照产生，从而避免了由于工艺和操作造成源极跟随晶体管的阈值电压Vmth的漂移，保证了信号数据的准确性。
类似地，可以得出发光电流Ioled＝K2(Vdd-Vdata2)2，其中K2是驱动晶体管N3的电流系数。此时发光电流Ioled不受驱动晶体管N3的阈值电压Vnth的影响，只与第三电压端补偿给驱动晶体管N3的数据信号电压Vdata2有关。因此，避免了由于工艺和操作造成驱动晶体管的阈值电压Vnth的漂移，使得阈值电压Vnth不会影响发光电流Ioled，保证了有机电致发光器件的正常工作。
根据本公开实施例的像素电路的驱动方法，复位单元用于根据第一信号端和第二信号端的输入信号控制第一节点、第二节点以及第三节点的电位，充电单元用于根据第二信号端的输入信号控制第二节点的电位，补偿单元用于根据第三信号端的输入信号和第二节点的电位控制第一节点和第三节点的电位，读取单元用于根据第四信号端的输入信号控制发光器件的第一极和读取端的输出信号。本实施例提供的技术方案通过对像素电路的源极跟随晶体管进行补偿，避免了由于源极跟随晶体管自身差异导致的输出电流不均一，使得输出电流与所述源极跟随晶体管的阈值电压无关。此外，通过共用驱动信号和扫描信号，本公开实施例不仅能实现高分辨率的硅基显示功能，还具备环境影像监测功能。
可以理解的是，以上实施方式仅仅是为了说明本公开实施例的原理而采用的示例性实 施方式，然而本公开实施例并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开实施例的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开实施例的保护范围。

Claims (9)

  1. 一种像素电路，包括：
    复位单元，所述复位单元与第一信号端、第一电压端、第二信号端、第一节点、第二节点以及第三节点连接，用于根据所述第一信号端和所述第二信号端的输入信号控制所述第一节点、所述第二节点以及所述第三节点的电位；
    充电单元，所述充电单元与所述第二信号端和所述第二节点连接，用于根据所述第二信号端的输入信号控制所述第二节点的电位；
    补偿单元，所述补偿单元分别与所述第二节点、所述第一节点、第二电压端、所述第三节点、第四节点、第三电压端、第三信号端、第五节点以及第六节点连接，用于根据所述第三信号端的输入信号和所述第二节点的电位控制所述第一节点和所述第三节点的电位；
    读取单元，连接发光器件的第一极，所述发光器件的第二极接地；所述读取单元分别与所述第一电压端、所述第四信号端、所述第四节点、所述第五节点、所述第六节点以及读取端连接，用于根据所述第四信号端的输入信号控制所述发光器件的第一极和所述读取端的输出信号。
  2. 根据权利要求1所述的像素电路，其中，所述复位单元包括第四晶体管、第一晶体管以及第七晶体管；
    所述第四晶体管的栅极与所述第一信号端连接，所述第四晶体管的第一极与所述第一电压端连接，所述第四晶体管的第二极与所述第二节点连接；
    所述第一晶体管的栅极与所述第二信号端连接，所述第一晶体管的第一极接地，所述第一晶体管的第二极与所述第一节点连接；
    所述第七晶体管的栅极与所述第二信号端连接，所述第七晶体管的第一极接地，所述第七晶体管的第二极与所述第三节点连接。
  3. 根据权利要求1所述的像素电路，其中，所述充电单元连接感光器件的第二极，所述感光器件的第一极接地，所述感光器件包括光电二极管。
  4. 根据权利要求1所述的像素电路，其中，所述充电单元包括第五晶体管和第二电容；
    所述第五晶体管的栅极与所述第二信号端连接，所述第五晶体管的第一极与所述感光器件的第二极连接，所述第五晶体管的第二极与所述第二节点连接；
    所述第二电容的第一极与所述第二节点连接，所述第二电容的第二极接地。
  5. 根据权利要求1所述的像素电路，其中，所述补偿单元包括第三晶体管、第二晶体管、第八晶体管、第九晶体管、第十一晶体管、第一电容以及第三电容；
    所述第三晶体管的栅极与所述第一节点连接，所述第三晶体管的第一极与所述第二节点连接，所述第三晶体管的第二极与所述第六节点连接；
    所述第二晶体管的栅极与所述第三信号端连接，所述第二晶体管的第一极与所述第一节点连接，所述第二晶体管的第二极与所述第六节点连接；
    所述第八晶体管的栅极与所述第三信号端连接，所述第八晶体管的第一极与所述第三节点连接，所述第八晶体管的第二极与所述第五节点连接；
    所述第九晶体管的栅极与所述第三节点连接，所述第九晶体管的第一极与所述第四节点连接，所述第九晶体管的第二极与所述第五节点连接；
    所述第十一晶体管的栅极与所述第三信号端连接，所述第十一晶体管的第一极与所述第四节点连接，所述第十一晶体管的第二极与所述第三电压端连接；
    所述第一电容的第一极与所述第一节点连接，所述第一电容的第二极与所述第二电压端连接；
    所述第三电容的第一极与所述第二电压端连接，所述第三电容的第二极与所述第三节点连接。
  6. 根据权利要求1所述的像素电路，其特征在于，所述读取单元包括第十晶体管、第十二晶体管以及第六晶体管；
    所述第十晶体管的栅极与所述第四信号端连接，所述第十晶体管的第一极与所述第一电压端连接，所述第十晶体管的第二极与所述第四节点连接；
    所述第十二晶体管的栅极与所述第四信号端连接，所述第十二晶体管的第一极与所述第五节点连接，所述第十二晶体管的第二极与所述发光器件的第一极连接；
    所述第六晶体管与所述第四信号端连接，所述第六晶体管的第一极与所述第六节点连接，所述第六晶体管的第二极与所述读取端连接。
  7. 根据权利要求2-6任一所述的像素电路，其中，所述第一晶体管至第十二晶体管均为N型晶体管或者均为P型晶体管。
  8. 一种显示装置，包括权利要求1-7任一所述的像素电路。
  9. 一种权利要求1-7任一所述的像素电路的驱动方法，所述第一电压端为第一电平，所述第二电压端为公共电压，所述第三电压端为数据信号电压；
    所述像素电路的驱动方法包括：
    在第一阶段，向所述第一信号端输入第二电平，向所述第二信号端输入第二电平，向所述第三信号端输入第一电平，向所述第四信号端输入第一电平；
    在第二阶段，向所述第一信号端输入第一电平，向所述第二信号端输入第二电平，向所述第三信号端输入第一电平，向所述第四信号端输入第一电平；
    在第三阶段，向所述第一信号端输入第一电平，向所述第二信号端输入第一电平，向所述第三信号端输入第二电平，向所述第四信号端输入第一电平；
    在第四阶段，向所述第一信号端输入第二电平，向所述第二信号端输入第一电平，向所述第三信号端输入第一电平，向所述第四信号端输入第二电平。
PCT/CN2017/097645 2017-01-18 2017-08-16 像素电路及其驱动方法、显示装置 WO2018133404A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/757,297 US10373558B2 (en) 2017-01-18 2017-08-16 Pixel circuit, a driving method thereof and a display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710035131.7A CN106782273A (zh) 2017-01-18 2017-01-18 像素电路及其驱动方法、显示装置
CN201710035131.7 2017-01-18

Publications (1)

Publication Number Publication Date
WO2018133404A1 true WO2018133404A1 (zh) 2018-07-26

Family

ID=58946240

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/097645 WO2018133404A1 (zh) 2017-01-18 2017-08-16 像素电路及其驱动方法、显示装置

Country Status (3)

Country Link
US (1) US10373558B2 (zh)
CN (1) CN106782273A (zh)
WO (1) WO2018133404A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3861715A4 (en) * 2018-10-27 2022-04-27 Huawei Technologies Co., Ltd. SENSOR AND INDICATOR

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106782273A (zh) 2017-01-18 2017-05-31 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN109461414B (zh) * 2018-11-09 2020-11-06 惠科股份有限公司 一种显示装置的驱动电路及方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100220093A1 (en) * 2009-03-02 2010-09-02 Sang-Moo Choi Organic light emitting display
US20110069058A1 (en) * 2009-09-22 2011-03-24 Bo-Yong Chung Pixel circuit of display panel, method of controlling the pixel circuit, and organic light emitting display including the display panel
CN103700345A (zh) * 2013-12-27 2014-04-02 京东方科技集团股份有限公司 有机发光二极管像素电路及其驱动方法、显示面板
CN104851392A (zh) * 2015-06-03 2015-08-19 京东方科技集团股份有限公司 一种像素驱动电路及方法、阵列基板和显示装置
CN105933623A (zh) * 2016-06-29 2016-09-07 京东方科技集团股份有限公司 像素电路及其驱动方法、图像传感器及图像获取装置
CN106782273A (zh) * 2017-01-18 2017-05-31 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9336717B2 (en) * 2012-12-11 2016-05-10 Ignis Innovation Inc. Pixel circuits for AMOLED displays

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100220093A1 (en) * 2009-03-02 2010-09-02 Sang-Moo Choi Organic light emitting display
US20110069058A1 (en) * 2009-09-22 2011-03-24 Bo-Yong Chung Pixel circuit of display panel, method of controlling the pixel circuit, and organic light emitting display including the display panel
CN103700345A (zh) * 2013-12-27 2014-04-02 京东方科技集团股份有限公司 有机发光二极管像素电路及其驱动方法、显示面板
CN104851392A (zh) * 2015-06-03 2015-08-19 京东方科技集团股份有限公司 一种像素驱动电路及方法、阵列基板和显示装置
CN105933623A (zh) * 2016-06-29 2016-09-07 京东方科技集团股份有限公司 像素电路及其驱动方法、图像传感器及图像获取装置
CN106782273A (zh) * 2017-01-18 2017-05-31 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3861715A4 (en) * 2018-10-27 2022-04-27 Huawei Technologies Co., Ltd. SENSOR AND INDICATOR
US11594161B2 (en) 2018-10-27 2023-02-28 Huawei Technologies Co., Ltd. Sensor and display device

Also Published As

Publication number Publication date
CN106782273A (zh) 2017-05-31
US20190073950A1 (en) 2019-03-07
US10373558B2 (en) 2019-08-06

Similar Documents

Publication Publication Date Title
CN106782272B (zh) 像素电路及其驱动方法、显示装置
WO2017197969A1 (zh) 有源像素传感器电路、驱动方法和图像传感器
US11238796B2 (en) Pixel circuit and control method therefor, display substrate and display device
US10140923B2 (en) Pixel driving system of AMOLED having initialization signal of alternating high and low levels and method for driving pixel of AMOLED having initialization signal of alternating high and low levels
TWI573117B (zh) 主動式有機發光二極體顯示器的像素電路
WO2017008484A1 (zh) 一种像素驱动电路及其驱动方法、显示面板和显示装置
CN108806599B (zh) 用于补偿oled像素电路的方法
US10235932B2 (en) OLED inverting circuit and display panel
WO2015003465A1 (zh) 一种触摸显示驱动电路、驱动方法及显示装置
WO2020001027A1 (zh) 像素驱动电路及方法、显示装置
WO2018000927A1 (zh) 像素电路、半导体摄像头检测电路以及显示装置
CN110232889B (zh) 像素驱动电路以及显示面板
WO2019029282A1 (zh) 像素电路及其驱动方法以及触控显示装置
WO2016155161A1 (zh) Oeld像素电路、显示装置及控制方法
US11341912B2 (en) Pixel circuit and method for driving the same, display panel and display device
WO2020182017A1 (zh) 像素电路、显示面板、显示装置和像素驱动方法
WO2018133404A1 (zh) 像素电路及其驱动方法、显示装置
US11295666B2 (en) Method for driving a pixel circuit with feedback compensation, a circuit for driving a light-emitting device, and a display apparatus
US10665147B2 (en) Photosensitive circuit, method of driving photosensitive circuit and display device
WO2018001014A1 (zh) 像素电路及其驱动方法、图像传感器及图像获取装置
TWI735338B (zh) 畫素驅動電路
WO2019205905A1 (zh) 像素驱动电路及其驱动方法、及显示装置
WO2016180110A1 (zh) 驱动电路及其驱动方法、显示基板及其驱动方法、显示装置
WO2017193630A1 (zh) 像素电路、驱动方法、阵列基板、显示面板及显示装置
TWI771075B (zh) 光感測畫素與具光感測功能的顯示裝置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17893398

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17893398

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 04/02/2020)

122 Ep: pct application non-entry in european phase

Ref document number: 17893398

Country of ref document: EP

Kind code of ref document: A1