WO2018129833A1

WO2018129833A1 - Smart sine-wave voltage conversion circuit based on mos tube full-bridge rectification

Info

Publication number: WO2018129833A1
Application number: PCT/CN2017/081782
Authority: WO
Inventors: 廖志刚; 李金龙
Original assignee: 广东百事泰电子商务股份有限公司
Priority date: 2017-01-12
Filing date: 2017-04-25
Publication date: 2018-07-19
Also published as: CN106787808A

Abstract

Provided is a smart sine-wave voltage conversion circuit based on MOS tube full-bridge rectification, comprising an alternating-current input unit (10), a MOS tube full-bridge rectifier unit (20), a PFC boost unit (30), a CLC filter unit (40), and an inverting phase-inversion unit (60). the MOS tube full-bridge rectifier unit comprises a first MOS tube (Q1), a second MOS tube (Q2), a third MOS tube (Q3), a fourth MOS tube (Q4), and a first capacitor (C1). The first MOS tube and fourth MOS tube conduct electricity simultaneously, and the second MOS tube and the third MOS tube conduct electricity simultaneously. The CLC filter unit comprises a filter inductor (L3), a first filter capacitor (C2), and a second filter capacitor (C3). The front end of the filter inductor is connected to the output end of the PFC boost unit, and the rear end of the filter inductor is used as the output end of the CLC filter unit. The first filter capacitor is connected between the front end of the filter inductor and a ground, and the second filter capacitor is connected between the rear end of the filter inductor and the ground. The circuit improves conversion efficiency, meets the requirements of fan-free heat dissipation, and reduces noise.

Description

Intelligent sine wave voltage conversion circuit based on MOS tube full bridge rectification

Technical field

The invention relates to a voltage conversion circuit, in particular to an intelligent sine wave voltage conversion circuit based on MOS tube full bridge rectification.

Background technique

In the prior art, the AC-to-AC intelligent buck-boost conversion device is also called a travel plug, and the voltage conversion circuit is a key circuit applied to the AC-to-AC intelligent buck-boost conversion device, which is also called a travel plug. The function of stepping down and stabilizing voltage and frequency in AC/AC conversion. At present, in the AC/AC portable device, the rectifier part mostly uses a diode or a rectifier bridge as a rectifying component. When the AC voltage reaches 90V, the rectifier diode or the bridge stack generates a serious heat. Therefore, a fan needs to be added in the portable AC-AC device. Cooling, but this approach will cause noise problems while the input PF value is low. In practical applications, due to the high-speed switching of the switching tube during the voltage conversion process, a certain high-frequency pulse signal exists on the output side of the circuit, thereby affecting the quality of the output voltage, and thus it is difficult to meet the conversion requirement.

Summary of the invention

The technical problem to be solved by the present invention is to provide a MOSFET based on the deficiencies of the prior art, which can improve the PF value of the voltage conversion device, filter high frequency crosstalk, reduce noise, reduce product cost, and reduce product volume. Intelligent sinusoidal voltage conversion circuit for bridge rectification.

In order to solve the above technical problems, the present invention adopts the following technical solutions.

An intelligent sinusoidal voltage conversion circuit based on MOS tube full bridge rectification, comprising: an AC input unit for accessing alternating current; a MOS tube full bridge rectifier unit comprising a first MOS tube and a second MOS a transistor, a third MOS transistor, a fourth MOS transistor, and a first capacitor, wherein a drain of the first MOS transistor and a source of the third MOS transistor are both connected to a first output end of the AC input unit, the second MOS The drain of the tube and the source of the fourth MOS transistor are both connected to the second output end of the AC input unit, and the source of the first MOS transistor and the source of the second MOS transistor are connected to each other and then rectified as a MOS tube. The output terminal of the cell is positive, the drain of the third MOS transistor and the drain of the fourth MOS transistor are connected to each other as a negative terminal of the output end of the MOS transistor full-bridge rectifying unit, and the gate of the first MOS transistor and the second a gate of the MOS transistor, a gate of the third MOS transistor, and a gate of the fourth MOS transistor are respectively used for accessing a PWM pulse signal, so that the first MOS transistor and the fourth MOS transistor are simultaneously turned on. The second MOS transistor and the third MOS transistor are simultaneously turned on, and the first capacitor is connected in parallel to the output end of the MOS tube full-bridge rectifying unit; a PFC liter Means, connected to the full bridge rectifier single MOS transistor a PFC boosting unit for boosting the output voltage of the MOS full-bridge rectifier unit; a CLC filtering unit including a filter inductor, a first filter capacitor, and a second filter capacitor, The front end of the filter inductor is connected to the output end of the PFC boosting unit, the rear end of the filter inductor is used as the output end of the CLC filter unit, and the first filter capacitor is connected between the front end of the filter inductor and the ground, the second The filter capacitor is connected between the back end of the filter inductor and the ground; an inverter inverter unit is connected to the output end of the CLC filter unit, and the inverter inverter unit is used for inverting the output voltage of the CLC filter unit into an alternating current .

Preferably, the PFC boosting unit includes a boosting inductor, a first switching transistor, a first rectifier diode, and an electrolytic capacitor, and a front end of the boosting inductor is connected to an output end of the input unit, and the boosting inductor is behind The end is connected to the drain of the first switch tube, the source of the first switch tube is grounded, the gate of the first switch tube is used to access a PWM control signal, and the drain of the first switch tube is connected The anode of the first rectifier diode, the cathode of the first rectifier diode serves as an output of the PFC boosting unit, and the cathode of the first rectifier diode is connected to the anode of the electrolytic capacitor, and the cathode of the electrolytic capacitor is grounded.

Preferably, a pull-down resistor is connected between the gate and the source of the first switching transistor.

Preferably, the method further includes a control unit, a gate of the first MOS transistor, a gate of the second MOS transistor, a gate of the third MOS transistor, a gate of the fourth MOS transistor, and a gate of the first switching transistor The control unit is electrically connected to the control unit, and the on/off states of the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, and the first switching transistor are controlled by the control unit.

Preferably, the first output end and the second output end of the AC input unit are respectively connected to the control unit through a current limiting resistor, so that the control unit acquires the phase of the AC voltage.

Preferably, the AC input unit comprises a socket, a first fuse, a lightning protection resistor, a common mode suppression inductor and a safety capacitor, wherein the first fuse is connected to a neutral or a live line of the socket, and the common mode rejection The front end of the inductor is connected in parallel to the socket, the lightning protection resistor is connected in parallel to the front end of the common mode suppression inductor, the safety capacitor is connected in parallel to the rear end of the common mode rejection inductor, and the back end of the common mode suppression inductor is used as an AC input unit. The output.

Preferably, the method further includes a DC voltage sampling unit, the DC voltage sampling unit includes a second sampling resistor and a third sampling resistor connected in series, and a front end of the second sampling resistor is connected to an output end of the CLC filtering unit. The rear end of the third sampling resistor is connected to the control unit, and the control unit acquires the electrical signal output by the CLC filtering unit by the second sampling resistor and the third sampling resistor.

Preferably, the inverter inverting unit comprises an inverter bridge composed of a second switching tube, a third switching tube, a fourth switching tube and a fifth switching tube, and a gate and a third switch of the second switching tube a gate of the tube, a gate of the fourth switch tube, and a gate of the fifth switch tube are respectively connected to the control unit, and the fourth switch tube, the fifth switch tube, and the second control unit are controlled by the control unit The six switch tubes and the seventh switch tube are turned on or off to cause the inverter inverting unit to output an AC voltage.

Preferably, the output of the inverter inverting unit has a second fuse in series.

Preferably, the control unit comprises a single chip microcomputer and its peripheral circuits.

In the intelligent sinusoidal voltage conversion circuit based on MOS tube full bridge rectification, the AC input unit is connected to the AC power source, so that the AC power is transmitted to the MOS tube full bridge rectifier unit, and in the MOS tube full bridge rectifier unit, when L When the sinusoidal half cycle is performed, the second MOS transistor and the third MOS transistor are turned on, and the current is formed by the fire L line, the second MOS transistor, the first capacitor, and the third MOS transistor, and when the N line is a sinusoidal half cycle, the first The MOS transistor and the fourth MOS transistor are turned on, and the current is formed by the N line, the first MOS transistor, the first capacitor, and the fourth MOS transistor; through the above process, a DC voltage is formed on the first capacitor, and the first capacitor is for The rectified ripple is filtered out, and smooth DC power is obtained and transmitted to the PFC boosting unit for boost conversion. Finally, the output voltage of the PFC boosting unit is inverted into an alternating current for use by the inverter inverting unit. In the above voltage conversion circuit, since the conduction internal resistance of the MOS transistor is small, the power consumption of the current on the MOS transistor is small, so the efficiency after rectification is high, and the PF value of the voltage conversion device can be effectively improved. At the same time, no fan cooling is required, which reduces noise, reduces product cost, and reduces product size. In addition, under the action of the CLC filtering unit, the high-frequency components in the envelope half-wave level containing the high-frequency pulse in the circuit can be filtered out, leaving only the low-frequency component to be transmitted to the inverter inverting unit, so that the inverter is inverted. The phase unit is converted to a higher quality sinusoidal alternating current, which in turn greatly increases the quality of the output voltage.

DRAWINGS

Figure 1 is a circuit schematic of a sinusoidal voltage conversion circuit.

Figure 2 is a circuit block diagram of the control unit.

detailed description

The invention will now be described in greater detail with reference to the drawings and embodiments.

The invention discloses an intelligent sinusoidal voltage conversion circuit based on MOS tube full bridge rectification, which is combined with FIG. 1 and FIG. 2 and includes:

An AC input unit 10 for accessing an alternating current;

A MOS full-bridge rectifier unit 20 includes a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, and a first capacitor C1. The drain of the first MOS transistor Q1 The source of the third MOS transistor Q3 is connected to the first output end of the AC input unit 10, and the drain of the second MOS transistor Q2 and the source of the fourth MOS transistor Q4 are both connected to the AC input unit 10. The output terminal of the first MOS transistor Q1 and the source of the second MOS transistor Q2 are connected to each other as the positive terminal of the output end of the MOS transistor full-bridge rectifying unit 20, and the third MOS transistor Q3 The drain and the drain of the fourth MOS transistor Q4 are connected to each other as the output terminal of the MOS transistor full-bridge rectifying unit 20, the gate of the first MOS transistor Q1, the gate of the second MOS transistor Q2, and the third The gate of the MOS transistor Q3 and the gate of the fourth MOS transistor Q4 are respectively used to access the PWM pulse signal, so that the first MOS transistor Q1 and the fourth MOS transistor Q4 are simultaneously turned on, and the second MOS transistor Q2 is turned on. Simultaneously conducting with the third MOS transistor Q3, the first capacitor C1 is connected in parallel to the output end of the MOS tube full-bridge rectifying unit 20;

a PFC boosting unit 30 is connected to the output end of the MOS tube full-bridge rectifying unit 20, and the PFC boosting unit 30 is configured to perform boost conversion on the output voltage of the MOS tube full-bridge rectifying unit 20;

A CLC filtering unit 40 includes a filter inductor L3, a first filter capacitor C2, and a second filter capacitor C3. The front end of the filter inductor L3 is connected to the output end of the PFC boost unit 30, and the back end of the filter inductor L3. As the output end of the CLC filtering unit 40, the first filter capacitor C2 is connected between the front end of the filter inductor L3 and the ground, and the second filter capacitor C3 is connected between the back end of the filter inductor L3 and the ground;

An inverter inverting unit 60 is connected to the output of the CLC filtering unit 40, and the inverter inverting unit 60 is configured to invert the output voltage of the CLC filtering unit 40 into alternating current.

In the above intelligent sinusoidal voltage conversion circuit, the AC input unit 10 is connected to the AC power source, so that the AC power is transmitted to the MOS tube full bridge rectifier unit 20, and in the MOS tube full bridge rectifier unit 20, when L is a sine half cycle, the first The second MOS transistor Q2 and the third MOS transistor Q3 are turned on, and the current is formed by the fire L line, the second MOS transistor Q2, the first capacitor C1, and the third MOS transistor Q3. When the N line is a sinusoidal half cycle, the first MOS transistor Q1 and the fourth MOS transistor Q4 are turned on, and the current is formed by the N line, the first MOS transistor Q1, the first capacitor C1, and the fourth MOS transistor Q4. Through the above process, a DC voltage is formed on the first capacitor C1. A capacitor C1 is used to filter out the rectified ripple, thereby obtaining a smooth direct current and transmitting it to the PFC boosting unit 30 for boost conversion. Finally, the output of the PFC boosting unit 30 is sinusoidal half-wave by the inverter inverting unit 60. The voltage is inverted to sinusoidal AC for use. In the above voltage conversion circuit, the MOS transistor is used as the rectifying device. Since the conduction internal resistance of the MOS transistor is small, the current consumption of the current on the MOS transistor is small, so the efficiency after rectification is high and effective. Increase the PF value of the voltage conversion device without the need for fan cooling, which reduces noise, reduces product cost, and reduces product size. Under the action of the CLC filtering unit 40, the high frequency components in the envelope half-wave level containing the high-frequency pulse in the circuit can be filtered out, leaving only the low-frequency component to be transmitted to the inverter inverting unit 60, so that the inverter is inverted. The phase unit 60 is converted to a higher quality sinusoidal alternating current, thereby greatly improving the quality of the output voltage.

In order to make the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3, and the fourth MOS transistor Q4 respond quickly, the present invention uses four resistors (R1, R2, R3, and R4) as four rectifications respectively. The pull-down resistor of the MOS transistor prevents mis-conduction.

Regarding the boosting portion, the PFC boosting unit 30 includes a boosting inductor L2, a first switching transistor Q5, a first rectifier diode D1, and an electrolytic capacitor C2. The front end of the boosting inductor L2 is connected to the output of the input unit 10. The back end of the boosting inductor L2 is connected to the drain of the first switching transistor Q5, the source of the first switching transistor Q5 is grounded, and the gate of the first switching transistor Q5 is used to access one PWM. a control signal, a drain of the first switching transistor Q5 is connected to an anode of the first rectifier diode D1, a cathode of the first rectifier diode D1 is an output end of the PFC boosting unit 30, and a cathode of the first rectifier diode D1 The positive electrode of the electrolytic capacitor C2 is connected, and the negative electrode of the electrolytic capacitor C2 is grounded.

Further, a pull-down resistor R5 is connected between the gate and the source of the first switching transistor Q5.

In the above PFC boosting unit 30, if the input grid voltage is lower than 230V, the control unit outputs a high frequency control signal PWM5 to the GATE of the first switching transistor Q5, and the full bridge rectified half wave AC voltage composed of four MOS tubes is A switching transistor Q5 is boosted by a PFC boosting method. The specific boosting principle is: when the first switching transistor Q5 is turned on, the current on the first capacitor C1 is formed by the boosting inductor L2 and the first switching transistor Q5 to GND. In the loop, the boosting inductor L2 stores energy; when the first switching transistor Q5 is turned off, an induced electromotive force is formed on the boosting inductor that is much higher than the input voltage, and the induced electromotive force is formed by rectifying the first rectifier diode D1 of the freewheeling tube. The unidirectional ripple voltage is then sent to the high frequency filter circuit for filtering. And the first switch tube Q5 controls the duty cycle change of the PWM1 according to the input fundamental voltage of the input grid voltage obtained by the AC sampling circuit, and the level rectified by the first rectifier diode D1 is sinusoidal but contains a high frequency The envelope half-wave level of the pulse. When the input grid voltage is equal to or greater than 230V, the single chip U1 turns off the high frequency modulation circuit, and the first switch tube Q5 does not work; the MOS full bridge rectified and filtered voltage is directly output through L2 and the first rectifier diode D1.

In order to achieve closed-loop control, the embodiment further includes a control unit 70, a gate of the first MOS transistor Q1, a gate of the second MOS transistor Q2, a gate of the third MOS transistor Q3, and a fourth MOS transistor Q4. The gates and the gates of the first switching transistors Q5 are electrically connected to the control unit 70, respectively, and the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3, and the fourth MOS are controlled by the control unit 70. The on and off states of the tube Q4 and the first switching tube Q5. Further, the control unit 70 includes a single chip U1 and its peripheral circuits.

Further, regarding the sampling of the alternating current signal, the first output end and the second output end of the alternating current input unit 10 are respectively connected to the control unit 70 through a current limiting resistor, so that the control unit 70 acquires the phase of the alternating current voltage. Specifically, the control unit samples the amplitude and phase of the AC voltage through the sampling resistors (R10, R11, R12, R14, R17, R18, R19, and R20), thereby controlling the first MOS transistor Q1 and the second MOS transistor Q2. The conduction phase and time of the three MOS transistors Q3 and the fourth MOS transistor Q4.

In this embodiment, the AC input unit 10 includes a socket, a first fuse F2, a lightning protection resistor RV1, a common mode suppression inductor L1, and a safety capacitor CX1. The first fuse F2 is connected in series to the neutral line of the socket or a front end of the common mode suppression inductor L1 is connected in parallel to the socket, and the lightning protection resistor RV1 is connected in parallel to the front end of the common mode suppression inductor L1. The gauge capacitor CX1 is connected in parallel to the rear end of the common mode rejection inductor L1, and the rear end of the common mode rejection inductor L1 serves as the output terminal of the AC input unit 10.

As a preferred manner, the embodiment further includes a DC voltage sampling unit 40, the DC voltage sampling unit 40 includes a second sampling resistor R13 and a third sampling resistor R15 connected in series, and the second sampling resistor R13 The front end is connected to the output end of the CLC filtering unit 40, the rear end of the third sampling resistor R15 is connected to the control unit 70, and the control unit 70 collects CLC filtering by the second sampling resistor R13 and the third sampling resistor R15. The electrical signal output by unit 40. The voltage sampling part is composed of R13 and R15, and is used for sending the collected voltage to the control unit, thereby determining the phase and the on-time of the inverter inverting unit.

Regarding the inverter part, the inverter inverting unit 60 includes an inverter bridge composed of a second switching tube Q6, a third switching tube Q7, a fourth switching tube Q8, and a fifth switching tube Q9, and the second switching tube The gate of Q6, the gate of the third switching transistor Q7, the gate of the fourth switching transistor Q8, and the gate of the fifth switching transistor Q9 are respectively connected to the control unit 70, and the fourth switch is controlled by the control unit 70. The tube Q1, the fifth switching transistor Q2, the sixth switching transistor Q3, and the seventh switching transistor Q4 are turned on or off to cause the inverter inverting unit 60 to output an alternating voltage. Further, the output of the inverter inverting unit 60 has a second fuse F1 connected in series.

The inverter inverting unit 50 is composed of a second switching tube Q6, a third switching tube Q7, a fourth switching tube Q8 and a fifth switching tube Q9. The filtered DC voltage is controlled by the second switching tube Q6, the load, and the fifth The switch tube Q9 forms a loop to supply power to the load to form a first half cycle power frequency level; the second half cycle power frequency level forms a loop through the fourth switch tube Q8, the load, and the third switch tube Q7, so that the load is on the load. A complete power frequency correction wave AC voltage is formed. After the PWM signal outputted by the control unit passes through the driving circuit, PWM6, PWM7L, PWM8, and PWM9L are respectively sent to the GATE poles of the second switching transistor Q6, the third switching transistor Q7, the fourth switching transistor Q8, and the fifth switching transistor Q9. The phase and frequency in the inverter inverter circuit operate in accordance with the mode set in the control chip.

The intelligent sinusoidal voltage conversion circuit based on MOS tube full bridge rectification disclosed in the invention has the characteristics of high efficiency, high PF value, and the like, and does not need a fan, and adopts a natural cold correct mode to eliminate noise. The invention can automatically adjust the output voltage in the input full voltage range, and fix the output frequency, and the output voltage is outputted as a sine wave, and has an automatic shaping function for the alternating voltage. Moreover, the invention includes a voltage and current sampling circuit, which can prevent waves. Surge voltage and current.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention. All modifications, equivalents, and improvements made within the technical scope of the present invention are intended to be included within the scope of the present invention.

Claims

An intelligent sine wave voltage conversion circuit based on MOS tube full bridge rectification, characterized in that it comprises:

An AC input unit (10) for accessing an alternating current;

A MOS full-bridge rectifier unit (20) includes a first MOS transistor (Q1), a second MOS transistor (Q2), a third MOS transistor (Q3), a fourth MOS transistor (Q4), and a first capacitor (C1) The drain of the first MOS transistor (Q1) and the source of the third MOS transistor (Q3) are both connected to the first output end of the AC input unit (10), and the second MOS transistor (Q2) The drain and the source of the fourth MOS transistor (Q4) are both connected to the second output of the AC input unit (10), the source of the first MOS transistor (Q1) and the source of the second MOS transistor (Q2) After the poles are connected to each other, the anode of the MOS tube full-bridge rectifier unit (20) is positive, and the drain of the third MOS transistor (Q3) and the drain of the fourth MOS transistor (Q4) are connected to each other as a full bridge of the MOS transistor. The output terminal of the rectifying unit (20) is negative, the gate of the first MOS transistor (Q1), the gate of the second MOS transistor (Q2), the gate of the third MOS transistor (Q3), and the fourth MOS transistor ( The gates of Q4) are respectively used to access the PWM pulse signals, so that the first MOS transistor (Q1) and the fourth MOS transistor (Q4) are simultaneously turned on, the second MOS transistor (Q2) and the third MOS The tube (Q3) is simultaneously turned on, and the first capacitor (C1) is connected in parallel to the output end of the MOS tube full-bridge rectifying unit (20);

A PFC boosting unit (30) is connected to the output end of the MOS tube full-bridge rectifying unit (20) for boosting the output voltage of the MOS tube full-bridge rectifying unit (20) Pressure conversion

a CLC filtering unit (40) includes a filter inductor (L3), a first filter capacitor (C2), and a second filter capacitor (C3), and a front end of the filter inductor (L3) is connected to the PFC boost unit (30) The output end of the filter inductor (L3) serves as an output end of the CLC filter unit (40), and the first filter capacitor (C2) is connected between the front end of the filter inductor (L3) and the ground. The second filter capacitor (C3) is connected between the back end of the filter inductor (L3) and the ground;

An inverter inverting unit (60) is connected to the output end of the CLC filtering unit (40) for inverting the output voltage of the CLC filtering unit (40) into alternating current.
The intelligent sinusoidal voltage conversion circuit based on MOS tube full bridge rectification according to claim 1, wherein the PFC boosting unit (30) comprises a boosting inductor (L2) and a first switching transistor (Q5). a first rectifier diode (D1) and an electrolytic capacitor (C2), the front end of the boost inductor (L2) is connected to the output end of the input unit (10), and the back end of the boost inductor (L2) is connected to a drain of the first switch transistor (Q5), a source of the first switch transistor (Q5) is grounded, and a gate of the first switch transistor (Q5) is configured to receive a PWM control signal, the first The drain of the switch transistor (Q5) is connected to the anode of the first rectifier diode (D1), the cathode of the first rectifier diode (D1) serves as the output terminal of the PFC boost unit (30), and the first rectifier diode (D1) The cathode is connected to the positive electrode of the electrolytic capacitor (C2), and the negative electrode of the electrolytic capacitor (C2) is grounded.
The intelligent sinusoidal voltage conversion circuit based on MOS tube full bridge rectification according to claim 2, wherein a pull-down resistor (R5) is connected between a gate and a source of the first switching transistor (Q5) .
The intelligent sinusoidal voltage conversion circuit based on MOS tube full bridge rectification according to claim 3, further comprising a control unit (70), a gate of the first MOS transistor (Q1), and a second The gate of the MOS transistor (Q2), the gate of the third MOS transistor (Q3), the gate of the fourth MOS transistor (Q4), and the gate of the first switching transistor (Q5) are electrically connected to the control unit (70, respectively). Controlling the first MOS transistor (Q1), the second MOS transistor (Q2), the third MOS transistor (Q3), the fourth MOS transistor (Q4), and the first switching transistor by the control unit (70) Q5) on and off status.
The intelligent sinusoidal voltage conversion circuit based on MOS tube full bridge rectification according to claim 4, wherein the first output end and the second output end of the AC input unit (10) pass through current limiting resistors respectively It is connected to the control unit (70) to enable the control unit (70) to acquire the phase of the alternating current voltage.
The intelligent sinusoidal voltage conversion circuit based on MOS tube full bridge rectification according to claim 1, wherein the AC input unit (10) comprises a socket, a first fuse (F2), and a lightning protection resistor (RV1). a common mode suppression inductor (L1) and a safety capacitor (CX1), the first fuse (F2) is connected in series to the neutral or the live line of the socket, and the front end of the common mode suppression inductor (L1) is connected in parallel to the socket The lightning protection resistor (RV1) is connected in parallel to the front end of the common mode rejection inductor (L1), the safety capacitor (CX1) is connected in parallel to the rear end of the common mode rejection inductor (L1), and the common mode rejection inductance ( The back end of L1) serves as the output of the AC input unit (10).
The intelligent sinusoidal voltage conversion circuit based on MOS tube full bridge rectification according to claim 4, further comprising a DC voltage sampling unit (40), wherein the DC voltage sampling unit (40) comprises a series connection in sequence a second sampling resistor (R13) and a third sampling resistor (R15), a front end of the second sampling resistor (R13) is connected to an output end of the CLC filtering unit (40), and the third sampling resistor (R15) The back end is connected to the control unit (70), and the control unit (70) acquires an electrical signal output by the CLC filtering unit (40) by the second sampling resistor (R13) and the third sampling resistor (R15).
The intelligent sinusoidal voltage conversion circuit based on MOS tube full bridge rectification according to claim 4, wherein the inverter inverting unit (60) comprises a second switching tube (Q6) and a third switching tube (Q7), an inverter bridge composed of a fourth switch tube (Q8) and a fifth switch tube (Q9), a gate of the second switch tube (Q6), a gate of the third switch tube (Q7), and a first The gates of the four switching transistors (Q8) and the gates of the fifth switching transistor (Q9) are respectively connected to the control unit (70), and the fourth switching transistor (Q1) and the fifth are controlled by the control unit (70). The switch tube (Q2), the sixth switch tube (Q3), and the seventh switch tube (Q4) are turned on or off to cause the inverter inverter unit (60) to output an AC voltage.
An intelligent sinusoidal voltage conversion circuit based on MOS tube full bridge rectification according to claim 8, wherein The output of the inverter inverter unit (60) has a second fuse (F1) connected in series.
The intelligent sinusoidal voltage conversion circuit based on MOS tube full bridge rectification according to claim 4, wherein the control unit (70) comprises a single chip (U1) and its peripheral circuits.