WO2018126691A1 - 移位寄存器单元及其驱动方法、移位寄存器以及显示装置 - Google Patents

移位寄存器单元及其驱动方法、移位寄存器以及显示装置 Download PDF

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Publication number
WO2018126691A1
WO2018126691A1 PCT/CN2017/097386 CN2017097386W WO2018126691A1 WO 2018126691 A1 WO2018126691 A1 WO 2018126691A1 CN 2017097386 W CN2017097386 W CN 2017097386W WO 2018126691 A1 WO2018126691 A1 WO 2018126691A1
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WIPO (PCT)
Prior art keywords
voltage
transistor
node
coupled
shift register
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Ceased
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PCT/CN2017/097386
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English (en)
French (fr)
Inventor
陈沫
张杨
高吉磊
傅武霞
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/750,417 priority Critical patent/US10204587B2/en
Publication of WO2018126691A1 publication Critical patent/WO2018126691A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a shift register, an array substrate, and a display device.
  • the liquid crystal display panel is composed of a vertical and horizontal array pixel matrix.
  • the gate scan signal is output through the gate driving circuit during the display process, and each pixel unit is scanned line by line.
  • Gate driver on Array is a technology that integrates a shift register on an array substrate.
  • Each GOA unit as a shift register unit sequentially transfers the scan signal to the next GOA unit, thereby turning on the switching transistors in the pixel unit row by row to input the data signals of the pixel units.
  • Embodiments described herein provide a shift register unit and a method of driving the same, a shift register, an array substrate, and a display device.
  • the shift register unit occupies a small area of the TFT array substrate, and a narrow bezel design can be realized.
  • a shift register unit includes an input circuit, a reset circuit, a noise reduction circuit, and an output circuit.
  • the input circuit is configured to control the voltage of the first node according to the first input signal from the first input and the second input signal from the second input, according to the first voltage from the first voltage terminal and the voltage of the first node The voltage of the second node.
  • the reset circuit is configured to be reset according to the reset signal terminal The signal and the second voltage from the second voltage terminal reset the voltage of the first node and the voltage of the second node.
  • the noise reduction circuit is configured to maintain a reset voltage of the first node and the second node in accordance with the first clock signal and the second voltage from the first clock signal terminal.
  • the output circuit is configured to provide a second clock signal or a second voltage from the second clock signal terminal to the output of the output circuit under control of the voltage of the second node and the first clock signal.
  • the shift register unit is composed of switching elements.
  • the input circuit includes a first transistor, a second transistor, and a third transistor.
  • the control electrode and the first electrode of the first transistor are coupled to the first input, and the second electrode of the first transistor is coupled to the first node.
  • the control electrode and the first electrode of the second transistor are coupled to the second input, and the second electrode of the second transistor is coupled to the first node.
  • the control electrode of the third transistor is coupled to the first node, the first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the second node.
  • the reset circuit includes a fourth transistor and a fifth transistor.
  • the control electrode of the fourth transistor is coupled to the reset signal terminal, the first electrode of the fourth transistor is coupled to the second voltage terminal, and the second electrode of the fourth transistor is coupled to the first node.
  • the control electrode of the fifth transistor is coupled to the reset signal terminal, the first electrode of the fifth transistor is coupled to the second voltage terminal, and the second electrode of the fifth transistor is coupled to the second node.
  • the noise reduction circuit includes a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor.
  • the control electrode and the first electrode of the sixth transistor are coupled to the first clock signal terminal, and the second electrode of the sixth transistor is coupled to the third node.
  • the control electrode of the seventh transistor is coupled to the first node, the first electrode of the seventh transistor is coupled to the second voltage terminal, and the second electrode of the seventh transistor is coupled to the third node.
  • the control electrode of the eighth transistor is coupled to the third node, the first electrode of the eighth transistor is coupled to the second voltage terminal, and the second electrode of the eighth transistor is coupled to the first node.
  • the control electrode of the ninth transistor is coupled to the third node, the first electrode of the ninth transistor is coupled to the second voltage terminal, and the second electrode of the ninth transistor is coupled to the second node.
  • a ratio of a channel width to length ratio of the sixth transistor to a channel width to length ratio of the seventh transistor is less than 1/4.
  • the output circuit includes a tenth transistor and an eleventh transistor.
  • a control electrode of the tenth transistor is coupled to the second node, and a first electrode of the tenth transistor is coupled to the second clock At the signal end, the second pole of the tenth transistor is coupled to the output terminal.
  • the control electrode of the eleventh transistor is coupled to the first clock signal terminal, the first electrode of the eleventh transistor is coupled to the second voltage terminal, and the second electrode of the eleventh transistor is coupled to the output terminal.
  • all of the transistors are N-type transistors, the first voltage terminal provides a high voltage and the second voltage terminal provides a low voltage.
  • all of the transistors are P-type transistors, the first voltage terminal provides a low voltage and the second voltage terminal provides a high voltage.
  • the first clock signal and the second clock signal have the same clock period and amplitude and opposite phases, and the duty ratios of the first clock signal and the second clock signal are both 1/2.
  • a driving method of driving a shift register unit as described above.
  • controlling the voltage of the first node to be the first voltage according to the first input signal from the first input terminal, controlling the voltage of the second node to be the first voltage, and controlling the shift register unit The output of the output outputs a second voltage.
  • maintaining the voltage of the first node as the first voltage according to the first input signal and the second input signal from the second input terminal maintaining the second node voltage as the first voltage, and controlling the shift register
  • the output of the unit outputs a first voltage.
  • N-1 is equal to half of the clock period of the second clock signal
  • m is a natural number greater than 1 and less than n.
  • a shift register is provided.
  • the shift register includes a plurality of cascaded shift register units as described above.
  • the first input end of the Nth stage shift register unit is coupled to the output end of the shift register unit of the first stage, the second input end is coupled to the output end of the shift register unit of the next stage, and the output end is coupled to the next stage shift.
  • the first input end of the bit register unit, the reset signal end is coupled to the output end of the N+M-1th stage shift register unit.
  • a first input of the first stage shift register unit inputs a scan enable signal.
  • the first time of the shift register unit input The clock signal and the second clock signal have the same clock period and amplitude and opposite phases, and the duty ratios of the first clock signal and the second clock signal are both 1/2.
  • the phase of the first clock signal input by the shift register unit other than the first stage shift register unit is delayed by 1/K period from the phase of the first clock signal input by the shift register unit of the previous stage.
  • K is an even number greater than 4
  • M is a natural number greater than K/2 and less than K.
  • an array substrate comprising a shift register as described above.
  • a display device comprising the array substrate as described above.
  • the area of the array substrate can be reduced without using a capacitor, and the gate voltage of the key transistor due to the boosting of the capacitor can be avoided. Large, transistor characteristics are subject to change.
  • FIG. 1 is a schematic block diagram of a shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 2 is an exemplary circuit diagram of a shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 3 is a timing diagram of signals of the shift register unit shown in Figure 2;
  • FIG. 4 is a schematic flowchart of a driving method of driving a shift register unit as shown in FIG. 1 according to an embodiment of the present disclosure
  • FIG. 5 is an exemplary circuit diagram of a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 6 illustrates a schematic structural view of a display device according to an embodiment of the present disclosure.
  • a transistor is taken as an example of a switching element. Since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction currents between the source and the drain (emitter and collector) of the N-type transistor and the P-type transistor are opposite, In the embodiments of the present disclosure, the controlled intermediate end of the transistor is collectively referred to as a control pole, the signal input terminal is referred to as a first pole, and the signal output terminal is referred to as a second pole.
  • the transistors employed in the embodiments of the present disclosure are primarily switching transistors.
  • any controlled switching device having a strobe signal input can be employed in embodiments of the present disclosure to implement the functionality of the switching element for receiving control signals (eg, for turning the controlled switching device on and off).
  • the controlled intermediate end of the switching device is called the control pole
  • the signal input is called the first pole
  • the signal output is called the second pole.
  • terms such as “first” and “second” are used to distinguish one component (or a portion of the component) from another component (or another portion of the component).
  • Existing GOA circuits generally have a capacitor boosting circuit that uses a capacitor to store a voltage to ensure that the gate voltage held by the transistor is held for more than two clock pulses, thereby achieving scan pulse output.
  • the capacitor design on the array substrate often requires a large space, which is not conducive to the development trend of the narrow frame of the liquid crystal panel.
  • the high voltage Vgh of the scanning signal needs to be higher than 25V.
  • Capacitor boost of existing GOA circuits The circuit can raise the voltage of some key nodes of the GOA internal circuit to twice the high voltage Vgh, that is, above 50V.
  • the transistor operates at such a high voltage, the characteristics are easily changed (for example, a shift of the threshold voltage is generated), so that the stability of the GOA unit during the long-time display of the panel is deteriorated, interfering with the output of the normal scan signal.
  • FIG. 1 shows a schematic block diagram of a shift register unit 100 in accordance with an embodiment of the present disclosure.
  • the shift register unit 100 may include an input circuit 110, a reset circuit 120, a noise reduction circuit 130, and an output circuit 140.
  • the input circuit 110 is coupled to the reset circuit 120, the noise reduction circuit 130, and the output circuit 140, and is configured to control the first according to a first input signal from the first input terminal Input1 and a second input signal from the second input terminal Input2
  • the voltage of the node P controls the voltage of the second node Q according to the first voltage from the first voltage terminal V1 and the voltage of the first node P.
  • the reset circuit 120 is connected to the input circuit 110, the noise reduction circuit 130, and the output circuit 140, and is configured to voltage the first node P according to a reset signal from the reset signal terminal Reset and a second voltage from the second voltage terminal V2. And the voltage of the second node Q is reset.
  • the noise reduction circuit 130 is connected to the input circuit 110, the reset circuit 120, and the output circuit 140, and is configured to hold the first node P and the second node Q according to the first clock signal and the second voltage from the first clock signal terminal Clock1. Reset voltage.
  • the output circuit 140 is connected to the input circuit 110, the reset circuit 120, and the noise reduction circuit 130, and is configured to set a second clock from the second clock signal terminal Clock2 under the control of the voltage of the second node Q and the first clock signal. A signal or a second voltage is supplied to the output G of the output circuit 140.
  • the shift register unit 100 is composed of a switching element that does not include a capacitor for holding a voltage in a conventional shift register unit.
  • FIG. 2 shows an example circuit diagram of a shift register unit 100 in accordance with an embodiment of the present disclosure.
  • the input circuit 110 includes a first transistor T1, a second transistor T2, and a third transistor T3.
  • the control electrode and the first electrode of the first transistor T1 are coupled to the first input terminal Input1, and the second electrode of the first transistor T1 is coupled to the first node P.
  • the control electrode and the first electrode of the second transistor T2 are coupled to the second input terminal Input2, and the second electrode of the second transistor T2 is coupled to the first node P.
  • the control electrode of the third transistor T3 is coupled to the first node P, the first electrode of the third transistor T3 is coupled to the first voltage terminal V1, and the second electrode of the third transistor T3 is coupled to the second node Q.
  • the reset circuit 120 includes a fourth transistor T4 and a fifth transistor T5.
  • the control electrode of the fourth transistor T4 is coupled to the reset signal terminal Reset, the first electrode of the fourth transistor T4 is coupled to the second voltage terminal V2, and the second electrode of the fourth transistor T4 is coupled to the first node P.
  • the control electrode of the fifth transistor T5 is coupled to the reset signal terminal Reset, the first electrode of the fifth transistor T5 is coupled to the second voltage terminal V2, and the second electrode of the fifth transistor T5 is coupled to the second node Q.
  • the noise reduction circuit 130 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.
  • the control electrode and the first electrode of the sixth transistor T6 are coupled to the first clock signal terminal Clock1, and the second electrode of the sixth transistor T6 is coupled to the third node R.
  • the control electrode of the seventh transistor T7 is coupled to the first node P, the first electrode of the seventh transistor T7 is coupled to the second voltage terminal V2, and the second electrode of the seventh transistor T7 is coupled to the third node R.
  • the control electrode of the eighth transistor T8 is coupled to the third node R, the first electrode of the eighth transistor T8 is coupled to the second voltage terminal V2, and the second electrode of the eighth transistor T8 is coupled to the first node P.
  • the control electrode of the ninth transistor T9 is coupled to the third node R, the first electrode of the ninth transistor T9 is coupled to the second voltage terminal V2, and the second electrode of the ninth transistor T9 is coupled to the second node Q.
  • the ratio of the channel width to length ratio of the sixth transistor T6 to the channel width to length ratio of the seventh transistor T7 when the sixth transistor T6 and the seventh transistor T7 are simultaneously turned on, if the second The voltage of the voltage terminal V2 is the second voltage (even in the case where the first clock signal is the first voltage), and the voltage of the third node R is the second voltage.
  • the ratio of the channel width to length ratio of the sixth transistor T6 to the channel width to length ratio of the seventh transistor T7 can be set to be less than 1/4.
  • the output circuit 140 includes a tenth transistor T10 and an eleventh transistor T11.
  • the control electrode of the tenth transistor T10 is coupled to the second node Q
  • the first electrode of the tenth transistor T10 is coupled to the second clock signal terminal Clock2
  • the second electrode of the tenth transistor T10 is coupled to the output terminal G.
  • the control electrode of the eleventh transistor T11 is coupled to the first clock signal terminal Clock1, the first electrode of the eleventh transistor T11 is coupled to the second voltage terminal V2, and the second electrode of the eleventh transistor T11 is coupled to the output terminal. G.
  • the first clock signal from the first clock signal terminal Clock1 and from the first The second clock signal of the two clock signal terminals Clock2 has the same clock period and amplitude and the opposite phase, and the duty ratio of the first clock signal and the second clock signal are both 1/2.
  • FIG. 3 shows a timing chart of respective signals of the shift register unit 100 shown in FIG. 2.
  • the operation of the shift register unit 100 shown in FIG. 2 will be described in detail below with reference to the timing chart shown in FIG. In the following description, assuming that all of the transistors are N-type transistors, the first voltage outputted by the first voltage terminal V1 is the high voltage v1, and the second voltage outputted by the second voltage terminal V2 is the low voltage v2.
  • the first clock signal terminal Clock1 outputs a first clock signal CLK5.
  • the second clock signal terminal Clock2 outputs the second clock signal CLK2.
  • the first clock signal CLK5 and the second clock signal CLK2 have the same clock period and amplitude and opposite phases, and the duty ratios of the first clock signal CLK5 and the second clock signal CLK2 are both 1/2.
  • the voltage v1 of the first voltage terminal V1 is greater than the high voltage Vgh of the clock signals (CLK2 and CLK5).
  • the first input terminal Input1 inputs the high voltage Vgh as the start of the working period of the intra shift register unit 100. Since the first input terminal Input1 inputs the high voltage Vgh, the first transistor T1 is turned on, so that the voltage of the first node P rises to the high voltage Vgh. The high voltage Vgh of the first node P turns on the third transistor T3, thereby causing the voltage of the second node Q to rise to the high voltage v1 of the first voltage terminal V1. At the same time, the high voltage Vgh of the first node P turns on the seventh transistor T7, and the high voltage Vgh of the first clock signal CLK5 turns on the sixth transistor T6.
  • the third node can be made by designing a ratio of a channel width to length ratio of the sixth transistor T6 and the seventh transistor T7 (for example, a ratio of a channel width to length ratio of the sixth transistor T6 and the seventh transistor T7 is less than 1/4)
  • the voltage of R is a low voltage.
  • the low voltage of the third node R turns off the eighth transistor T8 and the ninth transistor T9, so that the voltages of the first node P and the second node Q are not affected by the second voltage terminal V2.
  • the high voltage v1 of the second node Q turns on the tenth transistor T10 (the voltage v1 of the first voltage terminal V1 is set higher than the high voltage Vgh of the first clock signal, thereby ensuring that the tenth transistor T10 is fully turned on) , so that the output terminal G is synchronized with the second clock signal CLK2 Output low voltage v2.
  • the first clock signal CLK5 is the high voltage Vgh, the eleventh transistor T11 is turned on, and the output terminal G is also outputted with the low voltage v2.
  • the first input terminal Input1 and the first voltage terminal V1 are still input with the high voltage Vgh such that the first node P and the second node Q maintain a high voltage. Since the first node P is the high voltage Vgh, the seventh transistor T7 remains in an open state, so that the third node R maintains a low voltage. Therefore, the voltages of the first node P and the second node Q are not affected by the second voltage terminal V2. Since the first clock signal CLK5 is at a low voltage, the eleventh transistor T11 is turned off, so that the output terminal G is not affected by the second voltage terminal V2. The output terminal G outputs a high voltage Vgh in synchronization with the second clock signal CLK2 through the tenth transistor T10, thereby starting pixel scanning.
  • the first input terminal Input1 is still at the high voltage Vgh such that the voltages of the first node P, the second node Q, and the third node R are unchanged.
  • the second input terminal Input2 inputs the high voltage Vgh such that the second transistor T2 is turned on, and the second stage of the second transistor T2 outputs the high voltage Vgh. Therefore, the second input terminal Input2 and the first input terminal Input1 simultaneously maintain the voltage of the first node P as the high voltage Vgh. Since the first clock signal CLK5 is at a low voltage, the eleventh transistor T11 is turned off, so that the output terminal G is not affected by the second voltage terminal V2. The output terminal G outputs a high voltage Vgh in synchronization with the second clock signal CLK2 through the tenth transistor T10, thereby continuing pixel scanning.
  • the first input terminal Input1 becomes a low voltage, but the second input terminal Input2 inputs a high voltage Vgh, and therefore, similarly to the foregoing stages, the voltages of the first node P, the second node Q, and the third node R do not change. Since the first clock signal CLK5 is at a low voltage, the eleventh transistor T11 is turned off, so that the output terminal G is not affected by the second voltage terminal V2. The output terminal G outputs a high voltage Vgh in synchronization with the second clock signal CLK2 through the tenth transistor T10, thereby continuing pixel scanning.
  • the second input terminal Input2 still inputs the high voltage Vgh, so the voltages of the first node P, the second node Q and the third node R are unchanged, so that the tenth transistor T10 continues to be turned on.
  • the third node R still maintains a low voltage, so that the voltages of the first node P and the second node Q are not affected by the second voltage terminal V2.
  • the second clock signal CLK2 is lowered to a low voltage, so that the output terminal G synchronously outputs the low voltage v2.
  • the first clock signal CLK5 becomes the high voltage Vgh, so the eleventh transistor T11 is turned on, which also causes the voltage of the output terminal G to become the low voltage v2 of the second voltage terminal V2. Since the changes of the first clock signal CLK5 and the second clock signal CLK2 are synchronized, it is ensured that the output terminal G is rapidly lowered to the low voltage v2, thereby ending the pixel scanning.
  • the high voltage input to the reset signal terminal Reset turns on the fourth transistor T4 and the fifth transistor T5, so that the voltages of the first node P and the second node Q become the voltage of the second voltage terminal V2 (ie, drop to the low voltage v2) ). Since the first node P is a low voltage, the seventh transistor T7 is turned off. The high voltage Vgh from the first clock signal CLK5 turns on the sixth transistor T6. At this time, the voltage of the third node R is pulled up to a high voltage by the first clock signal CLK5, thereby turning on the eighth transistor T8 and the ninth transistor T9.
  • the eleventh transistor T11 is turned on, thereby connecting the output terminal G to the second voltage terminal V2, and outputting the low voltage v2 from the output terminal G.
  • the shift register unit 100 Before the start of the next frame of the shift register unit 100, during the high voltage period of the first clock signal CLK5, the third node R will become a high voltage, so that the first node P and the second node Q are connected to the second voltage terminal. V2. At the same time, the eleventh transistor T11 is turned on, thereby connecting the output terminal G to the second voltage terminal V2. Therefore, the shift register unit 100 according to the present embodiment can perform a smooth voltage between adjacent two frames, reducing the effect of noise.
  • the reset phase described above may also be some 1/6 of a clock cycle after the sixth phase and before the second clock signal CLK2 does not become a high voltage.
  • the transistors in shift register cell 100 as shown in FIG. 2 may also all be P-type transistors.
  • the first voltage outputted by the first voltage terminal V1 is the low voltage v1
  • the second voltage outputted by the second voltage terminal V2 is the high voltage v2.
  • the first clock signal CLK5 and the second clock signal CLK2 have the same clock period and amplitude and opposite phases, and the duty ratios of the first clock signal CLK5 and the second clock signal CLK2 are both 1/2.
  • the voltage v1 of the first voltage terminal V1 is smaller than the low voltage Vgl of the clock signals (CLK2 and CLK5).
  • the voltages of the various signals at various stages are opposite to the voltages of the various signals shown in Figure 3 at various stages.
  • FIG. 4 is a schematic flowchart of a driving method of driving the shift register unit 100 shown in FIG. 1 according to an embodiment of the present disclosure.
  • step S402 in the first time period, the voltage of the first node is controlled to be a first voltage according to the first input signal from the first input terminal, and the first voltage is supplied to the first voltage terminal to control the second node voltage to be the first
  • the voltage supplies a first voltage to the first clock signal terminal and a second voltage to the second clock signal terminal to control the output of the shift register unit 100 to output the second voltage.
  • step S404 in the second to n time period, the voltage of the first node is maintained as a first voltage according to the first input signal and the second input signal from the second input terminal, and the first voltage is supplied to the first voltage terminal to maintain
  • the second node voltage is a first voltage
  • a second voltage is supplied to the first clock signal terminal
  • a first voltage is supplied to the second clock signal terminal to control the output of the shift register unit 100 to output the first voltage.
  • step S406 in the n+1th to n+m-1 time period, the voltage of the first node is maintained as a first voltage according to the second input signal, and the first voltage is supplied to the first voltage terminal to maintain the second node voltage.
  • a first voltage is supplied to the first clock signal terminal and a second voltage is supplied to the second clock signal terminal to control the output of the shift register unit 100 to output the second voltage.
  • step S408 in the n+m period, a reset signal is provided to the reset signal terminal to make the voltage of the first node and the voltage of the second node be the second voltage, and provide the first voltage to the first clock signal terminal and
  • the second clock signal terminal provides a second voltage to control the shift of the shift register unit 100.
  • the output maintains the output of the second voltage.
  • the noise at the output of shift register unit 100 is reduced by a noise reduction circuit.
  • n-1 is equal to half of the clock period of the second clock signal
  • m is a natural number greater than 1 and less than n.
  • the transistors in shift register cell 100 are all N-type transistors, and the first voltage is a high voltage and the second voltage is a low voltage.
  • the transistors in shift register unit 100 are all P-type transistors, and the first voltage is a low voltage and the second voltage is a high voltage.
  • FIG. 5 is an exemplary circuit diagram of a shift register 500 in accordance with an embodiment of the present disclosure.
  • the shift register 500 may comprise a plurality of cascaded shift register unit R 1, ..., R N, R N + 1, ....
  • N denotes a certain stage of the shift register unit among the plurality of cascaded shift register units in the shift register 500, and does not represent the total number of shift register units included in the shift register 500.
  • the Nth stage shift register unit R N is the shift register unit 100 as shown in any of FIG. 1 or FIG.
  • the first input terminal Input1[N] of the Nth stage shift register unit R N is coupled to the output terminal G[N-1] of the shift register unit of the first stage, and the second input terminal Input2[N] is coupled to the next stage.
  • the output terminal G[N+1] of the shift register unit is coupled to the first input terminal Input1[N+1] of the shift register unit of the next stage, and the reset signal end is coupled to the N+th The output terminal G[N+M-1] of the M-1 stage shift register unit.
  • the first-stage shift register unit R 1 of a first input terminal Input1 [1] input scan start signal
  • a second input terminal Input2 [1] Continued coupled to an output shift register unit
  • the terminal G[2] is coupled to the first input terminal Input1[2] of the shift register unit of the next stage, and the reset signal terminal is coupled to the output terminal G of the M-stage shift register unit. ].
  • the second input terminal Input2 [2] is coupled Connected to the output terminal G[3] of the shift register unit of the next stage
  • the output terminal G[2] is coupled to the first input terminal Input1[3] of the shift register unit of the next stage
  • the reset signal end is coupled to the M+ The output terminal G[M+1] of the 1-stage shift register unit.
  • the first clock signal and the second clock signal input by the shift register unit of each stage have the same clock period and amplitude and opposite phases, and the duty ratios of the first clock signal and the second clock signal are both 1/2.
  • the phase of the first clock signal input by the shift register unit other than the first stage shift register unit is delayed by 1/K period from the phase of the first clock signal input by the shift register unit of the previous stage.
  • K is an even number greater than 4, and is used to mean that one clock period is equally divided into K time periods.
  • M is a natural number greater than K/2 and less than K. In the example shown in FIG. 5, K is 6, and M is 5.
  • FIG. 6 shows a schematic structural view of a display device 600 according to an embodiment of the present disclosure.
  • Display device 600 can include an array substrate 610.
  • Array substrate 610 can include shift register 500 as shown in FIG.
  • the shift register unit and the driving method thereof, the array substrate, and the display device according to the embodiments of the present disclosure can occupy less space of the array substrate without using a capacitor, and realize a narrower bezel design.
  • embodiments of the present disclosure can avoid a phenomenon in which the gate voltage of a key transistor is excessively large due to boosting of a capacitor, and transistor characteristics are liable to change.
  • the display device provided by the embodiment of the present disclosure can be applied to any product having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a wearable device, or a navigator.
  • a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a wearable device, or a navigator.

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Abstract

一种移位寄存器单元(100)，其包括输入电路(110)、复位电路(120)、降噪电路(130)和输出电路(140)。输入电路(100)被配置为根据来自第一输入端(Input1)的第一输入信号和来自第二输入端(Input2)的第二输入信号控制第一节点(P)的电压，根据来自第一电压端(V1)的第一电压和第一节点(P)的电压控制第二节点(Q)的电压。复位电路(120)被配置为根据来自复位信号端(Reset)的复位信号和来自第二电压端(V2)的第二电压，复位第一和第二节点(P和Q)的电压。降噪电路(130)被配置为根据来自第一时钟信号端(Clock1)的第一时钟信号和第二电压来保持第一和第二节点(P和Q)的复位电压。输出电路(140)被配置为根据第二节点(Q)的电压和第一时钟信号，将来自第二时钟信号端(Clock2)的第二时钟信号或第二电压提供给输出电路的输出端(G)。移位寄存器单元(100)由开关元件(T1-T11)组成。

Description

移位寄存器单元及其驱动方法、移位寄存器以及显示装置
相关申请的交叉引用
本申请要求于2017年01月03日递交的中国专利申请第201710001940.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，具体地，涉及移位寄存器单元及其驱动方法、移位寄存器、阵列基板以及显示装置。
背景技术
液晶显示面板由垂直和水平阵列式像素矩阵组成。在显示过程中通过栅极驱动电路输出栅极扫描信号，逐行扫描各像素单元。阵列基板栅极驱动(Gate driver on Array，简称GOA)是一种将移位寄存器集成于阵列基板上的技术。每个GOA单元作为一个移位寄存器单元将扫描信号依次传递给下一个GOA单元，从而逐行开启像素单元中的开关晶体管，以便输入像素单元的数据信号。
发明内容
本文中描述的实施例提供了一种移位寄存器单元及其驱动方法、移位寄存器、阵列基板以及显示装置。该移位寄存器单元占用TFT阵列基板的面积较小，可以实现窄边框设计。
根据本公开的第一个方面，提供了一种移位寄存器单元。该移位寄存器单元包括输入电路、复位电路、降噪电路和输出电路。输入电路被配置为根据来自第一输入端的第一输入信号和来自第二输入端的第二输入信号来控制第一节点的电压，根据来自第一电压端的第一电压和第一节点的电压来控制第二节点的电压。复位电路被配置为根据来自复位信号端的复位 信号和来自第二电压端的第二电压，对第一节点的电压和第二节点的电压复位。降噪电路被配置为根据来自第一时钟信号端的第一时钟信号和第二电压来保持第一节点和第二节点的复位电压。输出电路被配置为在第二节点的电压和第一时钟信号的控制下，将来自第二时钟信号端的第二时钟信号或者第二电压提供给输出电路的输出端。该移位寄存器单元由开关元件组成。
在本公开的实施例中，输入电路包括第一晶体管、第二晶体管和第三晶体管。第一晶体管的控制极和第一极耦接到第一输入端，第一晶体管的第二极耦接到第一节点。第二晶体管的控制极和第一极耦接到第二输入端，第二晶体管的第二极耦接到第一节点。第三晶体管的控制极耦接到第一节点，第三晶体管的第一极耦接到第一电压端，第三晶体管的第二极耦接到第二节点。
在本公开的实施例中，复位电路包括第四晶体管和第五晶体管。第四晶体管的控制极耦接复位信号端，第四晶体管的第一极耦接第二电压端，第四晶体管的第二极耦接第一节点。第五晶体管的控制极耦接复位信号端，第五晶体管的第一极耦接第二电压端，第五晶体管的第二极耦接第二节点。
在本公开的实施例中，降噪电路包括第六晶体管、第七晶体管、第八晶体管和第九晶体管。第六晶体管的控制极和第一极耦接到第一时钟信号端，第六晶体管的第二极耦接到第三节点。第七晶体管的控制极耦接到第一节点，第七晶体管的第一极耦接到第二电压端，第七晶体管的第二极耦接到第三节点。第八晶体管的控制极耦接到第三节点，第八晶体管的第一极耦接到第二电压端，第八晶体管的第二极耦接到第一节点。第九晶体管的控制极耦接到第三节点，第九晶体管的第一极耦接到第二电压端，第九晶体管的第二极耦接到第二节点。
在本公开的实施例中，第六晶体管的沟道宽长比与第七晶体管的沟道宽长比的比例小于1/4。
在本公开的实施例中，输出电路包括第十晶体管和第十一晶体管。第十晶体管的控制极耦接到第二节点，第十晶体管的第一极耦接到第二时钟 信号端，第十晶体管的第二极耦接到输出端。第十一晶体管的控制极耦接到第一时钟信号端，第十一晶体管的第一极耦接到第二电压端，第十一晶体管的第二极耦接到输出端。
在本公开的实施例中，所有晶体管都为N型晶体管，第一电压端提供高电压，第二电压端提供低电压。
在本公开的实施例中，所有晶体管都为P型晶体管，第一电压端提供低电压，第二电压端提供高电压。
在本公开的实施例中，第一时钟信号和第二时钟信号具有相同的时钟周期和振幅以及相反的相位，并且第一时钟信号与第二时钟信号的占空比均为1/2。
根据本公开的第二个方面，提供了一种驱动如上所述的移位寄存器单元的驱动方法。在该驱动方法中，在第一时间段，根据来自第一输入端的第一输入信号来控制第一节点的电压为第一电压，控制第二节点电压为第一电压，并控制移位寄存器单元的输出端输出第二电压。在第二至n时间段，根据第一输入信号和来自第二输入端的第二输入信号来保持第一节点的电压为第一电压，保持第二节点电压为第一电压，并控制移位寄存器单元的输出端输出第一电压。在第n+1至n+m-1时间段，根据第二输入信号来保持第一节点的电压为第一电压，保持第二节点电压为第一电压，并控制移位寄存器单元的输出端输出第二电压。在第n+m时间段，向复位信号端提供复位信号以使第一节点的电压和第二节点的电压为第二电压，控制移位寄存器单元的输出端保持输出第二电压。n-1等于第二时钟信号的时钟周期的一半，m为大于1且小于n的自然数。
根据本公开的第三个方面，提供了一种移位寄存器。该移位寄存器包括多个级联的如上所述的移位寄存器单元。第N级移位寄存器单元的第一输入端耦接上一级移位寄存器单元的输出端，第二输入端耦接下一级移位寄存器单元的输出端，输出端耦接下一级移位寄存器单元的第一输入端，复位信号端耦接第N+M-1级移位寄存器单元的输出端。第一级移位寄存器单元的第一输入端输入扫描启动信号。各级移位寄存器单元输入的第一时 钟信号和第二时钟信号具有相同的时钟周期和振幅以及相反的相位，并且第一时钟信号与第二时钟信号的占空比均为1/2。除了第一级移位寄存器单元之外的其它各级移位寄存器单元输入的第一时钟信号的相位比上一级移位寄存器单元输入的第一时钟信号的相位滞后1/K周期。K为大于4的偶数，M为大于K/2且小于K的自然数。
根据本公开的第四个方面，提供了一种阵列基板，其包括如上所述的移位寄存器。
根据本公开的第五个方面，提供了一种显示装置，其包括如上所述的阵列基板。
根据本公开的实施例的移位寄存器单元、移位寄存器、阵列基板以及显示装置，无需使用电容器，可以减少阵列基板的面积，还能够避免由于电容器升压而导致的关键晶体管的栅极电压过大，晶体管的特性容易变化的现象。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制，其中：
图1是根据本公开的实施例的移位寄存器单元的示意性框图；
图2是根据本公开的实施例的移位寄存器单元的示例性电路图；
图3是如图2所示的移位寄存器单元的各信号的时序图；
图4是根据本公开的实施例的驱动如图1所示的移位寄存器单元的驱动方法的示意性流程图；
图5是根据本公开的实施例的移位寄存器的示例性电路图；
图6示出根据本公开的实施例的显示装置的结构示意图。
具体实施方式
为了使本公开的实施例的目的、技术方案和优点更加清楚，下面将结 合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本公开保护的范围。
除非另外定义，否则在此使用的所有术语(包括技术和科学术语)具有与本公开主题所属的领域的技术人员所通常理解的相同含义。进一步将理解的是，诸如在通常使用的词典中定义的那些的术语应解释为具有与说明书上下文和相关技术中它们的含义一致的含义，并且将不以理想化或过于正式的形式来解释，除非在此另外明确定义。如在此所使用的，将两个或更多部分“连接”或“耦接”到一起的陈述应指该部分直接结合到一起或通过一个或多个中间部件结合。
在本公开的所有实施例中，以晶体管作为开关元件的示例。由于晶体管的源极和漏极(发射极和集电极)是对称的，并且N型晶体管和P型晶体管的源极和漏极(发射极和集电极)之间的导通电流方向相反，因此在本公开的实施例中，统一将晶体管的受控中间端称为控制极，信号输入端称为第一极，信号输出端称为第二极。本公开的实施例中所采用的晶体管主要是开关晶体管。应了解，在本公开的实施例中可以采用具有选通信号输入的任何受控开关器件来实现开关元件的功能，将用于接收控制信号(例如用于开启和关断受控开关器件)的开关器件的受控中间端称为控制极，信号输入端称为第一极，信号输出端称为第二极。另外，诸如“第一”和“第二”的术语仅用于将一个部件(或部件的一部分)与另一个部件(或部件的另一部分)区分开。
现有的GOA电路一般都存在电容升压电路，其利用电容器存储电压来保证从晶体管输出的栅极电压保持时间在2个时钟脉冲以上，从而实现扫描脉冲输出。但是，在阵列基板上实现电容器设计往往需要占用较大的空间，不利于液晶面板的窄边框发展趋势。
此外，为了充分打开像素单元的晶体管，保证像素电极的充电率，扫描信号的高电压Vgh需要达到25V电压以上。现有GOA电路的电容升压 电路可使GOA内部电路的一些关键节点的电压升高至高电压Vgh的两倍，即达到50V以上。晶体管在这么高的电压下工作，特性容易变化(例如，产生阈值电压的漂移)，从而使GOA单元在面板的长时显示过程中稳定性变差，干扰正常扫描信号的输出。
图1示出根据本公开的实施例的移位寄存器单元100的示意性框图。如图1所示，移位寄存器单元100可包括输入电路110、复位电路120、降噪电路130和输出电路140。
输入电路110连接到复位电路120、降噪电路130和输出电路140，并被配置为根据来自第一输入端Input1的第一输入信号和来自第二输入端Input2的第二输入信号来控制第一节点P的电压，根据来自第一电压端V1的第一电压和第一节点P的电压来控制第二节点Q的电压。
复位电路120连接到输入电路110、降噪电路130和输出电路140，并被配置为根据来自复位信号端Reset的复位信号和来自第二电压端V2的第二电压，对第一节点P的电压和第二节点Q的电压复位。
降噪电路130连接到输入电路110、复位电路120和输出电路140，并被配置为根据来自第一时钟信号端Clock1的第一时钟信号和第二电压来保持第一节点P和第二节点Q的复位电压。
输出电路140连接到输入电路110、复位电路120和降噪电路130，并被配置为在第二节点Q的电压和第一时钟信号的控制下，将来自第二时钟信号端Clock2的第二时钟信号或者第二电压提供给输出电路140的输出端G。
在本公开的实施例中，移位寄存器单元100由开关元件组成，其不包括在常规移位寄存器单元中用于保持电压的电容器。
图2示出根据本公开的实施例的移位寄存器单元100的示例电路图。如图2所示，输入电路110包括第一晶体管T1、第二晶体管T2和第三晶体管T3。第一晶体管T1的控制极和第一极耦接到第一输入端Input1，第一晶体管T1的第二极耦接到第一节点P。第二晶体管T2的控制极和第一极耦接到第二输入端Input2，第二晶体管T2的第二极耦接到第一节点P。 第三晶体管T3的控制极耦接到第一节点P，第三晶体管T3的第一极耦接到第一电压端V1，第三晶体管T3的第二极耦接到第二节点Q。
复位电路120包括第四晶体管T4和第五晶体管T5。第四晶体管T4的控制极耦接复位信号端Reset，第四晶体管T4的第一极耦接第二电压端V2，第四晶体管T4的第二极耦接第一节点P。第五晶体管T5的控制极耦接复位信号端Reset，第五晶体管T5的第一极耦接第二电压端V2，第五晶体管T5的第二极耦接第二节点Q。
降噪电路130包括第六晶体管T6、第七晶体管T7、第八晶体管T8和第九晶体管T9。第六晶体管T6的控制极和第一极耦接到第一时钟信号端Clock1，第六晶体管T6的第二极耦接到第三节点R。第七晶体管T7的控制极耦接到第一节点P，第七晶体管T7的第一极耦接到第二电压端V2，第七晶体管T7的第二极耦接到第三节点R。第八晶体管T8的控制极耦接到第三节点R，第八晶体管T8的第一极耦接到第二电压端V2，第八晶体管T8的第二极耦接到第一节点P。第九晶体管T9的控制极耦接到第三节点R，第九晶体管T9的第一极耦接到第二电压端V2，第九晶体管T9的第二极耦接到第二节点Q。
在一个示例中，通过设置第六晶体管T6的沟道宽长比与第七晶体管T7的沟道宽长比的比例，使得当第六晶体管T6和第七晶体管T7同时导通时，如果第二电压端V2的电压为第二电压(即使在第一时钟信号为第一电压的情况下)，则第三节点R的电压为第二电压。例如，可以将第六晶体管T6的沟道宽长比与第七晶体管T7的沟道宽长比的比例设置为小于1/4。
输出电路140包括第十晶体管T10和第十一晶体管T11。第十晶体管T10的控制极耦接到第二节点Q，第十晶体管T10的第一极耦接到第二时钟信号端Clock2，第十晶体管T10的第二极耦接到输出端G。第十一晶体管T11的控制极耦接到第一时钟信号端Clock1，第十一晶体管T11的第一极耦接到第二电压端V2，第十一晶体管T11的第二极耦接到输出端G。
在本实施例中，来自第一时钟信号端Clock1的第一时钟信号和来自第 二时钟信号端Clock2的第二时钟信号具有相同的时钟周期和振幅以及相反的相位，并且第一时钟信号与第二时钟信号的占空比均为1/2。
图3示出如图2所示的移位寄存器单元100的各信号的时序图。下面结合图3所示的时序图，对如图2所示的移位寄存器单元100的工作过程进行详细描述。在以下的描述中，假定所有晶体管都是N型晶体管，第一电压端V1输出的第一电压为高电压v1，第二电压端V2输出的第二电压为低电压v2。第一时钟信号端Clock1输出第一时钟信号CLK5。第二时钟信号端Clock2输出第二时钟信号CLK2。第一时钟信号CLK5和第二时钟信号CLK2具有相同的时钟周期和振幅以及相反的相位，并且第一时钟信号CLK5与第二时钟信号CLK2的占空比均为1/2。在此，第一电压端V1的电压v1大于时钟信号(CLK2和CLK5)的高电压Vgh。下面以一个时钟周期被平均分为六个阶段为例进行说明。在下文中，“1”表示高电压，“0”表示低电压。
在第一阶段(初始化阶段)，Input1＝1，Input2＝0，CLK5＝1，CLK2＝0，Reset＝0，V1＝1，V2＝0。
第一输入端Input1输入高电压Vgh作为一帧内移位寄存器单元100工作时段的开始。由于第一输入端Input1输入高电压Vgh，第一晶体管T1打开，从而使得第一节点P的电压升高为高电压Vgh。第一节点P的高电压Vgh将第三晶体管T3打开，从而使得第二节点Q的电压升高为第一电压端V1的高电压v1。同时，第一节点P的高电压Vgh使第七晶体管T7打开，并且第一时钟信号CLK5的高电压Vgh使第六晶体管T6打开。可通过设计第六晶体管T6与第七晶体管T7的沟道宽长比的比例(例如，第六晶体管T6与第七晶体管T7的沟道宽长比的比例小于1/4)来使第三节点R的电压为低电压。第三节点R的低电压将第八晶体管T8和第九晶体管T9关闭，从而使得第一节点P和第二节点Q的电压不受第二电压端V2影响。因此，第二节点Q的高电压v1将第十晶体管T10打开(将第一电压端V1的电压v1设定为比第一时钟信号的高电压Vgh更高，从而保证第十晶体管T10充分打开)，从而使得输出端G与第二时钟信号CLK2同步 输出低电压v2。并且由于第一时钟信号CLK5为高电压Vgh，第十一晶体管T11打开，也使得输出端G输出低电压v2。
在第二阶段(像素扫描阶段)，Input1＝1，Input2＝0，CLK5＝0，CLK2＝1，Reset＝0，V1＝1，V2＝0。
与第一阶段类似地，第一输入端Input1和第一电压端V1仍然输入高电压Vgh，使得第一节点P和第二节点Q保持高电压。由于第一节点P为高电压Vgh，第七晶体管T7保持打开状态，从而使得第三节点R保持低电压。因此，第一节点P和第二节点Q的电压不受第二电压端V2影响。由于第一时钟信号CLK5为低电压，第十一晶体管T11关闭，使得输出端G不受第二电压端V2的影响。输出端G通过第十晶体管T10，与第二时钟信号CLK2同步输出高电压Vgh，从而启动像素扫描。
在第三阶段(像素扫描阶段)，Input1＝1，Input2＝1，CLK5＝0，CLK2＝1，Reset＝0，V1＝1，V2＝0。
与前述阶段类似地，第一输入端Input1仍为高电压Vgh，使得第一节点P、第二节点Q和第三节点R的电压不变。此外，第二输入端Input2输入高电压Vgh，使得第二晶体管T2打开，第二晶体管T2的第二级输出高电压Vgh。因此，第二输入端Input2与第一输入端Input1同时保持第一节点P的电压为高电压Vgh。由于第一时钟信号CLK5为低电压，第十一晶体管T11关闭，从而使得输出端G不受第二电压端V2的影响。输出端G通过第十晶体管T10，与第二时钟信号CLK2同步输出高电压Vgh，从而继续像素扫描。
在第四阶段(像素扫描阶段)，Input1＝0，Input2＝1，CLK5＝0，CLK2＝1，Reset＝0，V1＝1，V2＝0。
第一输入端Input1变为低电压，但第二输入端Input2输入高电压Vgh，因此，与前述阶段类似地，第一节点P、第二节点Q和第三节点R的电压不变。由于第一时钟信号CLK5为低电压，第十一晶体管T11关闭，使得输出端G不受第二电压端V2的影响。输出端G通过第十晶体管T10，与第二时钟信号CLK2同步输出高电压Vgh，从而继续像素扫描。
在第五阶段(扫描结束阶段)，Input1＝0，Input2＝1，CLK5＝1，CLK2＝0，Reset＝0，V1＝1，V2＝0。
与第四阶段类似地，第二输入端Input2仍然输入高电压Vgh，因此第一节点P、第二节点Q和第三节点R的电压不变，从而使得第十晶体管T10继续打开。此时，第三节点R仍然保持低电压，使第一节点P和第二节点Q的电压不受第二电压端V2的影响。在此阶段，第二时钟信号CLK2降为低电压，从而使得输出端G同步输出低电压v2。同时，第一时钟信号CLK5变为高电压Vgh，因此第十一晶体管T11打开，也使得输出端G的电压变为第二电压端V2的低电压v2。由于第一时钟信号CLK5和第二时钟信号CLK2的变化同步进行，保证了输出端G迅速降为低电压v2，从而结束像素扫描。
在第六阶段，(复位阶段)，Input1＝0，Input2＝0，CLK5＝1，CLK2＝0，Reset＝1，V1＝1，V2＝0。
复位信号端Reset输入的高电压将第四晶体管T4和第五晶体管T5打开，从而使得第一节点P和第二节点Q的电压变为第二电压端V2的电压(即，降为低电压v2)。因为第一节点P为低电压，所以第七晶体管T7关闭。来自第一时钟信号CLK5的高电压Vgh将第六晶体管T6打开。此时，第三节点R的电压由第一时钟信号CLK5拉高为高电压，从而打开第八晶体管T8和第九晶体管T9。这同样使得第一节点P和第二节点Q连通第二电压端V2(也就是说，第一节点P和第二节点Q的电压变为第二电压端V2的低电压v2)，从而降低移位寄存器单元100的输出端G的噪声。此外，第十一晶体管T11打开，从而将输出端G连通第二电压端V2，并从输出端G输出低电压v2。
在移位寄存器单元100的下一帧开始之前，第一时钟信号CLK5每次高电压期间，第三节点R都将变为高电压，使第一节点P和第二节点Q连通第二电压端V2。同时第十一晶体管T11打开，从而将输出端G连通第二电压端V2。因此根据本实施例的移位寄存器单元100能够在相邻的两帧之间起到平稳电压，减小噪声的作用。
由图3可见，在一个替代示例中，上述复位阶段也可以是在第六阶段之后且第二时钟信号CLK2未变为高电压之前的某个1/6时钟周期。
此外，本领域的技术人员应当知道，在本实施例的一个替代实施例中，如图2所示的移位寄存器单元100中的晶体管也可以都是P型晶体管。在这种情况下，第一电压端V1输出的第一电压为低电压v1，第二电压端V2输出的第二电压为高电压v2。第一时钟信号CLK5和第二时钟信号CLK2具有相同的时钟周期和振幅以及相反的相位，并且第一时钟信号CLK5与第二时钟信号CLK2的占空比均为1/2。第一电压端V1的电压v1小于时钟信号(CLK2和CLK5)的低电压Vgl。在本替代实施例中，各信号在各个阶段的电压(未示出)与图3中示出的各信号在各个阶段的电压相反。
图4是根据本公开的实施例的驱动如图1所示的移位寄存器单元100的驱动方法的示意性流程图。
在步骤S402，在第一时间段，根据来自第一输入端的第一输入信号来控制第一节点的电压为第一电压，向第一电压端提供第一电压以控制第二节点电压为第一电压，向第一时钟信号端提供第一电压并且向第二时钟信号端提供第二电压以控制移位寄存器单元100的输出端输出第二电压。
在步骤S404，在第二至n时间段，根据第一输入信号和来自第二输入端的第二输入信号来保持第一节点的电压为第一电压，向第一电压端提供第一电压以保持第二节点电压为第一电压，向第一时钟信号端提供第二电压并且向第二时钟信号端提供第一电压以控制移位寄存器单元100的输出端输出第一电压。
在步骤S406，在第n+1至n+m-1时间段，根据第二输入信号来保持第一节点的电压为第一电压，向第一电压端提供第一电压以保持第二节点电压为第一电压，向第一时钟信号端提供第一电压并且向第二时钟信号端提供第二电压以控制移位寄存器单元100的输出端输出第二电压。
在步骤S408，在第n+m时间段，向复位信号端提供复位信号以使第一节点的电压和第二节点的电压为第二电压，向第一时钟信号端提供第一电压并且向第二时钟信号端提供第二电压以控制移位寄存器单元100的输 出端保持输出第二电压。在一个示例中，通过降噪电路降低移位寄存器单元100的输出端的噪声。
在本实施例中，n-1等于第二时钟信号的时钟周期的一半，m为大于1且小于n的自然数。
在本实施例的一个示例中，移位寄存器单元100中的晶体管都为N型晶体管，并且第一电压为高电压，第二电压为低电压。
在本实施例的另一个示例中，移位寄存器单元100中的晶体管都为P型晶体管，并且第一电压为低电压，第二电压为高电压。
图5是根据本公开的实施例的移位寄存器500的示例性电路图。如图5所示，移位寄存器500可包括多个级联的移位寄存器单元R1、…、RN、RN+1、…。在此，N表示移位寄存器500中的多个级联的移位寄存器单元中的某一级移位寄存器单元，并不表示移位寄存器500所包括的移位寄存器单元的总数。
在该实施例中，第N级移位寄存器单元RN是如图1或图2任一所示的移位寄存器单元100。第N级移位寄存器单元RN的第一输入端Input1[N]耦接上一级移位寄存器单元的输出端G[N-1]，第二输入端Input2[N]耦接下一级移位寄存器单元的输出端G[N+1]，输出端G[N]耦接下一级移位寄存器单元的第一输入端Input1[N+1]，复位信号端Reset耦接第N+M-1级移位寄存器单元的输出端G[N+M-1]。
例如，当N＝1时，第一级移位寄存器单元R1的第一输入端Input1[1]输入扫描启动信号，第二输入端Input2[1]耦接下一级移位寄存器单元的输出端G[2]，输出端G[1]耦接下一级移位寄存器单元的第一输入端Input1[2]，复位信号端Reset耦接第M级移位寄存器单元的输出端G[M]。
当N＝2时，第二级移位寄存器单元R2的第一输入端Input1[2]耦接上一级移位寄存器单元的输出端G[1]，第二输入端Input2[2]耦接下一级移位寄存器单元的输出端G[3]，输出端G[2]耦接下一级移位寄存器单元的第一输入端Input1[3]，复位信号端Reset耦接第M+1级移位寄存器单元的输出端G[M+1]。
各级移位寄存器单元输入的第一时钟信号和第二时钟信号具有相同的时钟周期和振幅以及相反的相位，并且第一时钟信号与第二时钟信号的占空比均为1/2。除了第一级移位寄存器单元之外的其它各级移位寄存器单元输入的第一时钟信号的相位比上一级移位寄存器单元输入的第一时钟信号的相位滞后1/K周期。在本实施例中，K为大于4的偶数，用于表示将一个时钟周期均分为K个时间段。M为大于K/2且小于K的自然数。在图5所示的示例中，K为6，M为5。
图6示出根据本公开的实施例的显示装置600的结构示意图。显示装置600可包括阵列基板610。阵列基板610可包括如图5所示的移位寄存器500。
从以上描述可以看出，根据本公开实施例的移位寄存器单元及其驱动方法、阵列基板以及显示装置，无需使用电容器，可以占用较少的阵列基板的空间，实现更窄边框设计。另外，本公开的实施例可以避免由于电容器升压而导致的关键晶体管的栅极电压过大，晶体管特性容易发生变化的现象。
本公开实施例提供的显示装置可以应用于任何具有显示功能的产品，例如，电子纸、移动电话、平板电脑、电视机、笔记本电脑、数码相框、可穿戴设备或导航仪等。
除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地，术语“包括”和“或”应当解释为包括在内的，除非本文中明确禁止这样的解释。在本文中使用术语“示例”之处，特别是当其位于一组术语之后时，所述“示例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其它方面组合实施。还应当理解，本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本 申请的范围。
以上对本公开的若干实施例进行了详细描述，但显然，本领域技术人员可以在不脱离本公开的精神和范围的情况下对本公开的实施例进行各种修改和变型。本公开的保护范围由所附的权利要求限定。

Claims (13)

  1. 一种移位寄存器单元，包括输入电路、复位电路、降噪电路和输出电路，
    其中，所述输入电路被配置为根据来自第一输入端的第一输入信号和来自第二输入端的第二输入信号来控制第一节点的电压，根据来自第一电压端的第一电压和所述第一节点的电压来控制第二节点的电压；
    所述复位电路被配置为根据来自复位信号端的复位信号和来自第二电压端的第二电压，对所述第一节点的电压和所述第二节点的电压复位；
    所述降噪电路被配置为根据来自第一时钟信号端的第一时钟信号和所述第二电压来保持所述第一节点和所述第二节点的复位电压；
    所述输出电路被配置为在所述第二节点的电压和所述第一时钟信号的控制下，将来自第二时钟信号端的第二时钟信号或者所述第二电压提供给所述输出电路的输出端；
    其中，所述移位寄存器单元由开关元件组成。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述输入电路包括：第一晶体管、第二晶体管和第三晶体管，
    其中，所述第一晶体管的控制极和第一极耦接到所述第一输入端，所述第一晶体管的第二极耦接到所述第一节点；
    所述第二晶体管的控制极和第一极耦接到所述第二输入端，所述第二晶体管的第二极耦接到所述第一节点；
    所述第三晶体管的控制极耦接到所述第一节点，所述第三晶体管的第一极耦接到所述第一电压端，所述第三晶体管的第二极耦接到所述第二节点。
  3. 根据权利要求1所述的移位寄存器单元，其中，所述复位电路包括：第四晶体管和第五晶体管，
    其中，所述第四晶体管的控制极耦接所述复位信号端，所述第四晶体管的第一极耦接所述第二电压端，所述第四晶体管的第二极耦接所述第一节点；
    所述第五晶体管的控制极耦接所述复位信号端，所述第五晶体管的第一极耦接所述第二电压端，所述第五晶体管的第二极耦接所述第二节点。
  4. 根据权利要求1所述的移位寄存器单元，其中，所述降噪电路包括：第六晶体管、第七晶体管、第八晶体管和第九晶体管，
    其中，所述第六晶体管的控制极和第一极耦接到所述第一时钟信号端，所述第六晶体管的第二极耦接到第三节点；
    所述第七晶体管的控制极耦接到所述第一节点，所述第七晶体管的第一极耦接到所述第二电压端，所述第七晶体管的第二极耦接到所述第三节点；
    所述第八晶体管的控制极耦接到所述第三节点，所述第八晶体管的第一极耦接到所述第二电压端，所述第八晶体管的第二极耦接到所述第一节点；
    所述第九晶体管的控制极耦接到所述第三节点，所述第九晶体管的第一极耦接到所述第二电压端，所述第九晶体管的第二极耦接到所述第二节点。
  5. 根据权利要求4所述的移位寄存器单元，其中，所述第六晶体管的沟道宽长比与所述第七晶体管的沟道宽长比的比例小于1/4。
  6. 根据权利要求1所述的移位寄存器单元，其中，所述输出电路包括：第十晶体管和第十一晶体管，
    其中，所述第十晶体管的控制极耦接到所述第二节点，所述第十晶体管的第一极耦接到所述第二时钟信号端，所述第十晶体管的第二极耦接到所述输出端；
    所述第十一晶体管的控制极耦接到所述第一时钟信号端，所述第十一晶体管的第一极耦接到所述第二电压端，所述第十一晶体管的第二极耦接到所述输出端。
  7. 根据权利要求1至6中任一项所述的移位寄存器单元，其中，所有晶体管都为N型晶体管，所述第一电压端提供高电压，所述第二电压端提供低电压。
  8. 根据权利要求1至6中任一项所述的移位寄存器单元，其中，所有晶体管都为P型晶体管，所述第一电压端提供低电压，所述第二电压端提供高电压。
  9. 根据权利要求1至6中任一项所述的移位寄存器单元，其中，所述第一时钟信号和所述第二时钟信号具有相同的时钟周期和振幅以及相反的相位，并且所述第一时钟信号与所述第二时钟信号的占空比均为1/2。
  10. 一种驱动如权利要求1-9任一项所述的移位寄存器单元的驱动方法，包括：
    在第一时间段，根据来自第一输入端的第一输入信号来控制第一节点的电压为第一电压，控制第二节点电压为第一电压，并控制所述移位寄存器单元的输出端输出第二电压；
    在第二至n时间段，根据所述第一输入信号和来自第二输入端的第二输入信号来保持所述第一节点的电压为第一电压，保持第二节点电压为第一电压，并控制所述移位寄存器单元的输出端输出第一电压；
    在第n+1至n+m-1时间段，根据所述第二输入信号来保持所述第一节点的电压为第一电压，保持所述第二节点电压为第一电压，并控制所述移位寄存器单元的输出端输出第二电压；以及
    在第n+m时间段，向复位信号端提供复位信号以使所述第一节点的电压和所述第二节点的电压为第二电压，控制所述移位寄存器单元的输出端保持输出第二电压；
    其中，n-1等于所述第二时钟信号的时钟周期的一半，m为大于1且小于n的自然数。
  11. 一种移位寄存器，包括多个级联的如权利要求1至9中任一项所述的移位寄存器单元，
    其中，第N级移位寄存器单元的第一输入端耦接上一级移位寄存器单元的输出端，第二输入端耦接下一级移位寄存器单元的输出端，输出端耦接下一级移位寄存器单元的第一输入端，复位信号端耦接第N+M-1级移位寄存器单元的输出端，
    其中，第一级移位寄存器单元的第一输入端输入扫描启动信号；
    各级移位寄存器单元输入的第一时钟信号和第二时钟信号具有相同的时钟周期和振幅以及相反的相位，并且所述第一时钟信号与所述第二时钟信号的占空比均为1/2；
    除了第一级移位寄存器单元之外的其它各级移位寄存器单元输入的第一时钟信号的相位比上一级移位寄存器单元输入的第一时钟信号的相位滞后1/K周期；
    其中，K为大于4的偶数，M为大于K/2且小于K的自然数。
  12. 一种阵列基板，包括如权利要求11所述的移位寄存器。
  13. 一种显示装置，包括如权利要求12所述的阵列基板。
PCT/CN2017/097386 2017-01-03 2017-08-14 移位寄存器单元及其驱动方法、移位寄存器以及显示装置 Ceased WO2018126691A1 (zh)

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