WO2018120812A1 - 一种用于阻挡层平坦化的化学机械抛光液 - Google Patents

一种用于阻挡层平坦化的化学机械抛光液 Download PDF

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WO2018120812A1
WO2018120812A1 PCT/CN2017/094329 CN2017094329W WO2018120812A1 WO 2018120812 A1 WO2018120812 A1 WO 2018120812A1 CN 2017094329 W CN2017094329 W CN 2017094329W WO 2018120812 A1 WO2018120812 A1 WO 2018120812A1
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polishing liquid
chemical mechanical
mechanical polishing
liquid according
acid
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PCT/CN2017/094329
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English (en)
French (fr)
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蔡鑫元
姚颖
荆建芬
潘依君
杜玲曦
宋凯
张建
杨俊雅
王雨春
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安集微电子科技(上海)股份有限公司
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    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09GPOLISHING COMPOSITIONS; SKI WAXES
    • C09G1/00Polishing compositions
    • C09G1/02Polishing compositions containing abrasives or grinding agents
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F3/00Brightening metals by chemical means
    • C23F3/04Heavy metals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625With simultaneous mechanical treatment, e.g. mechanico-chemical polishing

Definitions

  • the invention relates to the field of chemical mechanical polishing liquids, in particular to a chemical mechanical polishing liquid which can be used for planarization of a barrier layer.
  • CMP chemical mechanical polishing
  • the CMP process is a method of polishing an integrated circuit surface using a mixture containing abrasive particles and a polishing pad.
  • the substrate is placed in direct contact with a rotating polishing pad and a load is applied to the backside of the substrate with a load.
  • abrasive particles and a chemically active solution (often called a polishing solution or polishing slurry) to the gasket.
  • the polished film undergoes a chemical reaction and begins the polishing process.
  • the feature size is reduced, resulting in parasitic capacitances that increasingly affect the performance of the circuit.
  • low dielectric materials are needed to reduce the parasitic capacitance between adjacent metal lines.
  • the commonly used low dielectric material is BD (Black Diamond).
  • the CMP process must have lower butterfly depression and uniform polishing ability. Guarantee more reliable electrical performance.
  • the removal of the metal of the barrier layer needs to be completed quickly in a shorter time and at a lower pressure; in addition, the removal of the barrier layer requires the capping of the oxide and is good.
  • the polishing liquid is required to have strong controllability, high stability and easy cleaning for the removal rate selection ratio. .
  • CN1400266A discloses an alkaline chemical mechanical polishing liquid comprising a silica abrasive, a complexing agent, an amine compound chelating agent and a nonionic surfactant, which cannot be avoided for copper during barrier polishing.
  • patent CN101372089A discloses a chemical mechanical polishing slurry comprising silica abrasive particles, a corrosion inhibitor, an oxidizing agent, a nonionic fluorosurfactant, an aromatic sulfonic acid oxidizing agent surface compound, which overcomes Corrosion of copper metal layer, but low polishing rate and low polishing efficiency
  • patent CN1688665A discloses a chemical mechanical polishing slurry comprising an abrasive, an amphiphilic nonionic surfactant, an organic acid, a corrosion inhibitor, and the like The addition of the affinity nonionic surfactant increases the selection ratio of copper to silica removal rate, but reduces the polishing rate of silica and the barrier removal rate is not high.
  • a barrier polishing liquid suitable for a low dielectric material-copper interconnect process which has a high barrier removal rate and a process stop characteristic of a low dielectric material interface under mild conditions, and can be very
  • a good control solution for butterfly depressions, metal corrosion and surface contamination indicators is an urgent problem to be solved in the art.
  • the present invention is directed to a barrier polishing fluid suitable for use in a low dielectric material-copper interconnect process, having a high barrier removal rate and a process stop characteristic of a low dielectric material interface under milder conditions, and It can effectively control butterfly depression, metal corrosion and surface contaminants.
  • the present invention provides a chemical mechanical polishing liquid for barrier layer planarization, the polishing liquid comprising abrasive particles, an azole compound, a complexing agent, a siloxane-based surfactant, and an oxidizing agent.
  • the abrasive particles are silica particles; the mass percentage of the abrasive particles is preferably from 2 to 20%, more preferably from 5 to 15%; and the particle size of the abrasive particles is preferably from 10 to 250 nm. The best is 50 to 200 nm.
  • the azole compound is preferably selected from one or more of the group consisting of benzotriazole, methylbenzotriazole, 5-phenyltetrazolium, 5-amino-tetrazole, fluorenyl Phenyltetrazole, benzimidazole, naphthotriazole and/or 2-mercapto-benzothiazole.
  • the mass percentage concentration of the azole compound is preferably 0.001 to 1%, more preferably 0.01 to 0.5%.
  • the complexing agent is an organic carboxylic acid, an organic phosphonic acid, an amino acid and/or an organic amine, preferably one or more selected from the group consisting of acetic acid, propionic acid, oxalic acid, malonic acid, succinic acid, and lemon. Acid, ethylenediaminetetraacetic acid, 2-phosphonic acid butane-1,2,4-tricarboxylic acid, aminotrimethylidenephosphonic acid, hydroxyethylidene diphosphonic acid, ethylenediaminetetramethylenephosphonic acid, glycine and
  • the concentration of the complexing agent is preferably 0.001 to 2% by weight, more preferably 0.01 to 1% by weight.
  • the mass percentage concentration of the silicone surfactant is preferably 0.001 to 1.0%, more preferably 0.01 to 0.5%.
  • the oxidizing agent is selected from one or more of the group consisting of hydrogen peroxide, peracetic acid, potassium persulfate and/or ammonium persulfate.
  • it is hydrogen peroxide
  • the mass percentage of the oxidizing agent is preferably from 0.01 to 5%, more preferably from 0.1 to 2%.
  • the chemical mechanical polishing liquid described therein has a pH of 8.0 to 12.0, more preferably 9.0 to 11.0.
  • the chemical mechanical polishing liquid of the present invention may further contain other additives in the field such as a pH adjuster and a bactericide.
  • the chemical mechanical polishing liquid of the present invention can be prepared by concentration, diluted with deionized water and added with an oxidizing agent to the concentration range of the present invention.
  • the present invention provides a barrier polishing liquid suitable for a low dielectric material-copper interconnect process by adding a specific structure of a siloxane-based surfactant, which can achieve high barrier in milder conditions. Layer removal rate and process stop characteristics at low dielectric material interface, and can effectively control butterfly depression, metal corrosion and surface contaminants.
  • 1 is an SEM image of the surface topography of a Sematech 754 graphic chip after polishing with a comparative polishing liquid 1;
  • Figure 4 is an SEM image of the surface topography of the Sematech 754 graphics chip after 30 minutes of immersion with the polishing solution 1.
  • Table 1 shows the comparative polishing liquids 1-2 and the polishing liquids 1 to 13 of the present invention, according to the formulation given in the table, the components other than the oxidizing agent are uniformly mixed, and adjusted with KOH or HNO 3 to the required pH value. Add oxidizing agent before use and mix well. Water is the balance.
  • polishing machine is 12" Reflexion LK machine
  • polishing pad is Fujibo pad
  • lower pressure is 1.5 psi
  • polishing liquid flow rate is 300ml/min
  • polishing time is 1min .
  • the polishing liquid of the present invention can obtain a higher removal rate of the barrier layer Ta and silicon dioxide (TEOS) than the comparative polishing liquids 1 and 2, which can shorten the polishing time, increase the productivity, and simultaneously add Different amounts of siloxane surfactants control the removal rate of low dielectric material BD to be lower than TEOS, which is beneficial to control the polishing process of the graphic chip and the remaining thickness of the BD after polishing, and to ensure the surface uniformity of the chip. Moreover, by adding different amounts of siloxane-based surfactants, the removal rate of the dielectric material BD can be adjusted without affecting the removal rate of the barrier layer and silicon dioxide (TEOS), and the technical requirements under different process conditions can be met. .
  • TEOS barrier layer Ta and silicon dioxide
  • the patterned copper wafer was polished using the comparative polishing liquid 2 and the polishing liquids 1 to 3 of the present invention under the following conditions.
  • the graphics chip is a commercially available 12-inch Sematech 754 graphics chip.
  • the film material is copper/germanium/tantalum nitride/TEOS/BD from top to bottom.
  • the polishing process is divided into three steps. The first step is to remove the commercially available copper polishing solution. Most of the copper, the second step uses a commercially available copper polishing solution to remove residual copper, and the third step uses the barrier layer polishing solution of the present invention to block the barrier layer (yttrium/tantalum nitride), silicon dioxide TEOS, and part of the BD. Remove and stop on the BD layer.
  • the polishing machine is a 12" Reflexion LK machine
  • the polishing pad is Fujibo pad
  • the lower pressure is 1.5 psi
  • the polishing liquid flow rate is 300 ml/min. Polishing time is 70s.
  • the dish-shaped depression is a dish-shaped depression on the metal pad before the barrier layer is polished; the dielectric layer is eroded as a barrier layer having a line width of 0.18 ⁇ m and a density of 50% on the dense line region (50% copper/50% dielectric layer). Dielectric layer erosion, Refers to the corrective ability value after polishing.
  • the polishing liquid of the present invention can better correct the dishing and erosion generated on the wafer by the foreground (copper polishing) because the BD removal rate is suppressed. , obtained a better crystal round appearance.
  • the patterned copper wafer was polished using the comparative polishing liquid 1 and the polishing liquid 1 under the following conditions.
  • the graphics chip is a commercially available 12-inch Sematech 754 graphics chip.
  • the film material is copper/germanium/tantalum nitride/TEOS/BD from top to bottom.
  • the polishing process is divided into three steps. The first step is to remove the commercially available copper polishing solution. Most of the copper, the second step uses a commercially available copper polishing solution to remove residual copper, and the third step uses the barrier layer polishing solution of the present invention to block the barrier layer (yttrium/tantalum nitride), silicon dioxide TEOS, and part of the BD. Remove and stop on the BD layer.
  • FIG. 1 and 2 are SEM images of the surface topography of the Sematech 754 graphic chip after polishing the polishing liquid 1 and the polishing liquid 1, respectively.
  • Figure 3 and Figure 4 are SEM images of the surface topography of the Sematech 754 graphics chip after 30 minutes of immersion in Comparative Polishing Solution 1 and Polishing Solution 1, respectively. It can be seen from the comparison that the polishing liquid of the present invention effectively suppresses metal corrosion, especially the copper wire region, and the surface of the Sematech 754 graphic chip is clear and sharp after being polished and immersed by the polishing liquid of the present invention. No metal corrosion was observed and no contaminating particles remained.
  • wt% of the present invention refers to the mass percentage.

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Abstract

一种用于阻挡层平坦化的化学机械抛光液及其应用,该抛光液包含二氧化硅颗粒、唑类化合物、络合剂、硅氧烷类表面活性剂和氧化剂。该化学机械抛光液可以满足阻挡层抛光过程中对各种材料的抛光速率和选择比要求,对半导体器件表面的缺陷具有强的矫正能力,能够快速实现平坦化,提高工作效率,降低生产成本。

Description

一种用于阻挡层平坦化的化学机械抛光液 技术领域
本发明涉及化学机械抛光液领域,尤其涉及一种可用于阻挡层平坦化的化学机械抛光液。
背景技术
在集成电路制造中,互连技术的标准在提高,随着互连层数的增加和工艺特征尺寸的缩小,对硅片表面平整度的要求也越来越高,如果没有平坦化的能力,在半导体晶圆上创建复杂和密集的结构是非常有限的,化学机械抛光方法(CMP)就是可实现整个硅片平坦化的最有效的方法。
CMP工艺就是一种使用含研磨颗粒的混合物和抛光垫抛光集成电路表面。在典型的化学机械抛光方法中,将衬底直接与旋转抛光垫接触,用一载重物在衬底背面施加压力。在抛光期间,旋转垫片和操作台,同时在衬底背面保持向下的力,将研磨颗粒和化学活性溶液(通常称为抛光液或抛光浆料)涂于垫片上,抛光液与正在抛光的薄膜发生化学反应,开始进行抛光过程。
随着集成电路技术向超深亚微米(如:32nm、28nm)的方向发展,特征尺寸的减小,导致了寄生电容愈加严重地影响着电路的性能。为减小这一影响,需要采用低介电材料来降低相邻金属线之间的寄生电容。目前,常用的低介电材料为BD(Black Diamond),在其CMP工艺过程中,除了要严格控制表面污染物指标、杜绝金属腐蚀外,还要具备较低的蝶形凹陷和均一的抛光才能保证更可靠的电性能。尤其在其阻挡层的平坦化过程中,移除阻挡层的金属需要在更短的时间和更低的压力下快速完成;此外,移除阻挡层的同时还需要封盖氧化物并能很好地停止在低介电材料表面,形成互连线,并且对小尺寸图形不敏感。这对CMP提出了更高的要求,因为低介电材料为 掺杂碳的氧化硅,与二氧化硅具有相似的表面性,要控制停止层的残留厚度,就要求抛光液具有对去除速率选择比具备强的调控能力、高的稳定性及易清洗等特征。
现有技术中,CN1400266A公开一种碱性化学机械抛光液,其包含二氧化硅磨料、络合剂、胺类化合物螯合剂和非离子表面活性剂,其用于阻挡层抛光时无法避免对铜金属层的腐蚀现象;专利CN101372089A公开一种化学机械抛光浆料,其包含二氧化硅研磨颗粒、腐蚀抑制剂、氧化剂、非离子氟表面活性剂、芳族磺酸氧化剂表面化合物,其克服了对铜金属层的腐蚀,但是抛光速率低,抛光效率不高;专利CN1688665A公开一种化学机械抛光浆料,其包含研磨剂、两亲性非离子表面活性剂、有机酸、腐蚀抑制剂,该两亲性非离子表面活性剂的加入,提高了铜相对于二氧化硅的去除速率的选择比,但是降低了二氧化硅的抛光速率,且阻挡层去除速率不高
因此,提供一种适于低介电材料-铜互连制程中的阻挡层抛光液,在较温和的条件下具有高的阻挡层去除速率和低介电材料界面的工艺停止特性,并能很好的控制蝶形凹陷,金属腐蚀和表面污染物指标的抛光液是本领域亟待解决的问题。
发明内容
本发明旨在提供一种适于低介电材料-铜互连制程中的阻挡层抛光液,在较温和的条件下具有高的阻挡层去除速率及低介电材料界面的工艺停止特性,并且能有效控制蝶形凹陷,金属腐蚀和表面污染物现象。
具体地,本发明提供了一种用于阻挡层平坦化的化学机械抛光液,该抛光液包含研磨颗粒、唑类化合物、络合剂、硅氧烷类表面活性剂和氧化剂。
其中,所述硅氧烷类表面活性剂的化学式为:
Figure PCTCN2017094329-appb-000001
其中,Me=CH3,0≤m≤50,0≤n≤50; R=NHCH2CHCH2,CH2CH2COOH或(CH2)3O(C2H4O)xH,0≤x≤100。
其中研磨颗粒为二氧化硅颗粒;研磨颗粒的质量百分比浓度较佳的为2~20%,更佳的为5~15%;所述的研磨颗粒的粒径较佳的为10~250nm,更佳的为50~200nm。
其中唑类化合物,较佳的选自下列中的一种或多种:苯并三氮唑、甲基苯并三氮唑、5-苯基四氮唑、5-氨基-四氮唑、巯基苯基四氮唑、苯并咪唑,萘并三唑和/或2-巯基-苯并噻唑。所述的唑类化合物的质量百分比浓度较佳的为0.001~1%,更佳的为0.01~0.5%。
其中络合剂为有机羧酸、有机膦酸、氨基酸和/或有机胺,较佳的选自下列中的一种或多种:乙酸、丙酸、草酸、丙二酸、丁二酸、柠檬酸、乙二胺四乙酸、2-膦酸丁烷-1,2,4-三羧酸、氨基三甲叉膦酸、羟基乙叉二膦酸、,乙二胺四甲叉膦酸,甘氨酸和/或乙二胺,所述的络合剂的质量百分比的浓度较佳的为0.001~2%,更佳的为0.01~1%。
其中聚硅氧烷类表面活性剂的质量百分比浓度较佳的为:0.001~1.0%,更佳的为0.01~0.5%
其中氧化剂选自下列中的一种或多种:过氧化氢、过氧乙酸,过硫酸钾和/或过硫酸铵。较佳为过氧化氢,所述的氧化剂的质量百分比浓度较佳的为0.01~5%,更佳的为0.1~2%。
其中所述的化学机械抛光液的PH值为8.0~12.0,更佳的为9.0~11.0。
本发明的化学机械抛光液还可以包含pH调节剂和杀菌剂等其他本领域添加剂。
本发明的化学机械抛光液可以浓缩制备,使用时用去离子水稀释并添加氧化剂至本发明的浓度范围使用。
与现有技术相比较,本发明的技术优势在于:
本发明通过添加特定结构的硅氧烷类表面活性剂,提供一种适于低介电材料-铜互连制程中的阻挡层抛光液,其可在较温和的条件下实现高的阻挡 层去除速率及低介电材料界面的工艺停止特性,并且能有效控制蝶形凹陷,金属腐蚀和表面污染物等。
附图说明
图1为采用对比抛光液1抛光后Sematech754图形芯片的表面形貌的SEM图;
图2为采用抛光液1抛光后Sematech754图形芯片的表面形貌的SEM图;
图3为采用对比抛光液1浸渍30分钟后Sematech754图形芯片的表面形貌的SEM图;
图4为采用抛光液1浸渍30分钟后Sematech754图形芯片的表面形貌的SEM图。
具体实施方式
下面通过实施例的方式进一步说明本发明,但并不以此将本发明限制在所述的实施例范围之中。
表1给出了对比抛光液1~2和本发明的抛光液1~13,按表中所给的配方,将除氧化剂以外的其他组分混合均匀,用KOH或HNO3调节到所需要的pH值。使用前加氧化剂,混合均匀即可。水为余量。
表1对比抛光液1~2和本发明的抛光液1~13
Figure PCTCN2017094329-appb-000002
Figure PCTCN2017094329-appb-000003
Figure PCTCN2017094329-appb-000004
效果实施例1
采用对比抛光液1~2和本发明的抛光液1~9按照下述条件对铜(Cu)、钽(Ta)、二氧化硅(TEOS)和低介电材料(BD)进行抛光。抛光条件:抛光机台为12”Reflexion LK机台,抛光垫为Fujibo pad,下压力为1.5psi,转速为抛光盘/抛光头=113/107rpm,抛光液流速为300ml/min,抛光时间为1min。
表2对比抛光液1~2和本发明抛光液1~9对铜(Cu)、钽(Ta)、二氧化硅(TEOS)和低介电材料(BD)的去除速率
Figure PCTCN2017094329-appb-000005
由表2可见,与对比抛光液1与2相比,本发明的抛光液可以获得较高的阻挡层Ta和二氧化硅(TEOS)的去除速率,可以缩短抛光时间,提高产能,同时通过添加不同量的硅氧烷类表面活性剂,将低介电材料BD的去除速率控制在比TEOS低,有利于控制图形芯片的抛光过程和抛光后的BD剩余厚度,并保证芯片的表面均一性,而且通过添加不同量的硅氧烷类表面活性剂,可在不影响阻挡层和二氧化硅(TEOS)的去除速率的条件下调节介电材料BD的去除速率,满足不同工艺条件下的技术要求。
效果实施例2
采用对比抛光液2和本发明的抛光液1~3按照下述条件对带有图案的铜晶片进行抛光。该图形芯片为市售的12英寸Sematech754图形芯片,膜层材料从上至下为铜/钽/氮化钽/TEOS/BD,抛光过程分三步,第一步用市售的铜抛光液去除大部分的铜,第二步用市售的铜抛光液去除残留的铜,第三步用本发明的阻挡层抛光液将阻挡层(钽/氮化钽)、二氧化硅TEOS、和部分BD去除并停在BD层上。阻挡层抛光液抛光条件:抛光机台为12”Reflexion LK机台,抛光垫为Fujibo pad,下压力为1.5psi,转速为抛光盘/抛光头=113/107rpm,抛光液流速为300ml/min,抛光时间为70s。
表3对比抛光液2和本发明抛光液1~3对带有图案的铜晶片抛光后的矫正能力对比
Figure PCTCN2017094329-appb-000006
其中,碟形凹陷为阻挡层抛光前在金属垫上的碟形凹陷;介质层侵蚀为阻挡层在线宽为0.18微米,密度为50%的密线区域(50%铜/50%介电层)上的介质层侵蚀,
Figure PCTCN2017094329-appb-000007
是指抛光后的矫正能力值。
由表3可以看出,与对比抛光液2相比,本发明的抛光液由于抑制了BD的去除速率,能较好的修正前程(铜抛光后)在晶圆上产生的碟形凹陷和侵蚀,获得了较好的晶圆形貌。
效果实施例3
采用对比抛光液1和抛光液1按照下述条件对带有图案的铜晶片进行抛光。该图形芯片为市售的12英寸Sematech754图形芯片,膜层材料从上至下为铜/钽/氮化钽/TEOS/BD,抛光过程分三步,第一步用市售的铜抛光液去除大部分的铜,第二步用市售的铜抛光液去除残留的铜,第三步用本发明的阻挡层抛光液将阻挡层(钽/氮化钽)、二氧化硅TEOS、和部分BD去除并停在BD层上。
图1和图2分别采用对比抛光液1和抛光液1抛光后Sematech754图形芯片的表面形貌的SEM图。图3和图4分别采用对比抛光液1和抛光液1浸渍30分钟后Sematech 754图形芯片的表面形貌的SEM图。对比可以看出,本发明的抛光液有效的抑制了金属腐蚀,特别是对铜线区域有很好的保护,Sematech 754图形芯片经过本发明的抛光液抛光后和浸渍后,表面仍然清晰锐利,未发现金属腐蚀现象,且无污染颗粒残留。
应当理解的是,本发明所述wt%均指的是质量百分含量。
以上对本发明的具体实施例进行了详细描述,但其只是作为范例,本发明并不限制于以上描述的具体实施例。对于本领域技术人员而言,任何对本发明进行的等同修改和替代也都在本发明的范畴之中。因此,在不脱离本发明的精神和范围下所作的均等变换和修改,都应涵盖在本发明的范围内。

Claims (20)

  1. 一种用于阻挡层平坦化的化学机械抛光液,其特征在于,所述化学机械抛光液包含二氧化硅颗粒、唑类化合物、络合剂、硅氧烷类表面活性剂和氧化剂;其中,所述硅氧烷类表面活性剂的化学式为:
    Figure PCTCN2017094329-appb-100001
    其中,Me=CH3,0≤m≤50,0≤n≤50;R=NHCH2CHCH2,CH2CH2COOH或(CH2)3O(C2H4O)xH,0≤x≤100。
  2. 如权利要求1所述的化学机械抛光液,其特征在于,所述二氧化硅颗粒的质量百分比浓度为2~20%。
  3. 如权利要求2所述的化学机械抛光液,其特征在于,所述二氧化硅颗粒的质量百分比浓度为5~15%。
  4. 如权利要求1所述的化学机械抛光液,其特征在于,所述二氧化硅颗粒的粒径为10~250nm。
  5. 如权利要求4所述的化学机械抛光液,其特征在于,所述二氧化硅颗粒的粒径为50~200nm。
  6. 如权利要求1所述的化学机械抛光液,其特征在于,所述唑类化合物选自苯并三氮唑、甲基苯并三氮唑、5-苯基四氮唑、5-氨基-四氮唑、巯基苯基四氮唑、苯并咪唑,萘并三唑、2-巯基-苯并噻唑中的一种或多种。
  7. 如权利要求1所述的化学机械抛光液,其特征在于,所述唑类化合物的质量百分比浓度为0.001~1%,
  8. 如权利要求7所述的化学机械抛光液,其特征在于,所述唑类化合物的质量百分比浓度为0.01~0.5%。
  9. 如权利要求1所述的化学机械抛光液,其特征在于,所述络合剂选自有机羧酸、有机膦酸、氨基酸、有机胺中的一种或多种。
  10. 如权利要求9所述的化学机械抛光液,其特征在于,所述络合剂选自乙酸、丙酸、草酸、丙二酸、丁二酸、柠檬酸、乙二胺四乙酸、2-膦酸丁烷-1,2,4-三羧酸、氨基三甲叉膦酸、羟基乙叉二膦酸、乙二胺四甲叉膦 酸、甘氨酸、乙二胺中的一种或多种。
  11. 如权利要求1所述的化学机械抛光液,其特征在于,所述络合剂的质量百分比的浓度为0.001~2%。
  12. 如权利要求11所述的化学机械抛光液,其特征在于,所述络合剂的质量百分比的浓度为0.01~1%。
  13. 如权利要求1所述的化学机械抛光液,其特征在于,所述硅氧烷类表面活性剂的质量百分比浓度为0.001~1.0%。
  14. 如权利要求14所述的化学机械抛光液,其特征在于,所述硅氧烷类表面活性剂的质量百分比浓度为0.01~0.5%
  15. 如权利要求1所述的化学机械抛光液,其特征在于,所述氧化剂选自过氧化氢、过氧乙酸、过硫酸钾、过硫酸铵中的一种或多种。
  16. 如权利要求15所述的化学机械抛光液,其特征在于,所述氧化剂为过氧化氢。
  17. 如权利要求1所述的化学机械抛光液,其特征在于,所述氧化剂的质量百分比浓度为0.01~5%。
  18. 如权利要求17所述的化学机械抛光液,其特征在于,所述氧化剂的质量百分比浓度为0.1~2%。
  19. 如权利要求1所述的化学机械抛光液,其特征在于,所述化学机械抛光液的pH值为8.0~12.0。
  20. 如权利要求19所述的化学机械抛光液,其特征在于,所述化学机械抛光液的pH值为9.0~11.0。
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