WO2018116523A1 - Capteur d'images linéaire de photodétecteur à report et intégration - Google Patents

Capteur d'images linéaire de photodétecteur à report et intégration Download PDF

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Publication number
WO2018116523A1
WO2018116523A1 PCT/JP2017/030152 JP2017030152W WO2018116523A1 WO 2018116523 A1 WO2018116523 A1 WO 2018116523A1 JP 2017030152 W JP2017030152 W JP 2017030152W WO 2018116523 A1 WO2018116523 A1 WO 2018116523A1
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semiconductor substrate
signal
image sensor
tdi
linear image
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PCT/JP2017/030152
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English (en)
Japanese (ja)
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中西　淳治
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三菱電機株式会社
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Priority to JP2018557528A priority Critical patent/JP6732043B2/ja
Publication of WO2018116523A1 publication Critical patent/WO2018116523A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors

Definitions

  • the present invention relates to an improvement of a linear image sensor used in the field of remote sensing or the like, and relates to a TDI type linear image sensor that has a simple structure and operates at a higher speed and lower power consumption than before.
  • Various image sensors have been developed in which a large number of photodetectors are arranged in an array on a semiconductor substrate, and a signal charge readout circuit and an output amplifier are provided on the same semiconductor substrate.
  • a linear image sensor in which a plurality of photodetectors are arranged in a one-dimensional array is mounted on an artificial satellite or the like, and the direction perpendicular to the array is made coincident with the traveling direction of the artificial satellite. Take a picture.
  • the incident light amount is reduced by the reduction in the area of the photodetector and the S / N is deteriorated.
  • TDI Time Delay and Integration
  • FFT full frame transfer
  • CCD Charge Coupled Devices
  • This is a readout method of a CCD image sensor.
  • the TDI operation can be realized by matching the charge transfer in the vertical direction of the CCD with the moving speed of the satellite.
  • M-stage TDI operation is performed in the vertical direction of the CCD, the charge accumulation time is effectively M times, so that the sensitivity is improved M times and the S / N is improved to ⁇ M times.
  • the TDI stage number switching circuit performs vertical transfer in the forward direction up to the Mth stage of the TDI stage in the pixel area, and the vertical transfer direction from the Mth stage onward is reversed in the reverse direction. It is possible to set to.
  • linear image sensors used for remote sensing are required to increase the number of pixels in order to expand the observation width.
  • Conventional satellite optical sensors have been developed to have a pixel pitch of about 10 ⁇ m and a number of pixels of about several thousand pixels. In this case, an extremely long element having an element size of several tens of mm or more in the horizontal direction is developed. It becomes a scale element.
  • a reduction exposure apparatus (stepper) is used for forming a fine pattern, but the transfer area that can be transferred at one time is limited.
  • the upper limit of the transfer area is only about 20 mm square. Therefore, as one of methods for manufacturing a long image sensor having an element size exceeding several tens of mm using a stepper, for example, a method described in Patent Document 2 has been proposed.
  • Patent Document 2 paying attention to the fact that the pixel area of the image sensor and the horizontal CCD are periodically arranged, by transferring these areas in a plurality of times using a stepper, several tens of mm or more are transferred. This makes it possible to manufacture long sensors.
  • Patent Document 3 a method described in Patent Document 3 or Patent Document 4 has been proposed as a method for increasing the speed of signal reading in the horizontal direction and reducing the power consumption.
  • Patent Document 3 photoelectric conversion and vertical charge transfer are performed by a vertical CCD, and signal reading in the horizontal direction is performed by a CMOS circuit formed on the same substrate as the CCD. It is intended to combine advantages.
  • Patent Document 4 a vertical CCD that performs photoelectric conversion and vertical charge transfer and a CMOS circuit that performs horizontal signal readout are formed on separate chips, and both are electrically connected by metal bumps. is there.
  • the conventional TDI image sensor shown in Patent Document 3 has a problem that even if a CCD and a CMOS circuit are formed on the same substrate, the manufacturing processes are different from each other, so that the realization thereof is difficult.
  • the conventional TDI image sensor shown in Patent Document 4 proposed to solve this problem has a complicated structure when mounted on a package, and is difficult to mount with a long element used for remote sensing. There was a problem of being.
  • An object of the present invention is to solve the above problems and provide a TDI linear image sensor that can be mounted on a package more easily than before while operating at high speed and low power consumption.
  • a TDI linear image sensor includes a pixel array, a plurality of transfer elements, at least one first signal processing circuit, at least one first output pad, one first semiconductor substrate, and And at least one second semiconductor substrate.
  • a pixel array a plurality of pixels that perform photoelectric conversion are arranged in a two-dimensional array having a first direction and a second direction.
  • the plurality of transfer elements transfer the charges generated in the plurality of pixels in a first direction by time delay integration, and are adjacent to each other in the second direction.
  • At least one first signal processing circuit sequentially selects and outputs one of a plurality of signals respectively indicating the charges transferred by the plurality of transfer elements.
  • At least one first output pad outputs an output signal of the first signal processing circuit.
  • a pixel array, a plurality of transfer elements, and a first output pad are formed on one first semiconductor substrate.
  • a first signal processing circuit is formed on at least one second semiconductor substrate.
  • At least one second semiconductor substrate is electrically connected to one first semiconductor substrate.
  • TDI linear image sensor that can be mounted on a package more easily than before while operating at high speed and low power consumption.
  • the first semiconductor substrate and the second semiconductor substrate are electrically connected to each other, thereby speeding up the horizontal signal readout and reducing the power consumption. Can do.
  • the input / output pads can be arranged only on the first semiconductor substrate, the structure for mounting on the package is simplified, and the long elements can be easily mounted.
  • 1 is a perspective view showing a schematic structure of a TDI linear image sensor according to Embodiment 1 of the present invention.
  • 1 is a cross-sectional structure diagram of a TDI type linear image sensor according to a first embodiment of the present invention. It is a figure which shows the circuit arrangement
  • FIG. 1 shows the circuit arrangement
  • FIG. 10 is a diagram showing a circuit arrangement of a first semiconductor substrate 1C when a signal is read out by dividing a pixel array into a plurality of pixels in a TDI linear image sensor according to a fourth embodiment of the present invention.
  • FIG. 10 is a diagram showing a circuit arrangement of a first semiconductor substrate 1D when a signal is read out by dividing a pixel array into a plurality of pixels in a TDI linear image sensor according to a fifth embodiment of the present invention. It is a figure which shows the circuit arrangement
  • FIG. 1 is a perspective view showing a schematic structure of a TDI type linear image sensor according to Embodiment 1 of the present invention.
  • the TDI linear image sensor includes a first semiconductor substrate 1 and a second semiconductor substrate 2.
  • a plurality of pixels that perform photoelectric conversion are arranged in a two-dimensional array having a Y direction and an X direction to form a pixel array 3.
  • the + Y direction is also referred to as “first direction” or “vertical direction”
  • the + X direction is also referred to as “second direction” or “horizontal direction”.
  • the first semiconductor substrate 1 further includes other circuits such as a plurality of vertical CCDs that transfer charges generated in a plurality of pixels in the + Y direction and a plurality of column amplifiers that amplify the transferred charges.
  • a plurality of input / output pads 4 are formed on the + Z plane side of the first semiconductor substrate 1.
  • the second semiconductor substrate 2 is another semiconductor substrate on which a signal processing circuit made of a CMOS transistor such as a horizontal selection circuit is mounted.
  • the second semiconductor substrate 2 is bonded on the first semiconductor substrate 1 with the surfaces of the substrates facing each other.
  • FIG. 2 is a cross-sectional structure diagram of the TDI type linear image sensor according to the first embodiment of the present invention.
  • FIG. 2 shows a cross-section at a position corresponding to the A1-A1 ′ line of FIG. 1 when the first semiconductor substrate 1 and the second semiconductor substrate 2 of FIG.
  • the pixel array 3 and the column amplifier 5 are formed on the + Z plane side of the first semiconductor substrate 1, and the signal processing circuit 6 is formed on the ⁇ Z plane side of the second semiconductor substrate 2.
  • the column amplifier 5 is also referred to as a “first signal preprocessing circuit”, and the signal processing circuit 6 is also referred to as a “first signal processing circuit”.
  • the first semiconductor substrate 1 and the second semiconductor substrate 2 are electrically joined to each other by a plurality of metal bumps 7.
  • the metal bumps 7 are also referred to as “electrical connectors”.
  • the ⁇ Z surface of the first semiconductor substrate 1 is bonded onto a package 23 made of ceramic or the like.
  • the input / output pad 4 on the first semiconductor substrate 1 and the metal electrode 24 on the package 23 are electrically connected to each other by a wire bond 25.
  • a plurality of leads 26 are formed on the ⁇ Z surface side of the package 23.
  • FIG. 3 is a diagram showing a circuit arrangement of the first semiconductor substrate 1 of the TDI linear image sensor according to the first embodiment of the present invention.
  • a pixel array 3 on the first semiconductor substrate 1, a pixel array 3, a plurality of vertical CCDs 11, a plurality of column amplifiers 5, a plurality of input / output pads 4, and a plurality of metal bumps 7a, 7b, 7c (FIG. 2 corresponding to the metal bump 7).
  • the vertical CCD 11 is also referred to as a “transfer element”.
  • the position of the second semiconductor substrate 2 bonded onto the first semiconductor substrate 1 is indicated by a dotted frame.
  • FIG. 3 a case where one second semiconductor substrate 2 is bonded to one first semiconductor substrate 1 is shown.
  • a plurality of vertical CCDs 11 having a longitudinal direction in the Y direction and adjacent to each other in the X direction are formed so as to overlap with the pixel array 3.
  • Each vertical CCD 11 is formed along a plurality of pixels arranged in one column in the Y direction among the plurality of pixels of the pixel array 3.
  • a photodiode not shown
  • Each vertical CCD 11 integrates the charge generated in each pixel by time delay integration by the TDI operation, transfers it in the + Y direction, and outputs it from the end on the + Y side.
  • each column amplifier 5 is provided for each vertical CCD 11 and is formed so as to be connected to the + Y side end of each vertical CCD 11.
  • Each column amplifier 5 includes a source follower amplifier and the like, amplifies the charge transferred from the vertical CCD 11 and converts it into a voltage signal.
  • each column amplifier 5 is connected to the metal bump 7a through the metal wiring 8.
  • the output signal of each column amplifier 5 is sent to the signal processing circuit 6 on the second semiconductor substrate 2 through the metal wiring 8 and the metal bump 7a.
  • the output signal of the signal processing circuit 6 on the second semiconductor substrate 2 is returned to the circuit on the first semiconductor substrate 1 through the metal bumps 7c.
  • the metal bump 7 c is connected to one of the input / output pads 4 (used as an output pad) through the metal wiring 9.
  • the output signal of the TDI linear image sensor is output to the outside of the first semiconductor substrate 1 via the input / output pad 4 used as an output pad.
  • the input / output pad 4 that outputs the output signal of the signal processing circuit 6 on the second semiconductor substrate 2 is also referred to as a “first output pad”.
  • an output final stage buffer amplifier or the like may be formed on the first semiconductor substrate 1 before the input / output pad 4 used as an output pad.
  • a bias voltage and a clock signal necessary for driving the signal processing circuit 6 on the second semiconductor substrate 2 are given from the first semiconductor substrate 1 through the metal bumps 7b.
  • FIG. 4 is a diagram showing a circuit arrangement in the vicinity of the final stage of the vertical CCD of the TDI type linear image sensor according to Embodiment 1 of the present invention.
  • FIG. 4 shows an example of a four-phase drive CCD.
  • Each vertical CCD 11 includes a transfer channel 40 formed on the surface of a silicon substrate, and a plurality of transfer gates 33 each including first gates 31a and 31c and second gates 32b and 32d. These transfer gates 33 are supplied with transfer clocks ⁇ V1 to ⁇ V4 from the outside of the first semiconductor substrate 1 through the input / output pads 4 and wirings on the substrate.
  • a light shielding film 38 such as aluminum is formed on the surface of the silicon substrate to prevent generation of a false signal during imaging.
  • the range surrounded by the thick dotted line 30 corresponds to one pixel, and the region above the A2-A2 'line contributes to photoelectric conversion.
  • the signal charge generated in each pixel is transferred in the + Y direction by the transfer operation of the vertical CCD 11.
  • An accumulation gate 39 and a final gate 34 are formed at the end of the vertical CCD 11 on the + Y side.
  • the storage gate 39 is supplied with the storage control clock ⁇ ST and the final gate 34 is supplied with the bias voltage VGO via the input / output pad 4 and the wiring on the substrate.
  • a floating diffusion layer 35 and a channel end 37 made of an N-type impurity region or the like are formed at the + Y side end of the vertical CCD 11.
  • the floating diffusion layer 35 is connected to the input gate of the column amplifier 5.
  • the channel end portion 37 is connected to the reset potential VR through the input / output pad 4 and the wiring on the substrate.
  • the potential is read by the column amplifier 5, converted into a voltage signal, and output.
  • the floating diffusion layer 35 is connected to a reset transistor 36 for discharging the charge after reading.
  • the reset transistor 36 is turned on by the reset clock ⁇ R given through the input / output pad 4 and the wiring on the substrate, the potential of the floating diffusion layer 35 is reset to the reset potential VR.
  • FIG. 5 is a diagram showing a circuit arrangement of the second semiconductor substrate 2 of the TDI linear image sensor according to the first embodiment of the present invention.
  • a signal processing circuit 6 and a plurality of metal bumps 20a, 20b, 20c are formed on the second semiconductor substrate 2.
  • the plurality of metal bumps 20a are provided to face the plurality of metal bumps 7a on the first semiconductor substrate 1, and are connected to the plurality of metal bumps 7a, respectively. Accordingly, the plurality of metal bumps 20 a are connected to the output terminals of the column amplifier 5 on the first semiconductor substrate 1, respectively.
  • the metal bump 20b is provided to face the metal bump 7b on the first semiconductor substrate 1, and is connected to the metal bump 7b.
  • the metal bump 20c is provided to face the metal bump 7c on the first semiconductor substrate 1, and is connected to the metal bump 7c.
  • the signal processing circuit 6 includes a horizontal selection circuit 16, a plurality of horizontal selection MOS transistors 17, a horizontal selection line 18, and an output amplifier 19.
  • the signal processing circuit 6 is supplied with a bias voltage and a clock signal necessary for driving the signal processing circuit 6 from the first semiconductor substrate 1 through the metal bumps 20 b and the metal wirings 22.
  • the horizontal selection circuit 16 is composed of a CMOS transistor or the like.
  • the output amplifier 19 includes a source follower amplifier and the like. Each metal bump 20 a is connected to a horizontal selection line 18 through a horizontal selection MOS transistor 17. When one of the horizontal selection MOS transistors 17 is turned on by the horizontal selection circuit 16, the output signal of the column amplifier 5 connected thereto is transferred to the output amplifier 19 through the horizontal selection line 18 and amplified by the output amplifier 19.
  • the output signal of the output amplifier 19 is returned to the circuit on the first semiconductor substrate 1 via the metal wiring 21 and the metal bump 20c, and then the first semiconductor via the input / output pad 4 as described above. Output to the outside of the substrate 1.
  • the signal processing circuit 6 sequentially selects and outputs one of the output signals of the column amplifiers 5 (that is, a plurality of signals indicating the charges transferred by the CCD columns 11).
  • the TDI linear image sensor according to the first embodiment of the present invention includes the first semiconductor substrate 1 that forms the pixel array 3 and the vertical CCD 11, the signal processing circuit 6 including the horizontal selection circuit 16 and the like.
  • the second semiconductor substrate 2 to be formed is manufactured separately, and these are electrically connected by metal bumps 7 or the like. Therefore, when transferring charges in the vertical direction, a low-noise TDI operation, which is an advantage of the CCD, can be performed.
  • high-speed reading which is an advantage of CMOS, is possible, and power consumption is reduced. Therefore, according to the TDI linear image sensor according to the first embodiment of the present invention, it is possible to provide a TDI linear image sensor that can be mounted on a package more easily than before while operating at high speed and low power consumption. Can do.
  • the TDI linear image sensor according to the first embodiment of the present invention returns the signal processed by the signal processing circuit 6 of the second semiconductor substrate 2 to the first semiconductor substrate 1 through the metal bumps 7. Later, it is configured to output to the outside of the TDI type linear image sensor. Accordingly, all input / output with respect to the TDI linear image sensor is performed via the input / output pads 4 formed on the first semiconductor substrate 1. Therefore, the mounting form on the package is simplified.
  • the signal processing circuit 6 formed on the second semiconductor substrate 2 includes the horizontal selection circuit 16 .
  • the A / D conversion circuit and the signal processing circuit 6 are formed on the second semiconductor substrate 2.
  • a serialization circuit or the like may be further provided. Since these circuits are composed of CMOS, high-speed signal processing is possible. According to this configuration, it becomes difficult to be influenced by circuit noise in the subsequent stage, and noise can be reduced.
  • the metal bumps 7 are used for bonding the first semiconductor substrate 1 and the second semiconductor substrate 2, but other bonding methods using, for example, an anisotropic conductive film may be used. A similar effect can be obtained.
  • Patent Document 1 discloses an image sensor including a pixel group, a plurality of selection lines, a line selection circuit, a vertical shift register, and a horizontal transfer unit.
  • pixel group two-dimensionally arranged pixels having transfer electrodes for performing photoelectric conversion and vertically transferring the generated charges by time delay integration.
  • the plurality of selection lines are connected to each of the transfer electrodes.
  • the line selection circuit is connected to a selection line, and connects a multiphase transfer clock to a predetermined selection line.
  • the vertical shift register writes a predetermined selection signal for determining the connection state of the transfer clock in the line selection circuit to the line selection circuit.
  • the horizontal transfer unit horizontally transfers the charge integrated with time delay.
  • the number of stages of time delay integration can be controlled by using a predetermined selection signal.
  • a line selection circuit that generates a reverse-phase transfer clock by switching one of the phases of a multi-phase transfer clock by a selection signal that is a binary signal having a high level and a low level. You may prepare.
  • the number of stages of time delay integration can be controlled by using a selection signal that is a combination of a continuous high level signal and a continuous low level signal corresponding to a predetermined number of stages of time delay integration.
  • the TDI stage number control is performed on the ⁇ Y side of the pixel array 3 in FIG.
  • a circuit may be arranged.
  • FIG. FIG. 6 is a diagram showing a circuit arrangement of the first semiconductor substrate 1A of the TDI linear image sensor according to the second embodiment of the present invention. 6, the same reference numerals as those in FIG. 3 denote the same components as those in FIG.
  • one column amplifier 5 is provided for every four vertical CCDs 11 on the + Y side of the vertical CCD 11. Are formed and connected.
  • FIG. 7 is a diagram showing a circuit arrangement in the vicinity of the final stage of the vertical CCD of the TDI linear image sensor according to the second embodiment of the present invention.
  • FIG. 7 is obtained by changing a part of the circuit arrangement in the vicinity of the final stage of the vertical CCD from the case of the TDI type linear image sensor according to the first embodiment of the present invention shown in FIG. 7, the same reference numerals as those in FIG. 4 denote the same components as those in FIG. In FIG. 7, in order to distinguish the four vertical CCDs 11 connected to one column amplifier 5, reference numerals 11a to 11d are given.
  • a set of four vertical CCDs 11a to 11d is formed, and one column amplifier 5 is formed and connected to each set.
  • a first accumulation gate 42, first selection gates 43a to 43b, second selection gates 44a to 44d, a second accumulation gate 45, and a final gate 34 are formed in this order. Is done.
  • the first storage gate 42 is supplied with the storage control clock ⁇ ST1
  • the second storage gate 45 is supplied with the storage control clock ⁇ ST2
  • the final gate is biased.
  • a voltage VGO is applied.
  • the selection clocks ⁇ SEL1A to ⁇ SEL1B are supplied to the first selection gates 43a to 43b through the input / output pad 4 and the wiring on the substrate, and the selection clocks ⁇ SEL2A to ⁇ SEL2B are supplied to the second selection gates 44a to 44d.
  • the floating diffusion layer 35 and the reset transistor 36 are configured in the same manner as in the case of the TDI linear image sensor according to the first embodiment of the present invention shown in FIG.
  • FIG. 8 schematically shows the cross-sectional structure and the potential distribution of each part in the vicinity of the final stage of the vertical CCD 11a.
  • FIG. 8A shows a cross section of the vertical CCD 11a
  • FIG. 8B to FIG. 8N show patterns of potential changes due to the transfer operation in time series.
  • FIG. 9 shows the cross-sectional structure near the final stage of the vertical CCD 11d and the potential distribution of each part as in the case of FIG.
  • the vertical CCDs 11a and 11d include a gate electrode 46, a P-type silicon substrate 48, a transfer channel 47, a floating diffusion layer 35, a channel end 37, a field oxide film 50, And a P-type impurity region 51.
  • the gate electrode 46 is made of, for example, polysilicon.
  • the transfer channel 47 is made of, for example, an N-type impurity region.
  • the floating diffusion layer 35 and the channel end portion 37 are made of, for example, a high concentration N-type impurity region.
  • P-type impurity region 51 is provided for element isolation.
  • the hatched area indicated by reference numeral 52 schematically represents signal charges accumulated in the potential well.
  • FIG. 8B shows a state immediately after the floating diffusion layer 35 is reset. At this time, signal charges in the next imaging cycle are accumulated in the potential well below the gate electrode 46 of the transfer clock ⁇ V3. Next, the signal charges move below the gate electrode 46 of the accumulation control clock ⁇ ST1 by the transfer operations of FIG. 8C to FIG. 8E.
  • FIG. 8F when the two selection clocks ⁇ SEL1A, ⁇ SEL2A and the accumulation control clock ⁇ ST2 become high level, the signal charges move below the gate electrode 46 of the accumulation control clock ⁇ ST1.
  • FIG. 8G when the two selection clocks ⁇ SEL1A and ⁇ SEL2A are at a low level, and further in FIG.
  • the accumulation control clock ⁇ ST2 is at a low level, the signal charge moves to the floating diffusion layer 35. .
  • the potential of the floating diffusion layer 35 at this time is read from the column amplifier 5. After the potential is read, when the reset clock ⁇ R becomes a high level in FIG. 8I, the charge in the floating diffusion layer 35 is discharged (reset). Thereafter, in FIG. 8 (j) to FIG. 8 (m), the signal charges of the remaining vertical CCDs 11b to 11d are read in accordance with changes in the other selected clocks ⁇ SEL1B, ⁇ SEL2B, etc., and signal reading for one imaging period is performed. Complete.
  • FIG. 9 shows the reading operation of the vertical CCD 11d.
  • the signal charge is held under the gate electrode 46 of the accumulation control clock ⁇ ST1.
  • FIG. 9 (k) when the two selection clocks ⁇ SEL1B and ⁇ SEL2B are both at the high level, the signal charge moves below the gate electrode 46 of the accumulation control clock ⁇ ST2, and then in FIG. 9 (l), the accumulation control clock ⁇ ST2 is changed.
  • the signal level becomes low, the signal charge moves to the floating diffusion layer 35.
  • the potential of the floating diffusion layer 35 at this time is read from the column amplifier 5.
  • the reset clock ⁇ R becomes a high level in FIG. 9M
  • the charge in the floating diffusion layer 35 is discharged (reset), and signal reading for one imaging period is completed.
  • the output signals of the four vertical CCDs 11a to 11d are sequentially transferred to the column amplifier 5.
  • Image signals can be read out by sequentially reading out the charges of the four vertical CCDs 11a to 11d for each imaging cycle.
  • the number of arrangement of the column amplifiers 5 is reduced to 1 ⁇ 4 compared to the number of arrangement of the vertical CCDs 11 in the horizontal direction (ie, the number of horizontal pixels).
  • the arrangement number of the metal bumps 7a connected thereto is reduced to 1 ⁇ 4. Therefore, it is possible to widen the interval at which the column amplifier 5 and the metal bump 7a are arranged to about four times the pixel pitch.
  • the minimum interval when the metal bumps 7a are arranged is limited by the manufacturing apparatus, and generally about several tens of ⁇ m is the lower limit.
  • one column amplifier 5 is formed and connected for every four vertical CCDs 11, but one column amplifier 5 is formed and connected for each different number of vertical CCDs 11. May be.
  • a plurality of column amplifiers 5 are provided for each of several vertical CCDs 11 adjacent to each other among the plurality of vertical CCDs 11. Output signals of several vertical CCDs 11 connected to each column amplifier 5 are sequentially transferred to the column amplifier 5.
  • one column amplifier 5 may be formed and connected for every eight vertical CCDs 11.
  • the number of gate electrodes to which a selection clock is applied is determined according to the number of vertical CCDs 11 corresponding to one column amplifier 5. In this way, the same effect can be obtained by combining other numbers of vertical CCDs 11 and other numbers of column amplifiers 5.
  • Embodiment 3 In the TDI linear image sensor according to the third embodiment of the present invention, the pixel array region is divided into a plurality of regions, the image signals of the divided pixel regions are separately processed, and are separately provided outside the TDI linear image sensor. Read to.
  • the TDI linear image sensor according to the third embodiment of the present invention includes a first semiconductor substrate 1B shown in FIG. 10 and a second semiconductor substrate 2B shown in FIG.
  • FIG. 10 is a diagram showing a circuit arrangement of the first semiconductor substrate 1B of the TDI linear image sensor according to the third embodiment of the present invention. 10, the same reference numerals as those in FIG. 3 denote the same components as those in FIG.
  • the area of the pixel array is divided into two pixel areas 3a and 3b.
  • a set of metal bumps 7a, 7b, 7c corresponding to the pixel region 3a and another set of metal bumps 7a, 7b, 7c corresponding to the pixel region 3b are formed. .
  • FIG. 11 is a diagram showing a circuit arrangement of the second semiconductor substrate 2B of the TDI linear image sensor according to the third embodiment of the present invention. 11, the same reference numerals as those in FIG. 5 denote the same components as those in FIG.
  • Two horizontal selection circuits 16a and 16b are formed on the semiconductor substrate 2B.
  • a set of metal bumps 20a, 20b, and 20c is formed.
  • the signal processing circuit 6a includes a horizontal selection circuit 16a, a plurality of horizontal selection MOS transistors 17a, a horizontal selection line 18a, and an output amplifier 19a.
  • the signal processing circuit 6a is supplied with a bias voltage and a clock signal from the first semiconductor substrate 1B via the metal bumps 20b and the metal wirings 22 for the pixel region 3a.
  • Each metal bump 20a for the pixel region 3a is connected to a horizontal selection line 18a via a horizontal selection MOS transistor 17a.
  • the output signal of the output amplifier 19a is returned to the circuit on the first semiconductor substrate 1B via the metal wiring 21 and the metal bump 20c for the pixel region 3a, and then the first signal is input via the input / output pad 4 to the first signal. It is output to the outside of the semiconductor substrate 1B.
  • the signal processing circuit 6a sequentially selects and outputs one of the output signals of the column amplifier 5 corresponding to the pixel region 3a.
  • the signal processing circuit 6b includes a horizontal selection circuit 16b, a plurality of horizontal selection MOS transistors 17b, a horizontal selection line 18b, and an output amplifier 19b.
  • the signal processing circuit 6b receives supply of a bias voltage and a clock signal from the first semiconductor substrate 1B through the metal bumps 20b and the metal wirings 22 for the pixel region 3b.
  • Each metal bump 20a for the pixel region 3b is connected to a horizontal selection line 18b via a horizontal selection MOS transistor 17b.
  • the output signal of the output amplifier 19b is returned to the circuit on the first semiconductor substrate 1B via the metal wiring 21 and the metal bump 20c for the pixel region 3b, and then the first signal via the input / output pad 4 It is output to the outside of the semiconductor substrate 1B. Accordingly, the signal processing circuit 6b sequentially selects and outputs one of the output signals of the column amplifier 5 corresponding to the pixel region 3b.
  • the image signal of each pixel region 3a is output to the outside of the first semiconductor substrate 1B via one input / output pad 4, and the image signal of each pixel region 3b is output to the other input / output pad 4. To the outside of the first semiconductor substrate 1B.
  • the region of the pixel array 3 is divided into three or more, and the image signals of the divided pixel regions are separately processed, and the TDI linear image sensor You may read separately outside.
  • the output terminals of the plurality of column amplifiers 5 on the first semiconductor substrate are electrically connected to the input terminals of the plurality of signal processing circuits 6 on the second semiconductor substrate by the metal bumps 7.
  • the output terminals of the plurality of signal processing circuits 6 on the second semiconductor substrate are electrically connected to the plurality of input / output pads 4 used as output pads on the first semiconductor substrate by metal bumps 7, respectively. Is done.
  • the time required for the selection operation of the horizontal selection circuits 16a and 16b is determined by the TDI according to the first embodiment of the present invention. It can be longer than in the case of a linear image sensor. Accordingly, the signal reading noise can be reduced by reducing the signal reading speed.
  • FIG. FIG. 12 is a perspective view showing a schematic structure of a TDI type linear image sensor according to Embodiment 4 of the present invention. 12, the same reference numerals as those in FIG. 1 denote the same components as those in FIG.
  • the first semiconductor substrate 1C further includes other circuits such as a plurality of vertical CCDs, a plurality of column amplifiers, and a TDI stage number control circuit.
  • FIG. 13 is a sectional structural view of a TDI type linear image sensor according to Embodiment 4 of the present invention.
  • FIG. 13 shows a cross-section at a position corresponding to the line A4-A4 ′ of FIG. 12 when the first semiconductor substrate 1C and the second semiconductor substrate 2 of FIG. 13, the same reference numerals as those in FIG. 2 denote the same components as those in FIG.
  • the first semiconductor substrate 1C further includes a TDI stage number control circuit 10 in addition to the components of the first semiconductor substrate 1 of FIG.
  • the TDI stage number control circuit 10 operates in the same manner as the TDI stage number control circuit described in Patent Document 1, and is connected to the transfer gates of the plurality of vertical CCDs 11 to control the TDI stage number.
  • the TDI stage number control circuit 10 is formed, for example, on the ⁇ Y side of the pixel array 3 on the first semiconductor substrate 1C.
  • FIG. 14 is a diagram showing a circuit layout of the first semiconductor substrate 1C of the TDI linear image sensor according to the fourth embodiment of the present invention. 14, the same reference numerals as those in FIG. 3 denote the same components as those in FIG.
  • the region of the pixel array 3 on the first semiconductor substrate 1C is divided into four pixel regions, and four second semiconductor substrates 2 corresponding to these are formed into the first semiconductor substrate 1C. Be joined.
  • the output signal from the signal processing circuit on each second semiconductor substrate 2 is returned to the circuit on the first semiconductor substrate 1C via the four metal bumps 7c respectively corresponding to the four pixel regions of the pixel array 3. It is.
  • the output signals of the TDI linear image sensor are output in parallel to the outside of the first semiconductor substrate 1C via the four input / output pads 4 corresponding to the four pixel regions of the pixel array 3, respectively.
  • the region of the pixel array 3 is divided into a number other than four, and the number of second semiconductor substrates 2 corresponding to the number of divided pixel regions is provided. You may join to a 1st semiconductor substrate.
  • the output terminals of the plurality of column amplifiers 5 on the first semiconductor substrate are electrically connected to the input terminals of the signal processing circuits 6 on the plurality of second semiconductor substrates 2 by the metal bumps 7.
  • the output terminals of the signal processing circuits 6 on the plurality of second semiconductor substrates 2 are electrically connected to the plurality of input / output pads 4 used as output pads on the first semiconductor substrate, respectively, by metal bumps 7. Connected.
  • the signal processing circuits 6 on the plurality of second semiconductor substrates 2 sequentially select and output one of the output signals of the plurality of column amplifiers 5 respectively.
  • each of the plurality of second semiconductor substrates 2 may include one signal processing circuit 6.
  • a signal processing circuit 6 may be provided.
  • M1 is an integer of 2 or more and M2 is a multiple of M1
  • a total of M2 signal processing circuits 6 may be formed on the M1 second semiconductor substrates 2.
  • the TDI linear image sensor according to the fourth embodiment of the present invention increases the number of pixels in the horizontal direction and increases the observation width of the linear image sensor. be able to.
  • FIG. 15 shows the final image of a vertical CCD near the left end of one divided area when a signal is read out by dividing the area of the pixel array into a plurality of areas in the TDI linear image sensor according to the fourth embodiment of the present invention. It is a figure which shows the circuit arrangement
  • a plurality of column amplifiers 5 corresponding to one divided pixel region are arranged with a constant interval a.
  • a plurality of metal bumps 7a corresponding to the vertical CCD 11 near the center of the same pixel region (right side in FIG. 15) are arranged with an interval a.
  • the plurality of metal bumps 7a corresponding to the vertical CCD 11 in the vicinity of the left end of the same pixel region (left side in FIG. 15) are arranged with an interval b shorter than the interval a.
  • a plurality of metal bumps 7a corresponding to the vertical CCD 11 in the vicinity of the right end of the same pixel region are also arranged with an interval b.
  • the plurality of column amplifiers 5 corresponding to one divided pixel area have a plurality of columns corresponding to the same pixel area rather than the total length in the X direction of the area arranged on the first semiconductor substrate 1C.
  • the total length in the X direction of the region where the metal bumps 7a are arranged on the first semiconductor substrate 1C can be shortened.
  • the column amplifier 5 connected to the signal processing circuit 6 on the second semiconductor substrate 2 is the first semiconductor.
  • the metal bumps 7a are arranged so that the total length in the X direction of the region in which the corresponding metal bump 7a is arranged is shorter than the total length in the X direction of the region formed on the substrate 1C.
  • the TDI linear image sensor As described with reference to FIG. 15, according to the TDI linear image sensor according to the fourth embodiment of the present invention, one second region compared to the total length of one divided pixel region in the X direction.
  • the total length of the semiconductor substrate 2 in the X direction can be shortened.
  • the plurality of second semiconductor substrates 2 when the plurality of second semiconductor substrates 2 are bonded to the long image sensor in which a large number of pixels are arranged in the horizontal direction, the plurality of second semiconductor substrates 2 can be arranged in a row. This can reduce the size of the image sensor.
  • the arrangement of the metal bumps 7a described with reference to FIG. 15 is also applicable to a long linear image sensor manufactured by the method described in Patent Document 2, for example.
  • a method for manufacturing a linear image sensor that detects incident light by converting it into an electrical signal is disclosed.
  • the method includes a step of preparing a semiconductor substrate.
  • the method then includes the step of forming channel stopper regions juxtaposed in parallel and a transfer channel sandwiched between the channel stopper regions in the vicinity of the surface of the semiconductor substrate.
  • This method then includes a step of forming a gate insulating film covering at least the channel stopper region.
  • the method then includes a gate forming step of forming a transfer gate extending substantially perpendicular to the transfer channel on the gate insulating film.
  • the method then includes a step of forming an interlayer insulating film that covers the transfer gate.
  • the method then includes a patterning step of forming a photoresist layer on the interlayer insulating film and patterning the photoresist layer to form an opening pattern on the transfer gate.
  • the method then includes the steps of forming a hole in the interlayer insulating film using the photoresist layer as a mask and exposing the transfer gate on the bottom surface of the hole.
  • This method then includes a backing wiring forming step of forming a backing wiring connected to the transfer gate through the hole and extending along the channel stopper on the interlayer insulating film after removing the photoresist layer. .
  • This method then includes a step of forming a protective film on the interlayer insulating film and the backing wiring.
  • the patterning step includes a step of exposing the photoresist layer by a reduction exposure method.
  • FIG. FIG. 16 is a diagram showing a circuit arrangement of the first semiconductor substrate 1D of the TDI linear image sensor according to the fifth embodiment of the present invention.
  • FIG. 6 is a diagram showing a circuit arrangement in the vicinity of the final stage of a vertical CCD near the left end of one divided area. This is obtained by changing a part of the circuit arrangement near the final stage of the vertical CCD from the case of the TDI linear image sensor according to the fourth embodiment of the present invention shown in FIG.
  • the plurality of metal bumps 57 a are not arranged in a straight line, but are arranged in a bowl shape along two adjacent sides of the second semiconductor substrate 2. With this arrangement, the total length in the X direction of the region where the metal bumps 7a are arranged can be shortened without reducing the interval a between the metal bumps 7a. Even when this arrangement is used, when a plurality of second semiconductor substrates 2 are joined to a long image sensor in which a large number of pixels are arranged in a horizontal direction, the plurality of second semiconductor substrates 2 are arranged in a row. It becomes possible to arrange.
  • the TDI linear image sensor according to the fifth embodiment of the present invention it is not necessary to reduce the distance a between the metal bumps 7a, so that the pixel pitch can be further reduced as compared with the fourth embodiment. .
  • FIG. 17 is a diagram showing a circuit arrangement of the first semiconductor substrate 1E of the TDI linear image sensor according to the sixth embodiment of the present invention.
  • FIG. 18 is a cross-sectional structure diagram of a TDI linear image sensor according to Embodiment 6 of the present invention. 18 shows a cross section when the first semiconductor substrate 1E and the second semiconductor substrate 2 of FIG. 17 and 18, the same reference numerals as those in FIGS. 14 and 13 denote the same components as those in FIGS. 14 and 13.
  • FIGS. 17 and 18 are obtained by changing the circuit arrangement of the TDI stage number control circuit 10 from the case of the TDI linear image sensor according to the fourth embodiment of the present invention shown in FIGS. 14 and 13. That is, in the TDI linear image sensor according to the fourth embodiment of the present invention shown in FIG. 14, the TDI stage number control circuit 10 is arranged on the ⁇ Y side of the pixel array 3, whereas FIG. In the TDI linear image sensor according to the sixth embodiment of the present invention, the TDI stage number control circuit 10 is arranged on the + Y side of the pixel array 3.
  • the TDI stage number control circuit 10 is placed on the opposite side of the pixel array 3 across the plurality of column amplifiers 5 on the first semiconductor substrate 1E. Is formed.
  • the TDI stage number control circuit 10 is placed in a region below the second semiconductor substrate 2 on the first semiconductor substrate 1E. Can be arranged. Therefore, in the TDI linear image sensor according to the sixth embodiment of the present invention, the size of the first semiconductor substrate 1E can be reduced in the Y direction as compared with the first semiconductor substrate 1E in the case of FIG. it can.
  • FIG. 19 is a diagram showing a circuit arrangement of the first semiconductor substrate 1F of the TDI type linear image sensor array according to the seventh embodiment of the present invention. 19, the same reference numerals as those in FIG. 17 denote the same components as those in FIG.
  • the TDI type linear image sensor array according to the seventh embodiment of the present invention shown in FIG. 19 has a plurality of TDI type linear image sensors formed on the same substrate.
  • a linear image sensor is formed on the same substrate.
  • a multiband image sensor in which a plurality of image sensors are arranged in parallel and a spectral filter corresponding to RGB is formed on the incident surface is often used.
  • a color image is generated by combining the output signals of a plurality of image sensors, it is necessary to accurately correct the pixel position for each color. This is advantageous because it reduces the need to account for misalignment.
  • the horizontal reading is performed by the CMOS circuit on the second semiconductor substrate 2. Therefore, even if a plurality of TDI type linear image sensors are arranged, an increase in power consumption of the entire TDI type linear image sensor array can be suppressed.
  • FIG. 20 is a diagram showing a circuit arrangement of the first semiconductor substrate 1G of the TDI type linear image sensor according to the eighth embodiment of the present invention. 20, the same reference numerals as those in FIG. 17 denote the same components as those in FIG.
  • the column amplifier 105 is formed at the other end of the vertical CCD. Is done.
  • the output signal of the column amplifier 5 is read out via a signal processing circuit on the second semiconductor substrate 2 connected by the metal bump 7a, and input / output on the first semiconductor substrate 1G connected by the metal bump 7c.
  • the signal is output to the outside of the TDI type linear image sensor via the pad 4.
  • the output signal of the column amplifier 105 is read out via the signal processing circuit on the third semiconductor substrate 102 connected by the metal bump 107a, and is output on the first semiconductor substrate 1G connected by the metal bump 107c.
  • the data is output to the outside of the TDI linear image sensor via the input / output pad 4.
  • the column amplifier 105 is also referred to as a “second signal preprocessing circuit”
  • the signal processing circuit over the third semiconductor substrate 102 is also referred to as a “second signal processing circuit”.
  • the input / output pad 4 that outputs the output signal of the signal processing circuit on the third semiconductor substrate 102 is also referred to as a “second output pad”.
  • the TDI stage number control circuit 10 is formed on the first semiconductor substrate 1G.
  • the TDI stage number control circuit 10 controls the number of TDI stages in the same manner as the operation described in Patent Document 1.
  • the vertical CCD transfers charges in the forward direction (+ Y direction) from the first stage (+ Y side end) of the pixel array 3 to the M stage, and the pixel array 3 From the M + 1 stage to the last stage ( ⁇ Y side end), the vertical CCD transfers charges in the reverse direction ( ⁇ Y direction).
  • An output signal when the vertical CCD 11 is transferred in the forward direction is provided at the end on the + Y side of the first semiconductor substrate 1G via the column amplifier 5 and the signal processing circuit on the second semiconductor substrate 2.
  • the output signal when the vertical CCD 11 is transferred in the reverse direction passes through the column amplifier 105 and the signal processing circuit on the third semiconductor substrate 102 to the end portion on the ⁇ Y side of the first semiconductor substrate 1G. It is output from the input / output pad 4 provided.
  • the column amplifier 5 and the second semiconductor substrate 2 are formed at the + Y side end of the vertical CCD 11, and the column amplifier 105 and the third semiconductor substrate 102 are formed at the ⁇ Y side end of the vertical CCD 11.
  • the end can be selected and the charge can be read out in both directions.
  • a TDI linear image sensor capable of reading charges in both directions can be realized.
  • a TDI linear image sensor includes a pixel array, a plurality of transfer elements, at least one first signal processing circuit, at least one first output pad, one first semiconductor substrate, And at least one second semiconductor substrate.
  • the pixel array has a plurality of pixels that perform photoelectric conversion arranged in a two-dimensional array having a first direction and a second direction.
  • the plurality of transfer elements transfer the charges generated in the plurality of pixels in a first direction by time delay integration, and are adjacent to each other in the second direction.
  • At least one first signal processing circuit sequentially selects and outputs one of a plurality of signals respectively indicating the charges transferred by the plurality of transfer elements.
  • At least one first output pad outputs an output signal of the first signal processing circuit.
  • a pixel array, a plurality of transfer elements, and a first output pad are formed on one first semiconductor substrate.
  • a first signal processing circuit is formed on at least one second semiconductor substrate.
  • At least one second semiconductor substrate is electrically connected to one first semiconductor substrate.
  • N1 transfer elements and N2 first And a signal preprocessing circuit.
  • Each transfer element has a first end and a second end, and outputs the transferred charge from the first end.
  • Each first signal preprocessing circuit is provided for each of at least one of the N1 transfer elements, and is connected to a first end of at least one transfer element, and includes at least one Each of the output signals of the transfer elements is processed.
  • the first signal preprocessing circuit is formed on the first semiconductor substrate. The first signal processing circuit sequentially selects and outputs one of the output signals of the N2 first signal preprocessing circuits.
  • the output terminals of the N2 first signal preprocessing circuits on the first semiconductor substrate are connected to at least one first signal processing circuit on the at least one second semiconductor substrate by the first electrical connector. It may be electrically connected to the input terminal.
  • An output terminal of at least one first signal processing circuit on at least one second semiconductor substrate is electrically connected to at least one first output pad on the first semiconductor substrate by a second electrical connector. May be connected.
  • the N2 first signal preprocessing circuits when N1 is an integer of 4 or more and N3 is an integer of 2 or more, the N2 first signal preprocessing circuits have N1 transfers.
  • One element may be provided for each of N3 transfer elements adjacent to each other.
  • the output signals of the N3 transfer elements connected to the respective first signal preprocessing circuits of the N2 first signal preprocessing circuits are sequentially sent to the one first signal preprocessing circuit. Transferred.
  • N4 of N2 first signal preprocessing circuits A plurality of first signal processing circuits that sequentially select and output one of the output signals of the first signal preprocessing circuit may be provided.
  • the TDI linear image sensor according to the embodiment of the present invention includes a plurality of second semiconductor substrates each formed with at least one first signal processing circuit among the plurality of first signal processing circuits. Also good.
  • each of the second semiconductor substrates among the plurality of second semiconductor substrates is used as the first signal processing circuit on the second semiconductor substrate.
  • the first electrical connector is disposed in comparison with the total length in the second direction of the region where the first signal preprocessing circuit on the first semiconductor substrate to be connected is formed on the first semiconductor substrate.
  • the first electrical connector may be arranged so that the total length in the second direction of the region is shorter.
  • the TDI type linear image sensor according to the embodiment of the present invention may further include a TDI stage number control circuit that is connected to transfer gates of N1 transfer elements and controls the number of TDI stages.
  • the TDI stage number control circuit is formed on the first semiconductor substrate on the opposite side of the pixel array with the N2 first signal preprocessing circuits interposed therebetween.
  • the TDI linear image sensor includes N2 second signal preprocessing circuits, at least one second signal processing circuit, at least one second output pad, and at least one.
  • One third semiconductor substrate may be further provided.
  • N2 second signal preprocessing circuits are provided for each of at least one of the N1 transfer elements, connected to the second end of at least one transfer element, and at least Each output signal of one transfer element is processed.
  • At least one second signal processing circuit sequentially selects and outputs one of the output signals of the N2 second signal preprocessing circuits.
  • the at least one second output pad outputs an output signal of at least one second signal processing circuit.
  • At least one second signal processing circuit is formed on at least one third semiconductor substrate.
  • N2 second signal preprocessing circuits and at least one second output pad are formed on the first semiconductor substrate.
  • the output terminals of the N2 second signal preprocessing circuits on the first semiconductor substrate are connected to the at least one second signal processing circuit on the at least one third semiconductor substrate by the third electrical connector. Electrically connected to the input terminal.
  • An output terminal of at least one second signal processing circuit on at least one third semiconductor substrate is electrically connected to at least one second output pad on the first semiconductor substrate by a fourth electrical connector. Connected to.

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Abstract

L'invention concerne, dans un réseau de pixels (3), une pluralité de pixels permettant de réaliser une conversion photoélectrique, laquelle pluralité de pixels sont agencés dans un réseau bidimensionnel comportant une première direction et une seconde direction. Une pluralité de CCD verticaux (11) soumettent respectivement des charges électriques générées dans la pluralité de pixels au retard temporel et à une intégration, transfèrent les charges électriques dans la première direction, et sont adjacentes l'une à l'autre dans la seconde direction. Un circuit de traitement de signal (6) sélectionne et délivre en sortie de manière séquentielle un signal parmi une pluralité de signaux indiquant respectivement les charges électriques transférées par la pluralité de CCD verticaux (11). Un bloc d'entrée/sortie (4) délivre en sortie un signal de sortie du circuit de traitement de signal (6). Sur un premier substrat semi-conducteur (1), le réseau de pixels (3), la pluralité de CCD verticaux (11) et le bloc d'entrée/sortie (4) sont formés. Sur un second substrat semi-conducteur (2), le circuit de traitement de signal (6) est formé. Le second substrat semi-conducteur (2) est électriquement relié au premier substrat semi-conducteur (1).
PCT/JP2017/030152 2016-12-19 2017-08-23 Capteur d'images linéaire de photodétecteur à report et intégration WO2018116523A1 (fr)

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CN111430397A (zh) * 2020-04-01 2020-07-17 中国电子科技集团公司第四十四研究所 具有增透膜的多谱段tdiccd结构
JP2020136987A (ja) * 2019-02-22 2020-08-31 三菱電機株式会社 固体撮像素子
JP2022144301A (ja) * 2021-03-18 2022-10-03 株式会社東芝 固体撮像装置
CN115767301A (zh) * 2022-11-16 2023-03-07 中国电子科技集团公司第四十四研究所 基于3d式集成tdi-cmos图像传感器的多谱段时序控制方法

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JP2010093331A (ja) * 2008-10-03 2010-04-22 Mitsubishi Electric Corp イメージセンサ及びその駆動方法
JP2011244452A (ja) * 2010-05-17 2011-12-01 Commissariat A L'energie Atomique Et Aux Energies Alternatives 高ビデオキャプチャレートを有するｃｍｏｓテクノロジーのイメージセンサ
JP2013098853A (ja) * 2011-11-02 2013-05-20 Hamamatsu Photonics Kk 固体撮像装置
WO2014021417A1 (fr) * 2012-08-03 2014-02-06 国立大学法人 静岡大学 Élément semi-conducteur et dispositif de capture d'image à semi-conducteur

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JP2010093331A (ja) * 2008-10-03 2010-04-22 Mitsubishi Electric Corp イメージセンサ及びその駆動方法
JP2011244452A (ja) * 2010-05-17 2011-12-01 Commissariat A L'energie Atomique Et Aux Energies Alternatives 高ビデオキャプチャレートを有するｃｍｏｓテクノロジーのイメージセンサ
JP2013098853A (ja) * 2011-11-02 2013-05-20 Hamamatsu Photonics Kk 固体撮像装置
WO2014021417A1 (fr) * 2012-08-03 2014-02-06 国立大学法人 静岡大学 Élément semi-conducteur et dispositif de capture d'image à semi-conducteur

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020136987A (ja) * 2019-02-22 2020-08-31 三菱電機株式会社 固体撮像素子
CN111430397A (zh) * 2020-04-01 2020-07-17 中国电子科技集团公司第四十四研究所 具有增透膜的多谱段tdiccd结构
JP2022144301A (ja) * 2021-03-18 2022-10-03 株式会社東芝 固体撮像装置
JP7467380B2 (ja) 2021-03-18 2024-04-15 株式会社東芝 固体撮像装置
CN115767301A (zh) * 2022-11-16 2023-03-07 中国电子科技集团公司第四十四研究所 基于3d式集成tdi-cmos图像传感器的多谱段时序控制方法

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