WO2018090650A1 - 时钟补偿电路、时钟电路和微控制器 - Google Patents

时钟补偿电路、时钟电路和微控制器 Download PDF

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Publication number
WO2018090650A1
WO2018090650A1 PCT/CN2017/092482 CN2017092482W WO2018090650A1 WO 2018090650 A1 WO2018090650 A1 WO 2018090650A1 CN 2017092482 W CN2017092482 W CN 2017092482W WO 2018090650 A1 WO2018090650 A1 WO 2018090650A1
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Prior art keywords
circuit
clock
digital signal
capacitance value
capacitance
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PCT/CN2017/092482
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English (en)
French (fr)
Inventor
徐以军
彭新朝
张亮
冯玉明
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珠海格力电器股份有限公司
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Priority to KR1020197003201A priority Critical patent/KR102158947B1/ko
Priority to US16/331,057 priority patent/US10644684B2/en
Priority to EP17872201.3A priority patent/EP3544182A4/en
Priority to JP2019506097A priority patent/JP6728475B2/ja
Publication of WO2018090650A1 publication Critical patent/WO2018090650A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231—Astable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
    • H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
    • H03K4/50—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor
    • H03K4/501—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator
    • H03K4/502—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator the capacitor being charged from a constant-current source

Definitions

  • the present invention relates to the field of circuit design, and in particular to a clock compensation circuit, a clock circuit, and a microcontroller.
  • the RC clock is widely used in integrated circuits because of its simple structure.
  • the accuracy of the RC clock is often limited by the internal resistance, the accuracy of the capacitor, and the power supply and temperature. It cannot achieve very high accuracy at full temperature and full voltage.
  • the frequency fluctuation of the clock over the full temperature range and the full voltage range causes a deviation of the chip accuracy of ⁇ 2%. Therefore, in the related art, the frequency clock fluctuates due to the ambient temperature of the clock and the fluctuation of the power supply voltage, which causes a large deviation in the accuracy of the microcontroller.
  • a main object of the present invention is to provide a clock compensation circuit, a clock circuit and a microcontroller to solve the problem that the clock frequency of the output of the clock circuit fluctuates greatly in the related art.
  • the clock compensation circuit includes:
  • a detection circuit for detecting a capacitance control parameter capable of affecting a clock frequency of a clock circuit output
  • a control unit configured to adjust a capacitance value of the target capacitor in the clock circuit according to the capacitance control parameter detected by the detection circuit to change a clock frequency output by the clock circuit.
  • the detection circuit includes: a voltage detection circuit for detecting a power supply voltage of the clock circuit as a capacitance control parameter.
  • control unit includes: a first conversion module, configured to convert an analog signal corresponding to the power voltage detected by the voltage detecting circuit into a first digital signal; and a first transmission module, configured to input the first digital signal a control end of the target capacitor; and a first control module configured to adjust a capacitance value of the target capacitor by the first digital signal to change a clock frequency output by the clock circuit.
  • the detecting circuit further includes: a temperature detecting circuit for detecting an ambient temperature of an environment in which the clock circuit is located as a capacitance control parameter.
  • control unit further includes: a second conversion module, configured to convert an analog signal corresponding to an ambient temperature detected by the temperature detecting circuit into a second digital signal; and a second transmission module, configured to input the second digital signal into the target a control end of the capacitor; and a second control module configured to adjust a capacitance value of the target capacitor by the second digital signal to change a clock frequency of the clock circuit output.
  • a second conversion module configured to convert an analog signal corresponding to an ambient temperature detected by the temperature detecting circuit into a second digital signal
  • second transmission module configured to input the second digital signal into the target a control end of the capacitor
  • second control module configured to adjust a capacitance value of the target capacitor by the second digital signal to change a clock frequency of the clock circuit output.
  • the second control module includes: a first comparison submodule, configured to compare the detected ambient temperature with a preset temperature; and a first adjustment submodule configured to compare the ambient temperature to a preset temperature In the case that the capacitance value of the target capacitor is reduced to the first target capacitance value by the second digital signal; the second adjustment sub-module is configured to pass the second digital signal when the ambient temperature is greater than the preset temperature The capacitance of the target capacitor is increased to the second target capacitance value.
  • the first control module includes: a second comparison submodule, configured to compare a power supply voltage with a preset voltage; and a third adjustment submodule, configured to compare the power supply voltage to a preset voltage, The capacitance value of the target capacitor is reduced to a third target capacitance value by the first digital signal; and the fourth adjustment submodule is configured to pass the target digital capacitor by using the first digital signal when the power supply voltage is greater than the preset voltage The capacitance value is increased to the fourth target capacitance value.
  • the detecting circuit further includes: a comparator circuit disposed in the detecting circuit, configured to perform analog-to-digital conversion processing on the capacitance control parameter detected by the detecting circuit to be converted into a corresponding digital signal, wherein the control unit is specifically used The capacitance value of the target capacitor is adjusted according to the corresponding digital signal to change the clock frequency of the clock circuit output.
  • a clock circuit including a target capacitance capable of changing a clock frequency of an output of the clock circuit and the above-described clock compensation circuit is provided.
  • a microcontroller including the clock circuit is provided.
  • the clock compensation circuit can compensate the clock circuit as needed to reduce the clock power
  • the clock frequency of the road output fluctuates.
  • FIG. 1 is a schematic diagram of a clock compensation circuit according to an embodiment of the present invention.
  • FIG. 2 is a structural diagram of a clock circuit in the related art
  • FIG. 3 is a schematic diagram showing the operation of a clock circuit in the related art
  • FIG. 4 is a schematic diagram showing a frequency change of a clock circuit in a related art in a full voltage range
  • FIG. 5 is a schematic diagram showing a frequency change of a clock circuit in a related art in a full temperature range
  • FIG. 6 is a structural diagram of a clock circuit according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a frequency variation of a clock circuit in a full voltage range according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of frequency variation of a clock circuit over a full temperature range according to an embodiment of the present invention.
  • a clock compensation circuit is provided.
  • the clock compensation circuit includes the following structure:
  • the detection circuit 10 is configured to detect a capacitance control parameter that can affect the clock frequency of the clock circuit output.
  • the capacitance control parameter that can affect the clock frequency of the clock circuit output is detected by the detection circuit 10 in the clock compensation circuit.
  • the target capacitance is set in the clock circuit, and the capacitance value thereof is adjustable, and the change of the clock frequency of the output of the clock circuit can be realized by the digital signal input to the control terminal of the target capacitor.
  • the control unit 20 is connected to the detecting circuit 10 for adjusting the capacitance value of the target capacitor according to the capacitance control parameter detected by the detecting circuit 10 to change the clock frequency output by the clock circuit.
  • the control unit 20 connected to the detecting circuit 10 in the clock compensating circuit can adjust the capacitance value of the target capacitor according to the capacitance control parameter detected by the detecting circuit 10, thereby changing the clock frequency output by the clock circuit.
  • the clock circuit can be compensated as needed, thereby changing the clock frequency output by the clock circuit, and reducing the fluctuation of the clock frequency output by the clock circuit.
  • the detection circuit 10 includes: a voltage detection circuit 10 for detecting a power supply voltage of the clock circuit as a capacitance control parameter.
  • the detection circuit 10 of the clock compensation circuit includes a voltage detection circuit for detecting a power supply voltage of the clock circuit.
  • the voltage detecting circuit in the detecting circuit 10 detects the power supply voltage of the clock circuit, and adjusts the capacitance value of the target capacitor according to the power supply voltage to change the clock frequency output by the clock circuit.
  • the control unit 20 includes: a first conversion module, configured to convert an analog signal corresponding to a power supply voltage detected by the detection circuit 10 (specifically, a voltage detection circuit) a first digital signal; a first transmission module, configured to input a first digital signal to a control end of the target capacitor; and a first control module configured to control a capacitance value of the target capacitor by the first digital signal to change a clock circuit output Clock frequency.
  • a first conversion module configured to convert an analog signal corresponding to a power supply voltage detected by the detection circuit 10 (specifically, a voltage detection circuit) a first digital signal
  • a first transmission module configured to input a first digital signal to a control end of the target capacitor
  • a first control module configured to control a capacitance value of the target capacitor by the first digital signal to change a clock circuit output Clock frequency.
  • the detecting circuit 10 detects that the power supply voltage of the clock circuit is 5.3V.
  • the first conversion module converts the analog signal corresponding to the power supply voltage detected by the voltage detecting circuit into the first digital signal. That is, the first conversion module converts 5.3V into a first digital signal, and the first control module controls the capacitance value of the target capacitor through the first digital signal in the circuit in which the target capacitor is located to change the clock frequency of the clock circuit output. It should be noted that for the above The numerical values used for the examples are merely illustrative and do not represent the numbers that are normally adjusted during actual circuit operation.
  • the first control module includes: a second comparison submodule, configured to compare a power supply voltage with a preset voltage; and a third adjustment submodule, configured to: When the power supply voltage is less than the preset voltage, the capacitance value of the target capacitor is reduced to a third target capacitance value by the first digital signal; and the fourth adjustment submodule is configured to compare the power supply voltage to be greater than the preset voltage. In the case, the capacitance value of the target capacitor is increased to the fourth target capacitance value by the first digital signal.
  • the clock circuit operates with a power supply voltage ranging from 2.7V to 5.5V and a preset voltage of 5V.
  • the second comparison sub-module compares the detected power supply voltage with a preset voltage. If the detected power supply voltage is 4.5V, less than the preset voltage of 5V. If the capacitance of the target capacitor is 110F, the target capacitor can be adjusted from 50F to 550F. When the power supply voltage is less than the preset voltage, the third regulator sub-module will target The capacitance value of the capacitor is adjusted to 110F.
  • the fourth regulator sub-module increases the capacitance value 110F of the target capacitor to 130F when the power supply voltage is greater than the preset voltage.
  • the detection circuit 10 further includes: a temperature detection circuit, configured to detect an ambient temperature of an environment in which the clock circuit is located as a capacitance control parameter.
  • the detection circuit 10 of the clock compensation circuit includes a temperature detection circuit that detects the ambient temperature of the environment in which the clock circuit is located.
  • the control unit controls the target capacitance according to the ambient temperature of the environment in which the clock circuit is detected by the temperature detecting circuit to change the clock frequency output by the clock circuit.
  • the control unit 20 further includes: a second conversion module, configured to convert the analog signal corresponding to the ambient temperature detected by the detection circuit 10 into a second digital signal; a second transmission module, configured to input a second digital signal to the control end of the target capacitor; and a second control module, configured to control a capacitance value of the target capacitor by the second digital signal to change a clock frequency output by the clock circuit.
  • a second conversion module configured to convert the analog signal corresponding to the ambient temperature detected by the detection circuit 10 into a second digital signal
  • a second transmission module configured to input a second digital signal to the control end of the target capacitor
  • a second control module configured to control a capacitance value of the target capacitor by the second digital signal to change a clock frequency output by the clock circuit.
  • the mapping relationship between the ambient temperature and the voltage value is established in advance.
  • the detection circuit 10 detects that the ambient temperature of the environment where the clock circuit is located is 25 ° C, and the ambient temperature is 25 ° C.
  • the corresponding voltage value is 5V
  • the detection circuit 10 detects that the ambient temperature of the environment in which the clock circuit is located is 26 degrees Celsius, and the ambient temperature of 26° C. corresponds to a voltage value of 5.1V. Therefore, the analog signal corresponding to the ambient temperature detected by the temperature detecting circuit is specifically an analog signal corresponding to the voltage value corresponding to the ambient temperature detected by the temperature detecting circuit.
  • the second conversion module converts the analog signal corresponding to the voltage value corresponding to the ambient temperature detected by the temperature detecting circuit into a second digital signal
  • the second control module adjusts the capacitance value of the target capacitor through the second digital signal to change the clock circuit.
  • the clock frequency of the output It should be noted that the numerical values used for the above examples are merely illustrative and do not represent the numbers of the normal adjustments during the actual operation of the circuit, but only the techniques in the present invention are exemplified.
  • the second control module includes: a first comparison submodule, configured to compare the detected ambient temperature with a preset temperature; the first adjustment submodule And comparing, when the ambient temperature is less than the preset temperature, the capacitance value of the target capacitor is reduced to a first target capacitance value by using a second digital signal; and the second adjustment submodule is configured to compare the ambient temperature to be greater than In the case of the preset temperature, the capacitance value of the target capacitor is increased to the second target capacitance value by the second digital signal.
  • the temperature range of the ambient temperature of the clock circuit is: -40 ° C ⁇ 125 ° C
  • the preset temperature is 25 ° C
  • the first comparison sub-module compares the detected temperature with the preset temperature, if detected The ambient temperature is 15 ° C, which is less than the preset temperature is 25 ° C.
  • the target capacitor is adjustable from 50F to 550F
  • the target capacitor has a capacitance of 110F.
  • the first regulator The module reduces the capacitance of the target capacitor, 110F, to 100F.
  • the second regulator sub-module increases the capacitance value 110F of the target capacitor to 130 F when the temperature is greater than the preset voltage.
  • the detection circuit 10 further includes: a comparator circuit disposed in the detection circuit 10 for performing analog-to-digital conversion on the capacitance control parameter detected by the detection circuit 10. Processing, to be converted into a corresponding digital signal, wherein the control unit 20 is specifically configured to control the target capacitance according to the corresponding digital signal to adjust the clock frequency output by the clock circuit.
  • the comparator of the comparator circuit of the present invention outputs a high level according to the potential of the positive phase input terminal being higher than the inverting input terminal; the potential of the inverting input terminal is higher than the positive phase input terminal, and the output of the low level is self-characteristic, and the detection is detected.
  • the analog signal corresponding to the capacitance control parameter detected by the circuit 10 is converted into a corresponding digital signal.
  • the corresponding digital signal is 101010011, and the control end of the target capacitor is controlled according to the binary code to change the clock frequency output by the clock circuit.
  • the clock compensation circuit of the present invention in the lower voltage range, a plurality of comparator circuits are added according to actual precision requirements, and the comparator circuit needs to internally generate some hysteresis voltage to ensure The digital comparator generates a digital signal without turbulence. Since the output clock frequency of the clock circuit is linear with the ambient temperature, according to the actual temperature range, the number of digits of the digital control is designed under the premise of ensuring accuracy; the hysteresis voltage is made inside the comparator circuit to ensure that the comparator generates the number The signal does not create a disorder.
  • the clock compensation circuit detects the capacitance control parameter of the clock frequency that can affect the output of the clock circuit through the detection circuit 10; the control unit 20 adjusts the capacitance circuit according to the capacitance control parameter detected by the detection circuit.
  • the capacitance value of the target capacitor is used to change the clock frequency output by the clock circuit, which solves the problem that the clock frequency of the output of the clock circuit fluctuates greatly in the related art.
  • the capacitance value of the target capacitor in the clock circuit is adjusted according to the capacitance control parameter detected by the detection circuit 10, thereby changing the clock frequency output by the clock circuit, thereby achieving the effect of reducing the fluctuation of the clock frequency output by the clock circuit.
  • FIG. 2 is a structural diagram of a clock circuit in the related art.
  • FIG. 2 shows a block diagram of a chip internal clock circuit of a general structure.
  • a current bias proportional to the reference current source of 1:M is applied to the branches of R trim and R 0 .
  • Fig. 3 is a diagram showing the operation of a clock circuit in the related art. As shown in Figure 3, a voltage offset (V inp + and V inp- ) with a clock transition is applied to one end of the high speed comparator, and the other end is charged and discharged by two switchable current sources.
  • the sawtooth voltage V inn the voltage across the two ends through a high-speed comparator to obtain a square wave clock; since the capacitor resistance obtained during the actual manufacturing process of the chip tends to be 20% larger than the ideal nominal capacitance value and resistance value The deviation causes the actual internal clock circuit to be difficult to achieve high precision without the internal correction circuit, and even if there is an internal correction circuit, it will be generated due to the operating voltage and temperature of the chip. 5% deviation.
  • Fig. 4 is a diagram showing the frequency variation of the clock circuit in the related art in the full voltage range. It can be seen from the actual test results of FIG. 4 that the relationship between the output frequency and the power supply voltage is not a linear relationship, but is rather drastically changed within a range in which the power supply voltage is low. It can be seen in Figure 4 that the output frequency varies by approximately 5% over the full voltage range due to supply voltage variations.
  • Fig. 5 is a diagram showing the frequency variation of the clock circuit in the related art over the entire temperature range. As shown in Figure 5, the output frequency is linear with ambient temperature, and the output frequency variation due to supply voltage variations over the full temperature range is approximately ⁇ 2.5%.
  • FIG. 6 is a structural diagram of a clock circuit according to an embodiment of the present invention.
  • the detection circuit of the present invention is added to the circuit of FIG. 6. Specifically, a voltage sense circuit (Power sense) is added for power supply voltage detection, and an analog signal corresponding to the power supply voltage is converted into a binary code (a digital signal corresponding to the analog signal).
  • the binary code (the digital signal corresponding to the analog signal) is added to the C_trim circuit to control the internal capacitance of the system loop. The size thus adjusts the output frequency of the circuit to achieve automatic compensation of the power supply voltage.
  • FIG. 7 is a schematic diagram of a frequency variation of a clock circuit in a full voltage range according to an embodiment of the present invention; it can be seen from the actual test result of FIG. 7 that the variation is stable in a range of a low power supply voltage, in a full voltage range.
  • the output frequency change due to changes in the supply voltage is approximately ⁇ 0.6%. That is, the power supply voltage is automatically compensated for the clock circuit, thereby adjusting the clock frequency output by the clock circuit, and reducing the fluctuation of the clock frequency output by the clock circuit.
  • another detection circuit in the present invention is further added to the circuit of FIG. 6.
  • a temperature sense circuit is added to convert an analog signal corresponding to an ambient temperature of the environment in which the clock circuit is located.
  • the binary code (the digital signal corresponding to the analog signal) is added to the C_trim circuit by the binary code (the digital signal corresponding to the analog signal), and the internal capacitance of the system loop is controlled to adjust the output frequency of the circuit to achieve automatic compensation of the temperature. Effect.
  • FIG. 8 is a schematic diagram of frequency variation of a clock circuit over a full temperature range according to an embodiment of the present invention. It can be seen from the actual test results of Fig. 8 that the variation is stable over the entire temperature range and can achieve an accuracy of ⁇ 0.6% over the full temperature range. That is, by automatically compensating the temperature of the clock circuit, the clock frequency output by the clock circuit is adjusted, and the fluctuation of the clock frequency output by the clock circuit is reduced.
  • the embodiment of the present invention further provides a clock circuit including a target capacitor capable of changing a clock frequency output by the clock circuit and any clock compensation circuit provided by the embodiment of the present invention.
  • the clock circuit of any clock compensation circuit provided by the invention adjusts the clock frequency output by the clock circuit, thereby reducing the fluctuation of the clock frequency, thereby achieving the effect of reducing the deviation of the precision of the microcontroller, thereby achieving the reduction.
  • clock compensation circuit included in the above-mentioned clock circuit is the same as or similar to the clock compensation circuit in the above embodiment, and the specific content or function involved is not described in detail in the above embodiments.
  • the embodiment of the invention further provides a microcontroller, which comprises a clock circuit provided by an embodiment of the invention.
  • the micro-controller provided by the invention adjusts the clock frequency outputted by the clock circuit, thereby reducing the fluctuation of the clock frequency outputted by the clock circuit, and ensuring the precision deviation of the chip including the microcontroller.
  • the modules described as separate components may or may not be physically separated.
  • the components displayed as modules may or may not be physical modules, that is, may be located in one place, or may be distributed to multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules.
  • modules of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device, or they may be fabricated into individual integrated circuit modules, or multiple of them Modules or steps are made in a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software.

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Abstract

本发明公开了一种时钟补偿电路、时钟电路和微控制器。其中，该时钟补偿电路包括：检测电路，用于检测能够影响时钟电路输出的时钟频率的电容控制参数；控制单元，连接至检测电路，用于根据检测电路检测到的电容调节所述时钟电路中的目标电容的电容值，以改变所述时钟电路输出的时钟频率。通过本发明，解决了相关技术中时钟电路输出的时钟频率波动较大的问题。

Description

时钟补偿电路、时钟电路和微控制器 技术领域
本发明涉及电路设计领域，具体而言，涉及一种时钟补偿电路、时钟电路和微控制器。
背景技术
时钟作为微控制器中重要的一个模块，较高的精度和较宽的电源工作范围对于提高整个芯片的性能具有较为重要的意义。通常，RC时钟由于其结构较为简单，在集成电路中被广泛应用。但是RC时钟精度往往受内部电阻、电容的精度以及电源和温度所限，不能在全温度全电压下达到非常高的精度。在实际的应用中，时钟在全温度范围和全电压范围内的频率波动对芯片精度造成的偏差甚至达到了±2％。因此，相关技术中由于时钟所处的环境温度和电源电压大范围波动造成频率时钟波动，进而引起微控制器精度产生较大偏差。
针对相关技术中时钟电路输出的时钟频率波动较大的问题，目前尚未提出有效的解决方案。
发明内容
本发明的主要目的在于提供一种时钟补偿电路、时钟电路和微控制器，以解决相关技术中时钟电路输出的时钟频率波动较大的问题。
为了实现上述目的，根据本发明的一个方面，提供了一种时钟补偿电路。该时钟补偿电路包括：
检测电路，用于检测能够影响时钟电路输出的时钟频率的电容控制参数；
控制单元，连接至所述检测电路，用于根据所述检测电路检测到的所述电容控制参数调节所述时钟电路中的目标电容的电容值，以改变所述时钟电路输出的时钟频率。
进一步地，该检测电路包括：电压检测电路，用于检测时钟电路的电源电压作为电容控制参数。
进一步地，该控制单元包括：第一转换模块，用于将电压检测电路检测到的电源电压对应的模拟信号转化为第一数字信号；第一传输模块，用于将第一数字信号输入 目标电容的控制端；以及第一控制模块，用于通过第一数字信号调整目标电容的电容值，以改变时钟电路输出的时钟频率。
进一步地，该检测电路还包括：温度检测电路，用于检测时钟电路所处环境的环境温度作为电容控制参数。
进一步地，该控制单元还包括：第二转换模块，用于将温度检测电路检测到的环境温度对应的模拟信号转化为第二数字信号；第二传输模块，用于将第二数字信号输入目标电容的控制端；以及第二控制模块，用于通过第二数字信号调整目标电容的电容值，以改变时钟电路输出的时钟频率。
进一步地，该第二控制模块包括：第一比较子模块，用于将检测到的环境温度与预设温度进行数值比较；第一调节子模块，用于在比较出环境温度小于预设温度的情况下，通过第二数字信号将目标电容的电容值调小至第一目标电容值；第二调节子模块，用于在比较出环境温度大于预设温度的情况下，通过第二数字信号将目标电容的电容值调大至第二目标电容值。
进一步地，该第一控制模块包括：第二比较子模块，用于将电源电压与预设电压进行数值比较；第三调节子模块，用于在比较出电源电压小于预设电压的情况下，通过第一数字信号将目标电容的电容值调小至第三目标电容值；第四调节子模块，用于在比较出电源电压大于预设电压的情况下，通过第一数字信号将目标电容的电容值调大至第四目标电容值。
进一步地，该检测电路还包括：比较器电路，设置在检测电路中，用于对检测电路检测到的电容控制参数进行模数转化处理，以转化为对应的数字信号，其中，控制单元具体用于根据对应的数字信号对目标电容的电容值进行调整，以改变时钟电路输出的时钟频率。
为了实现上述目的，根据本发明的另一方面，提供了一种时钟电路，包括能够改变所述时钟电路输出的时钟频率的目标电容和上述时钟补偿电路。
为了实现上述目的，根据本发明的另一方面，提供了一种微控制器，包括该时钟电路。
基于本发明上述任一实施方案，通过对控制时钟电路输出的时钟频率的目标电容的电容控制参数的检测和目标电容的电容值的调整，实现时钟电路输出的时钟频率调整，进而使本发明的时钟补偿电路能够根据需要对时钟电路进行补偿，以减小时钟电 路输出的时钟频率波动。
附图说明
构成本发明的一部分的附图用来提供对本发明的进一步理解，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是根据本发明实施例提供的时钟补偿电路的示意图；
图2是相关技术中的时钟电路的结构图；
图3是相关技术中的时钟电路的工作原理图；
图4是相关技术中的时钟电路在全电压范围内的频率变化的示意图；
图5是相关技术中的时钟电路在全温度范围内的频率变化的示意图；
图6是根据本发明实施例提供的时钟电路的结构图；
图7是根据本发明实施例提供的时钟电路在全电压范围内的频率变化的示意图；
图8是根据本发明实施例提供的时钟电路在全温度范围内的频率变化的示意图。
具体实施方式
需要说明的是，在不冲突的情况下，本发明中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本发明。
为了使本技术领域的人员更好地理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
需要说明的是，本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、产品或设备固有的其它步骤或单元。
根据本发明的实施例，提供了一种时钟补偿电路。
图1是根据本发明实施例提供的时钟补偿电路的示意图。如图1所示，该时钟补偿电路包括以下结构：
检测电路10，用于检测能够影响时钟电路输出的时钟频率的电容控制参数。
在本发明中，通过时钟补偿电路中的检测电路10检测能够影响时钟电路输出的时钟频率的电容控制参数。在本发明中，目标电容设置在时钟电路中，其电容值可调，通过输入到目标电容的控制端的数字信号能够实现对时钟电路输出的时钟频率的改变。
控制单元20，连接至检测电路10，用于根据检测电路10检测到的电容控制参数调节目标电容的电容值，以改变时钟电路输出的时钟频率。
时钟补偿电路中的与检测电路10相连的控制单元20，能够根据检测电路10检测到的电容控制参数调整目标电容的电容值，从而改变时钟电路输出的时钟频率。
通过本发明中的时钟补偿电路中的检测电路10和控制单元20，能够根据需要对时钟电路进行补偿，从而改变时钟电路输出的时钟频率，减小了时钟电路输出的时钟频率的波动。
可选地，在本发明实施例提供的时钟补偿电路中，该检测电路10包括：电压检测电路10，用于检测时钟电路的电源电压作为电容控制参数。
具体地，电源电压为电容控制参数时，在本发明实施例提供的时钟补偿电路的检测电路10中，包括用于检测时钟电路的电源电压的电压检测电路。检测电路10中的电压检测电路检测到时钟电路的电源电压，根据该电源电压调整目标电容的电容值，以改变时钟电路输出的时钟频率。
可选地，在本发明实施例提供的时钟补偿电路中，该控制单元20包括：第一转换模块，用于将检测电路10(具体为电压检测电路)检测到的电源电压对应的模拟信号转化为第一数字信号；第一传输模块，用于将第一数字信号输入目标电容的控制端；以及第一控制模块，用于通过第一数字信号控制目标电容的电容值，以改变时钟电路输出的时钟频率。
例如，检测电路10检测时钟电路的电源电压为5.3V。第一转换模块将电压检测电路检测到的电源电压对应的模拟信号转化为第一数字信号。也即，第一转换模块将5.3V转化为第一数字信号，第一控制模块在目标电容所处的电路中通过第一数字信号控制目标电容的电容值，以改变时钟电路输出的时钟频率。需要说明的是，对于以上 用于举例的数值，只是方便说明，并不代表实际电路运行过程中正常调节的数字。
可选地，在本发明实施例提供的时钟补偿电路中，该第一控制模块包括：第二比较子模块，用于将电源电压与预设电压进行数值比较；第三调节子模块，用于在比较出电源电压小于预设电压的情况下，通过第一数字信号将目标电容的电容值调小至第三目标电容值；第四调节子模块，用于在比较出电源电压大于预设电压的情况下，通过第一数字信号将目标电容的电容值调大至第四目标电容值。
例如，时钟电路运行的电源电压的范围为：2.7V～5.5V，预设电压为5V，第二比较子模块将检测到的电源电压与预设电压进行数值比较，如果检测到的电源电压为4.5V，小于预设电压5V，如果目标电容的电容值为110F，该目标电容的可调范围为50F～550F，在比较出电源电压小于预设电压的情况下，第三调节子模块将目标电容的电容值110F调小至100F。如果检测到的电源电压为5.3V，大于预设电压5V，在比较出电源电压大于预设电压的情况下，第四调节子模块将目标电容的电容值110F调大至130F。需要说明的是，对于以上用于举例的数值，只是方便说明，并不代表实际电路运行过程中正常调节的数字。
可选地，在本发明实施例提供的时钟补偿电路中，该检测电路10还包括：温度检测电路，用于检测时钟电路所处环境的环境温度作为电容控制参数。
具体地，环境温度为电容控制参数时，在本发明实施例提供的时钟补偿电路的检测电路10中包括检测时钟电路所处环境的环境温度的温度检测电路。控制单元根据温度检测电路检测到的时钟电路所处环境的环境温度控制目标电容，以改变时钟电路输出的时钟频率。
可选地，在本发明实施例提供的时钟补偿电路中，该控制单元20还包括：第二转换模块，用于将检测电路10检测到的环境温度对应的模拟信号转化为第二数字信号；第二传输模块，用于将第二数字信号输入目标电容的控制端；以及第二控制模块，用于通过第二数字信号控制目标电容的电容值，以改变时钟电路输出的时钟频率。
需要说明的是，在本发明的该实施例中，预先建立了环境温度与电压值之间的映射关系，例如，检测电路10检测时钟电路所处环境的环境温度为25℃，环境温度25℃对应电压值为5V，检测电路10检测时钟电路所处环境的环境温度为26摄氏度，环境温度26℃对应电压值为5.1V等等。因此，温度检测电路检测到的环境温度对应的模拟信号具体是：温度检测电路检测到的环境温度对应的电压值所对应的模拟信号。也 即，第二转换模块将温度检测电路检测到的环境温度对应的电压值对应的模拟信号转化为第二数字信号，第二控制模块通过第二数字信号调整目标电容的电容值，以改变时钟电路输出的时钟频率。需要说明的是，对于以上用于举例的数值，只是举例说明，并不代表实际电路运行过程中正常调节的数字，只是对于本发明中的技术进行举例说明。
可选地，在本发明实施例提供的时钟补偿电路中，该第二控制模块包括：第一比较子模块，用于将检测到的环境温度与预设温度进行数值比较；第一调节子模块，用于在比较出环境温度小于预设温度的情况下，通过第二数字信号将目标电容的电容值调小至第一目标电容值；第二调节子模块，用于在比较出环境温度大于预设温度的情况下，通过第二数字信号将目标电容的电容值调大至第二目标电容值。
例如，时钟电路所处环境的环境温度的温度范围为：-40℃～125℃，预设温度为25℃，第一比较子模块将检测到的温度与预设温度进行数值比较，如果检测到环境温度为15℃，小于预设温度为25℃，如果目标电容的可调范围为50F～550F，目标电容的电容值为110F，在比较出温度小于预设电压的情况下，第一调节子模块将目标电容的电容值110F调小至100F。如果检测到环境温度为27℃，大于预设温度为25℃，在比较出温度大于预设电压的情况下，第二调节子模块将目标电容的电容值110F调大至130F。需要说明的是，对于以上用于举例的数值，只是方便说明，并不代表实际电路运行过程中正常调节的数字。
可选地，在本发明实施例提供的时钟补偿电路中，该检测电路10还包括：比较器电路，设置在检测电路10中，用于将检测电路10检测到的电容控制参数进行模数转化处理，以转化为对应的数字信号，其中，控制单元20具体用于根据对应的数字信号对目标电容进行控制，以调节时钟电路输出的时钟频率。
本发明中比较器电路的比较器，根据正相输入端的电位高于反相输入端，输出高电平；反相输入端的电位高于正相输入端，输出低电平的自身特性，将检测电路10检测到的电容控制参数对应的模拟信号，转化为对应的数字信号。例如，对应的数字信号为101010011，根据该二进制编码对目标电容的控制端进行控制，以改变时钟电路输出的时钟频率。
需要说明的是，在本发明的时钟补偿电路的结构中，在较低电压范围内，根据实际的精度要求，增加若干个比较器电路，而且比较器电路需要内部做些迟滞电压，保 证比较器产生数字信号不会产生紊乱。由于时钟电路的输出时钟频率与环境温度是线性关系，根据实际的温度范围，在保证精度的前提下，设计数字控制的位数；在比较器电路内部做些迟滞电压，从而保证比较器产生数字信号不会产生紊乱。
本发明实施例提供的时钟补偿电路，通过检测电路10检测能够影响时钟电路输出的时钟频率的电容控制参数；控制单元20根据所述检测电路检测到的所述电容控制参数调节所述时钟电路中的目标电容的电容值，以改变所述时钟电路输出的时钟频率，解决了相关技术中时钟电路输出的时钟频率波动较大的问题。根据检测电路10检测到的电容控制参数调整时钟电路中的目标电容的电容值，从而改变时钟电路输出的时钟频率，进而达到了减小时钟电路输出的时钟频率的波动的效果。
下面以对比描述进行说明。图2是相关技术中的时钟电路的结构图。如图2所示，图2中展示了一通用结构的芯片内部时钟电路结构图。一个与基准电流源呈1∶M正比的电流偏置加在Rtrim和R0的支路上。图3是相关技术中的时钟电路的工作原理图。如图3所示，产生一个随着时钟跳变的电压偏置(Vinp+和Vinp-)给到高速比较器的一端，另一端是通过两个可以切换的电流源给电容充放电得到一个锯齿波电压Vinn，两端电压通过高速比较器最后得到一个方波时钟；由于在芯片实际制造的过程中得到的电容电阻往往比理想标称的电容值和电阻值可能最大会有20％的偏差，导致实际做出来的内部时钟电路在没有内部校正电路的基础上很难达到很高的精度，而且即使有内部校正电路的存在，也会由于芯片所处的工作电压以及温度不同而产生大约5％的偏差。
图4是相关技术中的时钟电路在全电压范围内的频率变化的示意图。通过图4的实际测试结果中可以看出输出频率与电源电压的关系并不是直线关系，而是在电源电压较低的范围内变化较为剧烈。在图4中可以看出在全电压范围由于电源电压变化造成的输出频率变化大约为5％。
图5是相关技术中的时钟电路在全温度范围内的频率变化的示意图。如图5所示，输出频率与环境温度是线性关系，在全温度范围内由于电源电压变化造成的输出频率变化大约为±2.5％。
图6是根据本发明实施例提供的时钟电路的结构图。图6的电路中增加了本发明中的检测电路，具体地，增添了电压检测电路(Power sense)进行电源电压检测，将电源电压对应的模拟信号转化成二进制编码(模拟信号对应的数字信号)，将二进制编码(模拟信号对应的数字信号)加在C_trim电路上，控制连接在系统环路内部电容 大小从而调节电路输出频率，达到对电源电压自动补偿的效果。
根据包括电压检测电路(Power sense)的时钟电路进行检测，得到结果如图7所示。图7是根据本发明实施例提供的时钟电路在全电压范围内的频率变化的示意图；通过图7的实际测试结果可以看出，在电源电压较低的范围内变化较为稳定，在全电压范围由于电源电压变化造成的输出频率变化大约为±0.6％。也即，对时钟电路进行电源电压自动补偿，从而调节时钟电路输出的时钟频率，减小了时钟电路输出的时钟频率的波动。
可选的，在图6的电路中还增加了本发明中的另一种检测电路，具体地，增添了温度检测电路(Temperature sense)，将时钟电路所处环境的环境温度对应的模拟信号转化成二进制编码(模拟信号对应的数字信号)，将二进制编码(模拟信号对应的数字信号)加在C_trim电路上，控制连接在系统环路内部电容大小从而调节电路输出频率，达到对温度的自动补偿的效果。
根据包括温度检测电路(Temperature sense)的时钟电路进行检测，得到结果如图8所示。图8是根据本发明实施例提供的时钟电路在全温度范围内的频率变化的示意图。通过图8的实际测试结果可以看出，在全温度范围内变化较为稳定，在全温度范围之内能够达到±0.6％的精度。也即，通过对时钟电路进行温度进行自动补偿，从而调节时钟电路输出的时钟频率，减小了时钟电路输出的时钟频率的波动。
本发明实施例还提供了一种时钟电路，该时钟电路包括能够改变所述时钟电路输出的时钟频率的目标电容和本发明实施例提供的任意一种时钟补偿电路。本发明提供的任意一种时钟补偿电路的时钟电路，根据调节时钟电路输出的时钟频率，从而减小了时钟频率的波动，进而达到了减小微控制器精度的偏差的效果，进而达到了减小时钟电路输出的时钟频率的波动的效果。
需要说明的是，上述的时钟电路中包含的时钟补偿电路与上述实施例中的时钟补偿电路相同或类似，涉及的具体内容或功能在上述实施例中详细阐述，在此不再赘述。
本发明实施例还提供了一种微控制器，该微控制器包括本发明实施例提供的时钟电路。本发明提供的微控制器，根据调节时钟电路输出的时钟频率，从而减小了时钟电路输出的时钟频率的波动，保证了包含微控制器的芯片的精度偏差。
需要说明的是，对于前述的实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本发明并不受所描述的动作顺序的限制，因 为依据本发明，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本发明所必须的。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
显然，本领域的技术人员应该明白，上述的本发明的各模块可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的优选实施例，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种时钟补偿电路，其特征在于，包括：
    检测电路，用于检测能够影响时钟电路输出的时钟频率的电容控制参数；
    控制单元，连接至所述检测电路，用于根据所述检测电路检测到的所述电容控制参数调节所述时钟电路中的目标电容的电容值，以改变所述时钟电路输出的时钟频率。
  2. 根据权利要求1所述的电路，其特征在于，所述检测电路包括：
    电压检测电路，用于检测所述时钟电路的电源电压作为所述电容控制参数。
  3. 根据权利要求2所述的电路，其特征在于，所述控制单元包括：
    第一转换模块，用于将所述电压检测电路检测到的所述电源电压对应的模拟信号转化为第一数字信号；
    第一传输模块，用于将所述第一数字信号输入所述目标电容的控制端；以及
    第一控制模块，用于通过所述第一数字信号调整所述目标电容的电容值，以改变所述时钟电路输出的时钟频率。
  4. 根据权利要求1或2所述的电路，其特征在于，所述检测电路还包括：
    温度检测电路，用于检测所述时钟电路所处环境的环境温度作为所述电容控制参数。
  5. 根据权利要求4所述的电路，其特征在于，所述控制单元还包括：
    第二转换模块，用于将所述温度检测电路检测到的所述环境温度对应的模拟信号转化为第二数字信号；
    第二传输模块，用于将所述第二数字信号输入所述目标电容的控制端；以及
    第二控制模块，用于通过所述第二数字信号调整所述目标电容的电容值，以改变所述时钟电路输出的时钟频率。
  6. 根据权利要求5所述的电路，其特征在于，所述第二控制模块包括：
    第一比较子模块，用于将检测到的所述环境温度与预设温度进行数值比较；
    第一调节子模块，用于在比较出所述环境温度小于所述预设温度的情况下，通过所述第二数字信号将所述目标电容的电容值调小至第一目标电容值；
    第二调节子模块，用于在比较出所述环境温度大于所述预设温度的情况下，通过所述第二数字信号将所述目标电容的电容值调大至第二目标电容值。
  7. 根据权利要求3所述的电路，其特征在于，所述第一控制模块包括：
    第二比较子模块，用于将所述电源电压与预设电压进行数值比较；
    第三调节子模块，用于在比较出所述电源电压小于所述预设电压的情况下，通过所述第一数字信号将所述目标电容的电容值调小至第三目标电容值；
    第四调节子模块，用于在比较出所述电源电压大于所述预设电压的情况下，通过所述第一数字信号将所述目标电容的电容值调大至第四目标电容值。
  8. 根据权利要求1所述的电路，其特征在于，所述检测电路还包括：
    比较器电路，设置在所述检测电路中，用于对所述检测电路检测到的电容控制参数进行模数转化处理，以转化为对应的数字信号，
    其中，所述控制单元具体用于根据所述对应的数字信号对所述目标电容的电容值进行调整，以改变所述时钟电路输出的时钟频率。
  9. 一种时钟电路，其特征在于，包括：能够改变所述时钟电路输出的时钟频率的目标电容和权利要求1所述的时钟补偿电路。
  10. 一种微控制器，其特征在于，包括：权利要求9中所述的时钟电路。
PCT/CN2017/092482 2016-11-18 2017-07-11 时钟补偿电路、时钟电路和微控制器 WO2018090650A1 (zh)

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