WO2018090627A1 - 数据线多路分配器、显示基板、显示面板及显示装置 - Google Patents

数据线多路分配器、显示基板、显示面板及显示装置 Download PDF

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Publication number
WO2018090627A1
WO2018090627A1 PCT/CN2017/089744 CN2017089744W WO2018090627A1 WO 2018090627 A1 WO2018090627 A1 WO 2018090627A1 CN 2017089744 W CN2017089744 W CN 2017089744W WO 2018090627 A1 WO2018090627 A1 WO 2018090627A1
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sub
pixels
columns
transistors
data line
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PCT/CN2017/089744
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English (en)
French (fr)
Inventor
程鸿飞
李盼
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京东方科技集团股份有限公司
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Priority to EP17826124.4A priority Critical patent/EP3543988A4/en
Priority to US15/745,163 priority patent/US10643516B2/en
Publication of WO2018090627A1 publication Critical patent/WO2018090627A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0823—Several active elements per pixel in active matrix panels used to establish symmetry in driving, e.g. with polarity inversion
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0235—Field-sequential colour display
    • G—PHYSICS
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a data line demultiplexer, a display substrate, a display panel, and a display device.
  • the data line demultiplexer is a device in the display device for distributing data signals supplied from the source driving circuit to respective sub-pixels in the pixel unit.
  • the data line demultiplexer generally includes three switch signal terminals SW1 to SW3, m data signal terminals D1 to Dm, and 3 ⁇ m. Transistor. Additionally, the display device can also include a gate drive circuit for providing a gate drive signal to each of the sub-pixels in each of the pixel cells.
  • each transistor is connected to a column of sub-pixels, and each switching signal terminal is connected to a gate of a transistor for driving a sub-pixel of one color, for example, a switching signal terminal SW1 and a driving sub-pixel for driving a red sub-pixel
  • the switching signal terminal SW2 is connected to the gates of the transistors for driving the green sub-pixels
  • each of the data signal terminals is respectively connected to the sources of three adjacent transistors, and the three adjacent transistors are connected
  • the sub-pixels connected to the drain belong to the same pixel unit.
  • the display device is driven by column inversion
  • the switch signal terminal SW1 inputs a high voltage to drive the red sub-pixel
  • the data signal input by each data signal terminal may be a positive polarity voltage
  • the switch signal terminal SW2 inputs a high voltage.
  • the data signal input by each data signal end needs to jump to the negative polarity voltage; further, when driving the blue sub-pixel, the data signal input by each data signal end needs to jump to the positive pole again. Sex voltage.
  • the voltage polarity of the data signal outputted by each data signal terminal needs to be continuously inverted, and the power consumption of the display device is high.
  • the present disclosure provides a data line demultiplexer, a display substrate, a display panel, and a display device.
  • the technical solution is as follows:
  • a data line demultiplexer comprising: a switch module, a plurality of switch signal ends, and a plurality of data signal ends;
  • the switch module is respectively connected to the plurality of switch signal terminals, the plurality of data signal terminals, and the M column pixel units in the display device, wherein each column of the pixel units includes N columns of sub-pixels of different colors.
  • M is a positive integer
  • N is an integer greater than 1;
  • the switch module is capable of communicating each of the data signal ends with at least two columns of sub-pixels under control of the plurality of switch signal terminals, wherein two adjacent columns of the at least two columns of sub-pixels are in the The number of spaced columns in the display device is an odd number of sub-pixels.
  • two adjacent columns of sub-pixels of the at least two columns of sub-pixels are spaced apart by a column of sub-pixels in the display device.
  • the data line demultiplexer includes N switch signal terminals.
  • the data line demultiplexer includes M data signal terminals.
  • the switch module is capable of respectively connecting each of the data signal ends and the N columns of sub-pixels under the control of the plurality of switch signal terminals.
  • the switch module includes: k transistors, wherein k is a number of columns of sub-pixels in the display device;
  • each of the k transistors is connected to a switching signal terminal, the first pole is connected to a data signal terminal, and the second pole is connected to a column of sub-pixels.
  • the k transistors can be divided into N groups, each group including M transistors;
  • the gates of the M transistors in each group are connected to the same switching signal terminal, and the M columns of sub-pixels connected to the second poles of the M transistors in each group are sub-pixels of the same color.
  • the data line demultiplexer includes N switch signal terminals;
  • the switching signal terminals connected to the gates of any two sets of transistors are different, and the sub-pixels to which the second poles of any two sets of transistors are connected have different colors.
  • the data line demultiplexer includes M data signal terminals
  • Each of the data signal terminals is respectively connected to a first pole of the N transistors of the k transistors, and two adjacent ones of the N transistors are spaced apart by one transistor in the data line demultiplexer;
  • the second pole of the i-th transistor of the k transistors is connected to the i-th column sub-pixel, and the i is a positive integer equal to or less than k.
  • the data line demultiplexer includes M data signal terminals
  • Each of the data signal terminals is respectively connected to a first pole of N adjacent ones of the k transistors;
  • two adjacent columns of sub-pixels are spaced apart by one column of sub-pixels in the display device.
  • each column of the pixel unit includes three columns of sub-pixels of different colors
  • the data line demultiplexer includes three switch signal terminals.
  • the k transistors are all N-type transistors.
  • a display substrate comprising:
  • a data line demultiplexer as described in the first aspect is described.
  • a display panel comprising:
  • a display substrate as described in the second aspect is described.
  • a display device comprising:
  • a display panel as described in the third aspect is described.
  • a fifth aspect provides a driving method of a data line demultiplexer, where the data line demultiplexer includes a switch module, a plurality of switch signal ends, and a plurality of data signal ends, wherein the switch modules respectively a plurality of switching signal terminals, the plurality of data signal terminals are connected to the M columns of pixel units in the display device, wherein each column of the pixel units includes N columns of sub-pixels of different colors, and the M is a positive integer, N is an integer greater than 1, the switch module is capable of communicating each of the data signal ends with at least two columns of sub-pixels under control of the plurality of switch signal terminals, adjacent to the at least two columns of sub-pixels The number of spaced columns of the two columns of sub-pixels in the display device is an odd number of sub-pixels, and the driving method includes: during a display process of the image of the frame, the plurality of switch signal terminals are sequentially outputted into the switch module a corresponding transistor-on voltage signal, the voltage polarity of
  • the plurality of switch signal terminals sequentially output voltage signals that turn on respective ones of the switch modules.
  • two adjacent columns of sub-pixels of the at least two columns of sub-pixels are spaced apart by a column of sub-pixels in the display device.
  • the switch module includes: k transistors, the k is a number of columns of sub-pixels in the display device, and a gate of each of the k transistors is connected to a switch signal end, The first pole is connected to a data signal end, and the second pole is connected to a column of sub-pixels.
  • the k transistors can be divided into N groups, each group including M transistors, and the gates of the M transistors in each group are connected to the same switching signal terminal, and the M transistors in each group are The M columns of subpixels connected to the two poles are sub-pixels of the same color.
  • the switch module is capable of connecting each data signal end with at least two columns of sub-pixels under the control of a plurality of switch signal terminals, and adjacent to at least two columns of sub-pixels
  • the two columns of sub-pixels have an odd number of sub-pixels in the display device. Since in the column inversion driving process, the number of the spaced columns is the same as the polarity of the two columns of sub-pixels, each data signal end does not need to invert the data signal when driving at least two columns of sub-pixels to which it communicates.
  • the column polarity can be driven by the voltage polarity, and the power consumption of the display device during the driving process is low.
  • FIG. 1 is a schematic structural diagram of a data line demultiplexer in the related art
  • FIG. 2 is a schematic structural diagram of a data line demultiplexer according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another data line demultiplexer according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another data line demultiplexer according to an embodiment of the present disclosure.
  • FIG. 5 is a driving sequence diagram of a data line demultiplexer according to an embodiment of the present disclosure.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other devices having the same characteristics.
  • the transistors employed in the embodiments of the present disclosure are primarily switching transistors in accordance with their role in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as a first stage and the drain is referred to as a second stage. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor used in the embodiment of the present disclosure includes two types of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low voltage, and is turned off when the gate is at a high voltage, and the N-type switch is turned off. The transistor is turned on when the gate is at a high voltage and turned off when the gate is at a low voltage.
  • the data line demultiplexer 1 is a schematic structural view of a data line demultiplexer in the related art.
  • the data line demultiplexer 1 generally includes three switch signal terminals SW1 to SW3, m data signal terminals D1 to Dm, and 3 ⁇ m transistors.
  • the display device may further include a gate driving circuit 2 for supplying a gate driving signal to each sub-pixel in each pixel unit.
  • the present disclosure provides a data line demultiplexer 10.
  • the data line demultiplexer 10 can include a switch module 10, a plurality of switch signal terminals, and a plurality of data signal terminals.
  • the data line demultiplexer includes three switch signal terminals SW1, SW2, and SW3, and M data signal terminals D1, D2 through Dm.
  • the switch module 10 is respectively connected to the plurality of switch signal terminals, the plurality of data signal terminals, and the M column pixel units in the display device, wherein each column of the pixel units may include N columns of sub-pixels of different colors, where the M is A positive integer, which is an integer greater than one.
  • the switch module 10 is capable of communicating each data signal end with at least two columns of sub-pixels under control of the plurality of switch signal terminals, and adjacent two columns of sub-pixels of the at least two columns of sub-pixels are spaced apart in the display device The number is an odd number of subpixels.
  • the adjacent two columns of sub-pixels refer to two columns of sub-pixels that are connected to the same data signal end and are closely spaced.
  • the data signal terminal D1 can be connected to the three columns of sub-pixels R1, B1 and G2 through the switch module 10, respectively.
  • the sub-pixels R1 and B1 are spaced closest to each other, and are adjacent two columns of sub-pixels, and the adjacent two columns of sub-pixels R1 and B1 are spaced apart by a column of sub-pixels G1 in the display device;
  • Two columns of adjacent sub-pixels B1 and G2 are spaced apart by a column of sub-pixels R2 in the display device.
  • the data signal terminal D1 connected to the three columns of sub-pixels can be driven in the column inversion driving process.
  • the voltage polarity of the output data signal remains unchanged.
  • the voltage polarity is relative to the common voltage. When the signal voltage is higher than the common voltage, the signal voltage is said to be a positive polarity voltage; when the signal voltage is lower than the common voltage, the signal voltage is said to be a negative polarity voltage.
  • the switch module can connect each data signal end with at least two columns of sub-pixels under the control of a plurality of switch signal ends, the at least two columns.
  • the adjacent two columns of sub-pixels in the sub-pixel have an odd number of sub-pixels in the display device. Since the polarity of the two columns of sub-pixels having the odd number of spaced columns is the same in the column inversion driving process, each data signal end does not need to invert the data signal when driving at least two columns of sub-pixels that it communicates with.
  • the column polarity can be driven by the voltage polarity, and the power consumption of the display device during the driving process is low.
  • adjacent two columns of sub-pixels may be spaced apart by only one column of sub-pixels in the display device.
  • the adjacent two columns of sub-pixels R1 and B1 may be separated by only one column of sub-pixels G1.
  • Only one column of sub-pixels R2 may be spaced between adjacent two columns of sub-pixels B1 and G2.
  • the switch distributor may include three switch signal terminals SW1, SW2, and SW3.
  • the data line demultiplexer 10 may include M data signal terminals. That is, the number M of data signal terminals in the data line demultiplexer 10 may be the same as the number of columns of pixel units included in the display device.
  • the switch module 10 can respectively connect each data signal end with the N columns of sub-pixels under the control of the plurality of switch signal ends.
  • each pixel unit includes three sub-pixels, and the switch module 10 can connect each data signal end with three columns of sub-pixels, such as data signal terminal D1 and R1 column sub-pixel, respectively.
  • the column sub-pixel is connected to the G2 column sub-pixel; and in the data line demultiplexer 20 shown in FIG. 3, since each pixel unit includes only 2 sub-pixels, the switch module 10 can connect each data signal end with 2 columns of sub-pixels connected, for example, the data signal terminal D1 can be connected to the R1 column sub-pixel and the R2 column sub-pixel, respectively, and the data signal end D2 is connected to the G1 column sub-pixel and the G2 column sub-pixel, respectively.
  • each of the k transistors is connected to a switching signal terminal, the first pole is connected to a data signal terminal, and the second pole is connected to a column of sub-pixels.
  • the gate of the transistor T1 is connected to the switching signal terminal SW1
  • the first pole is connected to the data signal terminal D1
  • the second pole is connected to the sub-pixel column R1.
  • the k transistors can be divided into N groups, each of which includes M transistors.
  • the gates of the M transistors in each group are connected to the same switching signal terminal, and the M columns of sub-pixels connected to the second poles of the M transistors in each group are sub-pixels of the same color.
  • the data line demultiplexer includes N switch signal terminals; the switch signal terminals connected to the gates of any two sets of transistors are different, and the color of the sub-pixels connected to the second poles of any two sets of transistors different. That is, each switching signal terminal controls only sub-pixels of one color, and the sub-pixels of N colors are controlled by the N switching signal terminals.
  • the k transistors can be divided into three groups, wherein the first group can include M transistors such as T1, T4 to Tk-2, and the second group can include M2 such as T2, T5 to Tk-1, and the like.
  • the third group of transistors may include M transistors such as T3, T6 to Tk.
  • the gates of the M transistors in the first group are connected to the switch signal terminal SW1, and the second poles are connected to the red sub-pixels, and the switch signal terminal SW1 can pass through the M transistors of the first group. Controlling all red sub-pixels; the gates of the M transistors in the second group are connected to the switch signal terminal SW2, and the second poles are connected to the green sub-pixels, and the switch signal terminal SW2 can pass through the second group M transistors implement control of all green sub-pixels; the gates of M transistors in the third group are connected to the switching signal terminal SW3, and the second poles are connected to the blue sub-pixels, and the switching signal terminal SW3 can pass the The third set of M transistors implements control of all blue sub-pixels.
  • the data line demultiplexer 10 may include M data signal terminals.
  • each data signal end is respectively connected to a first pole of the N transistors of the k transistors, and two adjacent ones of the N transistors are spaced apart by one transistor in the data line demultiplexer 10;
  • the second pole of the ith transistor of the transistors is connected to the i-th column sub-pixel, which is a positive integer less than or equal to k.
  • the two adjacent transistors refer to the two transistors with the closest interval among the N transistors connected to the same data signal terminal.
  • the data signal terminal D1 is respectively connected to the first poles of the three transistors T1, T3, and T5, and the transistors T1 and T3 are the closest to each other, which are adjacent two transistors.
  • Two adjacent transistors T1 and T3 are spaced apart by a transistor T2 in the data line demultiplexer 10, and two other adjacent transistors T3 and T5 of the three transistors are spaced apart in the data line demultiplexer 10.
  • a transistor T4 it can also be seen from FIG. 2 that the second poles of the k transistors are sequentially associated with the corresponding sub-pixel columns.
  • the second pole of the first transistor T1 is connected to the first column sub-pixel R1, and the second pole of the second transistor T2 is connected to the second column sub-pixel B1.
  • the data line demultiplexer 30 may include M data signal terminals.
  • each of the data signal terminals is respectively connected to a first pole of N adjacent ones of the k transistors; and an adjacent two of the N columns of subpixels connected to the second pole of the N adjacent transistors
  • the column subpixels are spaced apart by a column of subpixels in the display device.
  • the data signal terminals D1 are respectively connected to the first poles of three adjacent transistors T1, T2 and T3, wherein the sub-pixels connected to the second pole of the transistor T1 are R1 column sub-pixels, and the transistor T2
  • the sub-pixels connected to the second pole are G2 column sub-pixels
  • the sub-pixels connected to the second pole of T3 are B1 column sub-pixels.
  • the three columns of sub-pixels R1, B1 and G2 two adjacent columns of sub-pixels R1 and B1 are spaced apart by one column of sub-pixels G1 in the display device, and two other columns of adjacent sub-pixels B1 and G2 are spaced apart in the display device.
  • the voltages stored in the sub-pixels in the same column are the same in the driving process of one frame of image, and the voltages stored in the adjacent two columns of sub-pixels are opposite in polarity.
  • the polarity of the voltage stored in each column of sub-pixels is opposite to the polarity of the previous frame.
  • the voltages of the R1 column sub-pixels and the G1 column sub-pixels are opposite in polarity, and the G1 column sub-pixels and the B1 column sub-pixels have opposite voltage polarities, but the number of the spacer columns is an odd number of sub-pixel poles.
  • the properties are the same, for example, the R1 column sub-pixel, the B1 column sub-pixel, and the G2 column sub-pixel are all positive.
  • the data line demultiplexer shown in any one of FIG. 2 to FIG. 4 is used to provide the data unit to the pixel unit, the sub-pixel column connected by each data signal end is a sub-pixel column arranged at intervals, and the interval is set.
  • the sub-pixel columns have the same polarity. Therefore, when driving in the column inversion mode, the polarity of the data signal outputted by each data signal end can be kept unchanged during the display of one frame of image, for example, can be maintained at all times.
  • the positive polarity voltage or the negative polarity voltage eliminates the need to reverse the voltage polarity, thereby reducing the power consumption of the display device.
  • the k transistors may all be N-type transistors.
  • the k transistors may also be P-type transistors, and the specific types of the transistors are not limited in the embodiments of the present disclosure.
  • the driving process may include three stages in the display of one frame of image.
  • the switching signal outputted by the switching signal terminal SW1 is a high voltage.
  • the first group of transistors T1, T4 to Tk-2 connected to the red sub-pixel are turned on, and the data signal is turned on.
  • the terminals D1 to Dm respectively input data signals to the corresponding sub-pixels through the first group of transistors.
  • the data voltages stored in the R1, B1, G2 to Bk column sub-pixels of the display device need to be positive polarity voltages; and G1, R2, B2 to Gk Leia
  • the data voltage stored by the pixel needs to be a negative voltage.
  • the data signal terminal D1 connected to the sub-pixel of the R1 column and the data signal outputted by the data signal terminal Dm connected to the sub-pixel of the Rk column may be positive polarity voltage.
  • the positive polarity voltage is higher than the common voltage Vcom
  • the voltage of the data signal outputted from the data signal terminal D2 connected to the R2 column sub-pixel may be a negative polarity voltage (the negative polarity voltage is lower than the common voltage Vcom).
  • the switching signal outputted by the switching signal terminal SW2 is a high voltage.
  • the second group of transistors T2, T5 to Tk-1 connected to the green sub-pixel are turned on. Since the display device is driven by the column inversion mode, for the structure shown in FIG. 2 and FIG. 4, referring to FIG. 5, the data signal terminal D1 connected to the sub-pixel of the G2 column and the sub-pixel of the Gk-1 column are connected.
  • the data signal outputted by the data signal terminal Dm can continue to maintain the positive polarity voltage, and the data signal outputted from the data signal terminal D2 connected to the G1 column sub-pixel can continue to maintain the negative polarity voltage.
  • the switching signal output from the switching signal terminal SW3 is a high voltage.
  • the second group of transistors T3, T6 to Tk connected to the blue sub-pixel are turned on.
  • the data signal terminal D1 connected to the B1 column sub-pixel and the data signal outputted from the data signal terminal Dm connected to the Bk column sub-pixel can continue to maintain the positive polarity voltage, and the data signal terminal D2 connected to the B2 column sub-pixel is output.
  • the data signal can continue to maintain a negative polarity voltage.
  • the voltage level of the data signal outputted by each data signal end may change, but the voltage level of the data signal outputted by each data signal end is extremely high.
  • the sex remains the same.
  • the voltage of the data signal outputted from the data signal terminal D1 in FIG. 5 is always positive, and the voltage of the data signal outputted from the data signal terminal D2 is always negative.
  • the data voltages of sub-pixels of different display lines in the same column may also be different, that is, in each stage, the data signal end
  • the voltage of the output data signal can be different, but the polarity is the same.
  • the data signal voltages of the sub-pixels of different display rows in the same column are the same; in the second phase t2, the data signal voltages of the sub-pixels of different display rows in the same column Different; in the third stage t3, the data signal voltages of the sub-pixels of different display lines in the same column are also different.
  • the voltage magnitude of the data signal outputted by each data signal end is not specifically limited in each stage, as long as the voltage polarity of the data signal outputted by each data signal end is maintained during the display of one frame of image. Can be changed.
  • the data line demultiplexer provided by the embodiment of the present disclosure performs column inversion driving on the display device
  • the voltage polarity of the data signal outputted by each data signal end is displayed during the display of one frame of image. It can be kept unchanged at all times, and only when the next frame image is displayed, the voltage polarity of the data signal jumps once, thereby effectively reducing the number of transitions of the data signal voltage polarity and reducing the power consumption of the display device.
  • the switch module can connect each data signal end with at least two columns of sub-pixels under the control of a plurality of switch signal ends, the at least two columns The adjacent two columns of sub-pixels in the pixel have an odd number of sub-pixels in the display device. Due to the column inversion driving process In the middle, the number of the spaced columns is the same, and the polarity of the two columns of sub-pixels is the same. Therefore, when each data signal end drives at least two columns of sub-pixels connected thereto, the column inverse can be realized without inverting the polarity of the data signal. The drive is driven, and the power consumption of the display device during the driving process is low.
  • the embodiment of the present disclosure further provides a display substrate, which may include: a data line demultiplexer as shown in any of FIGS. 2 to 4.
  • the embodiment of the present disclosure further provides a display panel, which may include: a display substrate provided with a data line demultiplexer as shown in any of FIGS. 2 to 4.
  • the embodiment of the present disclosure further provides a display device, where the display device includes: a display panel, and the display substrate in the display panel may include the data line demultiplexer as shown in any one of FIG. 2 to FIG. .
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OkED panel, an AMOkED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device may further include a source driving circuit, and the source driving circuit may be connected to the data signal end of the data line demultiplexer shown in any one of FIG. 2 to FIG. 4 to pass the data.
  • the line demultiplexer provides data signals for each pixel unit in the display device.

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Abstract

一种数据线多路分配器、显示基板、显示面板及显示装置，数据线多路分配器包括：开关模块、多个开关信号端（SW1，SW2，SW3）和多个数据信号端（D1，D2，……，DM）；开关模块能够在该多个开关信号端（SW1，SW2，SW3）的控制下，将每个数据信号端（D1，D2，……，DM）与至少两列亚像素连通，至少两列亚像素中相邻的两列亚像素在显示装置中间隔奇数列亚像素。由于在列反转驱动过程中，间隔奇数列的两列亚像素的极性相同，因此每个数据信号端（D1，D2，……，DM）在驱动其所连通的至少两列亚像素时，无需反转数据信号的电压极性即可实现列反转驱动，驱动过程中显示装置的功耗较低。。

Description

数据线多路分配器、显示基板、显示面板及显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种数据线多路分配器、显示基板、显示面板及显示装置。
背景技术
数据线多路分配器是显示装置中用于将源极驱动电路提供的数据信号分配至像素单元中各个亚像素的器件。
相关技术中，对于每个像素单元包括三种颜色亚像素的显示装置，其数据线多路分配器一般包括三个开关信号端SW1至SW3、m个数据信号端D1至Dm以及3×m个晶体管。另外，该显示装置还可以包括用于向每个像素单元中的各个亚像素提供栅极驱动信号的栅极驱动电路。其中，每个晶体管的漏极与一列亚像素相连，每个开关信号端与用于驱动一种颜色的亚像素的晶体管的栅极相连，例如，开关信号端SW1与用于驱动红色亚像素的晶体管的栅极相连，开关信号端SW2与用于驱动绿色亚像素的晶体管的栅极相连；每个数据信号端分别与三个相邻的晶体管的源极相连，且该三个相邻的晶体管的漏极所连接的亚像素属于同一个像素单元。由此可以实现将m路数据信号分配至3×m列亚像素的功能。
但是，若显示装置采用列反转的方式进行驱动，当开关信号端SW1输入高电压以驱动红色亚像素时，各个数据信号端输入的数据信号可以为正极性电压；开关信号端SW2输入高电压以驱动绿色亚像素时，各个数据信号端输入的数据信号则需要跳变至负极性电压；进一步的，在驱动蓝色亚像素时，该各个数据信号端输入的数据信号需要再次跳变至正极性电压。在该列反转驱动过程中，各数据信号端输出的数据信号的电压极性需要不断反转，显示装置的功耗较高。
发明内容
为了解决相关技术中显示装置功耗较高的问题，本公开提供了一种数据线多路分配器、显示基板、显示面板及显示装置。所述技术方案如下：
第一方面，提供了一种数据线多路分配器，所述数据线多路分配器包括：开关模块、多个开关信号端和多个数据信号端；
所述开关模块分别与所述多个开关信号端、所述多个数据信号端和所述显示装置中的M列像素单元相连，其中，每列所述像素单元包括N列不同颜色的亚像素，所述M为正整数，所述N为大于1的整数；
所述开关模块能够在所述多个开关信号端的控制下，将每个所述数据信号端与至少两列亚像素连通，所述至少两列亚像素中相邻的两列亚像素在所述显示装置中间隔列的数量为奇数的亚像素。
在一个实施例中，所述至少两列亚像素中相邻的两列亚像素在所述显示装置中间隔一列亚像素。
在一个实施例中，所述数据线多路分配器包括N个开关信号端。
在一个实施例中，所述数据线多路分配器包括M个数据信号端。
在一个实施例中，所述开关模块能够在所述多个开关信号端的控制下，将每个所述数据信号端与N列亚像素分别连通。
在一个实施例中，所述开关模块包括：k个晶体管，所述k为所述显示装置中亚像素的列数；
所述k个晶体管中每个晶体管的栅极与一个开关信号端相连，第一极与一个数据信号端相连，第二极与一列亚像素相连。
在一个实施例中，所述k个晶体管能够划分为N组，每组包括M个晶体管；
每组中M个晶体管的栅极与同一个开关信号端相连，且每组中M个晶体管的第二极所连接的M列亚像素为同一种颜色的亚像素。
在一个实施例中，所述数据线多路分配器包括N个开关信号端；
任意两组晶体管的栅极所连接的开关信号端不同，且任意两组晶体管的第二极所连接的亚像素的颜色不同。
在一个实施例中，所述数据线多路分配器包括M个数据信号端；
每个所述数据信号端分别与所述k个晶体管中的N个晶体管的第一极相连，所述N个晶体管中相邻两个晶体管在所述数据线多路分配器中间隔一个晶体管；
所述k个晶体管中第i个晶体管的第二极与第i列亚像素相连，所述i为小于等于k的正整数。
在一个实施例中，所述数据线多路分配器包括M个数据信号端；
每个所述数据信号端分别与所述k个晶体管中N个相邻的晶体管的第一极相连；
所述N个相邻的晶体管的第二极所连接的N列亚像素中，相邻两列亚像素在所述显示装置中间隔一列亚像素。
在一个实施例中，每列所述像素单元包括3列不同颜色的亚像素；
所述数据线多路分配器包括3个开关信号端。
在一个实施例中，所述k个晶体管均为N型晶体管。
第二方面，提供了一种显示基板，所述显示基板包括：
如第一方面所述的数据线多路分配器。
第三方面，提供了一种显示面板，所述显示面板包括：
如第二方面所述的显示基板。
第四方面，提供了一种显示装置，所述显示装置包括：
如第三方面所述的显示面板。
第五方面，提供了一种数据线多路分配器的驱动方法，所述数据线多路分配器包括开关模块、多个开关信号端和多个数据信号端，所述开关模块分别与所述多个开关信号端、所述多个数据信号端和显示装置中的M列像素单元相连，其中，每列所述像素单元包括N列不同颜色的亚像素，所述M为正整数，所述N为大于1的整数，所述开关模块能够在所述多个开关信号端的控制下，将每个所述数据信号端与至少两列亚像素连通，所述至少两列亚像素中相邻的两列亚像素在所述显示装置中间隔列的数量为奇数的亚像素，所述驱动方法包括：在一帧图像的显示过程中，所述多个开关信号端依次输出将所述开关模块中的相应的晶体管导通的电压信号，所述多个数据信号端中的每个数据信号端输出的数据信号的电压极性保持不变；以及在显示下一帧图像时，所述多个数据信号端中的每个数据信号端输出的数据信号的电压极性改变。
在一个实施例中，在所述下一帧图像的显示过程中，所述多个开关信号端依次输出将所述开关模块中的相应的晶体管导通的电压信号。
在一个实施例中，所述至少两列亚像素中相邻的两列亚像素在所述显示装置中间隔一列亚像素。
在一个实施例中，所述开关模块包括：k个晶体管，所述k为所述显示装置中亚像素的列数，所述k个晶体管中每个晶体管的栅极与一个开关信号端相连，第一极与一个数据信号端相连，第二极与一列亚像素相连。
在一个实施例中，所述k个晶体管能够划分为N组，每组包括M个晶体管，每组中M个晶体管的栅极与同一个开关信号端相连，且每组中M个晶体管的第二极所连接的M列亚像素为同一种颜色的亚像素。
本公开提供的技术方案带来的有益效果是：
本公开实施例提供的数据线多路分配器中，开关模块能够在多个开关信号端的控制下，将每个数据信号端与至少两列亚像素连通，该至少两列亚像素中相邻的两列亚像素在显示装置中间隔列的数量为奇数的亚像素。由于在列反转驱动过程中，间隔列的数量为奇数的两列亚像素的极性相同，因此每个数据信号端在驱动其所连通的至少两列亚像素时，无需反转数据信号的电压极性即可实现列反转驱动，该驱动过程中显示装置的功耗较低。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是相关技术中的一种数据线多路分配器的结构示意图；
图2是本公开实施例提供的一种数据线多路分配器的结构示意图；
图3是本公开实施例提供的另一种数据线多路分配器的结构示意图；
图4是本公开实施例提供的又一种数据线多路分配器的结构示意图；
图5是本公开实施例提供的一种数据线多路分配器的驱动时序图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
本公开实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。根据在电路中的作用，本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一级，漏极称为第二级。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开实施例所采用的开关晶体管包括P型开关晶体管和N型开关晶体管两种，其中，P型开关晶体管在栅极为低电压时导通，在栅极为高电压时截止，N型开关晶体管为在栅极为高电压时导通，在栅极为低电压时截止。
图1是相关技术中的一种数据线多路分配器的结构示意图。如图1所示，对于每个像素单元包括三种颜色亚像素的显示装置，其数据线多路分配器1一般包括三个开关信号端SW1至SW3、m个数据信号端D1至Dm以及3×m个晶体管。另外，如图1所示，该显示装置还可以包括用于向每个像素单元中的各个亚像素提供栅极驱动信号的栅极驱动电路2。本公开提供了一种数据线多路分配器10，参考图2，该数据线多路分配器10可以包括：开关模块10、多个开关信号端和多个数据信号端。例如，在图2中，数据线多路分配器包括三个开关信号端SW1、SW2和SW3，以及M个数据信号端D1、D2至Dm。
该开关模块10分别与该多个开关信号端、该多个数据信号端和该显示装置中的M列像素单元相连，其中，每列像素单元可以包括N列不同颜色的亚像素，该M为正整数，该N为大于1的整数。
该开关模块10能够在该多个开关信号端的控制下，将每个数据信号端与至少两列亚像素连通，该至少两列亚像素中相邻的两列亚像素在该显示装置中间隔列的数量为奇数的亚像素。其中，该相邻的两列亚像素是指，与同一个数据信号端连通且间隔最近的两列亚像素。
示例的，如图2所示，数据信号端D1可以通过该开关模块10分别与三列亚像素R1、B1和G2相连。在该三列亚像素中，亚像素R1与B1间隔最近，为相邻的两列亚像素，该相邻的两列亚像素R1与B1在该显示装置中间隔一列亚像素G1；另外 两列相邻的亚像素B1与G2在该显示装置中间隔一列亚像素R2。由于在列反转驱动的过程中，该三列亚像素R1、B1和G2的极性相同，因此，与该三列亚像素连通的数据信号端D1可以在列反转驱动的过程中，使输出的数据信号的电压极性保持不变。其中电压极性是相对于公共电压而言的，当信号电压高于公共电压时，称该信号电压为正极性电压；当信号电压低于公共电压时，称该信号电压为负极性电压。
综上所述，本公开实施例提供的数据线多路分配器10中，开关模块能够在多个开关信号端的控制下，将每个数据信号端与至少两列亚像素连通，该至少两列亚像素中相邻的两列亚像素在显示装置中间隔列的数量为奇数的亚像素。由于在列反转驱动过程中，间隔列的数量为奇数的的两列亚像素的极性相同，因此每个数据信号端在驱动其所连通的至少两列亚像素时，无需反转数据信号的电压极性即可实现列反转驱动，该驱动过程中显示装置的功耗较低。
在一个实施例中，每个数据信号端所连通的至少两列亚像素中，相邻的两列亚像素在该显示装置中可以仅间隔一列亚像素。示例的，参考图2，数据信号端D1通过该开关模块10所连通的三列亚像素R1、B1和G2中，相邻两列亚像素R1和B1之间可以仅间隔一列亚像素G1，相邻两列亚像素B1和G2之间可以仅间隔一列亚像素R2。
在实际应用中，减少每个数据信号端所连通的至少两列亚像素之间的间隔，可以避免开关模块与像素单元之间的走线过长，降低制造成本。
在一个实施例中，在本公开实施例中，该数据线多路分配器10可以包括N个开关信号端。也即是，数据线多路分配器10中开关信号端的个数N可以与显示装置中每个像素单元所包括的亚像素的个数相同。示例的，参考图2，在该数据线多路分配器10所在的显示装置中，每个像素单元包括红绿蓝三种颜色的亚像素，即N＝3，则相应的，该数据线多路分配器中可以包括3个开关信号端SW1、SW2和SW3。
进一步的，该数据线多路分配器10中可以包括M个数据信号端。也即是，数据线多路分配器10中数据信号端的个数M可以与显示装置中所包括的像素单元的列数相同。
在本公开实施例中，若该数据线多路分配器10中包括M个数据信号端，则由于该显示装置中包括M列像素单元，且每列像素单元中又包括N列亚像素，因此为了使得该M个数据信号端均匀地为该M×N列亚像素提供数据信号，该开关模块10可以在该多个开关信号端的控制下，将每个数据信号端与N列亚像素分别连通。
示例的，在图2中，每个像素单元包括3个亚像素，则开关模块10可以将每个数据信号端与3列亚像素连通，比如将数据信号端D1分别与R1列亚像素、B1列亚像素和G2列亚像素连通；而在图3所示的数据线多路分配器20中，由于每个像素单元仅包括2个亚像素，则开关模块10可以将每个数据信号端与2列亚像素连通，比如可以将数据信号端D1分别与R1列亚像素和R2列亚像素连通，并将数据信号端 D2分别与G1列亚像素和G2列亚像素连通。
参考图2和图3，在本公开实施例提供的数据线多路分配器中，开关模块10可以包括k个晶体管，该k可以为该显示装置中亚像素的列数，即该k满足：k＝M×N。
该k个晶体管中每个晶体管的栅极与一个开关信号端相连，第一极与一个数据信号端相连，第二极与一列亚像素相连。例如图2中，晶体管T1的栅极与开关信号端SW1相连，第一极与数据信号端D1相连，第二极与亚像素列R1相连。
在本公开实施例中，该k个晶体管能够划分为N组，每组中包括M个晶体管。每组中M个晶体管的栅极与同一个开关信号端相连，且每组中M个晶体管的第二极所连接的M列亚像素为同一种颜色的亚像素。
进一步的，若该数据线多路分配器包括N个开关信号端；则任意两组晶体管的栅极所连接的开关信号端不同，且任意两组晶体管的第二极所连接的亚像素的颜色不同。也即是，每个开关信号端仅控制一种颜色的亚像素，由该N个开关信号端实现对N种颜色的亚像素的控制。
示例的，参考图2，该k个晶体管可以分为3组，其中第一组可以包括T1、T4至Tk-2等M个晶体管，第二组可以包括T2、T5至Tk-1等M个晶体管，第三组可以包括T3、T6至Tk等M个晶体管。
该三组晶体管中，第一组中的M个晶体管的栅极均与开关信号端SW1相连，第二极均与红色亚像素相连，该开关信号端SW1可以通过该第一组的M个晶体管实现对所有红色亚像素的控制；第二组中的M个晶体管的栅极均与开关信号端SW2相连，第二极均与绿色亚像素相连，该开关信号端SW2可以通过该第二组的M个晶体管实现对所有绿色亚像素的控制；第三组中的M个晶体管的栅极均与开关信号端SW3相连，第二极均与蓝色亚像素相连，该开关信号端SW3可以通过该第三组的M个晶体管实现对所有蓝色亚像素的控制。
作为本公开一种可选的实现方式，参考图2，该数据线多路分配器10可以包括M个数据信号端。
其中，每个数据信号端分别与该k个晶体管中的N个晶体管的第一极相连，该N个晶体管中相邻两个晶体管在该数据线多路分配器10中间隔一个晶体管；该k个晶体管中第i个晶体管的第二极与第i列亚像素相连，该i为小于等于k的正整数。其中，相邻的两个晶体管是指与同一个数据信号端相连的N个晶体管中，间隔最近的两个晶体管。
示例的，参考图2，数据信号端D1分别与三个晶体管T1、T3和T5的第一极相连，该三个晶体管中，晶体管T1与T3的间隔最近，为相邻的两个晶体管，该相邻的两个晶体管T1和T3在该数据线多路分配器10中间隔一个晶体管T2，该三个晶体管中另外两个相邻的晶体管T3和T5在该数据线多路分配器10中间隔一个晶体管T4。并且，从图2中还可以看出，该k个晶体管的第二极顺次与对应的亚像素列相 连，即第一个晶体管T1的第二极与第一列亚像素R1相连，第二个晶体管T2的第二极与第二列亚像素B1相连。由此，即可实现同一个数据信号端所连通的N列亚像素为间隔设置的亚像素列。
作为本公开另一种可选的实现方式，参考图4，该数据线多路分配器30可以包括M个数据信号端。
其中，每个该数据信号端分别与该k个晶体管中N个相邻的晶体管的第一极相连；该N个相邻的晶体管的第二极所连接的N列亚像素中，相邻两列亚像素在该显示装置中间隔一列亚像素。
示例的，参考图4，数据信号端D1分别与三个相邻的晶体管T1、T2和T3的第一极相连，其中晶体管T1的第二极所连接的亚像素为R1列亚像素，晶体管T2的第二极所连接的亚像素为G2列亚像素，T3的第二极所连接的亚像素为B1列亚像素。该三列亚像素R1、B1和G2中，相邻的两列亚像素R1和B1在该显示装置中间隔一列亚像素G1，另外两列相邻的亚像素B1和G2在该显示装置中间隔一列亚像素R2。由此，也可以实现同一个数据信号端所连通的N列亚像素为间隔设置的亚像素列。
当显示装置采用列反转方式进行驱动时，在一帧图像的驱动过程中，同一列中的各亚像素中存储的电压极性相同，相邻两列亚像素中存储的电压极性相反，在下一帧中，各列亚像素中存储的电压极性与之上一帧的极性相反。例如图4中，R1列亚像素与G1列亚像素的电压极性相反，G1列亚像素与B1列亚像素与的电压极性相反，但其中间隔列的数量为奇数的的亚像素的极性是相同的，例如R1列亚像素、B1列亚像素和G2列亚像素均为正极性。若采用图2至图4任一所示的数据线多路分配器为该像素单元提供数据信号，则由于每个数据信号端所连通的亚像素列为间隔设置的亚像素列，该间隔设置的亚像素列的极性相同，因此，在采用列反转方式驱动时，在一帧图像的显示过程中，每个数据信号端输出的数据信号的极性可以保持不变，例如可以一直保持正极性电压或者负极性电压，而无需再进行电压极性的反转，由此可以降低该显示装置的功耗。
在一个实施例中，在本公开实施例中，该k个晶体管可以均为N型晶体管。当然，该k个晶体管也可以均为P型晶体管，本公开实施例对该晶体管的具体类型不做限定。
参考图5，其示出了本公开实施例提供的一种数据线多路分配器的驱动过程的时序图。参考图5，在一帧图像的显示过程中，该驱动过程可以包括三个阶段。在第一阶段t1中，开关信号端SW1输出的开关信号为高电压，此时，参考图2和图4，与红色亚像素连接的第一组晶体管T1、T4至Tk-2开启，数据信号端D1至Dm分别通过该第一组晶体管向对应的亚像素输入数据信号。
若该显示装置采用列反转方式驱动，参考图2和4，该显示装置中的R1、B1、G2至Bk列亚像素所存储的数据电压需要为正极性电压；而G1、R2、B2至Gk列亚 像素所存储的数据电压需要为负极性电压。对于图2和图4所示的结构，参考图5，与R1列亚像素连通的数据信号端D1，以及与Rk列亚像素连通的数据信号端Dm输出的数据信号的电压可以为正极性电压(该正极性电压高于公共电压Vcom)，与R2列亚像素连通的数据信号端D2输出的数据信号的电压可以为负极性电压(该负极性电压低于公共电压Vcom)。
在第二阶段t2中，开关信号端SW2输出的开关信号为高电压，此时，参考图2和图4，与绿色亚像素连接的第二组晶体管T2、T5至Tk-1开启。由于该显示装置采用列反转方式驱动，则对于图2和图4所示的结构，参考图5，此时与G2列亚像素连通的数据信号端D1，以及与Gk-1列亚像素连通的数据信号端Dm输出的数据信号可以继续保持正极性电压，与G1列亚像素连通的数据信号端D2输出的数据信号可以继续保持负极性电压。
在第三阶段t3中，开关信号端SW3输出的开关信号为高电压，此时，参考图2和图4，与蓝色亚像素连接的第二组晶体管T3、T6至Tk开启。此时与B1列亚像素连通的数据信号端D1，以及与Bk列亚像素连通的数据信号端Dm输出的数据信号可以继续保持正极性电压，与B2列亚像素连通的数据信号端D2输出的数据信号可以继续保持负极性电压。
需要说明的是，参考图5，在对不同颜色的亚像素进行驱动时，每个数据信号端所输出的数据信号的电压高低可能会改变，但每个数据信号端输出的数据信号的电压极性均保持不变。例如，图5中数据信号端D1输出的数据信号的电压始终保持正极性，数据信号端D2输出的数据信号的电压始终保持负极性。
当然，在实际应用中，在对同一种颜色的亚像素进行驱动时，同一列中不同显示行的亚像素的数据电压的高低也可以不同，也即是，在每个阶段中，数据信号端输出的数据信号的电压的高低可以不同，但极性相同。例如，图5所示的第一阶段t1中，同一列中不同显示行的亚像素的数据信号电压大小相同；在第二阶段t2中，同一列中不同显示行的亚像素的数据信号电压大小不同；在第三阶段t3中，同一列中不同显示行的亚像素的数据信号电压大小也不相同。本公开实施例对各个阶段中，每个数据信号端输出的数据信号的电压大小不做具体限定，只要保证每个数据信号端输出的数据信号的电压极性在一帧图像的显示过程中保持不变即可。
根据上述分析可知，采用本公开实施例提供的数据线多路分配器对显示装置进行列反转驱动时，在一帧图像的显示过程中，每个数据信号端输出的数据信号的电压极性可以始终保持不变，而只在下一帧图像显示时，数据信号的电压极性才跳变一次，从而有效减少了数据信号电压极性的跳变次数，降低了显示装置的功耗。
综上所述，本公开实施例提供的数据线多路分配器中，开关模块能够在多个开关信号端的控制下，将每个数据信号端与至少两列亚像素连通，该至少两列亚像素中相邻的两列亚像素在显示装置中间隔列的数量为奇数的亚像素。由于在列反转驱动过程 中，间隔列的数量为奇数的两列亚像素的极性相同，因此每个数据信号端在驱动其所连通的至少两列亚像素时，无需反转数据信号的极性即可实现列反转驱动，该驱动过程中显示装置的功耗较低。
本公开实施例还提供了一种显示基板，该显示基板可以包括：如图2至图4任一所示的数据线多路分配器。
进一步的，本公开实施例还提供了一种显示面板，该显示面板可以包括：设置有如图2至图4任一所示的数据线多路分配器的显示基板。
进一步的，本公开实施例还提供了一种显示装置，该显示装置中包括：显示面板，该显示面板中的显示基板可以包括如图2至图4任一所示的数据线多路分配器。该显示装置可以为：液晶面板、电子纸、OkED面板、AMOkED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要说明的是，该显示装置中还可以包括源极驱动电路，该源极驱动电路可以与图2至图4任一所示的数据线多路分配器的数据信号端相连，以便通过该数据线多路分配器为该显示装置中的各像素单元提供数据信号。
以上所述仅为本公开的较佳实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种数据线多路分配器，其特征在于，所述数据线多路分配器包括：开关模块、多个开关信号端和多个数据信号端；
    所述开关模块分别与所述多个开关信号端、所述多个数据信号端和显示装置中的M列像素单元相连，其中，每列所述像素单元包括N列不同颜色的亚像素，所述M为正整数，所述N为大于1的整数；
    所述开关模块能够在所述多个开关信号端的控制下，将每个所述数据信号端与至少两列亚像素连通，所述至少两列亚像素中相邻的两列亚像素在所述显示装置中间隔列的数量为奇数的亚像素。
  2. 根据权利要求1所述的数据线多路分配器，其特征在于，
    所述至少两列亚像素中相邻的两列亚像素在所述显示装置中间隔一列亚像素。
  3. 根据权利要求1所述的数据线多路分配器，其特征在于，
    所述数据线多路分配器包括N个开关信号端。
  4. 根据权利要求1至3任一所述的数据线多路分配器，其特征在于，
    所述数据线多路分配器包括M个数据信号端。
  5. 根据权利要求4所述的数据线多路分配器，其特征在于，
    所述开关模块能够在所述多个开关信号端的控制下，将每个所述数据信号端与N列亚像素分别连通。
  6. 根据权利要求1至3任一所述的数据线多路分配器，其特征在于，所述开关模块包括：k个晶体管，所述k为所述显示装置中亚像素的列数；
    所述k个晶体管中每个晶体管的栅极与一个开关信号端相连，第一极与一个数据信号端相连，第二极与一列亚像素相连。
  7. 根据权利要求6所述的数据线多路分配器，其特征在于，
    所述k个晶体管能够划分为N组，每组包括M个晶体管；
    每组中M个晶体管的栅极与同一个开关信号端相连，且每组中M个晶体管的第二极所连接的M列亚像素为同一种颜色的亚像素。
  8. 根据权利要求7所述的数据线多路分配器，其特征在于，所述数据线多路分配器包括N个开关信号端；
    任意两组晶体管的栅极所连接的开关信号端不同，且任意两组晶体管的第二极所连接的亚像素的颜色不同。
  9. 根据权利要求8所述的数据线多路分配器，其特征在于，所述数据线多路分配器包括M个数据信号端；
    每个所述数据信号端分别与所述k个晶体管中的N个晶体管的第一极相连，所述N个晶体管中相邻两个晶体管在所述数据线多路分配器中间隔一个晶体管；
    所述k个晶体管中第i个晶体管的第二极与第i列亚像素相连，所述i为小于等于k的正整数。
  10. 根据权利要求8所述的数据线多路分配器，其特征在于，所述数据线多路分配器包括M个数据信号端；
    每个所述数据信号端分别与所述k个晶体管中的N个相邻的晶体管的第一极相连；
    所述N个相邻的晶体管的第二极所连接的N列亚像素中，相邻两列亚像素在所述显示装置中间隔一列亚像素。
  11. 根据权利要求1至3任一所述的数据线多路分配器，其特征在于，
    每列所述像素单元包括3列不同颜色的亚像素；
    所述数据线多路分配器包括3个开关信号端。
  12. 根据权利要求6所述的数据线多路分配器，其特征在于，
    所述k个晶体管均为N型晶体管。
  13. 一种显示基板，其特征在于，所述显示基板包括：
    如权利要求1至12任一所述的数据线多路分配器。
  14. 一种显示面板，其特征在于，所述显示面板包括：
    如权利要求13所述的显示基板。
  15. 一种显示装置，其特征在于，所述显示装置包括：
    如权利要求14所述的显示面板。
  16. 一种数据线多路分配器的驱动方法，所述数据线多路分配器包括开关模块、多个开关信号端和多个数据信号端，所述开关模块分别与所述多个开关信号端、所述多个数据信号端和显示装置中的M列像素单元相连，其中，每列所述像素单元包括N列不同颜色的 亚像素，所述M为正整数，所述N为大于1的整数，所述开关模块能够在所述多个开关信号端的控制下，将每个所述数据信号端与至少两列亚像素连通，所述至少两列亚像素中相邻的两列亚像素在所述显示装置中间隔列的数量为奇数的亚像素，所述驱动方法包括：
    在一帧图像的显示过程中，所述多个开关信号端依次输出将所述开关模块中的相应的晶体管导通的电压信号，所述多个数据信号端中的每个数据信号端输出的数据信号的电压极性保持不变，相邻的数据信号端输出的数据信号的电压极性是相反的；以及
    在显示下一帧图像时，所述多个数据信号端中的每个数据信号端输出的数据信号的电压极性改变。
  17. 根据权利要求16所述的驱动方法，其中，在所述下一帧图像的显示过程中，所述多个开关信号端依次输出将所述开关模块中的相应的晶体管导通的电压信号。
  18. 根据权利要求16所述的驱动方法，其中，所述至少两列亚像素中相邻的两列亚像素在所述显示装置中间隔一列亚像素。
  19. 根据权利要求16所述的驱动方法，其中，所述开关模块包括：k个晶体管，所述k为所述显示装置中亚像素的列数，
    所述k个晶体管中每个晶体管的栅极与一个开关信号端相连，第一极与一个数据信号端相连，第二极与一列亚像素相连。
  20. 根据权利要求19所述的驱动方法，其中，所述k个晶体管能够划分为N组，每组包括M个晶体管，
    每组中M个晶体管的栅极与同一个开关信号端相连，且每组中M个晶体管的第二极所连接的M列亚像素为同一种颜色的亚像素。
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