WO2018076268A1 - 场效应晶体管结构及其制作方法 - Google Patents

场效应晶体管结构及其制作方法 Download PDF

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WO2018076268A1
WO2018076268A1 PCT/CN2016/103724 CN2016103724W WO2018076268A1 WO 2018076268 A1 WO2018076268 A1 WO 2018076268A1 CN 2016103724 W CN2016103724 W CN 2016103724W WO 2018076268 A1 WO2018076268 A1 WO 2018076268A1
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gate dielectric
bottom gate
dielectric layer
effect transistor
gate electrode
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PCT/CN2016/103724
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English (en)
French (fr)
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秦旭东
徐慧龙
张臣雄
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华为技术有限公司
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Priority to CN201680086216.1A priority Critical patent/CN109196651B/zh
Priority to PCT/CN2016/103724 priority patent/WO2018076268A1/zh
Publication of WO2018076268A1 publication Critical patent/WO2018076268A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • the invention belongs to the field of semiconductor devices and manufacturing, and in particular relates to a field effect transistor structure and a manufacturing method thereof.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • CMOS Complementary Metal Oxide Semiconductor
  • One common method of opening the band gap by graphene is to apply a vertical voltage to the bilayer graphene using a simple double gate structure. As shown in Fig. 1, the double-layered graphene is sandwiched between two parallel metal plates, and the band gap size varies with the voltage applied between the two plates.
  • 101 is a top gate electrode
  • 102 is a top gate dielectric layer
  • 103 is a double layer graphene
  • 104 is a bottom gate dielectric layer
  • 105 is a bottom gate electrode.
  • the 0.1eV bandgap can bring about a device switching ratio of almost two orders of magnitude, which is not enough for the need to make electronic devices using graphene.
  • Tao Chu et al. of Purdue University can open a band gap of 0.2 eV by using a thin dielectric and narrowing the channel at the same time, and can achieve a device room-to-switch ratio of 150.
  • this method improves the switching ratio of the device by sacrificing the on-state current, which makes the output performance of the device worse, which is also disadvantageous for the application of the graphene device.
  • embodiments of the present invention provide a field effect transistor structure and a fabrication method thereof, which can improve a device switching ratio without sacrificing an on-state current.
  • a field effect transistor structure comprising: a bottom gate electrode; a bottom gate dielectric layer covering the upper surface of the bottom gate electrode and the bottom gate electrode The upper surface contact; the nano-ribbed channel layer is composed of a plurality of parallel-separated two-layer graphene nano-strips covering the bottom-gate dielectric layer
  • the upper surface is in contact with the upper surface of the bottom gate dielectric layer; the source and the drain have a parallel spacing between the source and the drain, and are respectively in contact with the nano-ribbed channel layer, the source
  • the length direction of the drain and the length direction of the drain are both at an angle to the channel direction of the nano-ribbed channel layer, and the upper surface of the source and the upper surface of the drain are both opposite to the nano-ribbed channel layer
  • the upper surface is parallel; the top gate dielectric layer covers the upper surface of the nano-ribbed channel layer between the source and the drain, and is in contact with the upper surface of the nano-ribbed channel layer a top gate electrode covering
  • the influence of the charge center of the gate dielectric can be effectively reduced without sacrificing the on-state current of the device, so that the device can be better turned off. Increase the device switching ratio.
  • the parallel spacing means that the source and the drain are placed in parallel with a certain interval therebetween.
  • the bottom gate dielectric layer may cover the upper surface of the bottom gate electrode as a whole or may be partially covered.
  • the bottom gate dielectric layer may also cover at least a portion of the upper surface of the source and/or the drain.
  • each of the plurality of parallel spaced double-layer graphene nanoribbons has a width of 50 nm to 200 nm.
  • the source and the drain cover an upper surface of the nano-ribbed channel layer.
  • the contact area is larger, and the contact resistance is expected to be smaller.
  • the source and the drain cover an upper surface of the bottom gate dielectric layer, and the source and the drain are respectively in contact with opposite sides of the nano-ribbed channel layer. Both the length direction of the source and the length direction of the drain are perpendicular to the channel direction.
  • the widths of the top gate electrode and the bottom gate electrode are both equal to the spacing between the source and the drain.
  • top and bottom gates are self-aligned or self-aligned by other processes to reduce parasitic effects and improve device performance.
  • the field effect transistor structure further includes: a substrate having a recess, the recess having the same shape as the top gate electrode; wherein the bottom gate electrode is disposed in the recess In the trench, the top gate electrode is located directly above the bottom gate electrode.
  • the bottom gate and top gate structures are vertically symmetrical, which helps to better control the channel.
  • the field effect transistor structure can also adopt two upper and lower misaligned double gate structures, and three different channel regions are formed by the double gate dislocation structure, and the two sides can be different doped channels, and the middle can be Can open the channel of the band gap.
  • the bottom gate electrode also has the function of supporting the field effect transistor structure.
  • the bottom grid has both electrical and supporting functions and is simple to manufacture.
  • the gate dielectric layer of the first gate and/or the gate dielectric layer of the second gate have a thickness of 2 nm to 20 nm.
  • the use of a thinner gate dielectric layer can further effectively reduce the effects of charge centers in the gate dielectric, thereby increasing the device switching ratio.
  • the gate dielectric layer of the first gate and the gate dielectric layer of the second gate are the same material.
  • the gate dielectric layer of the first gate and the gate dielectric layer of the second gate may be formed by the same process.
  • the material of the gate dielectric layer of the first gate and/or the second gate comprises a common metal oxide or a high
  • the k-oxide, the source electrode and the material of the drain electrode comprise materials which are generally low resistivity and which form effective ohmic contact with graphene.
  • the source electrode and the drain electrode are made of gold, titanium, nickel, platinum, chromium, aluminum, copper, and At least one of tungsten.
  • the material of the substrate is a semiconductor or an insulator, which may be transparent or opaque.
  • a method for fabricating a field effect transistor structure comprising: fabricating a bottom gate electrode; forming a bottom gate dielectric layer on an upper surface of the bottom gate electrode; and growing a double layer on a surface of the bottom gate dielectric layer Graphene or transferring bilayer graphene onto the surface of the bottom gate dielectric layer; performing photolithography and etching on the bilayer graphene to form a plurality of parallel spaced double graphene nanoribbons a nano-ribbed channel layer; performing photolithography on the upper surface of the nano-ribbed channel layer to form an electrode of the source and the drain, the length direction of the source and the length direction of the drain are both opposite to the nano-ribbon
  • the channel layer has an angle in a channel direction, and a parallel spacing between the source and the drain; forming a top gate dielectric layer on an upper surface of the nano-ribbed channel layer between the source and the drain Forming the top gate electrode on the top gate dielectric layer.
  • the fabricating the bottom gate electrode includes: providing a substrate; performing a photolithography and etching on the substrate to form a recess; forming the bottom gate by evaporating metal in the recess An electrode having the same shape as the bottom gate electrode and located directly above the bottom gate electrode.
  • Figure 1 shows a schematic diagram of a vertical electric field applied to a bilayer graphene.
  • FIG. 2 is a schematic diagram showing the structure of a field effect transistor according to an embodiment of the present invention.
  • FIG. 3 is another schematic diagram of a field effect transistor structure provided by an embodiment of the present invention.
  • FIG. 4(a) to 4(g) are explanatory views showing the structure of the field effect transistor shown in Fig. 2 according to an embodiment of the present invention.
  • 5(a) to 5(h) are explanatory views showing the structure of the field effect transistor shown in Fig. 3 according to an embodiment of the present invention.
  • Graphene is a new type of two-dimensional planar structure carbon material. Since its discovery, its unique molecular structure and excellent physical properties have attracted widespread attention from scholars and industry. As an ideal two-dimensional material, graphene exhibits many amazing physical properties. Including ultra-high carrier mobility (up to 230,000cm 2 /Vs) and conductivity (up to 105S / m), band tunability and anomalous integer quantum Hall effect. Graphene has very unusual carrier behavior, like relativistic particles with a static mass of zero (Dirac fermion). Due to the difference in motion and electrons of Dirac fermions, when a magnetic field is applied to graphene, an abnormal quantum Hall effect occurs.
  • the intersection of the conduction band and the valence band of graphene is at the six vertices of the first Brillouin zone.
  • the electron dispersion relationship near these points is consistent with the characteristics of relativistic Dirac electrons. Therefore, these intersections are also called Dirac points, graphite.
  • the conduction band bottom and the valence band top of the alkene are degenerate at the Dirac point, thereby forming a semiconductor having a zero band gap, exhibiting metallic properties.
  • the development of graphene opening bandgap is of great significance.
  • the double-layer graphene has a large difference in band structure compared with single-layer graphene, and the double-layer graphene has passed the stacking structure of the two-layer graphite atomic layer and its advantages in functional modification.
  • Applying a vertical electric field thereon makes it easier to open the band gap than a single layer of graphene, especially when the bilayer graphene is stacked in an AB order (also called a Bernal stack).
  • the lattice constant is constant, so the band gap is fixed, and the position of the Fermi level can only be changed by doping.
  • the band gap of the channel can be changed by stress engineering, but once the device is completed, the band gap cannot be changed.
  • Applying a vertical electric field to the bilayer graphene the band gap will change, which is a characteristic that conventional semiconductor materials do not have, which provides more imagination for the application of the double layer.
  • the graphene-based electronic device may include a field effect transistor, a sensor, a solar cell, or the like.
  • the graphene field effect transistor will be described below as an example, and the present invention is not limited thereto.
  • the field effect transistor includes a bottom gate electrode 201, a bottom gate dielectric layer 202, a nano strip channel layer 203, a top gate dielectric layer 204, a top gate electrode 205, and a source from bottom to top.
  • the nano-ribbed channel layer is disposed between the top gate dielectric layer 204 and the bottom gate dielectric layer 202, and the bottom gate dielectric
  • the layer 202 and the top gate dielectric layer 204 are in surface contact
  • the nano-ribbed channel layer 203 is composed of a plurality of parallel-separated double-layer graphene nano-strips, and the source electrode 206 and the drain electrode 207 are respectively opposite to the nanometer
  • the strip channel layer 203 is in contact.
  • the switching ratio of the field effect transistor is the ratio of the on-state current to the off-current. Since the graphene does not have a band gap, the graphene field effect transistor cannot be completely turned off, and the switch is relatively small, so there is a great limitation in the application of the logic device. .
  • the field effect transistor structure provided by the embodiment of the invention adopts a plurality of parallel spaced double-layer graphene nano-strips as a channel layer, which can effectively reduce the charge center of the gate dielectric without sacrificing the on-state current of the device. The effect is to enable the device to have a good shutdown and increase the device switching ratio.
  • the bottom gate electrode and the bottom gate dielectric layer may be a global bottom gate structure as shown in FIG. 2, in other words, the bottom gate electrode of the embodiment of the present invention may further have a support field.
  • the bottom gate electrode and the bottom gate dielectric layer may also be an embedded partial bottom gate structure as shown in FIG. 3; or the bottom gate electrode may have a partial structure, and the bottom gate dielectric layer adopts a global structure.
  • the field effect transistor structure further includes: a substrate having a recess; wherein the bottom gate electrode is disposed in the recess, the top gate electrode and the bottom gate The electrodes are identical in shape and located directly above the bottom gate electrode.
  • the bottom gate is embedded in the substrate and is symmetrical with the top gate structure so that the channel can be better controlled.
  • the field effect transistor structure can also adopt two upper and lower misaligned double gate structures, and three different channel regions are formed by the double gate dislocation structure, and the two sides can be different doped channels, and the middle can open the band gap.
  • the channel can also adopt two upper and lower misaligned double gate structures, and three different channel regions are formed by the double gate dislocation structure, and the two sides can be different doped channels, and the middle can open the band gap. The channel.
  • the bottom gate dielectric layer in the embodiment of the present invention may be all covering the upper surface of the bottom gate electrode, or may be partially covered.
  • the bottom gate dielectric layer may also cover at least a portion of the upper surface of the source and/or the drain.
  • covering in the embodiments of the present invention may refer to both full coverage and partial coverage.
  • the direction of the two-layer graphene nano strip in the embodiment of the present invention may be perpendicular to the direction of the source electrode and the drain electrode as shown in FIG. 2 or FIG. 3, and may also be related to the source electrode and the drain electrode.
  • the embodiment of the present invention is described by way of example only in FIG. 2 or FIG. 3, but the present invention is not limited thereto.
  • the spacing between the source electrode and the drain electrode provided by the embodiment of the present invention may be greater than the width of the gate electrode of the top gate as shown in FIG. 2 or FIG. 3, or the width of the gate electrode is equal to the source electrode.
  • the spacing between the drain electrode and the drain electrode (so-called self-aligned structure).
  • the spacing between the source electrode and the drain electrode in the embodiment of the present invention refers to the leftmost end of the source from the rightmost end to the drain as shown in FIG. 2 or FIG. 3 .
  • the top gate dielectric layer can cover the source and / or at least a portion of the upper surface of the drain, and is fabricated using a self-aligned structure or other process between the source and the drain to reduce parasitic effects and improve device performance.
  • the process used is as follows: firstly depositing a seed layer and a metal oxide layer on the graphene as a gate dielectric, and then fabricating a T-type gate structure. Due to the protection of the T-type gate, the next step is to form a self-aligned source when the source and drain electrodes are evaporated. quasi. In order to reduce the parasitic capacitance, the switching speed and operating frequency of the field effect transistor structure can be improved, and the device size can be reduced to improve the integration of the circuit.
  • the source electrode and the drain electrode may be electrically contacted on the upper surface of the nano strip channel layer as described in FIG. 2 or FIG. 3, or may be in the nano strip.
  • the sides of the channel layer are electrically contacted or Schottky contacts, for example, may be in contact with both sides of the nanoribbed channel layer on the bottom gate dielectric.
  • the source and the drain cover the upper surface of the bottom gate dielectric layer, and the source and the drain are respectively in contact with opposite sides of the nano-ribbed channel layer, and the length direction of the source is The length direction of the drain is perpendicular to the channel direction.
  • the invention not limits the manner of electrical contact between the source and drain electrodes and the gate. The larger the contact area, the smaller the contact resistance is expected to be.
  • a two-layer graphene nano strip can be fabricated by photolithography and etching, and the width of the double-layer graphene nano strip should be greater than 10 nm, and the typical value is 50-200 nm. It has been found that the nano-strip structure can cut off the "short-circuit path" of electrons in the channel due to the charge center. At present, nano-strands are used to open the graphene bandgap, using the principle of quantum confinement effect, using nano-bands with a width of less than 10 nm. At this scale, the performance, width and edge state of the nano-bands are band gaps and migration. The rate has a big impact.
  • the narrower graphene nano-ribbons involve atomic-level precision manipulation, and the manufacturing process has certain difficulties.
  • the width of the double-layered graphene nanostrips needs to be optimized according to the process conditions. For example, a well-grown gate dielectric can use a wider strip, and vice versa.
  • the embodiment of the invention adopts multiple hundred ⁇
  • the meter-scale double-layer graphene nano-ribbon strip can improve the band gap of the double-layer graphene and the device switching ratio, is not affected by the edge state, and can reduce the difficulty in the manufacturing process.
  • a thinner gate dielectric layer having a thickness of typically 2 to 20 nm may be employed. Due to the inevitable defects and impurities in the gate dielectric of the double-layered graphene transistor, the charge center is introduced, and the gate electric field is partially shielded, so that the band gap cannot be modulated to form a leakage path. If a thicker gate dielectric layer is used, the leakage of the gate dielectric layer is more serious. Therefore, the thinness in the embodiment of the present invention generally refers to a thin gate dielectric layer within 100 nm, which can effectively reduce the influence of the charge center in the gate dielectric. .
  • the gate dielectric and the gate material of the top gate and the bottom gate may be the same, and the gate dielectric of the bottom gate and the gate dielectric of the top gate may be formed by the same process. This is more conducive to the performance of the device.
  • the material of the gate dielectric layer comprises a common metal oxide or high-k oxide, or a two-dimensional dielectric material such as boron nitride;
  • the source electrode and the material of the drain electrode include low resistivity and can Graphene forms a metal with better ohmic contact;
  • the material of the substrate includes a semiconductor or an insulator, which may be transparent or opaque.
  • the material of the source electrode and the drain electrode includes at least one of the following materials: gold, titanium, nickel, platinum, chromium, aluminum, copper, and tungsten.
  • the field effect transistor structure in the embodiment of the present invention can be fabricated on an insulating substrate, the substrate can be a transparent or opaque flexible substrate, and a flexible gated field emission triode (GFET) high frequency device can be Used on flexible folding electronic devices.
  • GFET flexible gated field emission triode
  • the field effect transistor structure provided by the embodiment of the present invention adopts multiple parallel double-layer graphene nano-strip structures as channels, and can be used without sacrificing on-state current (up to several hundred milliamperes or more). It effectively reduces the influence of the charge center of the gate dielectric, enables the device to be better turned off, and improves the switching ratio of the device (up to two to three orders of magnitude), which enhances the output capability of the device.
  • the use of a thinner gate dielectric layer further reduces the effects of charge centers in the gate dielectric.
  • the device structure provided by the embodiment of the invention is compatible with the traditional planar process, and is easy to realize low-cost batch production.
  • FIG. 4 is an explanatory view of the structure of the field effect transistor shown in FIG. 2 according to an embodiment of the present invention. It should be understood that, in order to explain the process effect, the illustration is not drawn according to the actual device structure ratio, and the specific manufacturing process steps are as follows. :
  • Step 1 As shown in Fig. 4(a), a substrate material is prepared, which needs to be electrically conductive, and may be a common semiconductor such as Si or Ge.
  • the substrate may be a rectangular substrate, and the doping concentration of the substrate may be lightly doped, and the doping concentration is 10 14 to 10 16 cm -3 .
  • Step 2 As shown in Fig. 4(b), a bottom gate dielectric is fabricated.
  • the bottom gate dielectric can be a common gate dielectric material such as aluminum oxide, germanium dioxide or germanium oxide.
  • the gate dielectric can be fabricated by an Atomic-layer deposition (ALD) method. A thinner bottom gate dielectric layer is used, typically having a thickness of 5 to 20 nm.
  • Step 3 As shown in FIG. 4(c), the bilayer graphene is grown or transferred.
  • the double-layered graphene can be formed on the surface of the bottom gate dielectric by direct growth, or can be grown by chemical vapor deposition (CVD) and then transferred to the bottom gate dielectric.
  • CVD chemical vapor deposition
  • the preparation methods of graphene mainly include: micro mechanical peeling method, pyrolytic SiC method, chemical stripping reduction method, etching carbon nanotube method, and chemical vapor deposition method.
  • the process for preparing graphene by the CVD method is as follows: first, a metal foil or a substrate carrying a metal thin film is placed in a reaction furnace; secondly, a mixed gas of methane, hydrogen, and argon is introduced and the cavity is introduced. Heating to 1000 ° C, the methane gas is decomposed at high temperature; finally, it is rapidly cooled.
  • the method for producing a two-layer graphene is not limited in the embodiment of the present invention.
  • Step 4 As shown in Fig. 4(d), a two-layer graphene nanoribbon was produced. This step can be photolithographically and etched on the bilayer graphene to form a bilayer graphene nanoribbon.
  • the width of the nanoribbons needs to be optimized according to the quality of the gate dielectric, typically on the order of 100 nanometers. For example, if the quality of the grown gate dielectric layer is better, a wider strip can be used, and vice versa.
  • Step 5 As shown in Fig. 4(e), a source/drain electrode is fabricated. This step can perform photolithography on both ends of the double-layer graphene nanoribbon to form a source-drain electrode pattern and primary metal evaporation.
  • the electrode material may be a commonly used metal such as gold, titanium, nickel, platinum, chromium, aluminum, copper or tungsten.
  • Step 6 As shown in FIG. 4(f), a top gate dielectric layer is formed.
  • the top gate dielectric layer and the bottom gate dielectric layer can be fabricated in the same process.
  • Step 7 As shown in Fig. 4(g), a top gate electrode is fabricated. This step can perform a photolithography on the double-layered graphene nanoribbon and between the source and drain electrodes to form a gate pattern and primary metal evaporation.
  • the electrode material may be a commonly used metal such as gold, titanium, nickel, platinum, chromium, aluminum, copper or tungsten.
  • FIG. 5 is an explanatory diagram of the structure of the field effect transistor shown in FIG. 3 according to an embodiment of the present invention. It should be understood that, in order to illustrate the process effect, the illustration is not drawn according to the actual device structure ratio, and the specific manufacturing process steps are as follows. :
  • Step 1 As shown in Fig. 5(a), the substrate material is prepared, and the substrate material may be a common silicon/diox. Silicon, silicon carbide, boron nitride, silicon nitride, and other insulating materials such as polyester resin, sapphire, and the like. In this embodiment, the substrate may not function as a bottom gate, but only functions as a supporting device and does not participate in device functions.
  • Step 2 As shown in FIG. 5(b), a bottom gate electrode is fabricated. This step requires a photolithography and etching to form a trench on the substrate, followed by evaporation of the metal to form a bottom gate electrode, and then etching away the sacrificial layer to obtain an embedded bottom gate electrode.
  • Step 3 As shown in FIG. 5(c), a bottom gate dielectric layer is formed.
  • the bottom gate dielectric can be a common gate dielectric material such as aluminum oxide, germanium dioxide or germanium oxide.
  • the gate dielectric can be fabricated by an Atomic-layer deposition (ALD) method. A thinner bottom gate dielectric layer is used, typically having a thickness of 5 to 20 nm.
  • Step 4 As shown in Fig. 5(d), the bilayer graphene is grown or transferred.
  • the double-layered graphene can be formed on the surface of the bottom gate dielectric by direct growth, or can be grown by chemical vapor deposition (CVD) and then transferred to the bottom gate dielectric.
  • CVD chemical vapor deposition
  • Step 5 As shown in Fig. 5(e), a two-layer graphene nanoribbon was produced. This step requires a photolithography and etching to form a bilayer graphene nanoribbon.
  • the width of the nanoribbons needs to be optimized according to the quality of the gate dielectric, typically on the order of 100 nanometers. For example, if the quality of the grown gate dielectric layer is better, a wider strip can be used, and vice versa.
  • Step 6 As shown in FIG. 5(f), a source/drain electrode is fabricated. This step requires that one end of the two-layer graphene nanoribbon strip can be photolithographically formed to form a source-drain electrode pattern and primary metal evaporation.
  • the electrode material may be a commonly used metal such as gold, titanium, nickel, platinum, chromium, aluminum, copper or tungsten.
  • Step 7 As shown in Fig. 5(g), a top gate dielectric layer is formed.
  • the top gate dielectric layer and the bottom gate dielectric layer can be fabricated in the same process.
  • Step 8 As shown in FIG. 5(h), a top gate electrode is fabricated. This step can perform a photolithography on the double-layered graphene nanoribbon and between the source and drain electrodes to form a gate pattern and primary metal evaporation.
  • the electrode material may be a commonly used metal such as gold, titanium, nickel, platinum, aluminum, copper or tungsten.
  • a bottom gate electrode may be deposited on the substrate by electron beam lithography and an electron beam evaporation reflow process; a hexagonal boron nitride h-BN film grown by CVD is transferred to the bottom gate metal electrode as a gate dielectric;
  • the dielectric layer can be completed by a multi-step growth process, such as a layer of a few nanometers thick germanium, which is then oxidized, and then a layer of yttrium oxide is grown thereon; the source electrode is deposited by electron beam lithography and metal evaporation reflow process.
  • a drain electrode with a drain electrode; a top gate metal electrode is deposited by electron beam lithography and an electron beam evaporation reflow process; a gate electrode is obtained by multi-step growth, such as a nanometer thick layer of titanium adhered to graphene, and then Gold is formed on the upper growth resistivity to form an electrode.
  • the size of the sequence numbers of the above processes does not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not be taken to the embodiments of the present invention.
  • the implementation process constitutes any limitation.
  • B corresponding to A means that B is associated with A, and B can be determined according to A.
  • determining B from A does not mean that B is only determined based on A, and that B can also be determined based on A and/or other information.

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Abstract

本发明实施例公开了一种场效应晶体管结构及其制作方法，该场效应晶体管结构包括：底栅电极；底栅介质层；纳米条带沟道层，所述纳米条带沟道层是由多个平行间隔开的双层石墨烯纳米条带构成，所述纳米条带沟道层覆盖于所述底栅介质层的上表面，且与所述底栅介质层的上表面接触；源极和漏极；顶栅介质层；顶栅电极。本发明实施例提供的场效应晶体管结构及其制作方法，能够在不牺牲器件开态电流的情况下，有效地减少栅介质电荷中心的影响，使器件能够有较好地关断，提升器件开关比。

Description

场效应晶体管结构及其制作方法 技术领域
本发明属于半导体器件及制造领域，特别是涉及一种场效应晶体管结构及其制作方法。
背景技术
自1960年金属-氧化物-半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)器件研制成功后，因其具有低功耗、可靠性高、尺寸易于缩小等优点，成为微处理器与半导体存储器等先进集成电路中不可或缺的核心部分，并迅速蓬勃发展。为了增加器件密度、响应速度以及芯片的功能，器件尺寸的按比例缩小是互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)技术长期以来的发展趋势。即根据摩尔定律，芯片的集成度每18个月至2年提高一倍。随着微电子领域器件尺寸的不断减小，硅材料逐渐接近其加工的极限。为延长摩尔定律的寿命，国际半导体工业界纷纷提出超越硅技术，其中最有希望的石墨烯应运而生。
室温下石墨烯电子迁移率大于10000cm2V-1s-1，大大超过硅、锗等常规的半导体材料，很适合制作电子器件。但是本征石墨烯是零带隙的，这造成石墨烯场效应晶体管的器件开关比低，饱和特性差，也不利于模拟应用。
石墨烯打开带隙的一种常用方法是采用简单的双栅结构对双层石墨烯施加垂直电压。如图1所示，双层石墨烯夹在两个平行的金属极板之间，其带隙大小随两极板间所施加的电压变化。其中，101为顶栅电极，102为顶栅介质层，103为双层石墨烯，104为底栅介质层，105为底栅电极。当图1中的顶栅电压VTG和底栅电压VBG发生变化时，可以打开不到0.1eV的带隙。对于石墨烯制作的电子器件来说，判定其性能优劣的重要指标包括器件开关比、载流子迁移率等。而0.1eV的带隙能够带来的器件开关比几乎都在两个数量级内，这对于利用石墨烯制作电子器件的需求来说是远远不够的。普度大学的Tao Chu等通过采用较薄的电介质，同时将沟道做窄，可以打开带隙0.2eV，并且可以将器件室温开关比达到150。但是这种方法是通过牺牲开态电流来提高器件开关比的，使得器件的输出性能变差，同样不利于石墨烯器 件的应用。
发明内容
有鉴于此，本发明实施例提供了一种场效应晶体管结构及其制作方法，能够在不牺牲开态电流的情况下，提高器件开关比。
第一方面，提供了一种场效应晶体管结构，该场效应晶体管结构包括：底栅电极；底栅介质层，该底栅介质层覆盖于该底栅电极的上表面，且与该底栅电极的上表面接触；纳米条带沟道层，该纳米条带沟道层是由多个平行间隔开的双层石墨烯纳米条带构成，该纳米条带沟道层覆盖于该底栅介质层的上表面，且与该底栅介质层的上表面接触；源极和漏极，该源极和该漏极之间具有平行间距，且分别与该纳米条带沟道层接触，该源极的长度方向和该漏极的长度方向均与该纳米条带沟道层的沟道方向有夹角，该源极的上表面与该漏极的上表面均与该纳米条带沟道层的上表面平行；顶栅介质层，该顶栅介质层覆盖于该源极和该漏极之间的该纳米条带沟道层的上表面，且与该纳米条带沟道层的上表面接触；顶栅电极，该顶栅电极覆盖于该顶栅介质层的上表面，且与该顶栅介质层的上表面接触，该顶栅电极与该底栅电极通过外部电路相连，该外部电路为除该场效应晶体管结构以外的电路。
采用多条平行间隔的双层石墨烯纳米条带作为沟道层，能够在不牺牲器件开态电流的情况下，有效地减少栅介质电荷中心的影响，使器件能够有较好的关断，提升器件开关比。
这里的平行间距是指源极和漏极平行放置，并且之间具有一定的间隔。
可选地，该底栅介质层可以是全部覆盖底栅电极的上表面，也可以是部分覆盖。该底栅介质层还可以覆盖于该源极和/或该漏极的至少部分上表面。
在一种可能的实现方式中，该多个平行间隔开的双层石墨烯纳米条带中的每个双层石墨烯纳米条带的宽度为50nm～200nm。
采用较宽的双层石墨烯纳米条带，不引入量子限制效应，从而能够有效地避免边缘态带来的影响，并且能够降低在制作工艺上的难度。
在一种可能的实现方式中，该源极和该漏极覆盖于该纳米条带沟道层的上表面。
通过在纳米条带沟道层的上表面制作源漏电极，接触面积更大，接触电阻有望做的更小。
在一种可能的实现方式中，该源极和该漏极覆盖于该底栅介质层的上表面，该源极和该漏极分别与该纳米条带沟道层相对的两侧接触，该源极的长度方向与该漏极的长度方向均与该沟道方向垂直。
在一种可能的实现方式中，该顶栅电极和该底栅电极的宽度均等于该源极和该漏极之间的间距。
顶栅和底栅采用自对准结构或采用其他工艺获得自对准结构，能够减少寄生效应，提升器件性能。
在一种可能的实现方式中，该场效应晶体管结构还包括：衬底，该衬底具有一凹槽，该凹槽与该顶栅电极的形状相同；其中，该底栅电极设置于该凹槽中，该顶栅电极位于该底栅电极的正上方。
底栅和顶栅结构上下对称，有利于更好地控制沟道。
可选地，该场效应晶体管结构还可以采用上下两个有错位的双栅结构，通过双栅的错位结构形成三个不同的沟道区域，两边可以为不同掺杂的沟道，中间可以为能够打开带隙的沟道。
在一种可能的实现方式中，该底栅电极还具有支撑该场效应晶体管结构的作用。
底栅既有导电作用，又有支撑作用，制作简单。
在一种可能的实现方式中，该第一栅极的栅极介质层和/或第二栅极的栅极介质层的厚度为2nm～20nm。
使用较薄的栅介质层，能够进一步有效地减小栅介质中电荷中心的影响，从而可以提升器件开关比。
在一种可能的实现方式中，该第一栅极的栅极介质层和该第二栅极的栅极介质层的材料相同。
采用相同材料制作底栅介质层和顶栅介质层，有利于优化器件性能。
可选地，还可以采用相同的工艺制作该第一栅极的栅极介质层和该第二栅极的栅极介质层。
结合上述第一方面的一些方面，在第一方面的第七种可能的实现方式中，该第一栅极和/或该第二栅极的栅极介质层的材料包括常见金属氧化物或高k氧化物，该源电极和该漏电极的材料包括常用低电阻率并能和石墨烯形成有效欧姆接触的材料。
可选地，该源电极和该漏电极的材料为金、钛、镍、铂、铬、铝、铜和 钨中的至少一种。
可选地，该衬底的材料为半导体或绝缘体，可以是透明或不透明的。
第二方面，提供了一种场效应晶体管结构的制作方法，该制作方法包括：制作底栅电极；在该底栅电极的上表面制作底栅介质层；在该底栅介质层表面生长双层石墨烯或将双层石墨烯转移到该底栅介质层表面上；在该双层石墨烯上进行一次光刻和刻蚀，形成由多个平行间隔开的双层石墨烯纳米条带构成的纳米条带沟道层；在该纳米条带沟道层的上表面进行一次光刻形成源极和漏极的电极，该源极的长度方向和该漏极的长度方向均与该纳米条带沟道层的沟道方向有夹角，该源极和该漏极之间具有平行间距；在该源极和该漏极之间的该纳米条带沟道层的上表面制作顶栅介质层；在该顶栅介质层上制作该顶栅电极。
在一种可能的实现方式中，该制作底栅电极包括：提供一衬底；在该衬底上进行一次光刻和刻蚀形成一凹槽；在该凹槽内通过蒸发金属形成该底栅电极，该顶栅电极与该底栅电极的形状相同且位于该底栅电极的正上方。
更多的方面和实施例将通过下面的详细描述加以呈现。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例中所需要使用的附图作简单地介绍，显而易见地，下面所描述的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了双层石墨烯施加垂直电场示意图。
图2示出了本发明实施例提供的场效应晶体管结构的一种示意图。
图3示出了本发明实施例提供的场效应晶体管结构的另一示意图。
图4(a)～图4(g)示出了本发明实施例提供的制作图2所示的场效应晶体管结构的说明图。
图5(a)～图5(h)示出了本发明实施例提供的制作图3所示的场效应晶体管结构的说明图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行 清楚、完整地描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都应属于本发明保护的范围。
石墨烯是一种新型二维平面结构碳材料。自发现以来，其独特的分子结构和优异的物理性能引起了学者和产业界的广泛关注。作为一种理想的二维材料，石墨烯表现出了诸多神奇的物理特性。包括超高的载流子迁移率(高达230000cm2/Vs)和电导率(高达105S/m)、能带可调性以及异常的整数量子霍尔效应等。石墨烯拥有极不寻常的载流子行为，像静质量为零的相对论粒子(狄拉克费米子)。由于狄拉克费米子的运动和电子不同，当在石墨烯上施加磁场时，将导致异常的量子霍尔效应出现。石墨烯的导带和价带的交点在第一布里渊区的六个顶点处，在这些点附近的电子色散关系符合相对论狄拉克电子的特征，因而这些交点也称为狄拉克点，石墨烯的导带底和价带顶在狄拉克点处简并，从而形成为零带隙的半导体，呈现金属性。为了能满足基于石墨烯半导体器件的需求，发展石墨烯打开带隙的技术具有重要意义。
研究发现，双层石墨烯与单层石墨烯相比能带结构有较大的差异，并且双层石墨烯因其双层石墨原子层的堆垛结构和在功能化改性方面的优势，通过在其上施加垂直的电场，比单层石墨烯更容易打开带隙，尤其是当双层石墨烯成AB次序堆叠(也称Bernal堆叠)时。在传统半导体中，晶格常数不变，因此带隙是固定的，通过掺杂只能改变费米能级的位置。通过应力工程可以改变沟道的带隙，但器件一旦做好，带隙就不能改变。对双层石墨烯施加垂直的电场，带隙会跟着改变，这一点是传统半导体材料不具有的特性，给双层的应用提供了更多的想象空间。
应理解，本发明实施例提供的基于石墨烯制作的电子器件可以包括场效应晶体管、传感器、太阳能电池等。为了描述方面，以下将以石墨烯场效应晶体管为例进行描述，本发明并不限于此。
图2和图3示出了本发明实施例的场效应晶体管结构两种示意图。如图2和图3所示，该场效应晶体管自下而上包括：底栅电极201、底栅介质层202、纳米条带沟道层203、顶栅介质层204、顶栅电极205、源电极206和漏电极207，其中，该底栅电极201和该顶栅电极205分别与除该场效应晶体管以外的外部电路相连，对该纳米条带沟道层203施加垂直的电场。该纳米条带沟道层设置于顶栅介质层204和底栅介质层202之间，且与底栅介质 层202以及顶栅介质层204表面接触，该纳米条带沟道层203是由多条平行间隔开来的双层石墨烯纳米条带构成，该源电极206和该漏电极207分别与该纳米条带沟道层203接触。
场效应晶体管的开关比为开态电流与关闭电流之比，由于石墨烯不存在带隙，石墨烯场效应晶体管无法完全关断，开关比较小，因此在逻辑器件的应用上具有很大的局限。而本发明实施例提供的场效应晶体管结构，采用多条平行间隔的双层石墨烯纳米条带作为沟道层，能够在不牺牲器件开态电流的情况下，有效地减少栅介质电荷中心的影响，使器件能够有较好的关断，提升器件开关比。
示例性地，在本发明实施例中，底栅电极和底栅介质层可以是如图2所示的采用全局底栅结构，换句话说，本发明实施例的底栅电极还可以具有支撑场效应晶体管结构的作用。将衬底和底栅电极的作用合二为一，制作简单。
示例性地，底栅电极和底栅介质层也可以是如图3所示的采用嵌入式的局部底栅结构；或者也可以是底栅电极采用局部结构，而底栅介质层采用全局结构，具体地，在本发明实施例中，该场效应晶体管结构还包括：衬底，该衬底具有一凹槽；其中，该底栅电极设置于该凹槽中，该顶栅电极与该底栅电极的形状相同且位于该底栅电极的正上方。将底栅嵌入到衬底中，和顶栅结构上下对称，从而可以更好地控制沟道。
该场效应晶体管结构还可以采用上下两个有错位的双栅结构，通过双栅的错位结构形成三个不同的沟道区域，两边可以为不同掺杂的沟道，中间可以为能够打开带隙的沟道。
可选地，在本发明实施例中的底栅介质层可以是全部覆盖底栅电极的上表面，也可以是部分覆盖。该底栅介质层还可以覆盖于该源极和/或该漏极的至少部分上表面。
应理解，在本发明实施例的“覆盖”均可以既指全部覆盖，也可以指部分覆盖。
还应理解，在本发明实施例中，应不限于采用双层石墨烯，还可以是单层石墨烯或其他的二维材料。只要构成的沟道能够提高在不牺牲器件开态电流的情况下，提升器件开关比的方案都在本发明保护范围之内。
需要说明的是，第一，本发明实施例中的双层石墨烯纳米条带的方向可以是图2或图3所示的与源电极和漏电极的方向垂直，也可以与源电极和漏 电极的方向带有任一角度，本发明实施例仅以图2或图3为例描述，但本发明并不限于此。
第二，本发明实施例提供的源电极和漏电极之间的间距可以是如图2或图3所示的大于顶栅的栅极电极的宽度，也可以是栅极电极的宽度等于源电极和漏电极之间的间距(即通常所说的自对准结构)。本发明实施例的源电极和漏电极之间的间距是指如图2或如图3所示的源极的最右端到漏极的最左端，具体地，顶栅电介质层可以覆盖源极和/或漏极的至少部分上表面，并在该源极和该漏极之间采用自对准结构或其他工艺制作，从而减少寄生效应，提升器件性能。
随硅栅工艺的发展，已可以实现栅极与源电极和漏电极的自对准。采用的工艺是：在石墨烯上首先淀积种子层和金属氧化物层，作为栅介质，然后制作T型栅极结构，由于T型栅的保护，下一步蒸发源漏电极的时候形成自对准。借以减小寄生电容,可提高场效应晶体管结构的开关速度和工作频率，同时也减小器件尺寸而提高电路的集成度。
第三，本发明实施例提供的场效应晶体管结构，源电极和漏电极可以采用如图2或图3所述的在纳米条带沟道层上表面制作电接触，也可以在那纳米条带沟道层的侧面制作电接触，或采用肖特基接触，例如，也可以是在底栅介质上与纳米条带沟道层的双侧接触。具体地，该源极和该漏极覆盖于该底栅介质层的上表面，该源极和该漏极分别与该纳米条带沟道层相对的两侧接触，该源极的长度方向与该漏极的长度方向均与该沟道方向垂直。本发明对源漏电极与栅极的电接触方式不作限定，接触面积越大，接触电阻有望做的越小。
在本发明实施例中，可以采用光刻和刻蚀的工艺制作双层石墨烯纳米条带，双层石墨烯纳米条带的宽度应大于10nm，典型值为50～200nm。研究发现，纳米条带结构可以切断由于电荷中心导致沟道中存在电子的“短路通道”。目前采用纳米条带打开石墨烯带隙的方法，利用的是量子限制效应原理，采用宽度小于10nm的纳米条带，在这个尺度下，纳米条带的性能、宽度以及边沿态对带隙及迁移率都有较大影响。此外，较窄的石墨烯纳米条带在制作上涉及到原子级精度的操控，制作工艺上有一定的难度。具体地，双层石墨烯纳米条带的宽度需要根据工艺条件进行优化，比如生长较好的栅介质可以使用较宽的条带，反之则减小条带宽度。本发明实施例采用多条百纳 米量级的双层石墨烯纳米条带，可以提高双层石墨烯的带隙以及器件开关比，不会受到边沿态等的影响，并且能够降低在制作工艺上的难度。
示例性地，在本发明实施例中，可以采用较薄的栅极介质层，其厚度典型值为2～20nm(以采用氧化铪为例)。由于双层石墨烯晶体管的栅介质中不可避免的存在缺陷和杂质，引入了电荷中心，部分屏蔽掉栅电场，使该处带隙无法被调制，形成漏电通道。如果采用较厚的栅介质层，其漏电会更严重，因此，本发明实施例中指的薄一般是指在100nm以内，采用较薄的栅介质层，能够有效减小栅介质中电荷中心的影响。
可选地，在本发明实施例中，顶栅和底栅的栅介质和栅的材料可以相同，还可以采用相同的工艺制作该底栅的栅介质和该顶栅的栅介质。这样更有利于器件的性能。
可选地，该栅极介质层的材料包括常用的金属氧化物或高k氧化物，或者是二维电介质材料如氮化硼；该源电极和该漏电极的材料包括低电阻率且能与石墨烯形成较好欧姆接触的金属；该衬底的材料包括半导体或绝缘体，可以是透明或不透明的。具体地，该源电极和该漏电极的材料包括以下材料中的至少一种材料：金、钛、镍、铂、铬、铝、铜和钨。
本发明实施例中的场效应晶体管结构可以制作在绝缘衬底上，衬底可以是透明或不透明的柔性衬底，柔性的栅控式场发射三极管(Gate Field Emission Triode，GFET)高频器件可以应用在可弯曲折叠的电子设备上面。
因此，本发明实施例提供的场效应晶体管结构，采用多条平行的双层石墨烯纳米条带结构作为沟道，能够在不牺牲开态电流(高达几百毫安或者更大)的情况下，有效地减少栅介质电荷中心的影响，使器件能够较好的关断，提升器件开关比(可以高达两到三个数量级)，使器件输出能力增强。采用较薄的栅介质层，能够进一步减小栅介质中电荷中心的影响。本发明实施例提供的器件结构和传统的平面工艺兼容，容易实现低成本批量制作。
下面将结合图4和图5详细描述本发明实施例提供的场效应晶体管结构的制作方法。
图4是本发明实施例提供的制作如图2所示的场效应晶体管结构的说明图，应理解，为了说明工艺效果，说明图中并不是按照实际器件结构比例所画，具体制作工艺步骤如下：
步骤1：如图4(a)所示，准备衬底材料，衬底材料需要能够导电，可以 是常见的Si，Ge等半导体。所述衬底可为矩形衬底，衬底的掺杂浓度可为轻掺杂，掺杂浓度为1014～1016cm-3。
步骤2：如图4(b)所示，制作底栅介质。底栅介质可以是三氧化二铝、二氧化铪或氧化钇等常用的栅极介质材料。栅介质可以采用原子层沉积(Atomic-layer deposition，ALD)方法制作。采用较薄的底栅介质层，厚度典型值为5～20nm。
步骤3：如图4(c)所示，生长或转移双层石墨烯。双层石墨烯可以通过直接生长的方法在底栅介质表面制作，也可以通过化学气相沉积(Chemical vapor deposition，CVD)方法生长，然后转移到底栅介质上。
目前石墨烯的制备方法主要有：微机械剥离法、热解SiC法、化学剥离还原法、刻蚀碳纳米管法以及化学气相沉淀法等。举例来说，利用CVD法制备石墨烯的流程是：首先，将金属箔或载有金属薄膜的基片置于反应炉中；其次，通入甲烷、氢气、氩气的混合气体并将腔体加热到1000℃，使甲烷气体在高温下分解；最后经过快速降温。本发明实施例对制作双层石墨烯的方法不作限制。
步骤4：如图4(d)所示，制作双层石墨烯纳米条带。该步骤可以在双层石墨烯上进行一次光刻和刻蚀，形成双层石墨烯纳米条带。纳米条带的宽度需要根据栅介质的质量进行优化选择，典型值为百纳米量级。比如，生长的栅介质层质量比较好，则可以使用较宽的条带，反之则减小条带宽度。
步骤5：如图4(e)所示，制作源漏电极。该步骤可以在双层石墨烯纳米条带的两端进行一次光刻形成源漏电极图形和一次金属蒸发。电极材料可以选用金、钛、镍、铂、铬、铝、铜或钨等常用的金属。
步骤6：如图4(f)所示，制作顶栅介质层。该顶栅介质层和底栅介质层制作过程可以相同。
步骤7：如图4(g)所示，制作顶栅电极。该步骤可以在双层石墨烯纳米条带上以及源漏电极之间进行一次光刻形成栅极图形和一次金属蒸发。电极材料可以选用金、钛、镍、铂、铬、铝、铜或钨等常用的金属。
图5是本发明实施例提供的制作如图3所示的场效应晶体管结构的说明图，应理解，为了说明工艺效果，说明图中并不是按照实际器件结构比例所画，具体制作工艺步骤如下：
步骤1：如图5(a)所示，准备衬底材料，衬底材料可以是常见的硅/二氧 化硅，碳化硅，氮化硼，氮化硅，也可以是其他绝缘材料如涤纶树脂、蓝宝石等。在本实施例中，衬底可以没有底栅的作用，仅仅起到支撑器件的作用，不参与器件功能。
步骤2：如图5(b)所示，制作底栅电极。该步骤需要进行一次光刻和刻蚀在衬底上形成沟槽，接着蒸发金属形成底栅电极，然后腐蚀掉牺牲层得到嵌入的底栅电极。
步骤3：如图5(c)所示，制作底栅介质层。底栅介质可以是三氧化二铝、二氧化铪或氧化钇等常用的栅极介质材料。栅介质可以采用原子层沉积(Atomic-layer deposition，ALD)方法制作。采用较薄的底栅介质层，厚度典型值为5～20nm。
步骤4：如图5(d)所示，生长或转移双层石墨烯。双层石墨烯可以通过直接生长的方法在底栅介质表面制作，也可以通过化学气相沉积(Chemical vapor deposition，CVD)方法生长，然后转移到底栅介质上。
步骤5：如图5(e)所示，制作双层石墨烯纳米条带。该步骤需要进行一次光刻和刻蚀，形成双层石墨烯纳米条带。纳米条带的宽度需要根据栅介质的质量进行优化选择，典型值为百纳米量级。比如，生长的栅介质层质量比较好，则可以使用较宽的条带，反之则减小条带宽度。
步骤6：如图5(f)所示，制作源漏电极。该步骤需要可以在双层石墨烯纳米条带的两端进行一次光刻形成源漏电极图形和一次金属蒸发。电极材料可以选用金、钛、镍、铂、铬、铝、铜或钨等常用的金属。
步骤7：如图5(g)所示，制作顶栅介质层。该顶栅介质层和底栅介质层制作过程可以相同。
步骤8：如图5(h)所示，制作顶栅电极。该步骤可以在双层石墨烯纳米条带上以及源漏电极之间进行一次光刻形成栅极图形和一次金属蒸发。电极材料可以选用金、钛、镍、铂、铝、铜或钨等常用的金属。
需要说明的是，本发明实施例提供的场效应晶体管结构的制作方法仅是示意性说明，本发明对每个部件的制作工艺并不限定。例如，可以利用电子束光刻以及电子束蒸发回流工艺在衬底上淀积底栅电极；用CVD法生长六方氮化硼h-BN薄膜转移到所述底栅金属电极上作为栅介质；栅介质层可以采用多步生长工艺完成，如先生长一层几纳米厚的钇，然后将其氧化，再在其上生长一层氧化铪；利用电子束光刻以及金属蒸发回流工艺淀积源电极和 漏电极；利用电子束光刻以及电子束蒸发回流工艺淀积顶栅金属电极；利用多步生长得到栅电极，如先生长一层几纳米厚与石墨烯粘附较好的钛，再在其上生长电阻率较低的金形成电极。
应理解，在本发明的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
另外，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
应理解，在本发明实施例中，“与A相应的B”表示B与A相关联，根据A可以确定B。但还应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
还应理解，在本文中使用的，除非上下文清楚地支持例外情况，单数形式“一个”(“a”、“an”、“the”)旨在也包括复数形式。还应当理解的是，在本文中使用的“和/或”是指包括一个或者一个以上相关联地列出的项目的任意和所有可能组合。
虽然现在本发明优选的实施例已经在此处描述，应理解，所用的术语的目的是具有描述性而非限制性词语的本质。对于本领域技术人员显然的是，根据上述教导，可以得出本发明的许多改型和变体。因此，应该理解，在附带的权利要求书的范围内，其中附图标记仅为方便而使用，并非以任何方式进行限制，本发明可以采用除上面具体描述之外的其他方式实施。

Claims (13)

  1. 一种场效应晶体管结构，其特征在于，所述场效应晶体管结构包括：
    底栅电极；
    底栅介质层，所述底栅介质层覆盖于所述底栅电极的上表面，且与所述底栅电极的上表面接触；
    纳米条带沟道层，所述纳米条带沟道层是由多个平行间隔开的双层石墨烯纳米条带构成，所述纳米条带沟道层覆盖于所述底栅介质层的上表面，且与所述底栅介质层的上表面接触；
    源极和漏极，所述源极和所述漏极之间具有平行间距，且分别与所述纳米条带沟道层接触，所述源极的长度方向和所述漏极的长度方向均与所述纳米条带沟道层的沟道方向有夹角，所述源极的上表面与所述漏极的上表面均与所述纳米条带沟道层的上表面平行；
    顶栅介质层，所述顶栅介质层覆盖于所述源极和所述漏极之间的所述纳米条带沟道层的上表面，且与所述纳米条带沟道层的上表面接触；
    顶栅电极，所述顶栅电极覆盖于所述顶栅介质层的上表面，且与所述顶栅介质层的上表面接触，所述顶栅电极与所述底栅电极通过除所述场效应晶体管结构以外的电路相连。
  2. 根据权利要求1所述的场效应晶体管结构，其特征在于，所述多个平行间隔开的双层石墨烯纳米条带中的每个双层石墨烯纳米条带的宽度为50nm～200nm。
  3. 根据权利要求1或2所述的场效应晶体管结构，其特征在于，所述源极和所述漏极覆盖于所述纳米条带沟道层的上表面。
  4. 根据权利要求1或2所述的场效应晶体管结构，其特征在于，所述源极和所述漏极覆盖于所述底栅介质层的上表面，所述源极和所述漏极分别与所述纳米条带沟道层相对的两侧接触，所述源极的长度方向与所述漏极的长度方向均与所述沟道方向垂直。
  5. 根据权利要求1至4中任一项所述的场效应晶体管结构，其特征在于，所述场效应晶体管结构还包括：
    衬底，所述衬底具有一凹槽，所述凹槽与所述顶栅电极的形状相同；
    其中，所述底栅电极设置于所述凹槽中，所述顶栅电极位于所述底栅电极的正上方。
  6. 根据权利要求1至5中任一项所述的场效应晶体管结构，其特征在于，所述底栅电极还具有支撑所述场效应晶体管结构的作用。
  7. 根据权利要求5所述的场效应晶体管结构，其特征在于，所述顶栅电极和所述底栅电极的宽度均等于所述源极和所述漏极之间的间距。
  8. 根据权利要求1至7中任一项所述的场效应晶体管结构，其特征在于，所述顶栅介质层还覆盖于所述源极和/或所述漏极的至少部分上表面。
  9. 根据权利要求1至8中任一项所述的场效应晶体管结构，其特征在于，所述底栅介质层和/或所述顶栅介质层的厚度为2nm～20nm。
  10. 根据权利要求1至9中任一项所述的场效应晶体管结构，其特征在于，所述底栅介质层和所述顶栅介质层的材料相同。
  11. 根据权利要求1至10中任一项所述的场效应晶体管结构，其特征在于，所述底栅介质层和/或所述顶栅介质层的材料包括高k介质材料，所述源电极和所述漏电极的材料包括以下材料中的至少一种：金、钛、镍、铬、铝、铜和钨。
  12. 一种场效应晶体管结构的制作方法，其特征在于，所述制作方法包括：
    制作底栅电极；
    在所述底栅电极的上表面制作底栅介质层；
    在所述底栅介质层表面生长双层石墨烯或将双层石墨烯转移到所述底栅介质层表面上；
    在所述双层石墨烯上进行一次光刻和刻蚀，形成由多个平行间隔开的双层石墨烯纳米条带构成的纳米条带沟道层；
    在所述纳米条带沟道层的上表面进行一次光刻形成源极和漏极的电极，所述源极的长度方向和所述漏极的长度方向均与所述纳米条带沟道层的沟道方向有夹角，所述源极和所述漏极之间具有平行间距；
    在所述源极和所述漏极之间的所述纳米条带沟道层的上表面制作顶栅介质层；
    在所述顶栅介质层上制作所述顶栅电极。
  13. 根据权利要求12所述的制作方法，其特征在于，所述制作底栅电极包括：
    提供一衬底；
    在所述衬底上进行一次光刻和刻蚀形成一凹槽；
    在所述凹槽内通过蒸发金属形成所述底栅电极，所述顶栅电极与所述底栅电极的形状相同且位于所述底栅电极的正上方。
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