WO2018072424A1 - 一种多芯片框架封装结构及其制造方法 - Google Patents

一种多芯片框架封装结构及其制造方法 Download PDF

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Publication number
WO2018072424A1
WO2018072424A1 PCT/CN2017/082262 CN2017082262W WO2018072424A1 WO 2018072424 A1 WO2018072424 A1 WO 2018072424A1 CN 2017082262 W CN2017082262 W CN 2017082262W WO 2018072424 A1 WO2018072424 A1 WO 2018072424A1
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Prior art keywords
chip
dielectric layer
package structure
layer
stage
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English (en)
French (fr)
Inventor
谢业磊
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present invention relates to semiconductor device packaging technology, and more particularly to a multi-chip frame package structure and a method of fabricating the same.
  • SiP System-in-package
  • QFP Quad Flat Package
  • the size of the chip carrier is closely related to the number of pins of the chip, thus limiting the feasibility of implementing SiP using QFP.
  • frame-type packages are usually used to implement SiP.
  • SiP packages are completed, the size of different components can seriously limit the package density. Especially for thinner products, the number of packageable components becomes a framework-type package and promotes SiP technology. The more serious problems encountered.
  • embodiments of the present invention provide a multi-chip frame package structure and a manufacturing method thereof to solve at least the above technical problems.
  • a first aspect of the embodiments of the present invention provides a multi-chip frame package structure, the package structure including: at least one carrier stage, at least one underlying chip, and at least one upper layer chip; the at least one stage is configured to be accommodated The at least one underlying chip and the at least one upper layer chip; the package structure further comprising: at least one first dielectric layer; wherein
  • the first dielectric layer is disposed above the underlying chip; the upper chip is disposed above the first dielectric layer; the underlying chip can be adjusted by adjusting an inclination angle of the first dielectric layer The positional relationship between the upper chips in order to increase the number of chips stacked on the at least one stage.
  • the package structure further includes: at least one second dielectric layer;
  • the second dielectric layer is disposed above the first layer upper chip of the at least one upper chip, and the second upper layer chip of the at least one upper chip is disposed above the second dielectric layer; wherein, by adjusting The tilt angle of the second dielectric layer can adjust a positional relationship between the first layer upper chip and the second layer upper chip in order to increase the number of chips stacked on the at least one stage.
  • the package structure further includes: a ground plane, a dielectric frame, and an extraction pin;
  • the ground plane is configured to connect to the underlying chip and/or the upper layer chip needs to be connected Ground pad
  • the lead-out pin is configured to connect the bottom chip and/or the pad on the upper chip that needs to be externally led out;
  • the medium frame is configured to connect the at least one stage, the ground plane, and the lead-out pin, and is configured to support the multi-chip frame package structure to ensure the multi-chip frame
  • the structure of the package structure is firm.
  • the package structure further includes: a molding body
  • the molding body is configured to package the at least one carrier stage, the at least one underlying chip, the at least one upper layer chip, and the at least one first dielectric layer to: the at least one stage, at least one underlying chip, at least An upper chip and at least one first dielectric layer are encapsulated inside the plastic body.
  • the package structure further includes: at least one third dielectric layer and at least one top chip;
  • the third dielectric layer is disposed above the molding body, and the top chip is disposed above the third dielectric layer, and the top chip can be adjusted by adjusting an inclination angle of the third dielectric layer
  • the position on the molding body is such as to increase the number of chips stacked on the at least one stage.
  • the package structure further includes: a metal connection line;
  • the metal connection line is configured to connect pads between each of the bottom chip of the at least one underlying chip or each of the at least one upper chip; and/or, the underlying chip and the upper layer a pad connection between the chips; and/or a pad of the chip in the underlying chip and the upper chip that needs to be connected to the lead pin, the ground plane, and the lead pin and the ground Flat connection.
  • a second aspect of the embodiments of the present invention provides a method for fabricating a multi-chip frame package structure, the package structure including: at least one carrier stage, at least one underlying chip, and at least one upper layer a chip and at least one first dielectric layer; the method comprising:
  • the upper chip is disposed above the first dielectric layer, and the upper chip is disposed above the first dielectric layer; wherein the bottom chip can be adjusted by adjusting an inclination angle of the first dielectric layer a positional relationship with the upper chip to facilitate increasing the number of chips stacked on the at least one stage.
  • the package structure further includes: at least one second dielectric layer; and correspondingly, the method further includes:
  • Adjusting the tilt angle of the second dielectric layer can adjust a positional relationship between the first layer upper chip and the second layer upper chip in order to increase the number of chips stacked on the at least one stage.
  • the package structure further includes: a molding body; correspondingly, the method further includes:
  • Encapsulating the at least one carrier stage, the at least one underlying chip, the at least one upper layer chip, and the at least one first dielectric layer to form the molding body to at least one of the carrier stages, at least one underlying chip, at least An upper chip and at least one first dielectric layer are encapsulated inside the plastic body.
  • the package structure further includes: at least one third dielectric layer and at least one top chip; and correspondingly, the method further includes:
  • the third dielectric layer is disposed above the molding body, and the top chip is disposed above the third dielectric layer, wherein the tilt angle of the third dielectric layer can be adjusted
  • the position of the top chip on the molding body is to increase the number of chips stacked on the at least one stage.
  • the multi-chip frame package structure and the manufacturing method thereof according to the embodiments of the present invention can skillfully make the chips are angularly offset from each other through various dielectric layers of oblique angles, so that the stacked chips have enough space to wire, so
  • the embodiment of the invention can effectively increase the number of the frame SiP package sealing chip, meet the requirements of the diversification of the package, and effectively solve the problem that the existing SiP frame package structure has limited number of chips in the multi-chip package, and the problem is increased.
  • the number of stacked chips lays the foundation for adapting to the current demand for lighter and thinner products.
  • FIG. 1 is a schematic structural view 1 of a multi-chip frame package structure according to an embodiment of the present invention
  • FIG. 2 to FIG. 4 are schematic structural diagrams of a multi-chip frame package structure in a manufacturing process according to an embodiment of the present invention
  • FIG. 5 is a second schematic structural diagram of a multi-chip frame package structure according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram 3 of a multi-chip frame package structure according to an embodiment of the present invention.
  • the multi-chip frame package structure can effectively increase the number of packaged SiP packaged and sealed chips, meets the requirements of diverse packages, and effectively solves the problem that the existing SiP frame package structure has a limited number of chips for multi-chip packaging; specifically,
  • the multi-chip frame package structure includes: at least one stage, at least one underlying chip, and at least one upper chip; the at least one stage is configured to receive the at least one underlying chip and the at least one upper chip;
  • the package structure further includes: at least one first dielectric layer; wherein the first dielectric layer is disposed above the underlying chip; the upper chip is disposed above the first dielectric layer; The tilt angle of a dielectric layer can adjust a positional relationship between the underlying chip and the upper chip to increase the number of chips stacked on the at least one stage.
  • the package structure further includes: a ground plane, a dielectric frame, an extraction lead, and a plastic package; wherein
  • the ground plane is configured to connect the underlying chip and/or the pad on the upper chip that needs to be grounded;
  • the lead-out pin is configured to connect the bottom chip and/or the pad on the upper chip that needs to be externally led out;
  • the medium frame is configured to connect the at least one stage, the ground plane, and the lead-out pin, and is configured to support the multi-chip frame package structure to ensure the multi-chip frame
  • the structure of the package structure is firm
  • the molding body is configured to package the at least one carrier stage, the at least one underlying chip, the at least one upper layer chip, and the at least one first dielectric layer to: the at least one stage, at least one underlying chip, at least An upper chip and at least one first dielectric layer are encapsulated inside the plastic body.
  • the molding body is configured to encapsulate the at least one carrier stage, the at least one underlying chip, the at least one upper layer chip, and the at least one first dielectric layer, and the ground plane, the dielectric frame, and the lead-out pins.
  • the multi-chip frame package structure includes:
  • the stage 102 is made of a metal material, and is configured to place a chip (such as an underlying chip and an upper chip) to be packaged; here, the underlying chip and the upper chip may be specifically a semiconductor chip; Correspondingly, the stage 102 is specifically configured to carry a semiconductor chip to be packaged and has a heat conducting effect;
  • a chip such as an underlying chip and an upper chip
  • the ground plane 103 is made of a metal material and is configured to connect pads (or pins) on the chip (such as the upper chip and/or the bottom chip) in the carrier 102 to be grounded; specifically, configured to provide The ground connection between the pad (or pin) of the chip and the external ground plane of the package (that is, the multi-chip frame package structure);
  • the lead pin 101 is configured to be connected to a chip (such as a chip on the upper layer and/or an underlying chip) in the stage 102 to be externally extracted; specifically, configured to provide a chip pad (or pin) and Electrical connection path of the external pins of the package;
  • a chip such as a chip on the upper layer and/or an underlying chip
  • the medium frame 104 is configured to connect the stage 102, the ground plane 103, and the lead-out pin 101, and is configured to support the entire package structure (ie, a package) to ensure the entire package.
  • the structure is firm.
  • At least one underlying chip 105 is laid flat above the stage 102;
  • At least one first dielectric layer 107 is placed over the underlying chip 105, and at least one upper chip 108 may be placed over the first dielectric layer 107.
  • the upper chip 108 may be in the form of a metal wire.
  • the bottom layer chips 105 are electrically connected through the pads 106; the upper layer chips 108 may be electrically connected to the ground plane 103 or the lead-out pins 101 by metal wire bonding;
  • the molding body 109 is configured to connect the stage 102, the ground plane 103, the lead pin 101, the dielectric frame 104, the underlying chip 105, the dielectric layer 107, the upper chip 108, and the chip (the upper chip and/or the lower chip)
  • the upper pad is plasticized to place the stage 102, the ground plane 103, the lead pin 101, the dielectric frame 104, the underlying chip 105, the pad 106 on the chip, and the dielectric layer 107.
  • the upper chip 108 is wrapped around the inside of the molding body 109. In practical applications, the molding body 109 is used to fill the entire package after the entire semiconductor chip is placed.
  • the package structure further includes: a metal connection line; wherein the metal connection line is configured to be the bottom chip or the bottom layer of the at least one underlying chip a pad connection between each of the upper chips in the at least one upper chip; and/or connecting the pad between the underlying chip and the upper chip; and/or, the underlying chip and the upper layer A pad of a chip in the chip that needs to be connected to the lead pin and a ground plane is connected to the lead pin and the ground plane. That is to say, in practical applications, the metal connection line is configured to connect the underlying chip, the upper chip, the lead-out pin, and the components in the ground plane that need to be connected.
  • the package structure further includes: at least one second dielectric layer; the second dielectric layer is disposed above the first layer upper chip of the at least one upper chip, the at least one upper chip a second upper layer chip is disposed above the second dielectric layer; wherein, between adjusting the tilt angle of the second dielectric layer, between the first layer upper chip and the second layer upper chip Positional relationship in order to increase the number of chips stacked on the at least one stage. That is to say, the positional relationship can also be adjusted through the dielectric layer between the upper chips, so that the positional relationship between the upper chips can be further adjusted, thereby facilitating the increase of the number of chips stacked on the at least one stage.
  • the package structure further includes: at least one third dielectric layer and at least one top chip; the third dielectric layer is disposed above the molding body, and the top chip is placed in the Above the third dielectric layer, the position of the top chip on the molding body can be adjusted by adjusting the inclination angle of the third dielectric layer, so as to increase the number of chips stacked on the at least one stage. That is to say, a dielectric layer can be further stacked on the upper chip, and an upper layer chip is stacked on the dielectric layer, so that it is convenient to adapt to the application scenario of multi-chip sealing.
  • the multi-chip frame package structure according to the embodiment of the present invention can ingeniously change the positional relationship between the stacked semiconductor chips by changing the shape of the dielectric layer added when stacking the semiconductor chips, thereby effectively improving the multi-layer chip playing.
  • the line space makes full use of the inner space of the package size, and completes more chip sealing in the same frame, which solves the problem that the chip cannot be properly stacked due to the excessive size of the chip in the prior art, and the problem that the excessive chip cannot be sealed is solved. .
  • the embodiment of the present invention can make the chips are angularly offset from each other through various inclined angle dielectric layers, so that the stacked chips have enough space to wire, thereby increasing the number of stacked chips, so as to adapt to the current It lays the foundation for the needs of lighter and thinner product applications.
  • the embodiment of the present invention completes stacking of multiple chips by changing the dielectric layer, the embodiment of the present invention is lower in cost and meets the existing high performance and low cost compared with the existing method of changing the frame. Chip development needs.
  • the embodiment provides a method for manufacturing a multi-chip frame package structure according to the first embodiment. Specifically, the method includes:
  • the package structure further includes: at least one second dielectric layer; and correspondingly, the method further includes: disposing the second layer above the first layer upper chip in the at least one upper chip a dielectric layer, a second layer upper chip of the at least one upper chip is disposed above the second dielectric layer, wherein the first layer upper chip and the first layer can be adjusted by adjusting an inclination angle of the second dielectric layer Positional relationship between the upper layers of the second layer so that And increasing the number of chips stacked on the at least one stage.
  • the package structure further includes: a molding body; and correspondingly, the method further includes: the at least one stage, at least one underlying chip, at least one upper chip, and at least one A dielectric layer is packaged to form the molding body to encapsulate the at least one carrier stage, the at least one underlying chip, the at least one upper layer chip, and the at least one first dielectric layer in the interior of the molding body.
  • the package structure further includes: at least one third dielectric layer and at least one top chip; respectively, the method further includes: disposing the third dielectric layer above the molding body, The top chip is disposed above the third dielectric layer, wherein a position of the top chip on the molding body can be adjusted by adjusting an inclination angle of the third dielectric layer, so as to increase the at least one slide The number of chips stacked on the stage.
  • FIG. 4 are schematic structural diagrams of a multi-chip frame package structure in a manufacturing process according to an embodiment of the present invention; the method according to the embodiment of the present invention is further described in detail below with reference to FIG. 2 to FIG. 4;
  • Step 1 as shown in FIG. 2, using a Candence SiP design software to complete a design of a multi-chip frame package structure having good heat dissipation characteristics; specifically, the multi-chip frame package structure includes a centrally located stage 102, distributed A lead pin 101 and a ground plane 103 around the stage 102, and a dielectric frame 104 connecting the stage 102, the lead pin 101, and the ground plane 103.
  • a Kovar alloy Fe-Ni-Co
  • a multi-layer method as shown in FIG. 1 is prepared by a punching method.
  • the chip frame; further, using hexagonal boron nitride as the material of the dielectric frame 104, the stage 102, the lead-out pin 101, and the ground plane 103 are partially joined by a die.
  • the stage can be a single block or a plurality of spaced planes.
  • the ground planes can be distributed around the entire package.
  • the lead pin can be divided Spread around the entire package.
  • Step 2 as shown in FIG. 3, a bottom chip 105 is laid on the upper surface of the stage 102, and the bottom chip 105 is bonded to the stage 102 by a conductive silver paste 110.
  • Step 3 a metal bump 106 is prepared on the upper surface of the underlying chip 105, and the metal bump 106 is made of gold. Between the metal bumps 106 on the underlying chip 105, and the metal bumps 106 on the underlying chip 105 and the ground plane 103 and the lead-out pins 101, by ultrasonic bonding technology, according to the metal The preparation of the electrical interconnection 111 is completed in the form of a wire.
  • the material of the interconnect is silver.
  • Step 4 as shown in FIG. 4, a first dielectric layer 107 is placed on the underlying chip 105, and the first dielectric layer 107 is bonded over the underlying chip 105 by a die attach film 112.
  • the material of the first dielectric layer 107 is hexagonal boron nitride.
  • the first dielectric layer may be set to a different shape as needed.
  • Step 5 as shown in FIG. 4, an upper layer chip 108 is placed on the upper surface of the first dielectric layer 107, and the upper layer chip 108 is bonded over the first dielectric layer 107 by a die bonding film.
  • a metal bump 106 is prepared on the upper surface of the upper chip 108, and the metal bump 106 is made of gold.
  • the metal bumps 106 on the upper chip 108 and the metal bumps 106 on the underlying chip 105 and the metal bumps 106 on the upper chip 108 and the ground plane 103 and the lead-out pins The preparation of the electrical metal interconnection 111 is completed in the form of metal wire by ultrasonic bonding technique between 101.
  • the material of the metal interconnect ie, the metal connection
  • Step 7 As shown in FIG. 1 , after the entire chip stack is completed, the entire package structure is plastically sealed by using a transfer molding technique in the entire package, and the silicone package is used as a material of the molding compound 109 to complete the fixing of the entire package. .
  • the stage 102, the ground plane 103, the lead pin 101, the dielectric frame 104, the bottom chip 105, and the solder on the chip The disk 106, the first dielectric layer 107, and the upper chip 108 are all located inside the molded body 109.
  • the metal bumps described above are pads on the chip; further, the above-mentioned carrier stage, ground plane, and lead pin materials are Kovar alloy (Fe-Ni-Co), alloy 42 (Alloy42) And one of the copper alloys; the method for preparing the metal interconnect is a wire bonding technique in thermocompression bonding and ultrasonic bonding; the material of the metal bump is gold, silver, lead One of the tin alloys; the material of the metal interconnection may be one of aluminum, gold, silver, copper, and palladium; the material of the dielectric layer and the dielectric frame may be hexagonal boron nitride, white gemstone, One of a spinel and a ceramic; the preparation method of the molded body is one of a transfer molding technique, a spray molding technique, and a preforming technique; and the material of the molded body is a phenolic resin or a silicone resin. .
  • a dielectric layer is stacked on the upper chip, and a top chip is stacked on the dielectric layer to accommodate multi-chip bonding.
  • a top chip is stacked on the dielectric layer to accommodate multi-chip bonding.
  • FIG. 6 inside the package, different sizes of the underlying chips can be placed above the carrier, and the dielectric layers of different shapes are also placed to complete the multi-chip packaging requirements, thereby adapting to More application scenarios.
  • the embodiment of the present invention can make the chips in the angled manner of the dielectric layers of the various angles, so that the chips in the stack have sufficient space to be wired. Therefore, the embodiment of the present invention can effectively increase the frame SiP package.
  • the number of chips satisfies the needs of various packages, and effectively solves the problem that the number of chips in the existing SiP frame package structure is limited for multi-chip packaging, and increases the number of stacked chips, so as to adapt to the current lighter and thinner The product application requirements laid the foundation.

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Abstract

一种多芯片框架封装结构，该封装结构包括：至少一个载片台（102）、至少一个底层芯片（105）以及至少一个上层芯片（108）；该至少一个载片台配置为容置该至少一个底层芯片和该至少一个上层芯片；该封装结构还包括：至少一个第一介质层（107）；其中，该第一介质层置于该底层芯片的上方；该上层芯片置于该第一介质层的上方；通过调整该第一介质层的倾斜角度能够调整该底层芯片与该上层芯片之间的位置关系，以便于增加该至少一个载片台上堆叠的芯片的数量。实施例还提供了一种多芯片框架封装结构的制造方法。

Description

一种多芯片框架封装结构及其制造方法
相关申请的交叉引用
本申请基于申请号为201610905878.9、申请日为2016年10月17日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及半导体器件封装技术，尤其涉及一种多芯片框架封装结构及其制造方法。
背景技术
在当今电子工程逐步发展的今天，小型化、轻量化及功能化的集成电路(IC)芯片越来越受到青睐。而且，随着半导体业晶园制程即将达到瓶颈，封装技术将成为提高芯片制造利润，挑战摩尔定律的一个重要角色。在这一庞大需求下，半导体封装密度会不断增加，从一个组件的开发，逐渐进入到了集结多个组件成为一个系统的阶段。系统级封装(SiP)作为一种多芯片封装技术是目前也是未来封装技术的发展趋势。其封装形态多样，而且可根据客户或产品的需求通过改变不同的芯片排列方式及内部接合技术来实现定制化或弹性生产，且适用于各种消费性产品市场。但随着SiP封装密度不断增加，需要组建的芯片种类不断增多，芯片尺寸的不同导致SiP封装时会面临许多键合技术带来的困难。这就需要在进行SiP封装时合理分配各个组件的位置及封装方式。
QFP(Quad Flat Package)为表面贴装型封装，通过在四边引出呈不同形状的引脚来完成内部芯片与板级上的连接，由于QFP中间框架用于放置 芯片的载片台大小与芯片的引脚数目息息相关，所以限制了利用QFP实现SiP的可行性。现有，通常使用框架类封装来实现SiP，但是，完成SiP封装时，不同组件的大小会严重制约可封装密度，尤其对于较薄的产品而言，可封装组件数目成为框架类封装发扬SiP技术时所遇到的较为严重的问题。
发明内容
为解决现有存在的技术问题，本发明实施例提供一种多芯片框架封装结构及其制造方法，以至少解决以上所述的技术问题。
为达到上述目的，本发明实施例的技术方案是这样实现的：
本发明实施例第一方面提供了一种多芯片框架封装结构，所述封装结构包括：至少一个载片台、至少一个底层芯片以及至少一个上层芯片；所述至少一个载片台配置为容置所述至少一个底层芯片和所述至少一个上层芯片；所述封装结构还包括：至少一个第一介质层；其中，
所述第一介质层置于所述底层芯片的上方；所述上层芯片置于所述第一介质层的上方；通过调整所述第一介质层的倾斜角度能够调整所述底层芯片与所述上层芯片之间的位置关系，以便于增加所述至少一个载片台上堆叠的芯片的数量。
上述方案中，所述封装结构还包括：至少一个第二介质层；
所述第二介质层置于所述至少一个上层芯片中第一层上层芯片的上方，所述至少一个上层芯片中第二层上层芯片置于所述第二介质层的上方；其中，通过调整所述第二介质层的倾斜角度能够调整所述第一层上层芯片和所述第二层上层芯片之间的位置关系，以便于增加所述至少一个载片台上堆叠的芯片的数量。
上述方案中，所述封装结构还包括：接地平面、介质框架以及引出引脚；其中，
所述接地平面，配置为连接所述底层芯片和/或所述上层芯片上需要接 地的焊盘；
所述引出引脚，配置为连接所述底层芯片和/或所述上层芯片上需要外接引出的焊盘；
所述介质框架，配置为将所述至少一个载片台、所述接地平面及所述引出引脚之间连接起来，并配置为支撑所述多芯片框架封装结构，以保证所述多芯片框架封装结构的结构牢固。
上述方案中，所述封装结构还包括：塑封体；
所述塑封体，配置为将所述至少一个载片台、至少一个底层芯片、至少一个上层芯片以及至少一个第一介质层封装，以将所述至少一个载片台、至少一个底层芯片、至少一个上层芯片以及至少一个第一介质层封装于所述塑封体的内部。
上述方案中，所述封装结构还包括：至少一个第三介质层和至少一个顶层芯片；
所述第三介质层置于所述塑封体的上方，所述顶层芯片置于所述第三介质层的上方，通过调整所述第三介质层的倾斜角度能够调整所述顶层芯片在所述塑封体上的位置，以便于增加所述至少一个载片台上堆叠的芯片的数量。
上述方案中，所述封装结构还包括：金属连接线；其中，
所述金属连接线，配置为将所述至少一个底层芯片中各底层芯片或所述至少一个上层芯片中各上层芯片之间的焊盘连接；和/或，将所述底层芯片与所述上层芯片之间的焊盘连接；和/或，将所述底层芯片和所述上层芯片中需要与所述引出引脚、接地平面进行连接的芯片的焊盘与所述引出引脚和所述接地平面连接。
本发明实施例第二方面提供了一种多芯片框架封装结构的制造方法，所述封装结构包括：至少一个载片台、至少一个底层芯片、至少一个上层 芯片以及至少一个第一介质层；所述方法包括：
在所述至少一个载片台上设置所述底层芯片；
在所述底层芯片上设置所述第一介质层，以所述第一介质层置于所述底层芯片的上方；
在所述第一介质层的上方设置所述上层芯片，以上所述上层芯片置于所述第一介质层的上方；其中，通过调整所述第一介质层的倾斜角度能够调整所述底层芯片与所述上层芯片之间的位置关系，以便于增加所述至少一个载片台上堆叠的芯片的数量。
上述方案中，所述封装结构还包括：至少一个第二介质层；相应地，所述方法还包括：
在所述至少一个上层芯片中第一层上层芯片的上方设置所述第二介质层，在所述第二介质层上的上方设置所述至少一个上层芯片中第二层上层芯片，其中，通过调整所述第二介质层的倾斜角度能够调整所述第一层上层芯片和所述第二层上层芯片之间的位置关系，以便于增加所述至少一个载片台上堆叠的芯片的数量。
上述方案中，所述封装结构还包括：塑封体；相应地，所述方法还包括：
将所述至少一个载片台、至少一个底层芯片、至少一个上层芯片以及至少一个第一介质层进行封装，形成所述塑封体，以将所述至少一个载片台、至少一个底层芯片、至少一个上层芯片以及至少一个第一介质层封装于所述塑封体的内部。
上述方案中，所述封装结构还包括：至少一个第三介质层和至少一个顶层芯片；相应地，所述方法还包括：
在所述塑封体的上方设置所述第三介质层，在所述第三介质层的上方设置所述顶层芯片，其中，通过调整所述第三介质层的倾斜角度能够调整 所述顶层芯片在所述塑封体上的位置，以便于增加所述至少一个载片台上堆叠的芯片的数量。
本发明实施例所述的多芯片框架封装结构及其制造方法，能够通过各种倾斜角度的介质层，巧妙让芯片在角度上相互错开，让堆叠后的芯片有足够的空间来打线，所以，本发明实施例能够有效增加框架SiP封装合封芯片的数目，满足了封装多样化的需求，而且，有效解决现有SiP框架封装结构对于多芯片封装时芯片数目的受限的问题，增加了堆叠芯片的数量，为适应目前对于更轻更薄的产品应用需求奠定了基础。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为本发明实施例多芯片框架封装结构的结构示意图一；
图2至图4为本发明实施例多芯片框架封装结构在制造过程中的结构示意图；
图5为本发明实施例多芯片框架封装结构的结构示意图二；
图6为本发明实施例多芯片框架封装结构的结构示意图三。
具体实施方式
为了能够更加详尽地了解本发明的特点与技术内容，下面结合附图对本发明的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本发明。
实施例一
本实施例提供了一种多芯片框架封装结构；本实施例所述的多芯片框 架封装结构能够有效增加框架SiP封装合封芯片的数目，满足了封装多样化的需求，而且，有效解决现有SiP框架封装结构对于多芯片封装时芯片数目的受限的问题；具体地，所述多芯片框架封装结构包括：至少一个载片台、至少一个底层芯片以及至少一个上层芯片；所述至少一个载片台配置为容置所述至少一个底层芯片和所述至少一个上层芯片；所述封装结构还包括：至少一个第一介质层；其中，所述第一介质层置于所述底层芯片的上方；所述上层芯片置于所述第一介质层的上方；通过调整所述第一介质层的倾斜角度能够调整所述底层芯片与所述上层芯片之间的位置关系，以便于增加所述至少一个载片台上堆叠的芯片的数量。
在实际应用中，所述封装结构还包括：接地平面、介质框架、引出引脚、以及塑封体；其中，
所述接地平面，配置为连接所述底层芯片和/或所述上层芯片上需要接地的焊盘；
所述引出引脚，配置为连接所述底层芯片和/或所述上层芯片上需要外接引出的焊盘；
所述介质框架，配置为将所述至少一个载片台、所述接地平面及所述引出引脚之间连接起来，并配置为支撑所述多芯片框架封装结构，以保证所述多芯片框架封装结构的结构牢固；
所述塑封体，配置为将所述至少一个载片台、至少一个底层芯片、至少一个上层芯片以及至少一个第一介质层封装，以将所述至少一个载片台、至少一个底层芯片、至少一个上层芯片以及至少一个第一介质层封装于所述塑封体的内部。具体地，所述塑封体配置为将所述至少一个载片台、至少一个底层芯片、至少一个上层芯片和至少一个第一介质层，以及所述接地平面、介质框架、引出引脚进行封装。
以下结合图1对本发明实施例做进一步详细说明；具体地，如图1所 示，所述多芯片框架封装结构，包括：
至少一个载片台102，所述载片台102为金属材料制成，配置为放置需要封装的芯片(如底层芯片和上层芯片)；这里，所述底层芯片和上层芯片可以具体为半导体芯片；相应地，所述载片台102具体配置为承载待封装的半导体芯片，并起到导热作用；
接地平面103，为金属材料制成，配置为连接所述载片台102中的芯片(如上层芯片和/或底层芯片)上需要接地的焊盘(或管脚)；具体地，配置为提供芯片需要接地的焊盘(或管脚)与封装体(也即多芯片框架封装结构)外部地平面的电性连接路径；
引出引脚101，配置为连接所述载片台102中的芯片(如上层芯片和/或底层芯片)上需要外接引出的焊盘；具体地，配置为提供芯片焊盘(或管脚)与封装体外部管脚的电性连接路径；
介质框架104，配置为将所述载片台102、所述接地平面103及所述引出引脚101之间连接起来，并配置为支撑整个封装结构(也即封装体)，以保证整个封装体的结构牢固。
至少一个底层芯片105，平铺放置于所述载片台102的上方；
至少一个第一介质层107，放置于所述底层芯片105的上方，且所述第一介质层107的上方可以放置至少一个上层芯片108，所述上层芯片108可以通过金属打线的形式与所述底层芯片105之间通过焊盘106进行电性连接；所述上层芯片108可以通过金属打线的形式与所述接地平面103或所述引出引脚101进行电连接；
塑封体109，配置为将所述载片台102、接地平面103、引出引脚101、介质框架104、底层芯片105、介质层107、上层芯片108以及芯片(如上层芯片和/或底层芯片)上的焊盘塑封，以将所述载片台102、接地平面103、引出引脚101、介质框架104、底层芯片105，芯片上的焊盘106、介质层 107、上层芯片108包覆于所述塑封体109的内部。在实际应用中，在完成整个半导体芯片放置后所述塑封体109用来填充整个封装体。
当然，为便于所述封装结构中各组件之间的连接，所述封装结构还包括：金属连接线；其中，所述金属连接线，配置为将所述至少一个底层芯片中各底层芯片或所述至少一个上层芯片中各上层芯片之间的焊盘连接；和/或，将所述底层芯片与所述上层芯片之间的焊盘连接；和/或，将所述底层芯片和所述上层芯片中需要与所述引出引脚、接地平面进行连接的芯片的焊盘与所述引出引脚和所述接地平面连接。也就是说，在实际应用中，所述金属连接线配置为将底层芯片、上层芯片、引出引脚、接地平面中需要连接的部件进行连接。
在一具体实施例中，所述封装结构还包括：至少一个第二介质层；所述第二介质层置于所述至少一个上层芯片中第一层上层芯片的上方，所述至少一个上层芯片中第二层上层芯片置于所述第二介质层的上方；其中，通过调整所述第二介质层的倾斜角度能够调整所述第一层上层芯片和所述第二层上层芯片之间的位置关系，以便于增加所述至少一个载片台上堆叠的芯片的数量。也就是说，上层芯片之间也可以通过介质层来调节位置关系，这样，能够进一步调节上层芯片之间的位置关系，进而便于增加所述至少一个载片台上堆叠的芯片的数量。
在另一具体实施例中，所述封装结构还包括：至少一个第三介质层和至少一个顶层芯片；所述第三介质层置于所述塑封体的上方，所述顶层芯片置于所述第三介质层的上方，通过调整所述第三介质层的倾斜角度能够调整所述顶层芯片在所述塑封体上的位置，以便于增加所述至少一个载片台上堆叠的芯片的数量。也就是说，在上层芯片上还可以再堆叠一个介质层，并在介质层上再堆叠一颗上层芯片，这样，便于适应多芯片合封的应用场景。
这样，本发明实施例所述的多芯片框架封装结构，能够巧妙的通过改变堆叠半导体芯片时添加的介质层的形状来改变堆叠的半导体芯片之间的位置关系，进而有效提高了多层芯片打线空间，充分利用了封装尺寸内部空间，在相同的框架内完成更多的芯片合封，解决了现有技术中由于芯片尺寸过大，无法正常堆叠而导致没法合封过多芯片的问题。
而且，本发明实施例能够通过各种倾斜角度的介质层，巧妙让芯片在角度上相互错开，让堆叠后的芯片有足够的空间来打线，因此，增加了堆叠芯片的数量，为适应目前对于更轻更薄的产品应用需求奠定了基础。
另外，由于本发明实施例是通过改变介质层的方式来完成多芯片的堆叠的，所以，与现有改变框架的方式相比，本发明实施例成本更低，满足现有高性能低成本的芯片开发需求。
实施例二
本实施例提供了一种实施例一所述的多芯片框架封装结构的制造方法；具体地，所述方法包括：
在所述至少一个载片台上设置所述底层芯片；在所述底层芯片上设置所述第一介质层，以所述第一介质层置于所述底层芯片的上方；在所述第一介质层的上方设置所述上层芯片，以上所述上层芯片置于所述第一介质层的上方；其中，通过调整所述第一介质层的倾斜角度能够调整所述底层芯片与所述上层芯片之间的位置关系，以便于增加所述至少一个载片台上堆叠的芯片的数量。
在一具体实施例中，所述封装结构还包括：至少一个第二介质层；相应地，所述方法还包括：在所述至少一个上层芯片中第一层上层芯片的上方设置所述第二介质层，在所述第二介质层上的上方设置所述至少一个上层芯片中第二层上层芯片，其中，通过调整所述第二介质层的倾斜角度能够调整所述第一层上层芯片和所述第二层上层芯片之间的位置关系，以便 于增加所述至少一个载片台上堆叠的芯片的数量。
在另一具体实施例中，，所述封装结构还包括：塑封体；相应地，所述方法还包括：将所述至少一个载片台、至少一个底层芯片、至少一个上层芯片以及至少一个第一介质层进行封装，形成所述塑封体，以将所述至少一个载片台、至少一个底层芯片、至少一个上层芯片以及至少一个第一介质层封装于所述塑封体的内部。
在实际应用中，所述封装结构还包括：至少一个第三介质层和至少一个顶层芯片；相应地，所述方法还包括：在所述塑封体的上方设置所述第三介质层，在所述第三介质层的上方设置所述顶层芯片，其中，通过调整所述第三介质层的倾斜角度能够调整所述顶层芯片在所述塑封体上的位置，以便于增加所述至少一个载片台上堆叠的芯片的数量。
图2至图4为本发明实施例多芯片框架封装结构在制造过程中的结构示意图；以下结合图2至图4对本发明实施例所述的方法做进一步详细说明；具体地，
步骤一，如图2所示，使用Candence SiP设计软件完成一种具有良好散热特性的多芯片框架封装结构的设计；具体地，所述多芯片框架封装结构包括位于中央的载片台102，分布于所述载片台102四周的引出引脚101和接地平面103，以及连接所述载片台102、引出引脚101和接地平面103的介质框架104。
具体地，使用Kovar合金(Fe-Ni-Co)作为所述载片台102和所述引出引脚101以及所述接地平面103的材料，通过冲膜的方法制备出如图1所示的多芯片框架；进一步地，使用六方氮化硼作为介质框架104的材料，通过冲模的方法将载片台102、引出引脚101和接地平面103部分连接起来。
这里，在实际应用中，所述载片台可以是一整块，也可以是隔开的多个平面。所述接地平面可以分布于整个封装体四周。所述引出引脚可以分 布于整个封装体四周。
步骤二，如图3所示，在所述载片台102上表面平铺放置一个底层芯片105，所述底层芯片105通过导电银胶110与所述载片台102进行粘结。
步骤三，在所述底层芯片105上表面制备出金属凸块106，所述金属凸块106材料为金。在所述底层芯片105上的金属凸块106之间，以及所述底层芯片105上的金属凸块106与所述接地平面103及所述引出引脚101之间通过超声波键合技术，按照金属打线的形式完成电性互连线111的制备。所述互连线的材料为银。
步骤四，如图4所示，在所述底层芯片105上放置一个第一介质层107，所述第一介质层107通过芯片粘结薄膜112粘结在所述底层芯片105的上方。所述第一介质层107的材料为六方氮化硼。这里，所述第一介质层可以根据需要设置为不同的形状。
步骤五，如图4所示，在所述第一介质层107上表面放置一个上层芯片108，所述上层芯片108通过芯片粘结薄膜粘结在所述第一介质层107的上方。
步骤六，在所述上层芯片108上表面制备金属凸块106，所述金属凸块106材料为金。在所述上层芯片108上的金属凸块106与所述底层芯片105上的金属凸块106之间以及所述上层芯片108上的金属凸块106与所述接地平面103及所述引出引脚101之间通过超声波键合技术，按照金属打线的形式完成电性金属互连线111的制备。所述金属互连线(也即金属连接线)的材料为银。
步骤七，如图1所示，在完成整个芯片堆叠后，在整个封装体内通过转移成型技术，选用硅胶述职作为塑封料109的材料对整个封装结构进行塑封，以完成整个封装体内部组件的固定。在塑封完成后所述载片台102、接地平面103、引出引脚101、介质框架104、底层芯片105，芯片上的焊 盘106、第一介质层107、上层芯片108都位于所述塑封体109内部。
这里，以上所述的金属凸块即为芯片上的焊盘；进一步地，以上所述的载片台、接地平面以及引出引脚材料为Kovar合金(Fe-Ni-Co)、合金42(Alloy42)及铜合金中的一种；所述金属互连线的制备方法为热压键合、超声波键合中的一种打线键合技术；所述金属凸块的材料为金、银、铅锡合金中的一种；所述金属互连线的材料可以为铝、金、银、铜、钯中的一种；所述介质层和介质框架的材料可以为六方氮化硼、白宝石、尖晶石、陶瓷中的一种；所述塑封体的制备方法为转移成型技术、喷射成型技术、预成型技术中的一种；所述塑封体的材料为酚醛树脂、硅胶树脂中的一种。
在实际应用中，如图5所示，在图1所示的封装结构的基础上，在上层芯片上再堆叠一个介质层，并在介质层上再堆叠一颗顶层芯片，以适应多芯片合封的应用场景进一步地，如图6所述，在封装内部，在载片台上方都可以放置不同尺寸的底层芯片，同样通过放置不同形状的介质层，以完成多芯片封装需求，从而适应更多的应用场景。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
工业实用性
本发明实施例能够通过各种倾斜角度的介质层，巧妙让芯片在角度上相互错开，让堆叠后的芯片有足够的空间来打线，所以，本发明实施例能够有效增加框架SiP封装合封芯片的数目，满足了封装多样化的需求，而且，有效解决现有SiP框架封装结构对于多芯片封装时芯片数目的受限的问题，增加了堆叠芯片的数量，为适应目前对于更轻更薄的产品应用需求奠定了基础。

Claims (10)

  1. 一种多芯片框架封装结构，所述封装结构包括：至少一个载片台、至少一个底层芯片以及至少一个上层芯片；所述至少一个载片台配置为容置所述至少一个底层芯片和所述至少一个上层芯片；所述封装结构还包括：至少一个第一介质层；其中，
    所述第一介质层置于所述底层芯片的上方；所述上层芯片置于所述第一介质层的上方；通过调整所述第一介质层的倾斜角度能够调整所述底层芯片与所述上层芯片之间的位置关系，以便于增加所述至少一个载片台上堆叠的芯片的数量。
  2. 根据权利要求1所述的多芯片框架封装结构，其中，所述封装结构还包括：至少一个第二介质层；
    所述第二介质层置于所述至少一个上层芯片中第一层上层芯片的上方，所述至少一个上层芯片中第二层上层芯片置于所述第二介质层的上方；其中，通过调整所述第二介质层的倾斜角度能够调整所述第一层上层芯片和所述第二层上层芯片之间的位置关系，以便于增加所述至少一个载片台上堆叠的芯片的数量。
  3. 根据权利要求1或2所述的多芯片框架封装结构，其中，所述封装结构还包括：接地平面、介质框架以及引出引脚；其中，
    所述接地平面，配置为连接所述底层芯片和/或所述上层芯片上需要接地的焊盘；
    所述引出引脚，配置为连接所述底层芯片和/或所述上层芯片上需要外接引出的焊盘；
    所述介质框架，配置为将所述至少一个载片台、所述接地平面及所述引出引脚之间连接起来，并配置为支撑所述多芯片框架封装结构，以保证所述多芯片框架封装结构的结构牢固。
  4. 根据权利要求1或2所述的多芯片框架封装结构，其中，所述封装结构还包括：塑封体；
    所述塑封体，配置为将所述至少一个载片台、至少一个底层芯片、至少一个上层芯片以及至少一个第一介质层封装，以将所述至少一个载片台、至少一个底层芯片、至少一个上层芯片以及至少一个第一介质层封装于所述塑封体的内部。
  5. 根据权利要求4所述的多芯片框架封装结构，其中，所述封装结构还包括：至少一个第三介质层和至少一个顶层芯片；
    所述第三介质层置于所述塑封体的上方，所述顶层芯片置于所述第三介质层的上方，通过调整所述第三介质层的倾斜角度能够调整所述顶层芯片在所述塑封体上的位置，以便于增加所述至少一个载片台上堆叠的芯片的数量。
  6. 根据权利要求1或2所述的多芯片框架封装结构，其中，所述封装结构还包括：金属连接线；其中，
    所述金属连接线，配置为将所述至少一个底层芯片中各底层芯片或所述至少一个上层芯片中各上层芯片之间的焊盘连接；和/或，将所述底层芯片与所述上层芯片之间的焊盘连接；和/或，将所述底层芯片和所述上层芯片中需要与所述引出引脚、接地平面进行连接的芯片的焊盘与所述引出引脚和所述接地平面连接。
  7. 一种多芯片框架封装结构的制造方法，所述封装结构包括：至少一个载片台、至少一个底层芯片、至少一个上层芯片以及至少一个第一介质层；所述方法包括：
    在所述至少一个载片台上设置所述底层芯片；
    在所述底层芯片上设置所述第一介质层，以所述第一介质层置于所述底层芯片的上方；
    在所述第一介质层的上方设置所述上层芯片，以上所述上层芯片置于所述第一介质层的上方；其中，通过调整所述第一介质层的倾斜角度能够调整所述底层芯片与所述上层芯片之间的位置关系，以便于增加所述至少一个载片台上堆叠的芯片的数量。
  8. 根据权利要求7所述的方法，其中，所述封装结构还包括：至少一个第二介质层；相应地，所述方法还包括：
    在所述至少一个上层芯片中第一层上层芯片的上方设置所述第二介质层，在所述第二介质层上的上方设置所述至少一个上层芯片中第二层上层芯片，其中，通过调整所述第二介质层的倾斜角度能够调整所述第一层上层芯片和所述第二层上层芯片之间的位置关系，以便于增加所述至少一个载片台上堆叠的芯片的数量。
  9. 根据权利要求7或8所述的方法，其中，所述封装结构还包括：塑封体；相应地，所述方法还包括：
    将所述至少一个载片台、至少一个底层芯片、至少一个上层芯片以及至少一个第一介质层进行封装，形成所述塑封体，以将所述至少一个载片台、至少一个底层芯片、至少一个上层芯片以及至少一个第一介质层封装于所述塑封体的内部。
  10. 根据权利要求9所述的方法，其中，所述封装结构还包括：至少一个第三介质层和至少一个顶层芯片；相应地，所述方法还包括：
    在所述塑封体的上方设置所述第三介质层，在所述第三介质层的上方设置所述顶层芯片，其中，通过调整所述第三介质层的倾斜角度能够调整所述顶层芯片在所述塑封体上的位置，以便于增加所述至少一个载片台上堆叠的芯片的数量。
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