CN113327917A - 一种多芯片封装方法及封装结构 - Google Patents
一种多芯片封装方法及封装结构 Download PDFInfo
- Publication number
- CN113327917A CN113327917A CN202110477237.9A CN202110477237A CN113327917A CN 113327917 A CN113327917 A CN 113327917A CN 202110477237 A CN202110477237 A CN 202110477237A CN 113327917 A CN113327917 A CN 113327917A
- Authority
- CN
- China
- Prior art keywords
- chips
- chip
- lead frame
- packaging
- slide holder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
Abstract
本发明提供一种多芯片封装方法及封装结构,方法包括:提供具有载片台及内引脚的引线框架;在载片台表面形成依次堆叠的多个芯片;其中,在形成多个芯片中的底层芯片时,采用表面贴装技术将底层芯片贴装在载片台表面;以及,在多个芯片中的任意相邻两个芯片之间设置金属夹片,金属夹片分别与该相邻两个芯片以及对应的内引脚电连接,以完成对多个芯片的封装。本发明采用表面贴装技术将底层芯片贴装在载片台表面,不仅能够很好地控制粘接材料溢出,还能够保证芯片良好的平整度。另外,在多个芯片中的任意相邻两个芯片之间设置金属夹片,不仅能够提升器件的电性能,还能有效防止芯片产生裂纹,并为设置在金属夹片上层的芯片的贴装提供良好的平台。
Description
技术领域
本发明属于芯片封装技术领域,具体涉及一种多芯片封装方法及封装结构。
背景技术
近些年来,随着电子封装小型化,芯片集成度和集成电路功率的提高,微电子封装技术正逐渐进入高速发展状态。与此同时,对半导体器件的性能要求也越来越高,对传统的分立器件也提出了更高的集成度要求。
多芯片封装、器件的小型化是半导体分立器件未来的发展方向。多芯片封装技术是一种可满足集成密度要求、提升整机性能的封装工艺,一般可分为2D结构封装和3D结构封装,这两种封装工艺各有优劣,但都是一种在单个塑料封装外壳内组合封装多颗芯片的单封装混合技术。传统的分立器件多芯片封装方案是基于水平面的平铺方案,相当于2D结构,如图1所示,这种结构一般适用于载片台较大的引线框架,例如TO247,然而,这种方案局限性较大,不利于器件的小型化。随着封装技术的发展,后来出现了基于竖直方向的堆叠方案,相当于3D结构,如图2所示,但这种结构比较粗糙,上层芯片与下方的接触面较小,容易发生掉芯片的风险,同时,芯片破损的潜在风险也会加大。
在封装工艺方面,分立器件通常采用高温焊料装片工艺及铝线键合工艺。高温焊料装片工艺所用的粘接材料导电导热性能较差,器件无法获得很好的电性能。同时,高温装片的过程不易控制,焊料在高温下流动性较强,会造成芯片四周焊料溢出较多,从而影响器件的可靠性。粗铝线键合工艺通常应用于对电流通过量要求较高的大功率器件,并且,在键合的过程中,需要对焊点施加超声与压力,容易造成芯片损伤。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一,提供一种多芯片封装方法及封装结构。
本发明的一个方面,提供一种多芯片封装方法,所述封装方法包括:
提供具有载片台及内引脚的引线框架;
在载片台表面形成依次堆叠的多个芯片;其中,
在形成所述多个芯片中的底层芯片时,采用表面贴装技术将所述底层芯片贴装在所述载片台表面;以及,
在所述多个芯片中的任意相邻两个芯片之间设置金属夹片,所述金属夹片分别与该相邻两个芯片以及对应的内引脚电连接,以完成对所述多个芯片的封装。
在一些实施方式中,所述引线框架包括多个引线框架单元,每个所述引线框架单元的内引脚均凸出于对应的载片台表面,在所述采用表面贴装技术将所述底层芯片贴装在所述载片台表面之前,还包括:
提供与所述引线框架形状相匹配的底座,所述底座设置有多个凹槽;
将每个引线框架单元设置在对应的凹槽中,以将所述引线框架固定在所述底座上。
在一些实施方式中,所述凹槽的深度为对应的所述引线框架单元厚度的1/3~2/3。
在一些实施方式中,所述采用表面贴装技术将所述底层芯片贴装在所述载片台表面,包括:
提供与所述引线框架形状相匹配的丝网结构,所述丝网结构上设置有多组通孔,每组所述通孔对应一个所述引线框架单元的载片台;
利用所述丝网结构向各所述引线框架单元的载片台表面刷银焊膏;
将所述底层芯片通过所述银焊膏贴装在所述载片台表面。
在一些实施方式中,所述利用所述丝网结构向各所述引线框架单元的载片台表面刷银焊膏,包括:
提供刮刀,所述刮刀上设置有多个开槽,每个所述开槽对应一个所述引线框架单元的内引脚;
利用所述刮刀将所述丝网结构表面的银焊膏刮平,以将所述银焊膏通过所述多组通孔漏印至各所述引线框架单元的载片台表面。
在一些实施方式中,所述在所述多个芯片中的任意相邻两个芯片之间设置金属夹片,包括:
分别在相邻两个所述芯片表面与内引脚表面进行点胶;
将所述金属夹片的两端分别放置在所述芯片表面的源极区域和所述内引脚表面,并通过高温回流,使得所述源极区域的焊点固定。
在一些实施方式中,在形成所述多个芯片中的顶层芯片时:
采用点胶工艺将所述顶层芯片固定在所述金属夹片上,再进行金铜线键合工艺。
在一些实施方式中,在形成所述多个芯片中的顶层芯片时:
在所述顶层芯片上形成焊球,将所述顶层芯片倒装在所述金属夹片上。
在一些实施方式中,所述多个芯片中的至少一个芯片为功率芯片,所述多个芯片中的其余芯片为控制电路芯片。
本发明的另一个方面,提供一种多芯片封装结构,所述封装结构包括:
引线框架,所述引线框架具有载片台及内引脚;
多个芯片,所述多个芯片依次堆叠设置在所述载片台表面;
金属夹片,所述金属夹片设置在所述多个芯片中的任意相邻两个芯片之间,所述金属夹片分别与该相邻两个芯片以及对应的内引脚电连接。
在一些实施方式中,所述封装结构还包括金铜线,所述金铜线设置在所述多个芯片中的顶层芯片与其下层芯片之间,以实现所述顶层芯片与其下层芯片的电连接。
在一些实施方式中,所述封装结构还包括焊球,所述焊球设置在所述多个芯片中的顶层芯片上,所述焊球将所述顶层芯片与其相邻的金属夹片电连接。
在一些实施方式中,所述多个芯片中的至少一个芯片为功率芯片,所述多个芯片中的其余芯片为控制电路芯片。
在一些实施方式中,所述封装结构还包括多个粘接层,所述多个粘接层分别设置在所述载片台与所述底层芯片之间,以及所述多个芯片与所述金属夹片之间。
本发明提供的多芯片封装方法及封装结构,在形成多个芯片中的底层芯片时,采用表面贴装技术将底层芯片贴装在载片台表面,不仅能够很好地控制粘接材料溢出,还能够保证芯片良好的平整度。另外,在多个芯片中的任意相邻两个芯片之间设置金属夹片,不仅能够提升器件的电性能,还能有效防止芯片产生裂纹,并为设置在金属夹片上层的芯片的贴装提供良好的平台。
附图说明
图1为现有技术中一种分立器件的2D封装结构的内部结构示意图;
图2为现有技术中另一种分立器件的3D封装结构的内部结构示意图;
图3为本发明一实施例的一种多芯片封装方法的流程图;
图4a为本发明另一实施例的一种多芯片封装结构的结构示意图;
图4b为图4a所示的多芯片封装结构的俯视图;
图5a为本发明另一实施例的一种多芯片封装结构的结构示意图;
图5b为图5a所示的多芯片封装结构的俯视图;
图6a为本发明另一实施例的一种底座的结构示意图;
图6b为图6a所示的底座的俯视图;
图7a为本发明另一实施例的一种底座的结构示意图;
图7b为图7a所示的底座的侧视图;
图8a为本发明另一实施例的一种丝网结构的结构示意图;
图8b为图8a所示的丝网结构的侧视图;
图9为本发明另一实施例的一种刮刀的结构示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案,下面结合附图和具体实施方式对本发明作进一步详细描述。
本发明的一个方面,如图3所示,提供一种多芯片封装方法 S100,方法S100包括:
S110、提供具有载片台及内引脚的引线框架。
示例性的,一并结合图4a至图5b,提供引线框架110,引线框架110具有载片台111及内引脚112。引线框架的具体结构和材料可以根据实际需要进行选择,本实施例对此并不限制。
S120、在载片台表面形成依次堆叠的多个芯片;其中,
在形成所述多个芯片中的底层芯片时,采用表面贴装技术将所述底层芯片贴装在所述载片台表面;以及,
在所述多个芯片中的任意相邻两个芯片之间设置金属夹片,所述金属夹片分别与该相邻两个芯片以及对应的内引脚电连接,以完成对所述多个芯片的封装。
示例性的,一并结合图4a至图5b,在载片台111表面可以形成依次堆叠的两个芯片,分别为底层芯片121和顶层芯片122。当然,在载片台表面也可以形成依次堆叠的三个芯片或者四个芯片、五个芯片等等,本领域技术人员可以根据实际需要选择芯片的具体数量,本实施例对此并不限制。
示例性的,一并结合图4a至图5b,在形成多个芯片中的底层芯片121时,可以采用表面贴装技术将底层芯片121贴装在载片台111表面。在多个芯片中的任意相邻两个芯片之间如底层芯片 121和顶层芯片122之间还可以设置金属夹片130,金属夹片130 分别与相邻的两个芯片即底层芯片121和顶层芯片122以及对应的内引脚112电连接。
本实施例的多芯片封装方法,在形成多个芯片中的底层芯片时,采用表面贴装技术将底层芯片贴装在载片台表面,不仅能够很好地控制粘接材料溢出,还能够保证芯片良好的平整度。另外,在多个芯片中的任意相邻两个芯片之间设置金属夹片,不仅能够提升器件的电性能,还能有效防止芯片产生裂纹,并为设置在金属夹片上层的芯片的贴装提供良好的平台。
需要说明的是,一并结合图4a至图5b,在引线框架110还包括外引脚113时,可以利用键合工艺,通过键合线141将底层芯片121与外引脚113电连接。键合线141可以为金铜线,也可以是其他材质的金属线,本领域技术人员可以根据实际需要进行选择。
示例性的,一并结合图6a至图7b,引线框架110可以包括多个引线框架单元114,每个引线框架单元114的内引脚112均凸出于对应的载片台111表面。在采用表面贴装技术将底层芯片121 贴装在载片台111表面之前,还包括:提供与引线框架110形状相匹配的底座200,底座200设置有多个凹槽210。将每个引线框架单元114设置在对应的凹槽210中,以将引线框架110固定在底座200上。
本实施例的多芯片封装方法,通过将引线框架固定在与其形状相匹配的底座上,能够防止在采用表面贴装技术时引线框架发生位移,从而提高封装质量。
示例性的,一并结合图6a至图7b,凹槽210的深度为对应的引线框架单元114厚度的1/3~2/3。例如,凹槽210的深度可以为对应的引线框架单元114厚度的1/3,也可以为对应的引线框架单元114厚度的1/2,还可以为对应的引线框架单元114厚度的2/3 等等,本领域技术人员可以根据实际需要进行选择,本实施例对此并不限制。通过将凹槽的深度设置为对应的引线框架单元厚度的1/3~2/3,可以使引线框架单元更加稳定地设置在对应的凹槽内,能够进一步防止在采用表面贴装技术时引线框架发生位移,从而提高封装质量。
示例性的,一并结合图4a至图5b以及图8a至图8b,采用表面贴装技术将底层芯片121贴装在载片台111表面,包括:提供与引线框架110形状相匹配的丝网结构300,丝网结构300上设置有多组通孔310,每组通孔310对应一个引线框架单元114的载片台111。利用丝网结构300向各引线框架单元114的载片台111 表面刷银焊膏。将底层芯片121通过银焊膏贴装在载片台111表面。
需要说明的是,每组通孔310的正投影可以落在对应的引线框架单元114的载片台111内,以使底层芯片121能够更好地贴装在载片台111表面。
本实施例的多芯片封装方法,在采用表面贴装技术时,利用与引线框架形状相匹配的丝网结构,且该丝网结构上的每组通孔对应一个引线框架单元的载片台,可以将粘接材料均匀地印制在对应的引线框架单元的载片台表面,从而能够很好地控制粘接材料溢出,同时保证芯片良好的平整度。另外,粘接材料采用的银焊膏,具有良好的导电导热性,能够有效提升器件的性能。
示例性的,一并结合图4a至图5b以及图8a至图9,利用丝网结构300向各引线框架单元114的载片台111表面刷银焊膏,包括:提供刮刀400,刮刀400上设置有多个开槽410,每个开槽 410对应一个引线框架单元114的内引脚112。利用刮刀400将丝网结构300表面的银焊膏刮平,以将银焊膏通过多组通孔310漏印至各引线框架单元114的载片台111表面。
本实施例的多芯片封装方法,通过利用设置有多个开槽的刮刀将丝网结构表面的焊膏刮平,并且每个开槽对应一个引线框架单元的内引脚,可以将焊膏通过丝网结构上的多组通孔均匀地漏印在对应的引线框架单元的载片台表面,从而有效地控制焊膏溢出,同时保证芯片良好的平整度,进而提升封装质量。
示例性的,在多个芯片中的任意相邻两个芯片之间设置金属夹片,包括:分别在相邻两个芯片表面与内引脚表面进行点胶。将金属夹片的两端分别放置在芯片表面的源极区域和内引脚表面,并通过高温回流,使得源极区域的焊点固定。
如图4a至图5b所示,可以在底层芯片121表面与内引脚112 表面进行点胶,将金属夹片130的两端分别放置在底层芯片121 表面的源极区域和内引脚112表面,并通过高温回流,使得源极区域的焊点固定,从而实现将底层芯片与内引脚电连接。
示例性的,在形成多个芯片中的顶层芯片时,可以采用点胶工艺将顶层芯片固定在金属夹片上,再进行金铜线键合工艺。如图4a和图4b所示,在形成顶层芯片122时,可以在金属夹片130 上进行点胶,将顶层芯片122固定在金属夹片130上后再进行固化,从而使顶层芯片122与金属夹片130相连接,之后再通过键合工艺将金铜线142进行键合,以实现顶层芯片122与其下层芯片即底层芯片121的电连接。
示例性的,在形成多个芯片中的顶层芯片时,还可以在顶层芯片上形成焊球,将顶层芯片倒装在金属夹片上。如图5a和图5b 所示,在形成顶层芯片122时,可以先在顶层芯片122表面进行植球以形成焊球143,之后将顶层芯片122倒置在金属夹片130 表面,经过固化后实现将顶层芯片122倒装在金属夹片130上。
示例性的,多个芯片中的至少一个芯片为功率芯片,多个芯片中的其余芯片为控制电路芯片。如图4a至图5b所示,底层芯片121可以为功率芯片,顶层芯片122可以为控制电路芯片,或者,顶层芯片122可以为功率芯片,底层芯片121可以为控制电路芯片,本领域技术人员可以根据实际需要进行设置,本实施例对此并不限制。
本发明的另一个方面,如图4a至图5b所示,提供一种多芯片封装结构100,该封装结构100可以采用前文记载的制备方法制作形成,具体可以参考前文相关记载,在此不作赘述。该封装结构100包括引线框架110、多个芯片以及金属夹片130。
示例性的,如图4a至图5b所示,引线框架110具有载片台 111及内引脚112。多个芯片依次堆叠设置在载片台111表面。金属夹片130设置在多个芯片中的任意相邻两个芯片之间,金属夹片130分别与该相邻两个芯片以及对应的内引脚112电连接。
本实施例的多芯片封装结构,在多个芯片中的任意相邻两个芯片之间设置金属夹片,不仅能够提升器件的电性能,还能有效防止芯片产生裂纹,并为设置在金属夹片上层的芯片的贴装提供良好的平台。
需要说明的是,一并结合图4a至图5b,引线框架110还可以包括外引脚113,在引线框架110包括外引脚113时,封装结构 100还可以包括键合线141,键合线141将底层芯片121与外引脚 113电连接。键合线141可以为金铜线,也可以是其他材质的金属线,本领域技术人员可以根据实际需要进行选择。
示例性的,如图4a和图4b所示,封装结构100还包括金铜线142,金铜线142设置在多个芯片中的顶层芯片122与其下层芯片之间,以实现顶层芯片与其下层芯片的电连接。
示例性的,如图5a和图5b所示,封装结构100还包括焊球 143,焊球143设置在多个芯片中的顶层芯片122上,焊球143将顶层芯片122与其相邻的金属夹片130电连接。
示例性的,多个芯片中的至少一个芯片为功率芯片,多个芯片中的其余芯片为控制电路芯片。
示例性的,如图4a至图5b所示,封装结构100还包括多个粘接层151,多个粘接层151分别设置在载片台111与底层芯片 121之间,以及多个芯片与金属夹片130之间。粘接层的粘接材料可以为银焊膏,由于银焊膏具有良好的导电导热性,使得封装结构能够具有更优的性能。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。
Claims (10)
1.一种多芯片封装方法,其特征在于,所述封装方法包括:
提供具有载片台及内引脚的引线框架;
在载片台表面形成依次堆叠的多个芯片;其中,
在形成所述多个芯片中的底层芯片时,采用表面贴装技术将所述底层芯片贴装在所述载片台表面;以及,
在所述多个芯片中的任意相邻两个芯片之间设置金属夹片,所述金属夹片分别与该相邻两个芯片以及对应的内引脚电连接,以完成对所述多个芯片的封装。
2.根据权利要求1所述的封装方法,其特征在于,所述引线框架包括多个引线框架单元,每个所述引线框架单元的内引脚均凸出于对应的载片台表面,在所述采用表面贴装技术将所述底层芯片贴装在所述载片台表面之前,还包括:
提供与所述引线框架形状相匹配的底座,所述底座设置有多个凹槽;
将每个引线框架单元设置在对应的凹槽中,以将所述引线框架固定在所述底座上。
3.根据权利要求2所述的封装方法,其特征在于,所述凹槽的深度为对应的所述引线框架单元厚度的1/3~2/3。
4.根据权利要求2所述的封装方法,其特征在于,所述采用表面贴装技术将所述底层芯片贴装在所述载片台表面,包括:
提供与所述引线框架形状相匹配的丝网结构,所述丝网结构上设置有多组通孔,每组所述通孔对应一个所述引线框架单元的载片台;
利用所述丝网结构向各所述引线框架单元的载片台表面刷银焊膏;
将所述底层芯片通过所述银焊膏贴装在所述载片台表面。
5.根据权利要求4所述的封装方法,其特征在于,所述利用所述丝网结构向各所述引线框架单元的载片台表面刷银焊膏,包括:
提供刮刀,所述刮刀上设置有多个开槽,每个所述开槽对应一个所述引线框架单元的内引脚;
利用所述刮刀将所述丝网结构表面的银焊膏刮平,以将所述银焊膏通过所述多组通孔漏印至各所述引线框架单元的载片台表面。
6.根据权利要求1所述的封装方法,其特征在于,所述在所述多个芯片中的任意相邻两个芯片之间设置金属夹片,包括:
分别在相邻两个所述芯片表面与内引脚表面进行点胶;
将所述金属夹片的两端分别放置在所述芯片表面的源极区域和所述内引脚表面,并通过高温回流,使得所述源极区域的焊点固定。
7.根据权利要求1所述的封装方法,其特征在于,在形成所述多个芯片中的顶层芯片时:
采用点胶工艺将所述顶层芯片固定在所述金属夹片上,再进行金铜线键合工艺。
8.根据权利要求1所述的封装方法,其特征在于,在形成所述多个芯片中的顶层芯片时:
在所述顶层芯片上形成焊球,将所述顶层芯片倒装在所述金属夹片上。
9.根据权利要求1至8任一项所述的封装方法,其特征在于,所述多个芯片中的至少一个芯片为功率芯片,所述多个芯片中的其余芯片为控制电路芯片。
10.一种多芯片封装结构,其特征在于,所述封装结构包括:
引线框架,所述引线框架具有载片台及内引脚;
多个芯片,所述多个芯片依次堆叠设置在所述载片台表面;
金属夹片,所述金属夹片设置在所述多个芯片中的任意相邻两个芯片之间,所述金属夹片分别与该相邻两个芯片以及对应的内引脚电连接。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110477237.9A CN113327917A (zh) | 2021-04-29 | 2021-04-29 | 一种多芯片封装方法及封装结构 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110477237.9A CN113327917A (zh) | 2021-04-29 | 2021-04-29 | 一种多芯片封装方法及封装结构 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN113327917A true CN113327917A (zh) | 2021-08-31 |
Family
ID=77414107
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202110477237.9A Pending CN113327917A (zh) | 2021-04-29 | 2021-04-29 | 一种多芯片封装方法及封装结构 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN113327917A (zh) |
-
2021
- 2021-04-29 CN CN202110477237.9A patent/CN113327917A/zh active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9917031B2 (en) | Semiconductor device, and method for assembling semiconductor device | |
JP4729244B2 (ja) | 半導体デバイス用非モールドパッケージ | |
CN106997871B (zh) | 一种功率模块的封装结构 | |
US8900993B2 (en) | Semiconductor device sealed in a resin section and method for manufacturing the same | |
CN112670278B (zh) | 一种芯片封装结构及芯片封装方法 | |
US20110042784A1 (en) | Mechanical Barrier Element for Improved Thermal Reliability of Electronic Components | |
CN111668196A (zh) | 半导体封装件以及相关方法 | |
US9748205B2 (en) | Molding type power module | |
CN114743947A (zh) | 基于to形式的功率器件封装结构及封装方法 | |
US7768104B2 (en) | Apparatus and method for series connection of two die or chips in single electronics package | |
US9698076B1 (en) | Metal slugs for double-sided cooling of power module | |
CN115527975A (zh) | 一种芯片封装结构及芯片封装方法 | |
CN113327917A (zh) | 一种多芯片封装方法及封装结构 | |
CN115966564A (zh) | 一种改善散热的芯片封装结构及其制备方法 | |
JP2020198388A (ja) | 半導体装置およびその製造方法 | |
CN116093044B (zh) | 多芯片集成方法及结构 | |
US11450623B2 (en) | Semiconductor device | |
CN111128910B (zh) | 芯片堆叠封装方法及芯片堆叠结构 | |
CN216015347U (zh) | 一种器件封装结构及组件 | |
CN217983321U (zh) | 一种双面散热的半导体芯片封装结构 | |
CN219917170U (zh) | 一种半桥模块 | |
KR101216777B1 (ko) | 전력 모듈 패키지 및 그 제조방법 | |
CN211828769U (zh) | 一种叠层芯片封装结构 | |
CN212113707U (zh) | 高密度封装引线框架结构及具有其的高密度封装结构 | |
KR101924258B1 (ko) | 반도체 패키지 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20221221 Address after: 226009 Free Seat Office Area, Floor 3, Building 11A, Zilang Science and Technology City, No. 60 Chongzhou Avenue, Nantong Development Zone, Jiangsu Province (No. A07) Applicant after: Tongfu Microelectronics Technology (Nantong) Co.,Ltd. Address before: 226010 room 337, No. 42, Guangzhou road, development zone, Nantong City, Jiangsu Province Applicant before: Tongfu microelectronics technology research and development branch |