WO2018072309A1 - 阵列基板像素连接结构及阵列基板 - Google Patents

阵列基板像素连接结构及阵列基板 Download PDF

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WO2018072309A1
WO2018072309A1 PCT/CN2016/111461 CN2016111461W WO2018072309A1 WO 2018072309 A1 WO2018072309 A1 WO 2018072309A1 CN 2016111461 W CN2016111461 W CN 2016111461W WO 2018072309 A1 WO2018072309 A1 WO 2018072309A1
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sub
pixel
pixels
pixel row
row
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PCT/CN2016/111461
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English (en)
French (fr)
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常鹏刚
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深圳市华星光电技术有限公司
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Priority to US15/327,771 priority Critical patent/US20180107075A1/en
Publication of WO2018072309A1 publication Critical patent/WO2018072309A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement

Definitions

  • the present invention relates to the field of liquid crystal display manufacturing technologies, and in particular, to an array substrate pixel connection structure and an array substrate.
  • LCD Liquid Crystal Display
  • Transistor LCDs are based on the advantages of lightness and thinness, combined with perfect picture and fast response characteristics, ensuring that they are the leader in the display market.
  • the pixel connection structure of the array substrate is one of the core parts of the thin film transistor LCD.
  • the pixel connection structure of the array substrate directly affects the aperture ratio, response speed and display picture quality of the liquid crystal display.
  • the research on the pixel structure of the liquid crystal display has been relatively mature. But there are still many areas that can be improved.
  • the driving of the liquid crystal display must have polarity reversal, and the electric field applied to the liquid crystal molecules is directional. If the electric field in the opposite direction is applied to the liquid crystal at different times, it is called polarity reversal. Sexual reversal is to avoid DC residual of the liquid crystal.
  • Common pixel array polarity inversion methods include frame inversion, column inversion, line inversion, and dot inversion. The effect of spatial point flipping is realized on the basis of column inversion, and there is no problem that the drive is too high due to frequent switching polarity, and has been widely used by the panel industry. However, if the existing liquid crystal inversion has a delicate picture, it must ensure that the resolution can only achieve 2D effect, and can not directly do 3D application.
  • An object of the present invention is to provide an array substrate pixel connection structure, which can realize a liquid crystal panel 2D and 3D effects.
  • the array substrate pixel connection structure includes a plurality of data lines, the plurality of data lines are arranged side by side in a first direction; a plurality of gate lines, the plurality of gate lines being arranged side by side in a second direction; The plurality of data lines and the plurality of gate lines intersect to define a plurality of sub-pixels, the plurality of sub-pixels are arranged in a matrix, the each sub-pixel includes a thin film transistor and a pixel electrode, and the plurality of sub-pixels are sequentially arranged along the second direction a first sub-pixel row, a second sub-pixel row, a third sub-pixel row, and a fourth sub-pixel row, wherein the first sub-pixel row and the sub-pixel in the second sub-pixel row are connected to the adjacent data line thereof, The sub-pixels in the third sub-pixel row and the fourth sub-pixel row are connected to data lines adjacent thereto, and the data lines connected to the third sub-pixel row and the fourth sub-pixel row are connected to the first sub-
  • the plurality of sub-pixels include a fifth sub-pixel row and a sixth sub-pixel row sequentially arranged along the second direction and the fourth sub-pixel row; the sub-pixels of the fifth sub-pixel row and the sixth sub-pixel row A data line adjacent to the side opposite to the first direction is connected.
  • the number of pixel units composed of sub-pixels included in the first sub-pixel row to the sixth sub-pixel row is the same.
  • each of the sub-pixels is connected by a data line adjacent to the left side or connected to a data line adjacent to the right side
  • the third and fourth sub-pixel rows are Each of the sub-pixels is connected by a data line adjacent to the right side or connected to a data line adjacent to the left side.
  • each of the sub-pixels is connected by a data line adjacent to the left side or connected to a data line adjacent to the right side.
  • the same sub-pixels in the pixel units of the same column in the first, second, third, fourth, fifth, and sixth sub-pixel rows are located in the same column along the second direction. .
  • the plurality of sub-pixels comprise three different color sub-pixels; in the first, second, third, fourth, fifth and sixth sub-pixel rows, each of the pixel rows Three sub-pixels of different colors are arranged in order.
  • first, second, third, fourth, fifth, and sixth sub-pixel rows, the sub-pixels located between two adjacent data lines of the first column are the same type of sub-pixels, and The sub-pixels in the first and second sub-pixel rows are connected to a first one of two adjacent data lines, and the third and fourth sub-pixels The sub-pixels in the pixel row are connected to the second data line, and the sub-pixels in the fifth and sixth sub-pixel rows are connected to the first data line.
  • the sub-pixels located between two adjacent data lines of the second column are the same type of sub-pixels, and The sub-pixels in the first and second sub-pixel rows are connected to data lines of the two adjacent data lines that are adjacent to the first column, and the sub-pixels in the third and fourth sub-pixel rows are connected to another data line.
  • the sub-pixels in the fifth and sixth sub-pixel rows are connected to the data lines of the first column.
  • the array substrate of the present invention comprises the array substrate pixel connection structure.
  • the pixels in the same row of the pixel connection structure of the array substrate of the present application are connected to the gate lines on the same side; in the same column of pixels, each two adjacent pixels are a combination of pixels, and adjacent pixels are combined to connect different data lines.
  • the simultaneous charging pixel combination the 2D effect can be achieved, and the 3D effect can also be achieved.
  • FIG. 1 is a schematic view showing a pixel connection structure of an array substrate of the present invention.
  • the present invention provides an array substrate and a pixel connection structure thereof.
  • the array substrate pixel connection structure includes a plurality of data lines 10, the plurality of data lines 10 are arranged side by side along the first direction A; a plurality of gate lines 20, the plurality of gate lines 20 along the second direction B Arranged side by side.
  • the plurality of data lines 10 and the plurality of gate lines 20 intersect to define a plurality of sub-pixels 30, and the plurality of sub-pixels 30 are formed
  • the matrix is arranged, and each of the sub-pixels includes a thin film transistor and a pixel electrode (not shown).
  • the plurality of sub-pixels include a first sub-pixel row 1, a second sub-pixel row 2, a third sub-pixel row 3, and a fourth sub-pixel row 4, which are sequentially arranged along the second direction B, the first sub-pixel row 1 and the sub-pixels in the second sub-pixel row 2 are connected to the data lines adjacent thereto, the sub-pixels in the third sub-pixel row 3 and the fourth sub-pixel row 4 are connected to the data lines adjacent thereto, and the The data lines connected to the third sub-pixel row 3 and the fourth sub-pixel row 4 and the data lines connected to the first sub-pixel row 1 and the second sub-pixel row 2 are in two opposite arrangement directions.
  • the plurality of sub-pixels further include a fifth sub-pixel row 5 and a sixth sub-pixel row 6 sequentially arranged along the second direction B and the fourth sub-pixel row 4; the fifth sub-pixel row 5 and the sixth sub-pixel
  • the sub-pixels of row 6 are connected to their adjacent data lines on the side opposite to the first direction A.
  • the data line connecting the first sub-pixel row 1 and the second sub-pixel row 2 sub-pixel is located on the left data line of two adjacent data lines, then the third sub-pixel row 3 and the fourth The data lines of the sub-pixels connected in the sub-pixel row 4 are located on the right of the two adjacent data lines.
  • each of the sub-pixels is connected by a data line adjacent to the left side or connected to a data line adjacent to the right side
  • the third sub-pixel In the pixel row 3 and the fourth sub-pixel row 4 each of the sub-pixels is connected by a data line adjacent to the right side or connected to a data line adjacent to the left side
  • each of the sub-pixels is connected by a data line adjacent to the left side or connected to a data line adjacent to the right side.
  • the first sub-pixel row to the sixth sub-pixel row that is, the first sub-pixel row 1, the second sub-pixel row 2, the third sub-pixel row 3, the fourth sub-pixel row 4, and the fifth sub-pixel row
  • the number of pixel units composed of sub-pixels included in both the fifth and sixth sub-pixel rows 6 is the same.
  • the plurality of sub-pixels include three different color sub-pixels; in the first sub-pixel row 1, the second sub-pixel row 2, the third sub-pixel row 3, the fourth sub-pixel row 4, and the fifth sub-pixel row 5 In the sixth sub-pixel row 6, the three different color sub-pixels in each pixel row are sequentially arranged.
  • the three different color sub-pixels in each pixel row are a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, respectively.
  • the first sub-pixel row 1, the second sub-pixel row 2, the third sub-pixel row 3, the fourth sub-pixel row 4, the fifth sub-pixel row 5, and the first are located in the same column.
  • the sub-pixel in row 2 connects the first data line of two adjacent data lines
  • the sub-pixel in the third sub-pixel row 3 and the fourth sub-pixel row 4 is connected to the second data line
  • the sub-pixels in the fifth and sixth sub-pixel rows 6 are connected to the first data line.
  • the first sub-pixel row 1, the second sub-pixel row 2, the third sub-pixel row 3, the fourth sub-pixel row 4, the fifth sub-pixel row 5, and the sixth sub-pixel row 6 are located in the second column.
  • the sub-pixels between two adjacent data lines are the same type of sub-pixels, and the sub-pixels in the first sub-pixel row 1 and the second sub-pixel row 2 are connected to the first column of two adjacent data lines.
  • the data lines, the third sub-pixel row 3, the sub-pixels of the fourth sub-pixel row 4 are connected to another data line, and the sub-pixels of the fifth sub-pixel row 5 and the sixth sub-pixel row 6 are connected to the data of the first column. line.
  • the data lines forming the first sub-pixel row 1, the second sub-pixel row 2, the third sub-pixel row 3, the fourth sub-pixel row 4, the fifth sub-pixel row 5, and the sixth sub-pixel row 6 are respectively S1 , S2, S3, S4, S5, S6 and S7.
  • the gate lines are G1, G2, G3, G4, G5, G6, and G7.
  • the sub-pixels are all connected to the gate line above it.
  • the first direction A is the direction of the data lines S1 to S7
  • the second direction B is the direction of the gate lines G1 to G7.
  • the gate lines G1 and G2 form the first sub-pixel row 1 , and the sub-pixels in the pixel row are sequentially arranged as RGB pixels.
  • the gate lines G2 and G3 form the second sub-pixel row 2, and the sub-pixels in the pixel row are sequentially arranged as RGB pixels.
  • the gate lines G3 and G4 form the third sub-pixel row 3, and the sub-pixels in the pixel row are sequentially arranged for the RGB pixels.
  • the gate lines G4 and G5 form the fourth sub-pixel row 4, and the sub-pixels in the pixel row are sequentially arranged as RGB pixels.
  • the gate lines G5 and G6 form the fifth sub-pixel row 5, and the sub-pixels in the pixel row are sequentially arranged for the RGB pixels.
  • the gate lines G6, G7 form the sixth sub-pixel row 6.
  • the sub-pixels in the pixel row are sequentially arranged for the RGB pixels.
  • the data lines S1, S2 form a first column D1, and the sub-pixels located between the data lines S1, S2 are the first R sub-pixels of the first sub-pixel row 1 to the sixth sub-pixel row.
  • the data lines S2, S3 form a second column D2, and the sub-pixels located between the data lines S2, S3 are the first G sub-pixels of the first sub-pixel row 1 to the sixth sub-pixel row.
  • the data lines S3, S4 form a third column D3, and the sub-pixels located between the data lines S3, S4 are the first B sub-pixels of the first sub-pixel row 1 to the sixth sub-pixel row.
  • the R sub-pixels of the first sub-pixel row 1 and the second sub-pixel row 2 are connected to the data line S1 of the first column, and the G sub-pixels of the first sub-pixel row 1 and the second sub-pixel row 2 A column of S2 connections, the first sub-pixel row 1, the second sub-pixel row 2 B sub-pixel are connected to the second column S3, the next group of pixel units are still connected in this connection order, that is, opposite to the first direction
  • the data line connection, that is, the first sub-pixel row 1, the second sub-pixel row 2 sub-pixel is connected to the data line on the left side of the pixel column.
  • the sub-pixels in the third sub-pixel row 3 and the fourth sub-pixel row 4 are connected to the data line S2 of the first column, and the G sub-pixels of the third sub-pixel row 3 and the fourth sub-pixel row 4
  • the S3 connection of the two columns, the B sub-pixel of the third sub-pixel row 3 and the fourth sub-pixel row 4 are connected with the S4 of the second column, and the pixel units of the next group are still connected in this connection order, that is, the same as the first direction.
  • the aligned data lines are connected, that is, the third sub-pixel row 3 and the fourth sub-pixel row 4 sub-pixel are connected to the data line on the right side of the pixel column.
  • R sub-pixels in the fifth sub-pixel row 5 and the sixth sub-pixel row 6 are connected to the data line S1 of the first column, and the G sub-pixels in the fifth sub-pixel row 5 and the sixth sub-pixel row 6 Connected to S2 of the first column, the B sub-pixels in the fifth sub-pixel row 5 and the sixth sub-pixel row 6 are connected to the S3 of the second column, and the pixel units of the next group are still connected in this connection order, that is, A data line connection in the opposite direction, that is, a fifth sub-pixel row 5 and a sixth sub-pixel row 6 sub-pixel are connected to the data line on the left side of the pixel column.
  • the gate lines G1 and G2 simultaneously illuminate two rows, that is, the gate lines of the first sub-pixel row 1 and the second sub-pixel row 2, then, S1 S4 simultaneously charges the R sub-pixels of the first sub-pixel row 1 and the second sub-pixel row 2 in the first column and the R sub-pixels in the next pixel cell, and the red is lit.
  • the gate lines G3 and G4 simultaneously illuminate two rows, that is, the gate lines G3 and G4 of the first sub-pixel row 1 and the second sub-pixel row 2, then S2 and S5 simultaneously give the first sub-pixel row 1 And the R sub-pixels of the second sub-pixel row 2 located in the second column and the R sub-pixels of the next pixel unit are charged, and the red is lit. In this way, the swapping of the sub-pixels is performed, and the sub-pixels of other colors are not mistakenly lit, and the 3D effect is achieved.

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Abstract

一种阵列基板像素连接结构，包括多条数据线（10），多条数据线（10）沿第一方向并排排列；多条栅极线（20）沿第二方向并排排列；多条数据线（10）和多条栅极线（20）交叉限定多个子像素（30），多个子像素（30）成矩阵排列，每个子像素（30）包括薄膜晶体管和像素电极，多个子像素（30）包括沿着第二方向依次排列的第一子像素行（1）、第二子像素行（2）、第三子像素行（3）及第四子像素行（4），第一子像素行（1）与第二子像素行（2）内的子像素连接与其相邻的数据线，第三子像素行（3）及第四子像素行（4）内的子像素连接与其相邻的数据线，并且第三子像素行（3）及第四子像素行（4）连接的数据线与第一子像素行（1）与第二子像素行（2）连接的数据线为两个相反的排列方向。还提供一种阵列基板。

Description

阵列基板像素连接结构及阵列基板
本发明要求2016年10月17日递交的发明名称为“阵列基板像素连接结构及阵列基板”的申请号201610902876.4的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示制造技术领域，尤其涉及一种阵列基板像素连接结构及阵列基板。
背景技术
液晶显示器(Liquid Crystal Display，LCD)已经广泛应用于我们生活的各个方面，从小尺寸的手机、摄像机、数码相机，中尺寸的笔记本电脑、台式机，大尺寸的家用电视到大型投影设备等，薄膜晶体管LCD在轻、薄优势的基础上，加上完美的画面及快速的响应特性，确保其在显示器市场上独占鳌头。
阵列基板像素连接结构是薄膜晶体管LCD的核心部分之一，阵列基板像素连接结构直接影响到液晶显示器的开口率、响应速度、显示画面质量等方面，目前对于液晶显示器的像素结构的研究已经比较成熟，但还有许多可以改进的方面。
液晶显示的驱动必须要有极性反转，施加在液晶分子上的电场是有方向性的，若在不同的时间，以相反方向的电场施加在液晶上，即称为极性反转，极性反转是为了避免液晶的直流残留。常见的像素阵列极性反转的方式有帧反转、列反转、行反转和点反转四种。在栏反转基础上实现空间点翻转的效果，又不会出现驱动因频繁切换极性而温度太高问题，已经被面板界广泛使用。而现有液晶反转如果具备细腻的画面又要保证分辨率只能实现2D效果，不能直接做3D应用。
发明内容
本发明的目的在于提供一种阵列基板像素连接结构，可以实现液晶面板的 2D及3D效果。
为了实现上述目的，本发明实施方式提供如下技术方案：
所述阵列基板像素连接结构，其包括多条数据线，所述多条数据线沿第一方向并排排列；多条栅极线，所述多条栅极线沿第二方向并排排列；所述多条数据线和所述多条栅极线交叉限定多个子像素，多个子像素成矩阵排列，所述每个子像素包括薄膜晶体管和像素电极，所述多个子像素包括沿着第二方向依次排列的第一子像素行、第二子像素行、第三子像素行及第四子像素行，所述第一子像素行与第二子像素行内的子像素连接与其相邻的数据线，所述第三子像素行及第四子像素行内的子像素连接与其相邻的数据线，并且所述第三子像素行及第四子像素行连接的数据线与所述第一子像素行与第二子像素行连接的数据线为两个相反的排列方向。
其中，所述多个子像素包括沿着第二方向与第四子像素行依次排列的第五子像素行及第六子像素行；所述第五子像素行及第六子像素行的子像素连接与其相邻的位于与第一方向相反一侧的数据线。
其中，所述第一子像素行至第六子像素行内包含的由子像素构成的像素单元数量相同。
其中，在第一、第二子像素行中，所述每个子像素由左侧相邻的数据线连接，或者与右侧相邻的数据线连接，所述第三、第四子像素行中，所述每个子像素由右侧相邻的数据线连接，或者与左侧相邻的数据线连接。
其中，所述第五及第六子像素行中，所述每个子像素由左侧相邻的数据线连接，或者与右侧相邻的数据线连接。
其中，沿着所述第二方向上，所述第一、第二、第三、第四、第五及第六子像素行中位于同一列的像素单元中的同类的子像素位于同一列中。
其中，所述多个子像素包括三种不同颜色的子像素；在所述第一、第二、第三、第四、第五及第六子像素行中的，每一像素行中的所述三种不同颜色的子像素顺次排列。
其中，所述第一、第二、第三、第四、第五及第六子像素行中，位于第一列的两条相邻的数据线之间的子像素为同一类子像素，并且所述第一、第二子像素行中子像素连接两条相邻的数据线中的第一条数据线，所述第三、第四子 像素行中的子像素连接第二条数据线，所述第五、第六子像素行中的子像素连接第一条数据线。
其中，所述第一、第二、第三、第四、第五及第六子像素行中，位于第二列的两条相邻的数据线之间的子像素为同一类子像素，并且所述第一、第二子像素行中子像素连接两条相邻的数据线中的靠近第一列的数据线，所述第三、第四子像素行中的子像素连接另一条数据线，所述第五、第六子像素行中的子像素连接靠近第一列的数据线。
本发明所述的阵列基板，包括所述的阵列基板像素连接结构。
本申请所述的阵列基板像素连接结构同一行的像素与同一侧的栅极线连接；同一列像素中，每两个相邻像素为一个像素组合，相邻的像素组合连接不同的数据线，采用同时充电像素组合，即可以实现2D效果，也可以实现3D效果。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明阵列基板像素连接结构的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
请参阅图1，本发明提供一种阵列基板及其像素连接结构。所述的阵列基板像素连接结构包括多条数据线10，所述多条数据线10沿第一方向A并排排列；多条栅极线20，所述多条栅极线20沿第二方向B并排排列。所述多条数据线10和所述多条栅极线20交叉限定多个子像素30，多个子像素30成 矩阵排列，所述每个子像素包括薄膜晶体管和像素电极(图未示)。
所述多个子像素包括沿着第二方向B依次排列的第一子像素行1、第二子像素行2、第三子像素行3及第四子像素行4，所述第一子像素行1与第二子像素行2内的子像素连接与其相邻的数据线，所述第三子像素行3及第四子像素行4内的子像素连接与其相邻的数据线，并且所述第三子像素行3及第四子像素行4连接的数据线与所述第一子像素行1与第二子像素行2连接的数据线为两个相反的排列方向。所述多个子像素还包括沿着第二方向B与第四子像素行4依次排列的第五子像素行5及第六子像素行6；所述第五子像素行5及第六子像素行6的子像素连接与其相邻的位于与第一方向A相反一侧的数据线。比如，所述第一子像素行1与第二子像素行2子像素连接的数据线位于两个相邻数据线中的左侧的数据线，那么所述第三子像素行3及第四子像素行4内的子像素连接的数据线位于两个相邻数据线中的右侧的数据线。
进一步的，在第一子像素行1与第二子像素行2中，所述每个子像素由左侧相邻的数据线连接，或者与右侧相邻的数据线连接，所述第三子像素行3及第四子像素行4中，所述每个子像素由右侧相邻的数据线连接，或者与左侧相邻的数据线连接。所述第五子像素行5及第六子像素行中，所述每个子像素由左侧相邻的数据线连接，或者与右侧相邻的数据线连接。
其中，所述第一子像素行至第六子像素行，即第一子像素行1、第二子像素行2、第三子像素行3、第四子像素行4、第五子像素行5及第六子像素行6内均包含的由子像素构成的像素单元数量相同。所述多个子像素包括三种不同颜色的子像素；在第一子像素行1、第二子像素行2、第三子像素行3、第四子像素行4、第五子像素行5及第六子像素行6中，每一像素行中的所述三种不同颜色的子像素顺次排列。本实施例中，每一像素行中的所述三种不同颜色的子像素分别为红色子像素R，绿色子像素G及蓝色子像素B。每一像素行中有多个依次排列的像素单元。
进一步的，沿着所述第二方向上，所述第一子像素行1、第二子像素行2、第三子像素行3、第四子像素行4、第五子像素行5及第六子像素行6中位于同一列的像素单元中的同类的子像素位于同一列中。
所述第一子像素行1、第二子像素行2、第三子像素行3、第四子像素行4、 第五子像素行5及第六子像素行6中，位于第一列的两条相邻的数据线之间的子像素为同一类子像素，并且第一子像素行1、第二子像素行2中子像素连接两条相邻的数据线中的第一条数据线，第三子像素行3、第四子像素行4中的子像素连接第二条数据线，第五子像素行5及第六子像素行6中的子像素连接第一条数据线。
所述第一子像素行1、第二子像素行2、第三子像素行3、第四子像素行4、第五子像素行5及第六子像素行6中，位于第二列的两条相邻的数据线之间的子像素为同一类子像素，并且第一子像素行1、第二子像素行2中子像素连接两条相邻的数据线中的靠近第一列的数据线，第三子像素行3、第四子像素行4中的子像素连接另一条数据线，第五子像素行5及第六子像素行6中的子像素连接靠近第一列的数据线。
如图1所示，下面以具体实施例进行解释说明。
形成所述第一子像素行1、第二子像素行2、第三子像素行3、第四子像素行4、第五子像素行5及第六子像素行6的数据线分别为S1、S2、S3、S4、S5、S6及S7。栅极线为G1、G2、G3、G4、G5、G6及G7。所述的子像素均与其上方的栅极线连接。所述第一方向A为数据线S1至S7的方向，第二方向B为栅极线G1至G7的方向。其中，栅极线G1、G2形成所述的第一子像素行1，该像素行内的子像素为过个RGB像素依次排列。栅极线G2、G3形成所述的第二子像素行2该像素行内的子像素为过个RGB像素依次排列。栅极线G3、G4形成所述的第三子像素行3，该像素行内的子像素为过个RGB像素依次排列。栅极线G4、G5形成所述的第四子像素行4该像素行内的子像素为过个RGB像素依次排列。栅极线G5、G6形成所述的第五子像素行5，该像素行内的子像素为过个RGB像素依次排列。栅极线G6、G7形成所述的第六子像素行6。该像素行内的子像素为过个RGB像素依次排列。
数据线S1、S2形成第一列D1，且位于数据线S1、S2之间的子像素为第一子像素行1至第六子像素行中的第一个R子像素。数据线S2、S3形成第二列D2，且位于数据线S2、S3之间的子像素为第一子像素行1至第六子像素行中的第一个G子像素。数据线S3、S4形成第三列D3，且位于数据线S3、S4之间的子像素为第一子像素行1至第六子像素行中的第一个B子像素。
所述第一子像素行1、第二子像素行2的R子像素与所述第一列的数据线S1连接，第一子像素行1、第二子像素行2的G子像素与第一列的S2连接，第一子像素行1、第二子像素行2的B子像素与第二列的S3连接，下一组的像素单元仍以此连接顺序连接，即与第一方向相反的数据线连接，也就是第一子像素行1、第二子像素行2子像素与像素列左侧的数据线连接。
所述第三子像素行3、第四子像素行4中的子像素与所述第一列的数据线S2连接，第三子像素行3、第四子像素行4的G子像素与第二列的S3连接，第三子像素行3、第四子像素行4的B子像素与第二列的S4连接，下一组的像素单元仍以此连接顺序连接，即与第一方向相同排列的数据线连接，也就是第三子像素行3、第四子像素行4子像素与像素列右侧的数据线连接。
所述第五子像素行5及第六子像素行6中的R子像素与所述第一列的数据线S1连接，第五子像素行5及第六子像素行6中的G子像素与第一列的S2连接，第五子像素行5及第六子像素行6中的B子像素与第二列的S3连接，下一组的像素单元仍以此连接顺序连接，即与第一方向相反的数据线连接，也就是第五子像素行5及第六子像素行6子像素与像素列左侧的数据线连接。
当所述阵列基板的驱动模块驱动所述像素结构，所述栅极线G1、G2同时点亮两行，即第一子像素行1及第二子像素行2的栅极线，那么，S1、S4会同时给第一子像素行1及第二子像素行2的位于第一列的R子像素以及下一个像素单元中的R子像素充电，则红色点亮。所述栅极线G3、G4同时点亮两行，即第一子像素行1及第二子像素行2的栅极线G3、G4，那么，S2、S5会同时给第一子像素行1及第二子像素行2位于第二列的R子像素及下一个像素单元的R子像素充电，则红色点亮。如此更替交换点亮子像素，不会错误点亮其它颜色的子像素，实现3D效果。
以上所述的实施方式，并不构成对该技术方案保护范围的限定。任何在上述实施方式的精神和原则之内所作的修改、等同替换和改进等，均应包含在该技术方案的保护范围之内。

Claims (18)

  1. 一种阵列基板像素连接结构，其中，包括多条数据线，所述多条数据线沿第一方向并排排列；多条栅极线，所述多条栅极线沿第二方向并排排列；所述多条数据线和所述多条栅极线交叉限定多个子像素，多个子像素成矩阵排列，所述每个子像素包括薄膜晶体管和像素电极，所述多个子像素包括沿着第二方向依次排列的第一子像素行、第二子像素行、第三子像素行及第四子像素行，所述第一子像素行与第二子像素行内的子像素连接与其相邻的数据线，所述第三子像素行及第四子像素行内的子像素连接与其相邻的数据线，并且所述第三子像素行及第四子像素行连接的数据线与所述第一子像素行与第二子像素行连接的数据线为两个相反的排列方向。
  2. 如权利要求1所述的阵列基板像素连接结构，其中，所述多个子像素包括沿着第二方向与第四子像素行依次排列的第五子像素行及第六子像素行；所述第五子像素行及第六子像素行的子像素连接与其相邻的位于与第一方向相反一侧的数据线。
  3. 如权利要求2所述的阵列基板像素连接结构，其中，所述第一子像素行至第六子像素行内包含的由子像素构成的像素单元数量相同。
  4. 如权利要求3所述的阵列基板像素连接结构，其中，在第一、第二子像素行中，所述每个子像素由左侧相邻的数据线连接，或者与右侧相邻的数据线连接，所述第三、第四子像素行中，所述每个子像素由右侧相邻的数据线连接，或者与左侧相邻的数据线连接。
  5. 如权利要求4所述的阵列基板像素连接结构，其中，所述第五及第六子像素行中，所述每个子像素由左侧相邻的数据线连接，或者与右侧相邻的数据线连接。
  6. 如权利要求3所述的阵列基板像素连接结构，其中，沿着所述第二方向上，所述第一、第二、第三、第四、第五及第六子像素行中位于同一列的像素单元中的同类的子像素位于同一列中。
  7. 如权利要求6所述的阵列基板像素连接结构，其中，所述多个子像素包括三种不同颜色的子像素；在所述第一、第二、第三、第四、第五及第六子像 素行中的，每一像素行中的所述三种不同颜色的子像素顺次排列。
  8. 如权利要求7所述的阵列基板像素连接结构，其中，所述第一、第二、第三、第四、第五及第六子像素行中，位于第一列的两条相邻的数据线之间的子像素为同一类子像素，并且所述第一、第二子像素行中子像素连接两条相邻的数据线中的第一条数据线，所述第三、第四子像素行中的子像素连接第二条数据线，所述第五、第六子像素行中的子像素连接第一条数据线。
  9. 如权利要求8所述的阵列基板像素连接结构，其中，所述第一、第二、第三、第四、第五及第六子像素行中，位于第二列的两条相邻的数据线之间的子像素为同一类子像素，并且所述第一、第二子像素行中子像素连接两条相邻的数据线中的靠近第一列的数据线，所述第三、第四子像素行中的子像素连接另一条数据线，所述第五、第六子像素行中的子像素连接靠近第一列的数据线。
  10. 一种阵列基板，其中，包括阵列基板像素连接结构，阵列基板像素连接结构包括多条数据线，所述多条数据线沿第一方向并排排列；多条栅极线，所述多条栅极线沿第二方向并排排列；所述多条数据线和所述多条栅极线交叉限定多个子像素，多个子像素成矩阵排列，所述每个子像素包括薄膜晶体管和像素电极，所述多个子像素包括沿着第二方向依次排列的第一子像素行、第二子像素行、第三子像素行及第四子像素行，所述第一子像素行与第二子像素行内的子像素连接与其相邻的数据线，所述第三子像素行及第四子像素行内的子像素连接与其相邻的数据线，并且所述第三子像素行及第四子像素行连接的数据线与所述第一子像素行与第二子像素行连接的数据线为两个相反的排列方向。
  11. 如权利要求10所述的阵列基板，其中，所述多个子像素包括沿着第二方向与第四子像素行依次排列的第五子像素行及第六子像素行；所述第五子像素行及第六子像素行的子像素连接与其相邻的位于与第一方向相反一侧的数据线。
  12. 如权利要求11所述的阵列基板，其中，所述第一子像素行至第六子像素行内包含的由子像素构成的像素单元数量相同。
  13. 如权利要求12所述的阵列基板，其中，在第一、第二子像素行中，所述每个子像素由左侧相邻的数据线连接，或者与右侧相邻的数据线连接，所 述第三、第四子像素行中，所述每个子像素由右侧相邻的数据线连接，或者与左侧相邻的数据线连接。
  14. 如权利要求13所述的阵列基板，其中，所述第五及第六子像素行中，所述每个子像素由左侧相邻的数据线连接，或者与右侧相邻的数据线连接。
  15. 如权利要求12所述的阵列基板像素连接结构，其中，沿着所述第二方向上，所述第一、第二、第三、第四、第五及第六子像素行中位于同一列的像素单元中的同类的子像素位于同一列中。
  16. 如权利要求15所述的阵列基板，其中，所述多个子像素包括三种不同颜色的子像素；在所述第一、第二、第三、第四、第五及第六子像素行中的，每一像素行中的所述三种不同颜色的子像素顺次排列。
  17. 如权利要求16所述的阵列基板，其中，所述第一、第二、第三、第四、第五及第六子像素行中，位于第一列的两条相邻的数据线之间的子像素为同一类子像素，并且所述第一、第二子像素行中子像素连接两条相邻的数据线中的第一条数据线，所述第三、第四子像素行中的子像素连接第二条数据线，所述第五、第六子像素行中的子像素连接第一条数据线。
  18. 如权利要求17所述的阵列基板，其中，所述第一、第二、第三、第四、第五及第六子像素行中，位于第二列的两条相邻的数据线之间的子像素为同一类子像素，并且所述第一、第二子像素行中子像素连接两条相邻的数据线中的靠近第一列的数据线，所述第三、第四子像素行中的子像素连接另一条数据线，所述第五、第六子像素行中的子像素连接靠近第一列的数据线。
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