WO2018064885A1 - 一种对可编程逻辑器件进行配置或更新的装置和方法 - Google Patents

一种对可编程逻辑器件进行配置或更新的装置和方法 Download PDF

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Publication number
WO2018064885A1
WO2018064885A1 PCT/CN2017/081355 CN2017081355W WO2018064885A1 WO 2018064885 A1 WO2018064885 A1 WO 2018064885A1 CN 2017081355 W CN2017081355 W CN 2017081355W WO 2018064885 A1 WO2018064885 A1 WO 2018064885A1
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Prior art keywords
programmable logic
logic device
control module
configuring
updating
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PCT/CN2017/081355
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English (en)
French (fr)
Inventor
谢元禄
张坤
孙海涛
刘璟
毕津顺
刘明
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中国科学院微电子研究所
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Priority to US16/337,978 priority Critical patent/US11294660B2/en
Publication of WO2018064885A1 publication Critical patent/WO2018064885A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/70—Software maintenance or management
    • G06F8/71—Version control; Configuration management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage

Definitions

  • the present application relates to the field of programmable logic devices and their configuration program memory technologies, and more particularly to an apparatus and method for configuring or updating a programmable logic device.
  • PLDs Programmable Logic Devices
  • FPGAs Field-Programmable Gate Arrays
  • the functions performed by the FPGA are determined by its internal configuration information.
  • SRAM static random access memory
  • the configuration information is in the slice. Stored in the SRAM unit, once the FPGA is powered down, the configuration information stored in the SRAM is lost. Therefore, it is often necessary to use non-volatile memory such as PROM or EEPROM for non-volatile storage of the configuration information required by the FPGA. And transmitting the configuration information to the FPGA for configuration or update after the system is powered on.
  • FPGA manufacturers provide a configuration memory chip for these FPGAs for FPGAs. Load configuration of configuration information. These memory chips include XCF01S with a storage capacity of 1Mbit, XCF02S with a storage capacity of 2Mbit, XCF04S and XQ18V04 with a storage capacity of 4Mbit, XC17V08 and XCF08P with a storage capacity of 8Mbit, and XC17V16 and XCF16P with a storage capacity of 16Mbit. XQR17V16 and XCF32P and XQF32P with 32Mbit storage capacity.
  • the interfaces of these models are compatible with the configuration interface of the FPGA chip. They can read, erase and write data from the JTAG host. Easily and quickly configure or update the FPGA.
  • FPGAs with larger configuration information capacity.
  • SPI is required for FPGAs with more than 32 Mbits of configuration information (referred to as large-capacity FGPA or large-capacity programmable logic devices).
  • Memory such as Flash, BPI PROM, or Platform Flash XL is used to configure the FPGA. Since these types of memory interfaces differ greatly from the memory configured for small-capacity FPGAs, the FPGA is configured with these kinds of memories. The ease of use is poor.
  • the use of a multi-chip memory with a storage capacity of less than or equal to 32 Mbit for splicing to configure the FPGA results in more circuit components and more board area.
  • the present invention provides an apparatus and method for configuring or updating a programmable logic device to provide a programmable logic device that can be used to configure a programmable logic device with a required configuration information exceeding 32 Mbit. And the purpose of the device compatible with the traditional configuration interface.
  • the embodiment of the present invention provides the following technical solutions:
  • An apparatus for configuring or updating a programmable logic device comprising: a control module and a storage module connected to the control module, wherein
  • the control module has a JTAG interface for connecting to a JTAG host and a configuration interface compatible with the programmable logic device to be configured;
  • the control module is configured to store the configuration information in the storage module after receiving the first control instruction including the configuration information through the JTAG interface, and to read the read information after receiving the configuration instruction Configuring information to configure the programmable logic device to be configured;
  • the configuration clock used by the control module to configure the programmable logic device to be configured is derived from the programmable logic device to be configured or the control module or an external clock source.
  • control module is further configured to perform a reading or erasing operation on the storage module according to the second control instruction sent by the JTAG host.
  • control module further includes a communication interface
  • the communication interface is used for connecting with a host computer
  • the control module is further configured to: after receiving the third control instruction sent by the upper computer, perform a storage, reading and erasing operation on the storage module according to the third control instruction.
  • the communication interface is an SPI bus interface or an IIC bus interface or a UART bus interface.
  • the storage module includes three storage units;
  • the control module performs the same operation for each of the storage units
  • the control module further includes a three-mode redundant voting voting circuit
  • the three-module redundant voting voting circuit is configured to perform a three-module redundancy operation on the data output by the three storage units, and use the same data in the data output by the three storage units as the reading of the control module. Take the result.
  • the storage unit is an SPI Flash memory or a BPI Flash memory or a NAND Flash memory or a programmable read only memory PROM.
  • control module is further configured to control the storage module to operate in a low power mode or an idle mode after receiving the configuration completion signal returned by the programmable logic device to be configured.
  • a package body is also included;
  • the package is used to package the storage module and the control module together.
  • control module is an ASIC chip or a CPLD chip.
  • a method of configuring or updating a programmable logic device wherein the apparatus for configuring or updating a programmable logic device according to any of the above is configured to update and update a programmable logic device.
  • an embodiment of the present invention provides an apparatus and method for configuring or updating a programmable logic device, wherein the apparatus for configuring or updating a programmable logic device includes a control module and a storage module connected to the control module, after receiving the first control instruction including the configuration information through the JTAG interface, the control module stores the configuration information in the storage module, because the control module
  • the configuration interface is compatible with the configuration interface of the programmable logic device to be configured, so after the configuration information is read, it can be converted into configuration information compatible with the configuration timing of the programmable logic device to be configured and Transmitting, thereby completing the process of configuring the programmable logic device to be configured, thereby avoiding the memory interface and the traditional configuration interface used in the prior art for configuring or updating a large-capacity programmable logic device to be configured. Save The problem of poor usability that occurs with large differences.
  • the device configured or updated by the programmable logic device configures or updates the programmable logic device to be configured, and does not need to use multiple memories with a storage capacity less than or equal to 32 Mbit for splicing, thereby avoiding
  • the problem is that the circuit components are more, the circuit structure is complicated, the circuit board area is large, and the system weight is large.
  • FIG. 1 is a schematic structural diagram of an apparatus for configuring or updating a programmable logic device according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a device for configuring or updating a programmable logic device and a JTAG host according to an embodiment of the present application;
  • FIG. 3 is a schematic structural diagram of a device for configuring or updating a programmable logic device and a programmable logic device to be configured according to an embodiment of the present application;
  • FIG. 4 is a schematic structural diagram of a device for configuring or updating a programmable logic device according to an embodiment of the present application, which is simultaneously connected to a JTAG host and a programmable logic device to be configured;
  • FIG. 5 is a schematic structural diagram of an apparatus for configuring or updating a programmable logic device according to a preferred embodiment of the present application
  • FIG. 6 is a schematic structural diagram of a device for configuring or updating a programmable logic device and a host computer according to a preferred embodiment of the present application;
  • FIG. 7 is a schematic structural diagram of a device for configuring or updating a programmable logic device according to a preferred embodiment of the present application, which is simultaneously connected with a host computer, a JTAG host, and a programmable logic device to be configured;
  • FIG. 8 is a schematic structural diagram of an apparatus for configuring or updating a programmable logic device according to another preferred embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a three-mode redundant voting voting circuit according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of an apparatus for configuring or updating a programmable logic device according to an embodiment of the present application
  • FIG. 11 is a schematic diagram of a structure of an apparatus for configuring or updating a programmable logic device and a connection with a JTAG host, a host computer, and a programmable logic device to be configured according to another embodiment of the present application;
  • FIG. 12 is a schematic flowchart diagram of a method for configuring or updating a programmable logic device according to an embodiment of the present application.
  • the embodiment of the present application provides a device for configuring or updating a programmable logic device.
  • the method includes: a control module 100 and a storage module 200 connected to the control module 100, where
  • the control module 100 has a JTAG interface for connecting to a JTAG host and a configuration interface compatible with the programmable logic device to be configured;
  • the control module 100 is configured to store the configuration information in the storage module 200 after receiving the first control instruction including the configuration information through the JTAG interface, and to read after receiving the configuration instruction.
  • the configuration information configures the programmable logic device to be configured;
  • the configuration clock used by the control module 100 to configure the programmable logic device to be configured is derived from the programmable logic device to be configured or the control module 100 or an external clock source.
  • the JTAG host A passes the JTAG interface of the control module 100 and the pair of programmable logic.
  • the device is configured to be configured or updated, and the JTAG host A sends a first control instruction including configuration information to the control module 100 via the JTAG interface, the control module The 100 responds to the first control instruction and writes the configuration information to the storage module 200.
  • the first control instruction herein includes a programming instruction sent by the JTAG host that includes configuration information.
  • the memory module 200 When programming (writing) the memory module 200, it should be noted that if the memory module 200 is composed of a memory that requires an empty operation before writing, such as SPI Flash or NAND Flash or NOR Flash, When the configuration information is written into the storage module 200, it is necessary to note that the memory module 200 needs to perform a check operation before writing, and the check operation indicates: information stored in the storage module 200. If the information stored in the storage module 200 is empty, the operation may be performed; if the information stored in the storage module 200 is not empty, the storage module 200 needs to be erased first. The stored information can then be written to.
  • a check operation before writing indicates: information stored in the storage module 200. If the information stored in the storage module 200 is empty, the operation may be performed; if the information stored in the storage module 200 is not empty, the storage module 200 needs to be erased first. The stored information can then be written to.
  • the device for configuring or updating the programmable logic device is connected to the programmable logic device B to be configured through a configuration interface of the control module 100, and reads the device after receiving the configuration command.
  • the configuration information configures the programmable logic device B to be configured.
  • the configuration command may be a system power-on information (that is, after the system is powered on, the control module reads the configuration information to configure the programmable logic device B to be configured), or may be on the system. After the power is triggered by a button disposed on the circuit board of the device configured or updated on the programmable logic device, the specific generation and transmission manner of the configuration command is not limited in the present application, and is determined according to actual conditions. .
  • the device for configuring or updating the programmable logic device can also be connected to the JTAG host A and the programmable logic device B to be configured at the same time, as shown in FIG. 4 .
  • control module 100 performs data transmission on the programmable logic device B to be configured (that is, when configuring the programmable logic device B to be configured), it is generally required to configure a clock to make the control module 100 and the It is stated that the programmable logic device B is configured to work synchronously.
  • the programmable logic device B to be configured generally has an active configuration mode and a passive configuration mode, when the programmable logic device is in an active configuration mode, it itself provides the configuration clock required in the configuration process to the
  • the control module 100 transmits to realize clock synchronization of the programmable logic device B to be configured and the control module 100; when the programmable logic device is in a passive configuration mode, the control module and the to-be-configurable programmable
  • the clock used by the logic device can be derived from the control module 100 or an external clock source.
  • the control module 100 When the clock used by the control module and the programmable logic device to be configured is derived from the control module 100, the control module 100 provides the configuration clock and The programmable logic device B is configured to transmit to synchronize the clock of the programmable logic device B to be configured with the control module 100 during the configuration process.
  • the clock used by the control module and the programmable logic device B to be configured is derived from an external clock source, the external clock source passes through the configuration interface of the control module 100 and the programmable logic device B to be configured
  • the connection node provides a configuration clock to the control module 100 and the to-be-configured logic device to implement clock synchronization between the programmable logic device B to be configured and the control module 100 during configuration.
  • the selection of the configuration mode of the programmable logic device B to be configured may be implemented by changing the level state of the corresponding pin, and accordingly, the control module 100 needs to receive the configuration clock or send the configuration clock. The judgment can also be achieved by different level states of their respective pins.
  • the JTAG host A refers to a computer or an FPGA or a Complex Programmable Logic Device (CPLD) or a microcontroller or a digital device pre-installed with JTAG software.
  • the programmable logic device B to be configured generally refers to a Field-Programmable Gate Array (FPGA). However, in other embodiments of the present application, the programmable logic device to be configured may also be a digital signal processor.
  • the type of the programmable logic device B to be configured in the present application is not limited, and is determined according to actual conditions.
  • the configuration interface of the control module 100 since the configuration interface of the control module 100 is compatible with the programmable logic device B to be configured, after the configuration information is read, it can be converted to be programmable with the to-be-configured
  • the configuration timing of the logic device B is compatible with the configuration information and is transmitted thereto, thereby completing the process of configuring the programmable logic device B to be configured, thereby avoiding the prior art for the large-capacity programmable logic device B to be configured. That is, there is no problem with the ease of use that comes with the easy-to-use configuration memory that is compatible with its traditional configuration interface.
  • the large-capacity to-be-configured programmable logic device B refers to a programmable logic device whose required configuration information exceeds 32 Mbit.
  • the problem of poor usability due to incompatibility between the memory interface and the configuration interface of the programmable logic device B to be configured specifically includes a complicated circuit structure and is not convenient and easy to use.
  • the device configured or updated by the programmable logic device configures or updates the programmable logic device B to be configured, so that it is not necessary to use multiple memories with a storage capacity less than or equal to 32 Mbit for splicing, thereby avoiding The above problems are brought about.
  • the JTAG host A can also pass the JTAG interface. Sending a second control instruction to the control module 100, and after the control module 100 receives the second control instruction, performing a reading or erasing operation on the storage module 200 according to the second control instruction.
  • the second control instruction refers to a read command or an erase command sent by the JTAG host A
  • the control module 100 receives the read command sent by the JTAG host A
  • the read command sent by the JTAG host A performs a read operation on the memory module 200; when the control module 100 receives the erase command sent by the JTAG host A, according to the read command sent by the JTAG host A
  • An erase operation is performed on the storage module 200.
  • control module 100 further includes a communication interface
  • the communication interface is used for connecting with a host computer
  • the control module 100 is further configured to perform a storage, reading, and erasing operation on the storage module 200 according to the third control instruction after receiving the third control instruction sent by the upper computer.
  • the third control instruction herein refers to a programming instruction or a read instruction or an erase instruction transmitted by the upper computer.
  • the control module 100 receives the read command sent by the upper computer, And performing a read operation on the storage module 200 according to the read instruction sent by the upper computer; when the control module 100 receives the erase command sent by the upper computer, according to the erase command sent by the upper computer
  • the storage module 200 performs an erase operation; when the control module 100 receives the programming instruction sent by the upper computer, performs a write operation on the storage module 200 according to the programming instruction sent by the upper computer.
  • the memory module 200 when programming (writing) the memory module 200, it should be noted that if the memory module 200 is composed of SPI Flash or NAND Flash or NOR Flash, the memory needs to be checked before writing.
  • the configuration information is written into the storage module 200, it is necessary to note that the memory module 200 needs to perform a check operation before writing, and the empty operation indicates that the storage module 200 is in the storage module 200.
  • the stored information is queried. If the information stored in the storage module 200 is empty, the write operation may be performed; if the information stored in the storage module 200 is not empty, the storage needs to be erased first. The information stored in module 200 can then be written to it.
  • the upper computer herein generally refers to any electronic device that can be connected to the control module 100 through the communication interface and can send a third control command to the control module 100.
  • the interface is connected to the control module 100 to perform erasing, reading or writing of configuration information on the storage module, thereby completing configuration or update of the programmable logic device B to be configured.
  • the host computer to implement a connection with the control module 100 through the communication interface to perform the storage module. Erasing, reading or writing, thereby completing the update of the programmable logic device B to be configured.
  • the communication interface may be connected to a different type of host computer C including the JTAG host A, but the JTAG interface can only be connected to the JTAG host A.
  • the upper computer C can send a third control instruction to the control module 100 through the communication interface, Write, read, and erase operations to the memory module 200 are implemented. Then, it means that the device that configures or updates the programmable logic device can not only use the JTAG host A to write or update the configuration information of the storage module 200, but also can be configured by the upper computer C. Save The storage module 200 implements the writing or updating of the configuration information, and the operation of configuring and updating the programmable logic device B to be configured is implemented by the control module 100 after being powered on again.
  • the device for configuring or updating the programmable logic device can also be connected to the JTAG host A, the host computer C, and the programmable logic device B to be configured at the same time.
  • the host computer C may be an FPGA or a CPLD or a single chip microcomputer or a DSP or other kinds of processors.
  • the type of the upper computer C is not limited in this application, and it depends on the actual situation.
  • the communication interface may be a Serial Peripheral Interface (SPI) bus interface or an IIC bus interface or a Universal Asynchronous Receiver/Transmitter (UART) bus interface.
  • SPI Serial Peripheral Interface
  • IIC IIC
  • UART Universal Asynchronous Receiver/Transmitter
  • the storage module 200 includes three storage units 210;
  • control module 100 The operations performed by the control module 100 on each of the storage units 210 are the same.
  • the control module 100 further includes a three-mode redundant voting voting circuit
  • the three-module redundant voting circuit is configured to perform a three-module redundancy operation on the data output by the three storage units 210, and use the same data in the data output by the three storage units 210 as the control module. 100 reading results.
  • the control module 100 After the three-mode redundant voting voting circuit performs a three-module redundancy operation on the data output by the three storage units 210 to obtain a reading result (ie, configuration information), the control module 100 The configuration information is transmitted to the configuration interface, and the configuration timing of the programmable logic device B to be configured is simulated at the configuration interface, so as to implement the programmable logic device B to be configured by using the configuration information.
  • the storage module 200 is configured by using three storage units 210, and the purpose of setting the three-mode redundant voting voting circuit in the control module 100 is to improve the pair of programmable logic.
  • a specific embodiment of the present application provides a feasible three-mode redundant voting circuit. Structure, as shown in Figure 9.
  • Reference numerals DIN_1, DIN_2 and DIN_3 in Fig. 9 are input terminals of the three-mode redundant voting voting circuit, respectively connected to the data output ends of the three memory cells 210; the symbol DOUT in Fig. 9 is the three-mode The output of the redundant voting circuit.
  • the storage unit 210 is an SPI Flash memory or a BPI Flash memory or a NAND Flash memory or a programmable read only memory PROM.
  • the specific type of the storage unit 210 is not limited in this application, and is determined according to actual conditions.
  • control module 100 is further configured to control the storage module 200 after receiving the configuration completion signal returned by the programmable logic device B to be configured. Operating in a low power mode or an idle mode to reduce the power consumption of the device that configures or updates the programmable logic device.
  • the JTAG host A may be connected through the JTAG interface of the control module 100, and the The JTAG host A sends a first control instruction or a second control instruction to the control module 100 to complete the storage, reading and erasing operations on the storage module 200.
  • the host computer C can still be connected through the communication interface of the control module 100, and the host computer C is used to the control module. 100 sends a third control instruction to complete the store, read, and erase operations on the memory module 200.
  • the apparatus for configuring or updating the programmable logic device further includes a package body 300;
  • the package 300 is used to package the storage module 200 and the control module 100 together.
  • the package 300 has an input and output module for extracting the external interface of the control module 100.
  • the external interface of the control module 100 includes the configuration interface and a JTAG interface.
  • the external interface of the control module 100 includes the communication interface, the configuration interface, and the JTAG interface.
  • control module 100 is an Application Specific Integrated Circuits (ASIC) chip or Programming logic device chip.
  • ASIC Application Specific Integrated Circuits
  • Programming logic device chip Programming logic device chip.
  • the specific implementation form of the control module 100 is not limited in this application, and is determined according to actual conditions.
  • a specific embodiment of the present application provides a specific structure of a device for configuring or updating a programmable logic device and a schematic diagram thereof for connecting to a JTAG host A and a host computer C.
  • the storage unit 210 is an SPI Flash chip.
  • the storage unit 210 of the control module 100 controls the interface as an SPI interface; the communication interface is an SPI interface; in the development and debugging phase of the programmable logic device B to be configured, a USB interface can be used and pre-installed.
  • the JTAG software is used as the JTAG host A.
  • the JTAG host A is connected to the JTAG interface of the control module 100 via a download line and a corresponding plug.
  • the download line is connected by a USB cable, a JTAG cable, and a USB to JTAG. Conversion circuit composition. Reading, writing and erasing operations on the data in the three storage units 210 can be performed by the control module 100 through the JTAG software pre-installed in the JTAG host A.
  • the control module 100 automatically reads the three storage units 210 after the device configured or updated by the programmable logic device is connected to the programmable logic device B to be configured through the configuration interface and powered up.
  • the three sets of data are voted three-to-two, the voting result is used as the configuration information, and the configuration interface is sent to the to-be-configured according to the configuration timing of the programmable logic device B to be configured.
  • the programmable logic device B can complete the power-on configuration of the programmable logic device B to be configured. After completing the power-on configuration of the programmable logic device B to be configured, the host computer C working with the programmable logic device B to be configured can still implement the three memory units 210 through the control module 100. The reading, writing and erasing operations of the data in the operation, thereby implementing the updating and upgrading of the function of the programmable logic device B to be configured.
  • the embodiments of the present application provide an apparatus for configuring or updating a programmable logic device, where the apparatus for configuring or updating a programmable logic device includes a control module 100 and is connected to the control module 100.
  • the storage module 200 after receiving the first control instruction including the configuration information through the JTAG interface, the control module 100 stores the configuration information in the storage module 200, due to the configuration of the control module 100.
  • the interface is compatible with the configuration interface of the programmable logic device B to be configured, so after reading the configuration information, it can be converted into configuration information compatible with the configuration timing of the programmable logic device B to be configured and Transmitting to it, thereby completing the process of configuring the programmable logic device B to be configured, thereby avoiding the prior art for
  • the capacity of the programmable logic device to be configured or updated has a large difference between the memory interface and the conventional configuration interface, and the ease of use arises.
  • the device configured or updated by the programmable logic device configures or updates the programmable logic device B to be configured, and does not need to use multiple memories with a storage capacity less than or equal to 32 Mbit, thereby avoiding splicing. Therefore, there are many circuit components, complicated circuit structure, large occupied circuit board area and large system weight.
  • the embodiment of the present application further provides a method for configuring or updating a programmable logic device, and the device for configuring or updating the programmable logic device according to any of the above embodiments is configured to configure the programmable logic device.
  • B is configured and updated.
  • the method for configuring or updating a programmable logic device includes:
  • S101 Providing means for configuring or updating a programmable logic device, wherein the device for configuring or updating the programmable logic device is the device for configuring or updating the programmable logic device according to any one of the foregoing embodiments;
  • S102 Connect the JTAG host A to the device for configuring or updating the programmable logic device, and input, by the JTAG host A, the first device including configuration information to the device configured or updated to the programmable logic device. a control instruction, where the device configured or updated by the programmable logic device stores the configuration information after receiving the first control instruction;
  • S104 determining whether it is necessary to update the configuration information in the programmable logic device B to be configured, and if so, proceed to S105;
  • S105 Write or update configuration information of the storage module of the device that configures or updates the programmable logic device by using the host computer C or the JTAG host A, where the device that configures or updates the programmable logic device is re- After power-on, the programmable logic device B to be configured is updated by using configuration information in the storage module.
  • step S102 the device configured or updated by the programmable logic device needs to pay attention to storing the configuration information after receiving the first control instruction: if the pair of programmable logic
  • the memory module inside the device that is configured or updated by the device is composed of a memory that needs to be emptied before writing, such as SPI Flash or NAND Flash or NOR Flash, when the configuration information is written into the storage module.
  • the memory module needs to perform a check operation before the write operation, and the check operation indicates that the information stored in the storage module is queried, and if the information stored in the storage module is empty, The write operation can be performed on the storage module; if the information stored in the storage module is not empty, the information stored in the storage module needs to be erased before the write operation can be performed.
  • updating the programmable logic device B to be configured by using the host computer C connected to the device configured or updated by the programmable logic device includes:
  • the control module 100 of the device for configuring or updating the programmable logic device uses the upper computer C to send a third control instruction to the device for configuring or updating the programmable logic device, the control module 100 of the device for configuring or updating the programmable logic device according to the third control instruction Updating configuration information in the storage module 200 of the device configured or updated to the programmable logic device, when the programmable logic device B to be configured connected to the device configured or updated to the programmable logic device is re-configured After the power is on, the control module 100 automatically reads the updated configuration information to configure the programmable logic device B to be configured, and implements updating of the programmable logic device B to be configured.
  • the process of updating the programmable logic device B to be configured by the JTAG host A connected to the device configured or updated by the programmable logic device is performed by using the upper computer C to be configured.
  • the process of programming logic device B to perform the update is similar, and the present application does not describe it here.
  • the embodiments of the present application provide an apparatus and method for configuring or updating a programmable logic device, where the apparatus for configuring or updating a programmable logic device includes a control module 100 and The storage module 200 connected to the control module 100, after receiving the first control instruction including the configuration information through the JTAG interface, the control module 100 writes the configuration information into the storage module 200, because the control The configuration interface of the module 100 is compatible with the configuration interface of the programmable logic device B to be configured, so that after the configuration information is read, it can be converted into a configuration timing compatible with the programmable logic device B to be configured.
  • Configuration information is transmitted to it, thereby completing the process of configuring the programmable logic device B to be configured, thereby avoiding the prior art configuration or update for the large-capacity programmable logic device to be configured.
  • Memory interface and traditional There is a big difference in the interface and the ease of use arises.
  • the device configured or updated by the programmable logic device configures or updates the programmable logic device B to be configured, and does not need to use multiple memories with a storage capacity less than or equal to 32 Mbit, thereby avoiding splicing. Therefore, there are many circuit components, complicated circuit structure, large occupied circuit board area and large system weight.

Abstract

本申请公开了一种对可编程逻辑器件进行配置或更新的装置和方法，其中，对可编程逻辑器件进行配置或更新的装置包括：控制模块和与控制模块连接的存储模块，其中，控制模块具有用于与JTAG主机连接的JTAG接口和与待配置可编程逻辑器件兼容的配置接口；控制模块用于在通过JTAG接口接收到包含配置信息的第一控制指令后，将配置信息存储于存储模块中，和用于在接收到配置指令后读取配置信息对待配置可编程逻辑器件进行配置；控制模块对待配置可编程逻辑器件进行配置时使用的配置时钟来源于待配置可编程逻辑器件或控制模块或外部时钟源。避免了由于存储器接口与大容量待配置可编程逻辑器件的配置接口的时序不兼容而出现的易用性较差的问题。

Description

一种对可编程逻辑器件进行配置或更新的装置和方法
本申请要求于2016年10月08日提交中国专利局、申请号为201610879153.7、发明名称为“一种对可编程逻辑器件进行配置或更新的装置和方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及可编程逻辑器件及其配置程序存储器技术领域，更具体地说，涉及一种对可编程逻辑器件进行配置或更新的装置和方法。
背景技术
包括现场可编程门阵列(Field－Programmable Gate Array，FPGA)在内的可编程逻辑器件(Programmable Logic Device，PLD)在许多领域正获得日益广泛的应用。以FPGA为例，FPGA所行使的功能由其内部的配置信息所决定，对于使用较为广泛的基于静态随机存取存储器(Static Random Access Memory，SRAM)的FPGA而言，所述配置信息在其片内存储于SRAM单元中，一旦FPGA掉电，存储于SRAM中的配置信息就会丢失，因此常常需要在其片外使用非挥发存储器如PROM或EEPROM等对FPGA所需的配置信息进行非挥发存储，并在系统上电后将所述配置信息传送给FPGA进行配置或更新。
对于所需配置信息的数据量小于或等于32Mbit的FPGA(简称小容量FPGA或小容量可编程逻辑器件)而言，FPGA的生产厂家为这些FPGA提供了配套的配置存储器芯片，用于对FPGA进行配置信息的加载配置，这些存储器芯片包括存储容量为1Mbit的XCF01S，存储容量为2Mbit的XCF02S，存储容量为4Mbit的XCF04S、XQ18V04，存储容量为8Mbit的XC17V08、XCF08P，存储容量为16Mbit的XC17V16、XCF16P、XQR17V16和存储容量为32Mbit的XCF32P、XQF32P等，这些型号的存储器芯片的接口与FPGA芯片的配置接口兼容，能够从JTAG主机对芯片中的数据进行读取、擦除和写入等操作，可以方便、快速地对FPGA进行配置或程序更新。
但是随着FPGA的不断发展，出现了一些所需配置信息容量更大的FPGA，对于所需配置信息超过32Mbit的FPGA(简称大容量FGPA或大容量可编程逻辑器件)而言，就需要采用SPI Flash、BPI PROM或Platform Flash XL等存储器来对FPGA进行配置，由于这些种类的存储器的接口与对小容量FPGA进行配置的存储器的接口存在较大差异，导致利用这些种类的存储器对FPGA进行配置时的易用性较差。而利用多片存储容量小于或等于32Mbit的存储器进行拼接以对FPGA进行配置的方案又会导致电路元器件较多、占用更多的电路板面积等问题出现。
因此，亟需一种可用于对所需配置信息超过32Mbit的可编程逻辑器件进行配置或更新，且与传统配置接口相兼容的装置。
发明内容
为解决上述技术问题，本发明提供了一种对可编程逻辑器件进行配置或更新的装置和方法，以实现提供一种可用于对所需配置信息超过32Mbit的可编程逻辑器件进行配置或更新，且与传统配置接口相兼容的装置的目的。
为实现上述技术目的，本发明实施例提供了如下技术方案：
一种对可编程逻辑器件进行配置或更新的装置，包括：控制模块和与所述控制模块连接的存储模块，其中，
所述控制模块具有用于与JTAG主机连接的JTAG接口和与待配置可编程逻辑器件兼容的配置接口；
所述控制模块用于在通过所述JTAG接口接收到包含配置信息的第一控制指令后，将所述配置信息存储于所述存储模块中，和用于在接收到配置指令后读取所述配置信息对所述待配置可编程逻辑器件进行配置；
所述控制模块对所述待配置可编程逻辑器件进行配置时使用的配置时钟来源于所述待配置可编程逻辑器件或所述控制模块或外部时钟源。
可选的，所述控制模块还用于根据所述JTAG主机发送的第二控制指令对所述存储模块进行读取或擦除操作。
可选的，所述控制模块还包括通信接口；
所述通信接口用于与上位机连接；
所述控制模块还用于在接收到所述上位机发送的第三控制指令后，根据所述第三控制指令对所述存储模块进行存储、读取和擦除操作。
可选的，所述通信接口为SPI总线接口或IIC总线接口或UART总线接口。
可选的，所述存储模块包括三个存储单元；
所述控制模块对每个所述存储单元进行的操作均相同；
所述控制模块还包括三模冗余投票表决电路；
所述三模冗余投票表决电路用于对所述三个存储单元输出的数据进行三模冗余运算，将所述三个存储单元输出的数据中多数相同的数据作为所述控制模块的读取结果。
可选的，所述存储单元为SPI Flash存储器或BPI Flash存储器或NAND Flash存储器或可编程只读存储器PROM。
可选的，所述控制模块还用于在接收到所述待配置可编程逻辑器件返回的配置完成信号后控制所述存储模块工作于低功耗模式或空闲模式。
可选的，还包括封装体；
所述封装体用于将所述存储模块和所述控制模块封装在一起。
可选的，所述控制模块的具体实现形式为ASIC芯片或CPLD芯片。
一种对可编程逻辑器件进行配置或更新的方法，应用上述任一项所述的对可编程逻辑器件进行配置或更新的装置对待配置可编程逻辑器件进行配置及更新。
从上述技术方案可以看出，本发明实施例提供了一种对可编程逻辑器件进行配置或更新的装置和方法，其中，所述对可编程逻辑器件进行配置或更新的装置包括控制模块和与所述控制模块连接的存储模块，所述控制模块在通过所述JTAG接口接收到包含配置信息的第一控制指令后，将所述配置信息存储于所述存储模块中，由于所述控制模块的配置接口与所述待配置可编程逻辑器件的配置接口相兼容，因此可以在读取所述配置信息后，将其转换为与所述待配置可编程逻辑器件的配置时序兼容的配置信息并向其传送，从而完成对所述待配置可编程逻辑器件进行配置的过程，进而避免了现有技术中由于用于对大容量的待配置可编程逻辑器件进行配置或更新的存储器接口与传统配置接口存 在较大差异而出现的易用性较差的问题。
进一步地，利用所述对可编程逻辑器件进行配置或更新的装置对所述待配置可编程逻辑器件进行配置或更新也无需利用多片存储容量小于或等于32Mbit的存储器进行拼接，从而避免了因此带来的电路元器件较多、电路结构复杂、占用电路板面积较大和系统重量较大的问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本申请的一个实施例提供的一种对可编程逻辑器件进行配置或更新的装置的结构示意图；
图2为本申请的一个实施例提供的对可编程逻辑器件进行配置或更新的装置与JTAG主机连接的结构示意图；
图3为本申请的一个实施例提供的对可编程逻辑器件进行配置或更新的装置与待配置可编程逻辑器件连接的结构示意图；
图4为本申请的一个实施例提供的对可编程逻辑器件进行配置或更新的装置同时与JTAG主机和待配置可编程逻辑器件连接的结构示意图；
图5为本申请的一个优选实施例提供的一种对可编程逻辑器件进行配置或更新的装置的结构示意图；
图6为本申请的一个优选实施例提供的一种对可编程逻辑器件进行配置或更新的装置与上位机连接的结构示意图；
图7为本申请的一个优选实施例提供的一种对可编程逻辑器件进行配置或更新的装置同时与上位机、JTAG主机和待配置可编程逻辑器件连接的结构示意图；
图8为本申请的另一个优选实施例提供的一种对可编程逻辑器件进行配置或更新的装置的结构示意图；
图9为本申请的一个实施例提供的一种三模冗余投票表决电路的结构示意 图；
图10为本申请的一个具体实施例提供的一种对可编程逻辑器件进行配置或更新的装置的结构示意图；
图11为本申请的另一个具体实施例提供的一种对可编程逻辑器件进行配置或更新的装置的结构及与JTAG主机、上位机和待配置可编程逻辑器件连接的示意图；
图12为本申请的一个实施例提供的一种对可编程逻辑器件进行配置或更新的方法的流程示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请实施例提供了一种对可编程逻辑器件进行配置或更新的装置，如图1所示，包括：控制模块100和与所述控制模块100连接的存储模块200，其中，
所述控制模块100具有用于与JTAG主机连接的JTAG接口和与待配置可编程逻辑器件兼容的配置接口；
所述控制模块100用于在通过所述JTAG接口接收到包含配置信息的第一控制指令后，将所述配置信息存储于所述存储模块200中，和用于在接收到配置指令后读取所述配置信息对所述待配置可编程逻辑器件进行配置；
所述控制模块100对所述待配置可编程逻辑器件进行配置时使用的配置时钟来源于所述待配置可编程逻辑器件或所述控制模块100或外部时钟源。
需要说明的是，在待配置可编程逻辑器件的开发调试阶段，如图2和图3所示，在图2中，JTAG主机A通过所述控制模块100的JTAG接口与所述对可编程逻辑器件进行配置或更新的装置连接，所述JTAG主机A经所述JTAG接口向所述控制模块100发送包含配置信息的第一控制指令，所述控制模块 100对所述第一控制指令进行响应，并将所述配置信息写入所述存储模块200。这里的第一控制指令包括所述JTAG主机发送的包含配置信息的编程指令。在对所述存储模块200进行编程(写入)时需要注意的是，如果所述存储模块200是由SPI Flash或NAND Flash或NOR Flash等在写入前需要查空操作的存储器组成的，在将所述配置信息写入所述存储模块200中时需要注意，在写入前需要对所述存储模块200进行查空操作，所述查空操作表示：对所述存储模块200内存储的信息进行查询，如果所述存储模块200内存储的信息为空，则可以对其进行写入操作；如果所述存储模块200内存储的信息不为空，则需要先擦除所述存储模块200内存储的信息，然后才可以对其进行写入操作。
在图3中，所述对可编程逻辑器件进行配置或更新的装置通过所述控制模块100的配置接口与所述待配置可编程逻辑器件B连接，当接收到所述配置指令后读取所述配置信息对所述待配置可编程逻辑器件B进行配置。其中，所述配置指令可以是系统上电信息(即系统上电之后，所述控制模块即读取所述配置信息对所述待配置可编程逻辑器件B进行配置)，也可以是在系统上电后通过设置于所述对可编程逻辑器件进行配置或更新的装置的电路板上的按键触发，本申请对所述配置指令的具体产生和发送方式并不做限定，具体视实际情况而定。
当然，所述对可编程逻辑器件进行配置或更新的装置也可以同时与所述JTAG主机A和所述待配置可编程逻辑器件B连接，如图4所示。
另外，所述控制模块100对所述待配置可编程逻辑器件B进行数据传输时(即对所述待配置可编程逻辑器件B进行配置时)通常需要配置时钟来使所述控制模块100与所述待配置可编程逻辑器件B同步工作。由于所述待配置可编程逻辑器件B一般具有主动配置模式和被动配置模式，当所述可编程逻辑器件处于主动配置模式时，其自身提供在配置过程中所需的所述配置时钟向所述控制模块100传送，以实现所述待配置可编程逻辑器件B和所述控制模块100的时钟同步；当所述可编程逻辑器件处于被动配置模式时，所述控制模块及所述待配置可编程逻辑器件所使用的时钟可以来源于所述控制模块100或外部时钟源。当所述控制模块及所述待配置可编程逻辑器件所使用的时钟来源于所述控制模块100时，所述控制模块100提供所述配置时钟并向所述 待配置可编程逻辑器件B传送以实现配置过程中所述待配置可编程逻辑器件B与所述控制模块100的时钟同步。当所述控制模块及所述待配置可编程逻辑器件B所使用的时钟来源于外部时钟源时，所述外部时钟源通过所述控制模块100的配置接口与所述待配置可编程逻辑器件B的连接节点，分别向所述控制模块100和所述待配置逻辑器件提供配置时钟，以实现配置过程中所述待配置可编程逻辑器件B与所述控制模块100的时钟同步。
所述待配置可编程逻辑器件B的配置模式的选择可以通过改变其相应引脚的电平状态来实现，那么相应的，所述控制模块100对需要接收所述配置时钟还是发送所述配置时钟的判断也可以通过其相应管脚的不同电平状态来实现。
在所述对可编程逻辑器件进行配置或更新的装置中，所述JTAG主机A是指预装有JTAG软件的计算机或FPGA或复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)或单片机或数字信号处理器(Digital Signal Processor，DSP)或其他种类的处理器，本申请对所述JTAG主机A的具体种类并不做限定，具体视实际情况而定。
在本申请中，所述待配置可编程逻辑器件B一般是指现场可编程门阵列(Field－Programmable Gate Array，FPGA)。但在本申请的其他实施例中，所述待配置可编程逻辑器件还可以是数字信号处理器(Digital Signal Processor)。本申请对所述待配置可编程逻辑器件B的种类并不做限定，具体视实际情况而定。
还需要说明的是，由于所述控制模块100的配置接口与所述待配置可编程逻辑器件B相兼容，因此可以在读取所述配置信息后，将其转换为与所述待配置可编程逻辑器件B的配置时序兼容的配置信息并向其传送，从而完成对所述待配置可编程逻辑器件B进行配置的过程，进而避免了现有技术中对于大容量待配置可编程逻辑器件B而言，没有与其传统配置接口兼容的方便易用的配置存储器而出现的易用性较差的问题。这里的大容量待配置可编程逻辑器件B是指所需配置信息超过32Mbit的可编程逻辑器件。
具体地，由于存储器接口与所述待配置可编程逻辑器件B的配置接口的时序不兼容而出现的易用性较差的问题具体包括电路结构复杂、没有方便易用的 JTAG调试接口和占用较多的所述待配置可编程逻辑器件B的管脚的问题。
现有技术中虽然有通过采用多片存储容量小于或等于32Mbit、但接口与传统配置接口兼容的存储器进行拼接以对所述待配置可编程逻辑器件B进行配置或更新的方案，以解决上面提到的易用性较差的问题。但是采用这种方案不可避免地就需要较多的元器件进行拼接配合，这不仅会使得电路方案更加复杂，而且会占用更多的电路板面积，增加系统的重量。这里的传统配置接口的说明见UG002(v2.2)《Virtex-II Platform FPGA User Guide》，对于传统配置接口的典型例子见UG002(v2.2)《Virtex-II Platform FPGA User Guide》第四章286～297页。本申请在此不做赘述。
而利用所述对可编程逻辑器件进行配置或更新的装置对所述待配置可编程逻辑器件B进行配置或更新，则无需利用多片存储容量小于或等于32Mbit的存储器进行拼接，从而避免了因此带来的上述问题。
在上述实施例的基础上，在本申请的一个实施例中，如图2所示，当所述控制模块100与所述JTAG主机A连接时，所述JTAG主机A还可以通过所述JTAG接口向所述控制模块100发送第二控制指令，当所述控制模块100接收到所述第二控制指令后，根据所述第二控制指令对所述存储模块200进行读取或擦除操作。
需要说明的是，所述第二控制指令是指由所述JTAG主机A发送的读取指令或擦除指令，所述控制模块100接收到所述JTAG主机A发送的读取指令时，根据所述JTAG主机A发送的读取指令对所述存储模块200进行读取操作；所述控制模块100接收到所述JTAG主机A发送的擦除指令时，根据所述JTAG主机A发送的读取指令对所述存储模块200进行擦除操作。
在上述实施例的基础上，在本申请的一个优选实施例中，如图5所示，所述控制模块100还包括通信接口；
所述通信接口用于与上位机连接；
所述控制模块100还用于在接收到所述上位机发送的第三控制指令后，根据所述第三控制指令对所述存储模块200进行存储、读取和擦除操作。
相似地，这里的第三控制指令是指通过所述上位机发送的编程指令或读取指令或擦除指令。当所述控制模块100接收到所述上位机发送的读取指令时， 根据所述上位机发送的读取指令对所述存储模块200进行读取操作；所述控制模块100接收到所述上位机发送的擦除指令时，根据所述上位机发送的擦除指令对所述存储模块200进行擦除操作；当所述控制模块100接收到所述上位机发送的编程指令时，根据所述上位机发送的编程指令对所述存储模块200进行写入操作。
同样的，在对所述存储模块200进行编程(写入)时需要注意的是，如果所述存储模块200是由SPI Flash或NAND Flash或NOR Flash等在写入前需要查空操作的存储器组成的，在将所述配置信息写入所述存储模块200中时需要注意，在写入前需要对所述存储模块200进行查空操作，所述查空操作表示：对所述存储模块200内存储的信息进行查询，如果所述存储模块200内存储的信息为空，则可以对其进行写入操作；如果所述存储模块200内存储的信息不为空，则需要先擦除所述存储模块200内存储的信息，然后才可以对其进行写入操作。
需要说明的是，这里的上位机泛指能够通过所述通信接口与所述控制模块100连接，并且能够向所述控制模块100发送第三控制指令的任意的电子设备。但一般而言，为了对所述待配置可编程逻辑器件B的配置或更新的便利性，我们习惯于在所述待配置可编程逻辑器件的调试阶段，利用所述JTAG主机A通过所述JTAG接口与所述控制模块100连接，以对所述存储模块进行配置信息的擦除、读取或写入，进而完成对所述待配置可编程逻辑器件B的配置或更新。当所述待配置可编程逻辑器件B配置完成后进入使用阶段，在这个阶段，我们一般利用所述上位机通过所述通信接口实现与所述控制模块100的连接，以对所述存储模块进行擦除、读取或写入，进而完成对所述待配置可编程逻辑器件B的更新。所述通信接口可以与包括所述JTAG主机A在内的不同种类的上位机C连接，但所述JTAG接口只能与所述JTAG主机A连接。
在本实施例中，如图6所示，当所述通信接口与所述上位机C连接后，所述上位机C可以通过所述通信接口向所述控制模块100发送第三控制指令，以实现对所述存储模块200的写入、读取和擦除操作。那么就意味着利用所述对可编程逻辑器件进行配置或更新的装置不仅可以利用JTAG主机A对所述存储模块200实现配置信息的写入或更新，还可以通过所述上位机C对所述存 储模块200实现配置信息的写入或更新，进而在再次上电后通过所述控制模块100实现对所述待配置可编程逻辑器件B的配置及更新的操作。
同样的，如图7所示，所述对可编程逻辑器件进行配置或更新的装置也可以同时与所述JTAG主机A、上位机C和待配置可编程逻辑器件B连接。
需要说明的是，所述上位机C可以为FPGA或CPLD或单片机或DSP或其他种类的处理器。本申请对所述上位机C的种类并不做限定，具体视实际情况而定。
所述通信接口可以为串行外设(Serial Peripheral Interface，SPI)总线接口或IIC总线接口或通用异步收发传输器(Universal Asynchronous Receiver/Transmitter，UART)总线接口。本申请对所述通信接口的具体种类并不做限定，具体视实际情况而定。
在上述实施例的基础上，在本申请的另一个优选实施例中，如图8所示，所述存储模块200包括三个存储单元210；
所述控制模块100对每个所述存储单元210进行的操作均相同。
所述控制模块100还包括三模冗余投票表决电路；
所述三模冗余投票表决电路用于对所述三个存储单元210输出的数据进行三模冗余运算，将所述三个存储单元210输出的数据中多数相同的数据作为所述控制模块100的读取结果。
在本实施例中，在所述三模冗余投票表决电路对所述三个存储单元210输出的数据进行三模冗余运算获得读取结果(即配置信息)后，所述控制模块100将所述配置信息传输至所述配置接口，并在所述配置接口模拟出所述待配置可编程逻辑器件B的配置时序，以实现利用所述配置信息对所述待配置可编程逻辑器件B进行配置或程序更新的目的。
需要说明的是，在本实施例中，利用三个存储单元210构成所述存储模块200，并在所述控制模块100中设置三模冗余投票表决电路的目的是提高所述对可编程逻辑器件进行配置或更新的装置读出的数据(配置信息)的可靠性，以满足高可靠性要求的应用领域(比如工业级、军级及宇航级等领域的应用需求)。
本申请的一个具体实施例提供了一种可行的三模冗余投票表决电路的结 构，如图9所示。图9中的标号DIN_1、DIN_2和DIN_3为所述三模冗余投票表决电路的输入端，分别于所述三个存储单元210的数据输出端连接；图9中的标号DOUT为所述三模冗余投票表决电路的输出端。
在上述实施例的基础上，在本申请的又一个实施例中，所述存储单元210为SPI Flash存储器或BPI Flash存储器或NAND Flash存储器或可编程只读存储器PROM。本申请对所述存储单元210的具体种类并不做限定，具体视实际情况而定。
在上述实施例的基础上，在本申请的一个优选实施例中，所述控制模块100还用于在接收到所述待配置可编程逻辑器件B返回的配置完成信号后控制所述存储模块200工作于低功耗模式或空闲模式，以降低所述对可编程逻辑器件进行配置或更新的装置的功耗。
需要说明的是，在本实施例中，当所述存储模块200工作于低功耗模式或空闲模式后，还可以通过所述控制模块100的JTAG接口连接所述JTAG主机A，并利用所述JTAG主机A向所述控制模块100发送第一控制指令或第二控制指令以完成对所述存储模块200的存储、读取和擦除操作。
同样的，当所述存储模块200工作于低功耗模式或空闲模式后，仍可以通过所述控制模块100的通信接口连接所述上位机C，并利用所述上位机C向所述控制模块100发送第三控制指令以完成对所述存储模块200的存储、读取和擦除操作。
在上述任一实施例的基础上，在本申请的一个具体实施例中，如图10所示，所述对可编程逻辑器件进行配置或更新的装置还包括封装体300；
所述封装体300用于将所述存储模块200和所述控制模块100封装在一起。
需要说明的是，所述封装体300具有输入输出模块，用于将所述控制模块100的对外接口引出。在本申请的一个实施例中，所述控制模块100的对外接口包括所述配置接口和JTAG接口。在本申请的另一个实施例中，所述控制模块100的对外接口包括所述通信接口、配置接口和JTAG接口。
在上述任一实施例的基础上，在本申请的再一个实施例中，所述控制模块100为专用集成电路(Application Specific Integrated Circuits，ASIC)芯片或可 编程逻辑器件芯片。本申请对所述控制模块100的具体实现形式并不做限定，具体视实际情况而定。
在上述实施例的基础上，本申请的一个具体实施例提供了一种具体的对可编程逻辑器件进行配置或更新的装置的结构及其与JTAG主机A和上位机C连接的示意图。如图11所示，在本实施例中，所述存储单元210为SPI Flash芯片。所述控制模块100的存储单元210控制接口为SPI接口；所述通信接口为SPI接口；在所述待配置可编程逻辑器件B的开发调试阶段，可以使用一台带有USB接口、预装了JTAG软件的计算机作为所述JTAG主机A，所述JTAG主机A经由一条下载线以及相应的插头连接至所述控制模块100的JTAG接口，所述下载线由USB电缆、JTAG电缆及USB转JTAG的转换电路组成。通过所述JTAG主机A中预装的JTAG软件可以通过所述控制模块100对所述三个存储单元210中的数据进行读取、写入和擦除操作。当所述对可编程逻辑器件进行配置或更新的装置通过所述配置接口与所述待配置可编程逻辑器件B连接并且上电后，所述控制模块100自动读取所述三个存储单元210中的数据，对三组数据进行三取二的投票表决，将表决结果作为所述配置信息，并在所述配置接口按照所述待配置可编程逻辑器件B的配置时序发送给所述待配置可编程逻辑器件B，即可完成所述待配置可编程逻辑器件B的上电配置工作。完成对所述待配置可编程逻辑器件B的上电配置之后，与所述待配置可编程逻辑器件B一同工作的上位机C仍然可以通过所述控制模块100实现对所述三个存储单元210中的数据的读取、写入和擦除操作，进而实现所述待配置可编程逻辑器件B功能的更新和升级。
综上所述，本申请实施例提供了一种对可编程逻辑器件进行配置或更新的装置，所述对可编程逻辑器件进行配置或更新的装置包括控制模块100和与所述控制模块100连接的存储模块200，所述控制模块100在通过所述JTAG接口接收到包含配置信息的第一控制指令后，将所述配置信息存储于所述存储模块200中，由于所述控制模块100的配置接口与所述待配置可编程逻辑器件B的配置接口相兼容，因此可以在读取所述配置信息后，将其转换为与所述待配置可编程逻辑器件B的配置时序兼容的配置信息并向其传送，从而完成对所述待配置可编程逻辑器件B进行配置的过程，进而避免了现有技术用于对大 容量的待配置可编程逻辑器件进行配置或更新的存储器接口与传统配置接口存在较大差异而出现的易用性较差的问题。
进一步地，利用所述对可编程逻辑器件进行配置或更新的装置对所述待配置可编程逻辑器件B进行配置或更新也无需利用多片存储容量小于或等于32Mbit的存储器进行拼接，从而避免了因此带来的电路元器件较多、电路结构复杂、占用电路板面积较大和系统重量较大的问题。
相应的，本申请实施例还提供了一种对可编程逻辑器件进行配置或更新的方法，应用上述任一实施例所述的对可编程逻辑器件进行配置或更新的装置对待配置可编程逻辑器件B进行配置及更新。
具体的，在本申请的一个实施例中，如图12所示，所述对可编程逻辑器件进行配置或更新的方法包括：
S101：提供对可编程逻辑器件进行配置或更新的装置，所述对可编程逻辑器件进行配置或更新的装置为上述任一实施例所述的对可编程逻辑器件进行配置或更新的装置；
S102：将JTAG主机A与所述对可编程逻辑器件进行配置或更新的装置连接，并通过所述JTAG主机A向所述对可编程逻辑器件进行配置或更新的装置输入包含配置信息的第一控制指令，所述对可编程逻辑器件进行配置或更新的装置接收到所述第一控制指令后对所述配置信息进行存储；
S103：系统上电后，完成对与所述对可编程逻辑器件进行配置或更新的装置连接的待配置可编程逻辑器件B的配置；
S104：判断是否需要对所述待配置可编程逻辑器件B中的配置信息进行更新，如果是，则进入S105；
S105：利用上位机C或JTAG主机A对所述对可编程逻辑器件进行配置或更新的装置的存储模块进行配置信息的写入或更新，所述对可编程逻辑器件进行配置或更新的装置重新上电后利用所述存储模块中的配置信息对所述待配置可编程逻辑器件B进行更新。
在步骤S102中，所述对可编程逻辑器件进行配置或更新的装置接收到所述第一控制指令后对所述配置信息进行存储时需要注意：如果所述对可编程逻 辑器件进行配置或更新的装置内部的存储模块是由SPI Flash或NAND Flash或NOR Flash等在写入前需要查空操作的存储器组成的，在将所述配置信息写入所述存储模块中时需要注意，在写入前需要对所述存储模块进行查空操作，所述查空操作表示：对所述存储模块内存储的信息进行查询，如果所述存储模块内存储的信息为空，则可以对其进行写入操作；如果所述存储模块内存储的信息不为空，则需要先擦除所述存储模块内存储的信息，然后才可以对其进行写入操作。
具体地，利用与所述对可编程逻辑器件进行配置或更新的装置连接的上位机C对所述待配置可编程逻辑器件B进行更新包括：
利用所述上位机C向所述对可编程逻辑器件进行配置或更新的装置发送第三控制指令，所述对可编程逻辑器件进行配置或更新的装置的控制模块100根据所述第三控制指令对所述对可编程逻辑器件进行配置或更新的装置的存储模块200中的配置信息进行更新，当与所述对可编程逻辑器件进行配置或更新的装置连接的待配置可编程逻辑器件B重新上电后，所述控制模块100自动读取更新后的配置信息对所述待配置可编程逻辑器件B进行配置，实现对所述待配置可编程逻辑器件B的更新。
同样的，利用与所述对可编程逻辑器件进行配置或更新的装置连接的JTAG主机A对所述待配置可编程逻辑器件B进行更新的过程与利用所述上位机C对所述待配置可编程逻辑器件B进行更新的过程类似，本申请在此不做赘述。
综上所述，本申请实施例提供了一种对可编程逻辑器件进行配置或更新的装置和方法，其中，所述对可编程逻辑器件进行配置或更新的装置包括控制模块100和与所述控制模块100连接的存储模块200，所述控制模块100在通过所述JTAG接口接收到包含配置信息的第一控制指令后，将所述配置信息写入所述存储模块200中，由于所述控制模块100的配置接口与所述待配置可编程逻辑器件B的配置接口相兼容，因此可以在读取所述配置信息后，将其转换为与所述待配置可编程逻辑器件B的配置时序兼容的配置信息并向其传送，从而完成对所述待配置可编程逻辑器件B进行配置的过程，进而避免了现有技术中由于用于对大容量的待配置可编程逻辑器件进行配置或更新的存储器接口与传统配 置接口存在较大差异而出现的易用性较差的问题。
进一步地，利用所述对可编程逻辑器件进行配置或更新的装置对所述待配置可编程逻辑器件B进行配置或更新也无需利用多片存储容量小于或等于32Mbit的存储器进行拼接，从而避免了因此带来的电路元器件较多、电路结构复杂、占用电路板面积较大和系统重量较大的问题。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种对可编程逻辑器件进行配置或更新的装置，其特征在于，包括：控制模块和与所述控制模块连接的存储模块，其中，
    所述控制模块具有用于与JTAG主机连接的JTAG接口和与待配置可编程逻辑器件兼容的配置接口；
    所述控制模块用于在通过所述JTAG接口接收到包含配置信息的第一控制指令后，将所述配置信息存储于所述存储模块中，和用于在接收到配置指令后读取所述配置信息对所述待配置可编程逻辑器件进行配置；
    所述控制模块对所述待配置可编程逻辑器件进行配置时使用的配置时钟来源于所述待配置可编程逻辑器件或所述控制模块或外部时钟源。
  2. 根据权利要求1所述的对可编程逻辑器件进行配置或更新的装置，其特征在于，所述控制模块还用于根据所述JTAG主机发送的第二控制指令对所述存储模块进行读取或擦除操作。
  3. 根据权利要求1所述的对可编程逻辑器件进行配置或更新的装置，其特征在于，所述控制模块还包括通信接口；
    所述通信接口用于与上位机连接；
    所述控制模块还用于在接收到所述上位机发送的第三控制指令后，根据所述第三控制指令对所述存储模块进行存储、读取和擦除操作。
  4. 根据权利要求3所述的对可编程逻辑器件进行配置或更新的装置，其特征在于，所述通信接口为SPI总线接口或IIC总线接口或UART总线接口。
  5. 根据权利要求1所述的对可编程逻辑器件进行配置或更新的装置，其特征在于，所述存储模块包括三个存储单元；
    所述控制模块对每个所述存储单元进行的操作均相同；
    所述控制模块还包括三模冗余投票表决电路；
    所述三模冗余投票表决电路用于对所述三个存储单元输出的数据进行三模冗余运算，将所述三个存储单元输出的数据中多数相同的数据作为所述控制模块的读取结果。
  6. 根据权利要求5所述的对可编程逻辑器件进行配置或更新的装置，其 特征在于，所述存储单元为SPI Flash存储器或BPI Flash存储器或NAND Flash存储器或可编程只读存储器PROM。
  7. 根据权利要求1所述的对可编程逻辑器件进行配置或更新的装置，其特征在于，所述控制模块还用于在接收到所述待配置可编程逻辑器件返回的配置完成信号后控制所述存储模块工作于低功耗模式或空闲模式。
  8. 根据权利要求1-7任一项所述的对可编程逻辑器件进行配置或更新的装置，其特征在于，还包括封装体；
    所述封装体用于将所述存储模块和所述控制模块封装在一起。
  9. 根据权利要求1-7任一项所述的对可编程逻辑器件进行配置或更新的装置，其特征在于，所述控制模块的具体实现形式为ASIC芯片或CPLD芯片。
  10. 一种对可编程逻辑器件进行配置或更新的方法，其特征在于，应用权利要求1-9任一项所述的对可编程逻辑器件进行配置或更新的装置对待配置可编程逻辑器件进行配置及更新。
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