WO2018063389A1 - Micro-diodes électroluminescentes à géométries inclinées ou incurvées permettant une efficacité énergétique améliorée - Google Patents

Micro-diodes électroluminescentes à géométries inclinées ou incurvées permettant une efficacité énergétique améliorée Download PDF

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Publication number
WO2018063389A1
WO2018063389A1 PCT/US2016/054985 US2016054985W WO2018063389A1 WO 2018063389 A1 WO2018063389 A1 WO 2018063389A1 US 2016054985 W US2016054985 W US 2016054985W WO 2018063389 A1 WO2018063389 A1 WO 2018063389A1
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Prior art keywords
micro led
geometry
sidewall
layer
substrate
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PCT/US2016/054985
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English (en)
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Khaled Ahmed
Ricky J. TSENG
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Intel Corporation
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Priority to PCT/US2016/054985 priority Critical patent/WO2018063389A1/fr
Priority to TW106127347A priority patent/TW201826567A/zh
Publication of WO2018063389A1 publication Critical patent/WO2018063389A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations

Definitions

  • Micro light emitting diodes are light emitting semiconductor devices of microscale dimensions. Due to their high contrast, fast response times, and low energy consumption compared to organic LEDs (OLEDs), micro LEDs are currently being considered for incorporation into mobile devices, including smartwatches, smartphones, and head-mounted displays.
  • Figure 1A illustrates a square micro LED geometry.
  • Figure IB illustrates a lens-shaped micro LED geometry in accordance with an implementation of the disclosure.
  • Figure 1C illustrates a micro LED geometry with convex angled sidewalls in accordance with an implementation of the disclosure.
  • Figure ID illustrates a micro LED geometry with concave angled sidewalls in accordance with an implementation of the disclosure.
  • Figure IE illustrates a reverse lens-shaped micro LED geometry in accordance with an implementation of the disclosure.
  • Figure IF illustrates a micro LED geometry with opposing lens-shaped portions in accordance with an implementation of the disclosure.
  • Figure 1G illustrates a lens-shaped micro LED with convex angled sidewalls in accordance with an implementation of the disclosure.
  • Figure 1H illustrates a micro LED with convex angled sidewalls and opposing lens- shaped portions in accordance with an implementation of the disclosure.
  • Figure 2 illustrates a simulated device setup for evaluating micro LED efficiency.
  • Figure 3 is a plot illustrating display power reduction versus power efficacy for micro LEDs according to implementations of the disclosure.
  • Figure 4A is a plot showing luminous intensity for various simulated micro LED geometries according to implementations of the disclosure.
  • Figure 4B is a plot showing luminance for various simulated micro LED geometries according to implementations of the disclosure.
  • Figure 5 is a flow diagram illustrating a method of fabricating a micro LED with angled or curved geometry according to an implementation of the disclosure.
  • Figure 6A illustrates an intermediate structure during the fabrication of a micro LED according to an implementation of the disclosure.
  • Figure 6B illustrates another intermediate structure during the fabrication of a micro LED according to an implementation of the disclosure.
  • Figure 6C illustrates a micro LED fabricated according to an implementation of the disclosure.
  • Figure 6D illustrates a micro LED after subsequent processing according to an implementation of the disclosure.
  • Figure 7 illustrates a micro LED having a square geometry after fabrication according to an implementation of the disclosure.
  • Figure 8 illustrates a micro LED having a lens-shaped geometry after fabrication according to an implementation of the disclosure.
  • Figure 9 is an electron micrograph of a side profile of a micro LED with square geometry.
  • Figure 10 is an electron micrograph of a side profile of a micro LED with convex angled sidewalls fabricated according to an implementation of the disclosure.
  • Figure 11 is an interposer for use with one or more of the implementations of the disclosure.
  • Figure 12 is a computing device built in accordance with implementations of the disclosure.
  • Micro LED technology is a competing technology in the emerging display technology space.
  • a significant factor affecting power consumption in micro LED technologies is difficulty in achieving high external quantum efficiency.
  • External quantum efficiency (which may also be referred to as "light extraction efficiency”) is limited by internal reflection at the boundary between the material of a given LED and its surrounding medium. Due to a large difference of the refractive index at the boundary, much of the generated light is "trapped" inside the LED, and is often re-absorbed or wasted as heat within the LED before it is able to exceed the critical angle (typically about 16 degrees (°) from a direction normal to the interface of the LED and its surrounding medium) needed for it to escape. Consequently, overall transmitted light from the LED is low, with greater power needed to achieve practical levels of illumination.
  • the disclosed implementations improve external quantum efficiency by altering the micro LED geometry, which greatly increases the chances of the generated light overcoming the critical angle limitation and thus escaping from the micro LED structure.
  • Certain implementations utilize angled sidewalls, curved surfaces, and combinations thereof, which improve the external quantum efficiency significantly (e.g., an increase from a 15% baseline to greater than 60%).
  • Another way is to passivate with higher refractive index dielectric materials, such as silicon nitride (SiN), silicon dioxide (Si0 2 ), AlOx, and/or TiOx, as a surrounding medium for the micro LED device. Such passivation may reduce the index difference between the micro LED material and air, which increases the critical angle for light extraction.
  • the terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate.
  • the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure.
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V, group IV materials, or group Ill-nitrides, such as gallium nitride (GaN).
  • a plurality of transistors such as metal-oxide- semiconductor field-effect transistors
  • MOSFET metal-oxide-semiconductor
  • the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both.
  • Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
  • implementations may also be carried out using nonplanar transistors.
  • Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer.
  • the gate dielectric layer may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide and/or a high-k dielectric material.
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
  • the gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor.
  • the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide.
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.
  • the gate electrode when viewed as a cross-section of the transistor along the source-channel-drain direction, may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U- shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack.
  • the sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are known in the art and generally include deposition and etching. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
  • source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor.
  • the source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process.
  • dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions.
  • An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process.
  • the substrate may first be etched to form recesses at the locations of the source and drain regions.
  • the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
  • the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further implementations, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
  • ILD interlayer dielectrics
  • the ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials.
  • dielectric materials include, but are not limited to, Si0 2 , carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or
  • the ILD layers may include pores or air gaps to further reduce their dielectric constant.
  • Figures 1A-1H illustrate several exemplary micro LED geometries in accordance with various implementations of the disclosure.
  • Figure 1A for example, illustrates a micro
  • the micro LED 100 having a square geometry.
  • the micro LED 100 includes a lower contact 102, a multiple quantum well (MQW) layer 104, and an upper contact 106, and is disposed on a support 108.
  • MQW multiple quantum well
  • each of the contacts 102 and 106 may be, for example, doped semiconductor layers.
  • the contact 102 may be a P-type semiconductor layer and the contact 106 may be an N-type semiconductor layer, or vice versa.
  • the contacts 102 and 106 may include materials such as silicon, germanium, or other III-V materials.
  • the contacts 112, 116, 122, 126, 132, 136, 142, 146, 152, 156, 162, 166, 172, and 176 of Figures 1B-1H may be similar in composition to contacts 102 and 106.
  • the MQW layer 104 has a composition tuned for the emission light at particular wavelengths.
  • the MQW layer 104 may include indium gallium nitride in different ratios to produce blue/green light, or may include aluminum indium gallium phosphide to produce red light.
  • a "multiple quantum well" or “MQW” refers to a multi-layered semiconductor structure for which quantum mechanical effects may be controlled.
  • a layer within the MQW may confine particles (e.g., electrons or holes) in one dimension, but allow movement of the particles in other dimensions.
  • the MQW layer 104 may include one or more stacks that include a layer of indium gallium nitride (InGaN) above a layer of GaN.
  • InGaN indium gallium nitride
  • a stack within the MQW layer 104 may be repeated multiple times (e.g., 4-8 times).
  • the indium content of the InGaN layers for a MQW may be approximately 40% for a red LED, 38-39% for a yellow LED, 35% for a green LED, and 25% for blue LED.
  • the tolerance for the aforementioned indium content for the different color LEDs may be + 3%.
  • the term "wavelength" may refer to the peak emission wavelength of a light emitting device. It may be noted that a typical emission spectra of a semiconductor light emitting device is a narrow band of wavelength centered around the peak wavelength.
  • Each of the MQW layers 114, 124, 134, 144, 154, 164, and 174 of Figures 1B-1H may be similar to the MQW layer 104.
  • Each of the supports 108, 118, 128, 138, 148, 158, 168, and 178 illustrated in Figures 1A-1H may be a substrate or one or more layers disposed on the substrate, such as a semiconductor layer, a metal layer, a layer formed according to a damascene process (e.g., a conductor embedded in an insulator), etc.
  • a damascene process e.g., a conductor embedded in an insulator
  • compositions of the various micro LEDS 100, 110, 120, 130, 14, 150, 160, and 170 may be similar, their overall geometries differ and affect their light extraction efficiencies.
  • a given micro LED may be exposed to air or vacuum, or may be encapsulated within a material, such as a dielectric layer.
  • additional materials/layers may be deposited adjacent to or on top of a given micro LED.
  • Figures 1A-1H illustrate side profiles of different micro LEDs, the micro LEDs, from a top down perspective, may be of any suitable shape, including, but not limited to, square, rectangular, circular, oval, triangular, etc.
  • the micro LED 100 has a square geometry with substantially verticals sidewalls and a planar upper surface.
  • the contact 102, the MQW 104, and the contact 106 define
  • an upper surface of the contact 106 is planar and parallel with respect to a lower surface of the contact 102.
  • the micro LED 110 has a convex lens-shaped geometry with the contact 116 having a curved top surface that meets substantially vertical sidewalls that extend down to the support 118.
  • the contact 112, the MQW layer 114, and a first portion of the contact 116 define substantially vertical sidewalls, while a second portion of the contact 116 defines a convex curved upper surface.
  • the lens-shaped geometry of the contact 116 may have a spherical curvature or the curvature of an optical lens.
  • the contact 116 may have a concave lens-shaped geometry, with the upper surface of the contact 116 defining a concave curve.
  • the micro LED 120 has a convex angled sidewall geometry, with the contact 122, the MQW layer 124, and the contact 126 defining planar angled sidewalls that extend in an inward direction from the support 128.
  • An angle of the sidewalls, or portions thereof, are with respect to a lower surface of the contact 122 (i.e., the interface between the contact 122 and the support 128.
  • the angle of the sidewalls of the micro LED 120 illustrated as a 70° angle. In certain implementations, other angles may be used. In certain
  • different sidewalls may define different angles with respect to the lower surface of the contact 122.
  • an upper surface of the contact 126 is planar and parallel with respect to the lower surface of the contact 122.
  • the micro LED 130 has a concave angled sidewall geometry, with the contact 132, the
  • the MQW layer 134, and the contact 136 defining angled sidewalls that extend in an outward direction from the support 138.
  • the angle of the sidewalls, or portions thereof are with respect to a lower surface of the contact 132 (i.e., the interface between the contact 132 and the support 138.
  • the angle of the sidewalls of the micro LED 120 illustrated as a 110° angle.
  • an upper surface of the contact 136 is planar with respect to the lower surface of the contact 132.
  • the micro LED 140 has a reverse lens- shaped geometry, with the MQW layer 144 and the contact 146 defining substantially vertical sidewalls, and the contact 142 defining a convex curved surface such that an apex of the concave surface contacts the support 148.
  • an upper surface of the contact 146 is planar with respect to the lower surface of the support 148 (i.e., parallel to a tangent plane of the apex of the contact 142).
  • the micro LED 150 has a geometry with opposing lens-shaped portions.
  • Each of the contacts 152 and 156 define convex curved surfaces with the MQW layer 154 disposed therebetween.
  • the MQW layer 154 defines substantially vertical sidewalls.
  • the micro LED 160 has a convex lens-shaped geometry with convex angled sidewalls.
  • the contact 162, the MQW layer 164, and a first portion of the contact 166 define planar angled sidewalls, while a second portion of the contact 166 defines a convex curved upper surface.
  • the micro LED 170 has geometry with convex angled sidewalls and opposing lens- shaped portions.
  • the MQW layer 174 and a portion of the contact 176 define planar angled sidewalls, while a second portion of the contact 176 defines a convex curved upper surface.
  • the contact 172 defines a convex curved surface such that an apex of the concave surface contacts the support 178.
  • Figure 2 illustrates a simulated device setup 200 for evaluating micro LED efficiency.
  • the device setup 200 includes a micro LED 202 having a central MQW layer 204 disposed between an upper semiconductor contact layer 206 and a lower semiconductor contact layer 204.
  • a detector 212 is disposed 1 millimeter away from the micro LED 202.
  • a metal reflector 210 is disposed behind the micro LED 202 for reflecting emitted light toward the detector 212.
  • a light ray 214 is depicted as originating from the MQW layer, reflecting off an internal surface of the upper semiconductor contact layer 206, and escaping toward the detector 212.
  • the dimensions of the micro LED 202 are 5x5x5 ⁇ , with the MQW layer 204 being 0.4 ⁇ thick.
  • the micro LED 202 is illustrated as having a square geometry, other geometries may be simulated, such as any of the geometries illustrated in Figures 1B-1H.
  • Three device geometries were simulated based on the simulated device setup 200, including a square geometry (e.g., micro LED 100), a lens-shaped geometry (e.g., micro LED 110), and an angled- sidewall geometry (e.g., micro LED 120).
  • the square geometry micro LED was defined to be 5 ⁇ in width, 5 ⁇ in length, and 5 ⁇ in height.
  • the lens- shaped micro LED was defined to have similar dimensions as the square geometry micro LED, except for the addition of a curved cap with a radius of 2.5 ⁇ .
  • the angled- sidewall geometry micro LED included angled sidew alls oriented at approximately 73° with respect to a lower surface of the micro LED, with the lower surface and an upper surface of the micro LED being 5x5 ⁇ and 2x2 ⁇ , respectively.
  • the simulations revealed that the square geometry resulted in an external quantum efficiency of 14.4%, the lens-shaped geometry resulted in an external quantum efficiency of 45%, and the angled- sidewall geometry resulted in an external quantum efficiency of 66%, with the lens- shaped geometry and the angled- sidewall geometry yielding a 3 and 4.5 times higher efficiency, respectively, than the square geometry.
  • Figure 3 is a plot 300 illustrating display power reduction versus power efficacy of red, green, and blue micro LEDs based on simulations of the micro LED geometry, which illustrates the large power efficacy needed for achieving 5x power reduction.
  • the power efficacies labeled as 200 lm/W, 100 lm/W, and 50 lm/W correspond to green micro LEDs.
  • Figure 4A is a plot 400 showing luminous intensity for various simulated micro LED geometries, including a square geometry 402, a lens-shaped geometry 404, and an angled- sidewall geometry 406.
  • Figure 4B is a plot 450 showing luminance for a square geometry 452, a lens geometry 454, and an angled geometry 456. In each plot, the luminous intensity and luminance for the angled-sidewall and lens-shaped geometries appear to be about 4.5 times greater than that of the square geometry.
  • Figure 5 is a flow diagram illustrating a method 500 for fabricating a micro LED with angled or curved geometry according to an implementation of the disclosure. Certain elements of the method 500 may be performed in a different order, simultaneously with other elements, or with additional intermediate elements, and certain elements may be omitted in some implementations, as would be appreciated by one of ordinary skill in the art.
  • the process begins at block 510, where a metal contact is deposited onto a substrate.
  • the metal contact may be deposited, for example, by physical vapor deposition (PVD), such as sputtering or evaporation, or by chemical vapor deposition (CVD).
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • the metal contact may have one or more intervening layers/materials between it and the substrate.
  • the metal contact may be patterned, e.g., using photolithographic methods.
  • a layered stack is formed on the metal contact.
  • the layered stack may comprise multiple semiconductor layers (e.g., III-V or III-N semiconductors).
  • one or more of the layers may be doped prior to the formation of the next layer in the stack.
  • the layered stack includes an MQL layer, which may be a heteroepitaxial III-V semiconductor film stack that of GaN or GaP and/or alloys thereof (e.g., InGaN or InGaP).
  • Any suitable deposition technique may be used for depositing the layered stack, including, but not limited to PVD, CVD, and epitaxial methods.
  • the substrate 602 may be selected from a variety of materials including, but not limited to, sapphire, quartz, silicon dioxide, silicon, gallium nitride (GaN), germanium, silicon carbide, such as 3C-silicon carbide (3C-SiC), or combinations thereof.
  • the substrate 602 is single-crystal silicon having a crystallographic orientation of (100), (111), (110), or other crystallographic orientation.
  • the layered stack 608 may include a lower semiconductor layer 610, an upper semiconductor layer 614, and an MQW layer 612 disposed therebetween.
  • the lower semiconductor layer 610 and the upper semiconductor layer 614 are doped III-V semiconductors (e.g., with the lower semiconductor layer 610 being a P-type semiconductor and the upper semiconductor layer 614 being an N-type semiconductor layer, or vice versa).
  • the MQW layer 612 may be an undoped, multi-layered stack comprising InGaP, InGaN, AlInGaP, AlInGaN, or combinations thereof with various atomic ratios.
  • the MQW layer 612 is grown epitaxially.
  • the intermediate layer 606 is a doped semiconductor layer. In certain implementations, the intermediate layer 606 is omitted. In certain implementations, additional layers may be included.
  • a thickness of each of the lower semiconductor layer 610 and the upper semiconductor layer 614 is independently selected from 1 ⁇ to 5 ⁇ .
  • a total thickness of the MQW layer 612 (including all sub-layers) is from 0.1 ⁇ to 2 ⁇ , or from 0.5 ⁇ to 1 ⁇ .
  • an overall thickness of the layered stack 608 ranges from 2 ⁇ to 15 ⁇ , or from 3 ⁇ to 10 ⁇ .
  • a mask layer is deposited above the layered stack, which may be patterned to produce a hard mask (e.g., using photolithographic methods).
  • An exemplary hard mask 616 is illustrated Figure 6B, which is shown as having been patterned on the layered stack 608.
  • the hard mask 616 may be may be from 200 nm to 1000 nm in thickness.
  • the patterned hard mask 616 may expose portions of the layered stack 608 so that the exposed portions can be etched while portions of the layered stack 608 directly beneath the hard mask 616 are protected.
  • regions of the layered stack that are exposed by the patterned hard mask are etched to form a micro LED. Endpoint detection procedures may be utilized to detect when the etching is complete. After etching, the hard mask may be removed, for example, by a planarization process.
  • FIG. 6C illustrates a micro LED 620 having been patterned in accordance with block 540.
  • the micro LED includes a lower surface 622, an upper surface 624, and an angled sidewall 626.
  • An angle 628 of the angled sidewall 626 with respect to the lower surface 622 may be selected to range from, for example, 60° to 80°.
  • the etch chemistry as well as the compositions of the layers of the micro LED 620 and the intermediate layer 606 may be selected and optimized for producing the angled geometry of the micro LED 620 and the intermediate layer 606, as well as for producing any of the other geometries disclosed herein.
  • a metal contact is formed on the micro LED using any suitable deposition process.
  • the micro LED is encapsulated in a dielectric layer to provide electrical isolation and physical support.
  • the dielectric layer comprises one or more of SiN, Si0 2 , AlOx, or TiOx.
  • the micro LED is not encapsulated but is maintained in air or under vacuum conditions.
  • any other subsequent processing is performed, such as the deposition of a conducting indium tin oxide (ITO) layer above the dielectric layer.
  • ITO conducting indium tin oxide
  • Figure 6D illustrates a dielectric layer 632, an upper contact layer 634, and an upper transparent layer 630 (e.g., an ITO layer), which may have been deposited in accordance with blocks 550, 560, and 570 of the method 500.
  • Figures 7 and 8 illustrate other geometries that may be fabricated in accordance with various implementations of the method 500.
  • Figure 7 illustrates a micro LED 720 having a square geometry.
  • the micro LED 700 includes a lower semiconductor layer 710, an upper semiconductor layer 714, and an MQW layer 712 disposed therebetween.
  • An intermediate layer 706 and lower contact layer 704 may be disposed between the micro LED 720 and a substrate 702.
  • Figure 8 illustrates a micro LED 720 having a lens-shaped geometry.
  • the micro LED 800 includes a lower semiconductor layer 810, an upper semiconductor layer 814 having a lens-shaped upper surface, and an MQW layer 812 disposed therebetween.
  • An intermediate layer 806 and lower contact layer 804 may be disposed between the micro LED 820 and a substrate 802.
  • Figure 9 is an electron micrograph 900 of a side profile of a micro LED 902 with square geometry.
  • the micro LED 902 includes a lower P-type semiconductor layer 904, an
  • the lower surface of the micro LED 902 surface being contacts a metal contact layer 910 on a substrate 914.
  • the micro LED 902 has near- vertical sidewalls 912, with the slight curvature being an artifact of the etching process.
  • the structure shown in the electron micrograph 900 is similar to the schematic of Figure 7, except that no intermediate layer 606 is present.
  • Figure 10 is an electron micrograph 1000 of a side profile of a micro LED 1002 with convex angled sidewalls 1025 fabricated according to an implementation of the disclosure.
  • the micro LED 1002 includes a lower N-type semiconductor layer 1004, an MQW layer
  • the micro LED 1002 is encapsulated within an oxide layer 1018 and is disposed between an upper metal contact 1016 and an intermediate N-type semiconductor layer 1010, which contacts a lower metal contact 1012 on a substrate 1014.
  • An upper transparent layer 630 e.g., ITO
  • An angle between the sidewall 1025 and a lower surface of the micro LED is about 62°.
  • the micro LEDs 902 and 1002 were produced according to an exemplary implementation for illustrative purposes. It is to be understood that the
  • implementations described herein may be modified as desired to optimize the etching process and improve the uniformity of the sidewalls, as well as modify the etching process to produce different micro LED geometries, as would be appreciated by one of ordinary skill in the art.
  • FIG 11 illustrates an interposer 1100 for use with one or more implementations of the disclosure.
  • the interposer 1100 is an intervening substrate used to bridge a first substrate 1102 to a second substrate 1104.
  • the first substrate 1102 may be, for instance, an integrated circuit die.
  • the second substrate 1104 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 1100 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 1100 may couple an integrated circuit die to a ball grid array (BGA) 1106 that can subsequently be coupled to the second substrate 1104.
  • BGA ball grid array
  • the first and second substrates 1102/1104 are attached to opposing sides of the interposer 1100. In other implementations, the first and second substrates 1102/1104 are attached to the same side of the interposer 1100. And in further implementations, three or more substrates are interconnected by way of the interposer 1100.
  • the interposer 1100 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further,
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer may include metal interconnects 1108 and vias 1110, including but not limited to through- silicon vias (TSVs) 1112.
  • the interposer 1100 may further include embedded devices 1114, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1100.
  • RF radio-frequency
  • apparatuses or processes disclosed herein may be used in the fabrication of the interposer 1100, and/or may be interfaced directly with the interposer 1100.
  • Figure 12 illustrates a computing device 1200 built in accordance with
  • the computing device 1200 may include a number of components. In one implementation, these components are attached to one or more motherboards. In an alternate implementation, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as an SoC used for mobile devices.
  • SoC system-on-a-chip
  • the components in the computing device 1200 include, but are not limited to, an integrated circuit die 1202 and at least one communications logic unit 1208.
  • the communications logic unit 1208 is fabricated within the integrated circuit die 1202 while in other implementations the communications logic unit 1208 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 1202.
  • the integrated circuit die 1202 may include a CPU 1204 as well as on-die memory 1206, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin-transfer torque memory (STT-MRAM). It may be noted that, in certain implementations, the integrated circuit die 1202 may include fewer elements (e.g., without the processor 1204 and/or on-die memory 1206) or additional elements other than the processor 1204 and on-die memory 1206. In one implementation, integrated circuit die 1202 may include one or more micro LED arrays 1205 with or without the processor 1204 and/or on-die memory 1206.
  • eDRAM embedded DRAM
  • SRAM spin-transfer torque memory
  • integrated circuit die 1202 may be a part of a micro LED-based display device with multiple micro LED arrays 1205 and a thin film transistor (TFT) backplane, with or without the processor 1204 and/or on-die memory 1206.
  • the integrated circuit die 1202 may include some or all the elements described herein, as well as include additional elements.
  • Computing device 1200 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1210 (e.g., DRAM), nonvolatile memory 1212 (e.g., ROM or flash memory), a graphics processing unit 1214 (GPU), a digital signal processor 1216, a crypto processor 1242 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 1220, at least one antenna 1222 (in some implementations two or more antenna may be used), a display or a touchscreen display 1224 (e.g., incorporating one more arrays of the micro LEDs disclosed herein), a touchscreen controller 1226, a battery 1230 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1228 (which may further include a compass), a motion coprocessor or sensors 1232 (that may include an accelerometer,
  • the computing device 1200 may incorporate further transmission, telecommunication, or radio functionality not already described herein.
  • the computing device 1200 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.
  • the computing device 1200 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.
  • the communications logic unit 1208 enables wireless communications for the transfer of data to and from the computing device 1200.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some implementations they might not.
  • the communications logic unit 1208 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 1200 may include a plurality of communications logic units 1208. For instance, a first communications logic unit 1208 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second
  • communications logic unit 1208 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1204 of the computing device 1200 includes one or more devices, such as transistors, metal interconnects, or micro LEDs formed in accordance with
  • processor may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communications logic unit 1208 may also include one or more devices, such as transistors, metal interconnects, or micro LEDs formed in accordance with implementations of the disclosure.
  • another component housed within the computing device 1200 may contain one or more devices, such as transistors, metal interconnects, or micro LEDs formed in accordance with implementations of the disclosure.
  • the computing device 1200 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 1200 may be any other electronic device that processes data.
  • Example 1 is an apparatus comprising a substrate and a micro LED formed above the substrate.
  • the micro LED comprises an upper surface, a lower surface, and a sidewall.
  • a geometry of the micro LED includes an angled sidewall geometry, a lens-shaped geometry, or a combination thereof.
  • the angled sidewall geometry is such that an angle between the sidewall and the lower surface is from 60° to 80° or from 100° to 120°.
  • Example 2 the subject matter of Example 1 can optionally provide that the angle between the sidewall and the lower surface is from 60° to 65° or from 115° to 120°.
  • Example 3 the subject matter of Example 1 can optionally provide that the angle between the sidewall and the lower surface is from 65° to 70° or from 110° to 115°.
  • Example 4 the subject matter of Example 1 can optionally provide that the angle between the sidewall and the lower surface is from 70° to 75° or from 105° to 110°.
  • Example 5 the subject matter of Example 1 can optionally provide that the angle between the sidewall and the lower surface is from 75° to 80° or from 100° to 105°.
  • Example 6 the subject matter of any one of Examples 1-5 can optionally provide that the sidewall spans from the lower surface to the top surface.
  • Example 7 the subject matter of any one of Examples 1-6 can optionally provide that the upper surface of the micro LED defines a concave or convex curve.
  • Example 8 the subject matter of any one of Examples 1-7 can optionally provide that an external quantum efficiency of the micro LED is greater than 40%.
  • Example 9 the subject matter of any one of Examples 1-7 can optionally provide that an external quantum efficiency of the micro LED is greater than 50%.
  • Example 10 the subject matter of any one of Examples 1-7 can optionally provide that an external quantum efficiency of the micro LED is greater than 60%.
  • Example 11 the subject matter of any one of Examples 1-7 can optionally provide that an external quantum efficiency of the micro LED is greater than 65%.
  • Example 12 the subject matter of any one of Examples 1-11 can optionally provide that the micro LED comprises a layered stack.
  • the layered stack comprises: a lower conductive layer that defines the lower surface of the micro LED; a upper conductive layer that defines the upper surface of the micro LED; and a multi quantum well (MQW) layer disposed between and in contact with the lower conductive layer and the upper conductive layer.
  • MQW multi quantum well
  • Example 13 the subject matter of Example 12 can optionally provide that the MQW layer comprises indium gallium nitride or aluminum indium gallium phosphide.
  • Example 14 the subject matter of any of Examples 12-13 can optionally provide that the upper conductive layer comprises a P-type semiconductor (i.e., a doped
  • the lower conductive layer comprises an N-type semiconductor.
  • Example 15 the subject matter of any of Examples 12-13 can optionally provide that the upper conductive layer comprises an N-type semiconductor, and the lower conductive layer comprises a P-type semiconductor.
  • Example 16 the subject matter of any one of Examples 1-15 can optionally provide that a height of the micro LED is less than 10 micrometers, and a width of the micro LED is less than 10 micrometers.
  • Example 17 the subject matter of any one of Examples 1-16 can optionally provide that a semiconductor layer is disposed between the lower surface of the micro LED and the substrate.
  • Example 18 the subject matter of Example 17 can optionally provide a lower metal contact layer is disposed between the semiconductor layer and the substrate, with the metal layer being in contact with both the semiconductor layer and the substrate.
  • Example 19 the subject matter of any one of Examples 1-18 can optionally provide that an upper metal contact layer is disposed above and in contact with the upper surface of the micro LED.
  • Example 20 is a display device comprising: a backplane interface comprising a plurality of metal interconnects; and an array of micro LEDs.
  • An individual micro LEDs of the array is electrically coupled to at least one of the plurality of metal interconnects.
  • the individual micro LED comprises: an upper surface, a lower surface, and a sidewall.
  • a geometry of the individual micro LED includes an angled sidewall geometry, a lens- shaped geometry, or a combination thereof. The angled sidewall geometry is such that an angle between the sidewall and the lower surface is from 60° to 80° or from 100° to 120°.
  • Example 21 the subject matter of Example 20 can optionally provide that the angle between the sidewall and the lower surface is from 60° to 65° or from 115° to 120°.
  • Example 22 the subject matter of Example 20 can optionally provide that the angle between the sidewall and the lower surface is from 65° to 70° or from 110° to 115°.
  • Example 23 the subject matter of Example 20 can optionally provide that the angle between the sidewall and the lower surface is from 70° to 75° or from 105° to 110°.
  • Example 24 the subject matter of Example 20 can optionally provide that the angle between the sidewall and the lower surface is from 75° to 80° or from 100° to 105°.
  • Example 25 the subject matter of any one of Examples 20-24 can optionally provide that the sidewall of the individual micro LED spans from the lower surface to the top surface.
  • Example 26 the subject matter of any one of Examples 20-25 can optionally provide that the upper surface of the individual micro LED defines a concave or convex curve.
  • Example 27 the subject matter of any one of Examples 20-26 can optionally provide that an external quantum efficiency of the individual micro LED is greater than 40%.
  • Example 28 the subject matter of any one of Examples 20-26 can optionally provide that an external quantum efficiency of the individual micro LED is greater than 50%.
  • Example 29 the subject matter of any one of Examples 20-26 can optionally provide that an external quantum efficiency of the individual micro LED is greater than 60%.
  • Example 30 the subject matter of any one of Examples 20-26 can optionally provide that an external quantum efficiency of the individual micro LED is greater than 65%.
  • Example 31 the subject matter of any one of Examples 20-30 can optionally provide that the individual micro LED comprises a layered stack.
  • the layered stack comprises: a lower conductive layer that defines the lower surface of the individual micro LED; a upper conductive layer that defines the upper surface of the individual micro LED; and a multi quantum well (MQW) layer disposed between and in contact with the lower conductive layer and the upper conductive layer.
  • MQW multi quantum well
  • Example 32 the subject matter of Example 31 can optionally provide that the MQW layer comprises indium gallium nitride or aluminum indium gallium phosphide.
  • Example 33 the subject matter of any of Examples 31-32 can optionally provide that the upper conductive layer comprises a P-type semiconductor, and the lower conductive layer comprises an N-type semiconductor.
  • Example 34 the subject matter of any of Examples 31-32 can optionally provide that the upper conductive layer comprises an N-type semiconductor, and the lower conductive layer comprises a P-type semiconductor.
  • Example 35 the subject matter of any one of Examples 20-35 can optionally provide that a height of the individual micro LED is less than 10 micrometers, and a width of the individual micro LED is less than 10 micrometers.
  • Example 36 the subject matter of any one of Examples 20-36 can optionally provide that a semiconductor layer is disposed between the lower surface of the individual micro LED and the substrate.
  • Example 37 the subject matter of Example 36 can optionally provide a lower metal contact layer is disposed between the semiconductor layer and the substrate, with the metal layer being in contact with both the semiconductor layer and the substrate.
  • Example 38 the subject matter of any one of Examples 20-37 can optionally provide that an upper metal contact layer is disposed above and in contact with the upper surface of the individual micro LED.
  • Example 39 is a method of forming a micro LED.
  • the method comprises forming a layered stack above a substrate, and etching the layered stack to form the micro LED.
  • the micro LED comprises an upper surface, a lower surface, and a sidewalk
  • a geometry of the micro LED includes an angled sidewall geometry, a lens-shaped geometry, or a combination thereof.
  • the angled sidewall geometry is such that an angle between the sidewall and the lower surface is from 60° to 80° or from 100° to 120.
  • Example 40 the subject matter of Example 39 can optionally provide that the angle between the sidewall and the lower surface is from 60° to 65° or from 115° to 120°.
  • Example 41 the subject matter of Example 39 can optionally provide that the angle between the sidewall and the lower surface is from 65° to 70° or from 110° to 115°.
  • Example 42 the subject matter of Example 39 can optionally provide that the angle between the sidewall and the lower surface is from 70° to 75° or from 105° to 110°.
  • Example 43 the subject matter of Example 39 can optionally provide that the angle between the sidewall and the lower surface is from 75° to 80° or from 100° to 105°.
  • Example 44 the subject matter of any one of Examples 39-43 can optionally provide that the sidewall spans from the lower surface to the top surface.
  • Example 45 the subject matter of any one of Examples 39-44 can optionally provide that the upper surface of the micro LED defines a concave or convex curve.
  • Example 46 the subject matter of any one of Examples 39-45 can optionally provide that an external quantum efficiency of the micro LED is greater than 40%.
  • Example 47 the subject matter of any one of Examples 39-46 can optionally provide that an external quantum efficiency of the micro LED is greater than 50%.
  • Example 48 the subject matter of any one of Examples 39-47 can optionally provide that an external quantum efficiency of the micro LED is greater than 60%.
  • Example 49 the subject matter of any one of Examples 39-47 can optionally provide that an external quantum efficiency of the micro LED is greater than 65%.
  • Example 50 the subject matter of any one of Examples 39-49 can optionally provide that the micro LED comprises a layered stack.
  • the layered stack comprises: a lower conductive layer that defines the lower surface of the micro LED; a upper conductive layer that defines the upper surface of the micro LED; and a multi quantum well (MQW) layer disposed between and in contact with the lower conductive layer and the upper conductive layer.
  • MQW multi quantum well
  • Example 51 the subject matter of Example 50 can optionally provide that the MQW layer comprises indium gallium nitride or aluminum indium gallium phosphide.
  • Example 52 the subject matter of any of Examples 50-51 can optionally provide that the upper conductive layer comprises a P-type semiconductor, and the lower conductive layer comprises an N-type semiconductor.
  • Example 53 the subject matter of any of Examples 50-51 can optionally provide that the upper conductive layer comprises an N-type semiconductor, and the lower conductive layer comprises a P-type semiconductor.
  • Example 54 the subject matter of any one of Examples 39-53 can optionally provide that a height of the micro LED is less than 10 micrometers, and a width of the micro LED is less than 10 micrometers.
  • Example 55 the subject matter of any one of Examples 39-54 can optionally provide that the method further comprises depositing a lower metal contact layer on the substrate prior to forming the layered stack.
  • Example 56 the subject matter of Example 55 can optionally provide that the method further comprises depositing a semiconductor layer on the lower metal contact layer prior to forming the layered stack.
  • Example 57 the subject matter of any one of Examples 39-56 can optionally provide that the method further comprises depositing an upper metal contact layer above and in contact with the upper surface of the micro LED.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

La présente invention concerne des dispositifs incorporant des micro-diodes électroluminescentes à géométries inclinées ou incurvées, et des procédés de production desdits dispositifs incorporant des micro-diodes électroluminescentes à géométries inclinées ou incurvées. Dans un mode de réalisation, un appareil comprend un substrat et une micro-diode électroluminescente formée au-dessus du substrat. La micro-DEL comprend une surface supérieure, une surface inférieure et une paroi latérale. Une géométrie de la micro-DEL peut être sélectionnée à partir d'une géométrie de paroi latérale inclinée, d'une géométrie en forme de lentille, ou d'une combinaison de ces dernières.
PCT/US2016/054985 2016-09-30 2016-09-30 Micro-diodes électroluminescentes à géométries inclinées ou incurvées permettant une efficacité énergétique améliorée WO2018063389A1 (fr)

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TW106127347A TW201826567A (zh) 2016-09-30 2017-08-11 具有用於改善功率效率之斜角或曲面幾何之微型發光二極體

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WO2023142151A1 (fr) * 2022-01-31 2023-08-03 Jade Bird Display (Shanghai) Company Structure de micro-del et panneau de micro-affichage

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TWI698994B (zh) * 2019-09-16 2020-07-11 錼創顯示科技股份有限公司 微型半導體晶片、微型半導體元件結構、以及轉移裝置
US11916172B2 (en) 2019-09-16 2024-02-27 PlayNitride Display Co., Ltd. Epitaxial structure, semiconductor structure including the same, and semiconductor pickup element for transferring the same

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WO2023142151A1 (fr) * 2022-01-31 2023-08-03 Jade Bird Display (Shanghai) Company Structure de micro-del et panneau de micro-affichage

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