WO2018057041A1 - Pixel électroluminescent multicolore monolithique - Google Patents

Pixel électroluminescent multicolore monolithique Download PDF

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Publication number
WO2018057041A1
WO2018057041A1 PCT/US2016/053824 US2016053824W WO2018057041A1 WO 2018057041 A1 WO2018057041 A1 WO 2018057041A1 US 2016053824 W US2016053824 W US 2016053824W WO 2018057041 A1 WO2018057041 A1 WO 2018057041A1
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Prior art keywords
led
micro pyramid
micro
pixel
pyramid led
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PCT/US2016/053824
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English (en)
Inventor
Khaled Ahmed
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Intel Corporation
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Priority to PCT/US2016/053824 priority Critical patent/WO2018057041A1/fr
Publication of WO2018057041A1 publication Critical patent/WO2018057041A1/fr

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00Electroluminescent light sources
    • H05B33/12Light sources with substantially two-dimensional radiating surfaces
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0016Processes relating to electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40Materials therefor
    • H01L33/42Transparent materials

Definitions

  • a light emitting diode may be a semiconductor device, such as a p-n junction diode, that emits light when activated.
  • a voltage may be applied to the terminals of an LED causing a release of photons. The energy of the released photons (also referred to as
  • LEDs may correspond to the color of light emitted from the LED.
  • LEDs are used in many applications such as indictor lamps, numeric readouts, aviation lighting, automotive headlamps, general lighting, traffic signals, and so forth. More recently, LEDs are used in LED displays that display images and videos, for example.
  • Figure 1 illustrates a graph of the Indium content of different color light emitting diodes using Indium Gallium Nitride, according to an implementation.
  • Figure 2A-2H illustrates a fabrication process for a monolithic multi-color light emitting diode pixel, according to an implementation.
  • Figure 3 illustrates a process flow for fabricating a monolithic multi-color light emitting diode pixels on a wafer, according to another implementation.
  • Figure 4 is a flow diagram of a fabrication process for a monolithic multi-color light emitting diode pixel, according to an implementation.
  • Figure 5A-5C is a flow diagram of a fabrication process for a monolithic multi-color light emitting diode pixel, according to another implementation.
  • Figure 6 illustrates an interposer, according to implementations.
  • Figure 7 is a computing device built in accordance implementation of the present disclosure.
  • LED display panels offer a combination of display resolution and low power consumption that has helped drive demand in such applications as televisions, wearable devices, virtual reality displays, and augmented displays.
  • An LED display such as active matrix LED display, may include multiple pixels, where a pixel may be the smallest addressable or controllable unit of the display.
  • a multi-color LED pixel may include multiple colors, such as red, green, and blue (RGB) LEDs. Fabrication of different color LEDs often occurs on separate wafers (e.g., non-monolithic), where a single wafer may be dedicated to a single color LED.
  • Different color LEDs from different wafers may be transferred from the respective wafers to a backplane, such as a thin-film-transistor (TFT) backplane, where the different color LEDs are integrated to form multi-color LED pixels.
  • TFT thin-film-transistor
  • the process of transferring particular color LEDs to a TFT backplane is repeated for each color LED, and ultimately affects throughput, yield, and cost.
  • Fabricating a monolithic multi-color LED pixel (also referred to as "monolithic multi-color micro LED pixel” herein) presents significant challenges, but improves yield, throughput, and cost of manufacturing.
  • monolithic multi-color LED pixels may be transferred once to a TFT backplane, rather than making three transfers (e.g., one for each color LED for a RGB pixel).
  • Monolithic may refer to an electronic circuit, such as a multicolor LED pixel, disposed or otherwise fabricated on a common material, such as a substrate of a wafer.
  • Challenges to fabricating monolithic multi-color LED pixels may include the temperature differences to fabricated different color LEDs and process and material variations in fabricating different color LEDs.
  • the present disclosure addresses the above-mentioned and other deficiencies by forming a monolithic multi-color LED pixel above a substrate of a wafer.
  • the monolithic multi-color LED pixel includes a blue micro pyramid LED, a green micro pyramid LED, and a red micro pyramid LED.
  • the blue micro pyramid LED is formed prior to the green micro pyramid LED, and the green micro pyramid LED is formed prior to the red micro pyramid LED.
  • a micro pyramid may refer to at least part of a device, such as an micro pyramid LED, that is grown or otherwise fabricated to have a pyramid shape or structure.
  • the fabrication process e.g., micro fabrication process
  • the fabrication process may control the minimum feature size of the micro pyramid on the micrometer scale (e.g., within 1 micrometer ( ⁇ ) or larger).
  • the fabrication process may control the minimum feature size of the micro pyramid on the nanometer scale.
  • the pyramid shape may have four sides. In other implementations, the pyramid shape may have three or more sides.
  • different color LEDs may be formed on a same die.
  • the different color LEDs may be part of the monolithic multi-color LED pixel.
  • the forming the monolithic multi-color light emitting diode (LED) pixel above the substrate includes forming a yellow micro pyramid LED above the substrate.
  • the substrate is a single wafer.
  • forming the monolithic multi-color light emitting diode (LED) pixel above the substrate includes disposing a cladding layer above the substrate, disposing a first protective layer above the cladding layer, and forming multiple trenches in the first protective layer.
  • the blue micro pyramid LED, the green micro pyramid LED, and the red micro pyramid LED are formed over a separate one of the multiple trenches.
  • a width of the multiple trenches is less than or equal to 25 micrometers.
  • the cladding layer includes Gallium Nitride (GaN).
  • the cladding layer includes Indium Gallium Nitride (InGaN).
  • forming the monolithic multi-color light emitting diode (LED) pixel above the substrate includes forming multiple rods in the multiple trenches, forming multiple micro pyramids above the multiple rods, and depositing a second protective layer above the multiple micro pyramids. The method also includes removing the second protective layer over a first micro pyramid of the multiple micro pyramids, and forming a blue multiple quantum well of the blue micro pyramid LED above the first pyramid.
  • forming the monolithic multi-color light emitting diode (LED) pixel above the substrate includes depositing a third protective layer above the blue micro pyramid LED and removing the second protective layer over a second micro pyramid of the plurality of micro pyramids.
  • the method includes forming a green multiple quantum well of the green micro pyramid LED above the second pyramid and depositing a fourth protective layer above the green micro pyramid LED.
  • the method also includes removing the second protective layer over a third micro pyramid of the multiple micro pyramids and forming a red multiple quantum well of the red micro pyramid LED above the third pyramid.
  • forming the monolithic multi-color light emitting diode (LED) pixel above the substrate includes disposing a transparent electrode above the blue micro pyramid LED, the green micro pyramid LED, and the red micro pyramid LED. In implementations, forming the monolithic multi-color light emitting diode (LED) pixel above the substrate includes disposing a reflective electrode above the blue micro pyramid LED, the green micro pyramid LED, and the red micro pyramid LED.
  • the blue micro pyramid LED, the green micro pyramid LED, and the red micro pyramid LED of the monolithic multi-color light emitting diode (LED) pixel share a conductive contact to connect a supply voltage to the monolithic multi-color (LED) pixel.
  • the sides of the blue micro pyramid LED, the green micro pyramid LED, and the red micro pyramid LED of the monolithic multi-color light emitting diode (LED) pixel are surrounded by a protective layer.
  • a wafer or integrated circuit die includes a cladding layer and a monolithic multi-color light emitting diode (LED) pixel disposed above the cladding layer.
  • the monolithic multi-color LED pixel includes a blue micro pyramid LED, a green micro pyramid LED, and a red micro pyramid LED.
  • the wafer or integrated circuit die includes a yellow micro pyramid LED.
  • the wafer or integrated circuit die includes a protective layer disposed above the cladding layer and multiple trenches formed in the protective layer.
  • the blue micro pyramid LED, the green micro pyramid LED, and the red micro pyramid LED are positioned above a separate one of the multiple trenches.
  • the wafer or integrated circuit die includes multiple trenches with a width that is less than or equal to 25 micrometers.
  • the wafer or integrated circuit die includes multiple transparent electrodes disposed above the blue micro pyramid LED, the green micro pyramid LED, and the red micro pyramid LED.
  • the wafer or integrated circuit die includes a conductive contact shared by the blue micro pyramid LED, the green micro pyramid LED, and the red micro pyramid LED.
  • the conductive contact connects a supply voltage to the monolithic multi-color (LED) pixel.
  • the wafer or integrated circuit die includes a protective layer disposed around sides of the blue micro pyramid LED, the green micro pyramid LED, and the red micro pyramid LED.
  • Figure 1 illustrates a graph of the Indium content of different color light emitting diodes using Indium Gallium Nitride, according to an implementation.
  • Graph 100 shows the Indium content of LEDs for light emission of different colors.
  • the Indium content may refer to the Indium content of the multiple quantum well (MQW) of an LED, or the Indium content of a particular layer (e.g., Indium Gallium Nitride (InGaN)) of the MQW.
  • MQW multiple quantum well
  • a multiple quantum well may refer to a layered semiconductor structure for which many quantum mechanical effects may be controlled.
  • a layer of the MQW may confine particles (e.g., electrons or holes) in one dimension, but allow movement of the particles in other dimensions.
  • a MQW may include one or more stacks that include a layer of Indium Gallium Nitride (InGaN) above a layer of Gallium Nitride (GaN).
  • InGaN Indium Gallium Nitride
  • GaN Gallium Nitride
  • a stack of a MQW may be repeated multiple times (e.g., 4-8 times).
  • the Indium content of the InGaN layers for a MQW may be approximately 40% for a red LED, 38-39% for a yellow LED, 35% for a green LED, and 25% for blue LED.
  • the tolerance for the aforementioned Indium content for the different color LEDs may be + 3%.
  • the emission wavelength may be determined by the band gap of the active region of the LED together with thickness determined confinement effects.
  • the active region includes one or more quantum wells (QW).
  • QW quantum wells
  • the active region (e.g., quantum well) material is preferably ternary, such as InxGal-xN, where 0 ⁇ x ⁇ l.
  • the band gap of such Ill-nitride is dependent on the amount of Indium incorporated in the active region (e.g., in the QW(s)). Higher Indium incorporation will yield a smaller band gap and thus longer wavelength of the emitted light.
  • the term QW quantum well
  • wavelength may refer to the peak emission wavelength of the LED. It may be noted that a typical emission spectra of a semiconductor LED is a narrow band of wavelength centered around the peak wavelength.
  • FIG. 2A-2H illustrates a fabrication process for a monolithic multi-color light emitting diode pixel, according to an implementation.
  • Fabrication process 200 includes wafer 201 at various stages of the fabrication process 200, according to one exemplary
  • fabrication process 200 is shown for purposes of illustration, rather than limitation. Fabrication process 200 may be performed in any order, include any number of processes, and include more, the same, or fewer processes. It may also be noted that for purposes of illustration, rather than limitation, materials are illustrated in the various layers of fabrication process 200. Other materials, other or in addition to the materials illustrated in Figures 2A-2H, may also be used in other implementations.
  • Figures 2A-2H shows the formation of a monolithic multi-color light emitting diode (LED) pixel above the substrate 210 of the wafer 201. It may be noted that multiple multi-color light emitting diode (LED) pixels may be formed on wafer 201.
  • LED monolithic multi-color light emitting diode
  • Wafer 201A illustrates a substrate 210.
  • substrate 210 may be Sapphire.
  • Substrate 210 may be a variety of materials, including, but not limited to, Silicon, Gallium Nitride (GaN), Germanium, or Silicon Carbide such as 3C-Silicon Carbide (3C-SiC).
  • Substrate 210 may be silicon on insulator (SOI).
  • SOI silicon on insulator
  • substrate 210 is silicon.
  • Crystallographic orientation of a substantially monocrystalline substrate 210 may be any of (100), (111), or (110). Other crystallographic orientations are also possible. The crystallographic orientations of substrate 210 may be offcut.
  • substrate 210 is (100) silicon with crystalline substrate surface region having cubic crystallinity. In another implementation, for a (100) silicon substrate 210, the semiconductor surface may be miscut, or offcut, for example 2-10° toward [110]. In another implementation, substrate 210 is (111) silicon with crystalline substrate surface region having hexagonal crystallinity.
  • a cladding layer 215 may be disposed or grown over substrate 210.
  • the cladding layer 215 may serve as a seed layer to grow micro pyramids as further described with at least respect to the following Figures. It may be noted that cladding layer 215 may influence the material type of the micro pyramids disposed above cladding layer 215.
  • cladding layer 215 may be GaN, such as N-type GaN (N-GaN).
  • Cladding layer 215 may be a variety of materials including one or more of Aluminum Nitride (A1N), GaN (e.g., P-type GaN or N-type GaN), or Aluminum Gallium Nitride (AlGaN) (e.g., with different Al compositions).
  • the cladding layer may be approximately 1 to 4 micrometers ( ⁇ ) thick.
  • a buffer layer (not shown) may be disposed between cladding layer 215 (e.g., seed layer of N-GaN) and substrate 210.
  • An appropriate buffer layer may be disposed corresponding to the material type of substrate 210.
  • a protective layer 220A (e.g., first protective layer) may be disposed or deposited above cladding layer 215.
  • the protective layer, such as protective layer 220A may also be referred to as a "hard mask” or “hard mask layer” herein.
  • protective layer 220A may be Silicon Nitride (Si 3 N 4 ).
  • Protective layer, such as protective layer 220A may be a variety of materials including one or more of Silicon Oxide (Si0 2 ) or Silicon Nitride (Si 3 N 4 ).
  • Protective layer 220A may be 200-1000nm thick, for example.
  • multiple trenches 216 are formed in protective layer 220A.
  • the trenches may remove an area of the protective layer 220 A to expose the cladding layer 215 in the area of trenches 216.
  • micrometer lithography may be used to open trenches 216 in protective layer 220A.
  • the width of the trenches 216 may be ⁇ to 25 ⁇ in width.
  • Micro pyramid LEDs may be grown in trenches 216.
  • the width of the trenches 216 may be referred to as the minimum feature size of a micro pyramid LED, and enable the use of micrometer lithography equipment to reduce the cost of the fabrication equipment.
  • element numbers herein, such as trench 216 may refer to all the elements having the same base number, such as trench 216A, 216B, and 216C, while a base element number with a corresponding letter, such as trench 216A, may refer to only the specific element number (e.g., trench 216A), unless otherwise specified.
  • Wafer 201B illustrates the formation of rod 217 in trenches 216.
  • Rods 217 are disposed above cladding layer 215.
  • Rod 217A may be grown in trench 216A.
  • Rod 217B may be grown in trench 216B.
  • Rod 217C may be grown in trench 216C.
  • rods 217 may also be referred to as "micro-rods" and be considered as part of (e.g., a base portion) of a micro pyramid.
  • Rod 217 may have material characteristics of cladding layer 215.
  • cladding layer 215 may be a seed layer and an N-GaN rod 217 may be grown on an N-GaN cladding layer 215, and so forth.
  • rod 217 may be InGaN with Indium content of approximately 10% with a tolerance of + 3%.
  • wafer 201C illustrates the formation of pyramid 218 (also referred to as "micro pyramid” herein) disposed above rods 217.
  • Pyramids 218 may be grown a respective one of rods 217. It may be noted that the rods 217 may be allowed to continue to grow to form pyramids 218. It may also be noted that the growth of rod 217 and pyramid 218 may be a single process in some implementations.
  • Micro pyramid may refer to pyramid 218 or both rod 217 and pyramid 218.
  • Pyramid 218 may have material characteristics of rod 217. For example, an N-GaN pyramid may be grown on an N-GaN rod. In one implementation, pyramid 218 may be InGaN with Indium content of approximately 10% with a tolerance of + 3%.
  • wafer 201D illustrates a formation of a blue multiple quantum well (MQW) 221 disposed above pyramid 218C, and cladding layer 222C disposed above blue MQW 221.
  • protective layer 220B e.g., second protective layer
  • Protective layer 220B may be disposed or deposited above protective layer 220A and above pyramids 218.
  • Protective layer 220B may be a similar or different material than protective layer 220A, and have similar features as described with respect to protective layer 220A.
  • Protective layer 220B may be planarized after deposition.
  • Protective layer 220B may be removed above pyramid 218C by etching a trench.
  • Blue MQW 221 is disposed or grown above pyramid 218C.
  • a MQW such as blue MQW 221
  • the blue MQW 221 may be deposited prior to other colored MQWs so that the high temperature used to form the blue MQW 221 does not affect other color MQWs formed at lower temperatures.
  • other color MQWs formed at lower temperatures than the blue MQW 221 may have minimal effect on the previously formed blue MQW 221.
  • Cladding layer 222C is disposed above blue MQW 221.
  • cladding layer 222C is P-type GaN (P-GaN).
  • pyramid 218 (and rod 217) may be the N-type junction of a LED
  • cladding layer 222 may be the P- type junction of the LED.
  • the dopant type for pyramid 218 and cladding layer 222 may be reversed, in some implementations.
  • Cladding layer 222 may be a variety of materials similar as described with respect to pyramid 218 and with opposite dopant type.
  • wafer 201E illustrates a formation of a green multiple quantum well (MQW) 223 disposed above pyramid 218B, and cladding layer 222B disposed above green MQW 223.
  • another protective layer e.g., third protective layer
  • the third protective layer may also be referred to as protective layer 220B, but it may be noted that some portion of protective layer 220B (e.g., above cladding layer 222A) may be formed from a subsequent process as described with respect to Figure 2C.
  • Protective layer 220B may be removed above pyramid 218B by etching a trench.
  • Green MQW 223 is disposed or grown above pyramid 218B.
  • a MQW such as green MQW 223, may include multiple layers and a specific Indium content to produce a corresponding color electroluminescence. It may be noted that the green MQW 223 may be deposited after the blue MQW 221 and prior to other colored MQWs.
  • Cladding layer 222B is disposed above the green MQW 223. Cladding layer 222B may include similar features as cladding layer 222C.
  • wafer 201F illustrates a formation of a red multiple quantum well (MQW) 224 disposed above pyramid 218 A, and cladding layer 222A disposed above red MQW 224.
  • another protective layer e.g., fourth protective layer
  • the fourth protective layer may also be referred to as protective layer 220B, but it may be noted that some portion of protective layer 220B (e.g., above cladding layer 222B) may be formed from a subsequent process as described with respect to Figure 2D.
  • Protective layer 220B may be removed above pyramid 218A by etching a trench.
  • Red MQW 224 is disposed or grown above pyramid 218A.
  • a MQW such as red MQW 224, may include multiple layers with a specific Indium content to produce a corresponding color electroluminescence. It may be noted that the red MQW 224 may be deposited after the blue MQW 221 and the green MQW 223.
  • Cladding layer 222A is disposed above the red MQW 224. Cladding layer 222A may include similar features as cladding layer 222C.
  • a yellow micro pyramid LED (not shown) may be formed in a similar manner as described with respect to the Figures 2A-2H.
  • a trench may be formed in protective layer 220A.
  • a rod and pyramid may be grown in the trench.
  • a yellow MQW may be disposed on the pyramid followed by a cladding layer. The yellow MQW may be formed subsequent the formation of the blue MQW 221 or after the formation of the green MQW 223 but prior to the formation of the red MQW 224.
  • wafer 201G illustrates a protective layer disposed above the red micro pyramid LED 231, the green micro pyramid LED 232, and the blue micro pyramid LED 233.
  • another protective layer e.g., fifth protective layer
  • the fifth protective layer may also be referred to as protective layer 220B, but it may be noted that some portion of protective layer 220B (e.g., above red micro pyramid LED 231) may be formed from a subsequent process as described with respect to Figure 2E.
  • wafer 201H illustrates trenches (also referred to as "holes” herein) formed above the cladding layer 222 of the red micro pyramid LED 231, the green micro pyramid LED 232, and the blue micro pyramid LED 233.
  • protective layer 220B above the red micro pyramid LED 231, the green micro pyramid LED 232, and the blue micro pyramid LED 233 may be removed or etched to expose the cladding layers 222 of the respective micro pyramid LEDs.
  • wafer 2011 illustrates transparent electrodes 230 formed above the cladding layer 222 of red micro pyramid LED 231, the green micro pyramid LED 232, and the blue micro pyramid LED 233.
  • Transparent electrode 230 is disposed or deposited over the red micro pyramid LED 231, the green micro pyramid LED 232, and the blue micro pyramid LED 233 to allow the emission of light to radiate in a direction opposite substrate 210.
  • transparent electrode 230 may be Indium- Tin-Oxide (ITO).
  • Transparent electrode 230 may be a variety of materials including one or more of ITO or Zinc Oxide or other appropriate conductive transparent material.
  • a reflective electrode (not shown) may be used in the place of transparent electrode 230. With a reflective electrode, the micro pyramid LEDs would radiate light towards the direction of substrate 210.
  • a conductive contact such as a metal contact
  • a metal contact may be formed through protective layer 220A and 220B to cladding layer 215.
  • the conductive contact would be shared between the blue micro pyramid LED 233, the green micro pyramid LED 232, and the red micro pyramid LED 231 of the monolithic multi-color light emitting diode (LED) pixel and connect to a supply voltage (not shown) to activate the micro pyramids LEDs. It may be noted that in a non-monolithic LED pixel the LEDs may not share a conductive contact.
  • the cladding layer 215 may be the common contact shared by the between the blue micro pyramid LED 233, the green micro pyramid LED 232, and the red micro pyramid LED 231 of the monolithic multi-color light emitting diode (LED) pixel.
  • the conductive contact may connect to cladding layer 215 through the backside (e.g., from the direction of substrate 210).
  • the bottom of wafer 201 may be removed to expose the cladding layer 215.
  • the cladding layer 215 may be placed on pads on the TFT backplane.
  • an etch may be applied to separate the cladding layer 215 associated with different color LEDs of a monolithic multicolor light emitting diode (LED) pixel, so that the color LED may be individually controlled.
  • LED monolithic multicolor light emitting diode
  • a monolithic multi-color LED pixel may include two or more different color micro pyramid LEDs.
  • wafer 2011 shows a monolithic multi-color LED pixel including a blue micro pyramid LED, a green micro pyramid LED, and a red micro pyramid LED.
  • red micro pyramid LED 231, green micro pyramid LED 232, and blue micro pyramid LED 233 of the monolithic multi-color LED pixel are surrounded (e.g., contiguous and without a boundary) by a protective layer 220A and 220B.
  • a non-monolithic multi-color LED pixel may have different color LEDs that are diced separately and later integrated on a backplane to form a pixel.
  • the associated protective layer of a non-monolithic multi-color LED pixel may not be contiguous and may have a boundary between two LEDs of a pixel.
  • Figure 3 illustrates a process flow for fabricating monolithic multi-color LED pixels on a wafer, according to another implementation.
  • the horizontal row shows different fabrication processes 340, and the vertical row shows different wafer processes 350.
  • Fabrication process 340A may include epitaxy (EPI). Epitaxy may be the deposition of one or more epitaxial films or layers. For example, an epitaxial process may include metal organic chemical vapor deposition (MOCVD) performed at a variety of temperatures.
  • Fabrication process 340B may include a hard mask process where a material is used as an etch mask.
  • a hard mask process may include plasma-enhanced chemical vapor deposition (PECVD).
  • Fabrication process 340C may include a photolithography process that uses light to transfer a pattern to the wafer. Fabrication process 340D may include an etching process to remove one or more layers (or parts of one or more layers) from the surface of a wafer.
  • the etching process may include dry etch or wet etch.
  • Fabrication process 340E may include a protective layer process, and may include the deposition of materials such as Silicon Dioxide (Si0 2 ).
  • Fabrication process 340F may include a planarization process to smooth the surface of the wafer.
  • the planarization process may include chemical-mechanical planarization (CMP).
  • Fabrication process 340G may include a photolithography process and may be similar to fabrication process 340C.
  • Fabrication process 340H may include a metallization process to form connections to the circuits, such as multi-color LED pixels.
  • the metallization process may include physical vapor deposition (PVD).
  • PVD physical vapor deposition
  • a wafer may start at wafer process 350A undergo the various wafer processes 350A through 350R.
  • Wafer processes 350 align with different fabrication processes 340.
  • wafer process 350A includes a seeding process to form a seed layer (e.g., cladding layer), such as N-GaN.
  • Fabrication process 340A such as MOCVD, may be used to form the seed layer.
  • Wafer process 350B may include the formation of a hard mask layer.
  • Wafer process 350C and 350D may include the formation of trenches for the micro pyramids.
  • Wafer process 350A - 350D may further be described with respect to wafer 201 A of Figure 2A.
  • Wafer process 350E may include the formation of the micro pyramids (rods and pyramid) in and above the trenches.
  • Wafer process 350E may further be described with respect to wafer 201B and 201C of Figure 2A and 2B, respectively.
  • Wafer process 350F may include the formation, planarization, and lithography of a protective layer (e.g., second protective layer).
  • Wafer process 350G may include the etching of the protective layer.
  • Wafer process 350H may include the formation of the blue MQW and cladding layer of the blue micro pyramid LED.
  • Wafer processes 350F-350H may further be described with respect to wafer 201D of Figure 2C.
  • Wafer process 3501 may include the formation, planarization, and lithography of a protective layer (e.g., third protective layer).
  • Wafer process 350J may include the etching of the protective layer.
  • Wafer process 350K may include the formation of the green MQW and cladding layer of the green micro pyramid LED. Wafer processes 350I-350K may further be described with respect to wafer 201E of Figure 2D. Wafer process 350L may include the formation, planarization, and lithography of a protective layer (e.g., fourth protective layer). Wafer process 350M may include the etching of the protective layer. Wafer process 350N may include the formation of the red MQW and cladding layer of the red micro pyramid LED. Wafer processes 350L-350N may further be described with respect to wafer 20 IF of Figure 2E. Wafer process 350O may include the formation, planarization, and lithography of a protective layer (e.g., fifth protective layer). Wafer processes 350O may further be described with respect to wafer 201G of Figure 2F.
  • a protective layer e.g., fourth protective layer
  • Wafer processes 350M may include the etching of the protective layer.
  • Wafer process 350N may include the formation of the
  • Wafer process 350P may include forming a trench for a conductive contact to, for example, the uppermost layer to the cladding layer.
  • Wafer process 350Q may include depositing the conductive contact material in the trench.
  • Wafer process 350R may include an etch process to etch conductive contact.
  • the wafer may also include a reflective or transparent electrode, and the associated wafer processes may be implemented to fabricate the reflective or transparent electrode.
  • wafer processes 350 have been described for purposes of illustration rather than limitation. It may be further noted that the same, fewer or additional wafer processes may be used. It also may be noted that the same or different materials as described or illustrated may be used to in the various wafer processes 350.
  • Figure 4 is a flow diagram of a fabrication process for a monolithic multi-color light emitting diode pixel, according to an implementation. It may be noted that features of Figures 2A-2H may be described below to help illustrate method 400. Method 400 may be performed as operations. It may be noted that method 400 may be performed in any order and may include the same, more, or fewer operations. It may be noted that method 400 may be performed by one or more pieces of semiconductor fabrication equipment or fabrication tools.
  • Method 400 begins at operation 405 that provides a substrate 210 for the wafer 201.
  • a monolithic multi-color light emitting diode (LED) pixel is formed above the substrate 210 of the wafer 201.
  • the multi-color LED pixel includes a blue micro pyramid LED, a green micro pyramid LED, and a red micro pyramid LED. Additional details of method 400 may be described at least with respect to Figure 2A-2H
  • Figure 5A-5C are a flow diagram of a fabrication process for a monolithic multi-color light emitting diode pixel, according to another implementation. It may be noted that features of Figures 2A-2H may be described below to help illustrate method 500.
  • Method 500 may be performed as operations. It may be noted that method 500 may be performed in any order and may include the same, more, or fewer operations. It may be noted that method 500 may be performed by one or more pieces of semiconductor fabrication equipment or fabrication tools.
  • Method 500 begins at operation 505 where a cladding layer 215 is disposed above the substrate 210.
  • a first protective layer 220A is disposed above the cladding layer 215.
  • multiple trenches 216 are formed in the first protective layer 220A.
  • rods 217 are disposed in the trenches 216.
  • the rods 217 are allowed to continue to grow to form pyramids 218 above the rods 217.
  • a second protective layer 220B is disposed above the pyramids 218.
  • method 500 continues to operation 535.
  • the second protective layer 220B over a first micro pyramid 218C is removed.
  • a blue multiple quantum well 221 of the blue micro pyramid LED is disposed above the first pyramid 218C.
  • cladding layer 222C is disposed above the blue MQW 221.
  • a third protective layer 220B is disposed above the blue micro pyramid LED 233.
  • the second protective layer 220B over a second micro pyramid 218B is removed.
  • a green multiple quantum well 223 of the green micro pyramid LED 232 is disposed above the second pyramid 218B.
  • method 500 continues to operation 565.
  • cladding layer 222B is disposed above green MQW 223.
  • a fourth protective layer 220B is disposed above the green micro pyramid LED 232.
  • the second protective layer 220B over a third micro pyramid 218A is removed.
  • a red multiple quantum well 224 of the red micro pyramid LED 231 is disposed above the third pyramid 218 A.
  • FIG. 6 illustrates an interposer, according to implementations.
  • the interposer 600 may be an intervening substrate used to bridge a first substrate 602 to a second substrate 604.
  • the first substrate 602 may be, for instance, an integrated circuit die, such as a multi-color LED pixel.
  • the second substrate 604 may be, for instance, a memory module, a computer motherboard, backplane, or another integrated circuit die.
  • first substrate 602 may be an integrated circuit die described with respect to Figure 2A-2H.
  • an interposer 600 may couple an integrated circuit die to a ball grid array (BGA) 606 that can subsequently be coupled to the second substrate 604.
  • BGA ball grid array
  • the first and second substrates 602/604 are attached to opposing sides of the interposer 600.
  • the first and second substrates 602/604 are attached to the same side of the interposer 600.
  • three or more substrates are interconnected by way of the interposer 600.
  • the interposer 600 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further,
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer may include metal interconnects 608 and vias 610, including but not limited to through- silicon vias (TSVs) 612.
  • the interposer 600 may further include embedded devices 614, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 600.
  • RF radio- frequency
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 600.
  • FIG. 7 is a computing device built in accordance implementation of the present disclosure.
  • the computing device 700 may include a number of components. In one implementation, the components are attached to one or more motherboards. In an alternate implementation, some or all of these components are fabricated onto a single system-on-a- chip (SoC) die, such as an SoC used for mobile devices.
  • SoC system-on-a- chip
  • the components in the computing device 700 include, but are not limited to, an integrated circuit die 702 and at least one communications logic unit 708.
  • the communications logic unit 708 is fabricated within the integrated circuit die 702 while in other implementations the communications logic unit 708 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 702.
  • the integrated circuit die 702 may include a CPU 704 as well as on-die memory 706, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin-transfer torque memory (STT-MRAM). It may be noted that in implementations integrated circuit die 702 may include fewer elements (e.g., without processor 704 and/or on-die memory 706) or additional elements other than processor 704 and on-die memory 706. In one example, integrated circuit die 702 may be an LED, such as a monolithic multi-color LED pixel 705, with or without processor 704 and/or on-die memory 706.
  • integrated circuit die 702 may be LED display with multiple monolithic multi-color LED pixels 705 and a TFT backplane, with or without processor 704 and/or on-die memory 706.
  • integrated circuit die 702 may include some or all the elements described herein, as well as include additional elements.
  • Computing device 700 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 710 (e.g., DRAM), nonvolatile memory 712 (e.g., ROM or flash memory), a graphics processing unit 714 (GPU), a digital signal processor 716, a crypto processor 742 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 720, at least one antenna 722 (in some implementations two or more antenna may be used), a display or a touchscreen display 824 (e.g., that may include integrated circuit die 702) , a touchscreen controller 726, a battery 728 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 727, a compass (not shown), a motion coprocessor or sensors 732 (that may include an accelerometer, a gyro
  • the computing device 700 may incorporate further transmission, telecommunication, or radio functionality not already described herein.
  • the computing device 700 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.
  • the computing device 700 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.
  • the communications logic unit 708 enables wireless communications for the transfer of data to and from the computing device 700.
  • the term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium.
  • the communications logic unit 708 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 700 may include a plurality of communications logic units 708.
  • a first communications logic unit 708 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 708 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 704 (also referred to "processing device” herein) of the computing device 700 includes one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure.
  • the term "processor” or “processing device” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • Processor 704 represents one or more general- purpose processing devices such as a microprocessor, a central processing unit, or the like.
  • processor 704 may be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLrW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets.
  • processor 704 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like.
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • DSP digital signal processor
  • the communications logic unit 708 may also include one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure.
  • another component housed within the computing device 700 may contain one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure.
  • the computing device 700 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 700 may be any other electronic device that processes data.
  • one layer disposed above or over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer "on" a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate.
  • the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure.
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to
  • a plurality of transistors such as metal-oxide- semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate.
  • MOSFET metal-oxide- semiconductor field-effect transistors
  • the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both.
  • Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
  • FinFET transistors such as double-gate transistors and tri-gate transistors
  • wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
  • Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer.
  • the gate dielectric layer may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide (Si0 2 ) and/or a high-k dielectric material.
  • the high-k dielectric material may include elements such as Hafnium, Silicon, Oxygen, Titanium, Tantalum, Lanthanum, Aluminum, Zirconium, Barium, Strontium, Yttrium, Lead, Scandium, Niobium, and Zinc.
  • high-k materials that may be used in the gate dielectric layer include, but are not limited to, Hafnium Oxide, Hafnium Silicon Oxide, Lanthanum Oxide, Lanthanum Aluminum Oxide, Zirconium Oxide, Zirconium Silicon Oxide, Tantalum Oxide, Titanium Oxide, Barium Strontium Titanium Oxide, Barium Titanium Oxide, Strontium Titanium Oxide, Yttrium Oxide, Aluminum Oxide, Lead Scandium Tantalum Oxide, and Lead Zinc Niobate.
  • an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
  • the gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor.
  • the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
  • metals that may be used for the gate electrode include, but are not limited to, Ruthenium, Palladium, Platinum, Cobalt, Nickel, and conductive metal oxides, e.g., Ruthenium Oxide.
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, Hafnium, Zirconium, Titanium, Tantalum, Aluminum, alloys of these metals, and carbides of these metals such as Hafnium Carbide, Zirconium Carbide, Titanium Carbide, Tantalum Carbide, and Aluminum Carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.
  • the gate electrode when viewed as a cross-section of the transistor along the source-channel-drain direction, may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack.
  • the sidewall spacers may be formed from a material such as Silicon Nitride, Silicon Oxide, Silicon Carbide, Silicon Nitride doped with Carbon, and Silicon Oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack. [0076] In implementations, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor.
  • the source and drain regions may be formed using either an implantation/diffusion process or an etching/deposition process.
  • dopants such as Boron, Aluminum, Antimony, Phosphorous, or Arsenic may be ion- implanted into the substrate to form the source and drain regions.
  • An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process.
  • the substrate may first be etched to form recesses at the locations of the source and drain regions.
  • An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions.
  • the source and drain regions may be fabricated using a Silicon alloy such as Silicon Germanium or Silicon Carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as Boron, Arsenic, or Phosphorous.
  • the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy.
  • one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
  • one or more interlayer dielectrics are deposited over the MOS transistors.
  • the ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, Silicon Dioxide (Si0 2 ), Carbon doped oxide (CDO), Silicon Nitride, organic polymers such as Perfluorocyclobutane or Polytetrafluoroethylene, Fluorosilicate glass (FSG), and organosilicates such as
  • the ILD layers may include pores or air gaps to further reduce their dielectric constant.

Abstract

L'invention concerne un appareil comprenant un pixel de DEL multicolore monolithique et un procédé de fabrication d'un dispositif à DEL. Le procédé consiste à utiliser un substrat pour la tranche. Le procédé consiste également à former un pixel de diode électroluminescente (DEL) multicolore monolithique au-dessus du substrat de la tranche. Le pixel de DEL multicolore monolithique comprend une DEL de micro-pyramide bleue, une DEL de micro-pyramide verte et une DEL de micro-pyramide rouge. D'autres modes de réalisation peuvent être décrits et/ou revendiqués.
PCT/US2016/053824 2016-09-26 2016-09-26 Pixel électroluminescent multicolore monolithique WO2018057041A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100857410B1 (ko) * 2007-03-08 2008-09-08 전북대학교산학협력단 백색 엘이디의 제조방법
JP2009049209A (ja) * 2007-08-20 2009-03-05 Hokkaido Univ 半導体発光素子アレー、およびその製造方法
US20090189144A1 (en) * 2008-01-29 2009-07-30 Nathaniel Quitoriano Device For Absorbing Or Emitting Light And Methods Of Making The Same
KR20110131801A (ko) * 2010-05-31 2011-12-07 삼성전자주식회사 발광 소자 및 다중 파장의 광을 만드는 방법
US20160093665A1 (en) * 2014-09-26 2016-03-31 Glo Ab Monolithic image chip for near-to-eye display

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100857410B1 (ko) * 2007-03-08 2008-09-08 전북대학교산학협력단 백색 엘이디의 제조방법
JP2009049209A (ja) * 2007-08-20 2009-03-05 Hokkaido Univ 半導体発光素子アレー、およびその製造方法
US20090189144A1 (en) * 2008-01-29 2009-07-30 Nathaniel Quitoriano Device For Absorbing Or Emitting Light And Methods Of Making The Same
KR20110131801A (ko) * 2010-05-31 2011-12-07 삼성전자주식회사 발광 소자 및 다중 파장의 광을 만드는 방법
US20160093665A1 (en) * 2014-09-26 2016-03-31 Glo Ab Monolithic image chip for near-to-eye display

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