WO2017111827A1 - Pixel de del à nanofils - Google Patents

Pixel de del à nanofils Download PDF

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Publication number
WO2017111827A1
WO2017111827A1 PCT/US2015/000385 US2015000385W WO2017111827A1 WO 2017111827 A1 WO2017111827 A1 WO 2017111827A1 US 2015000385 W US2015000385 W US 2015000385W WO 2017111827 A1 WO2017111827 A1 WO 2017111827A1
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WIPO (PCT)
Prior art keywords
aer
type gan
led
layer
create
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PCT/US2015/000385
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English (en)
Inventor
Khaled Ahmed
Prashant Majhi
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Intel Corporation
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Priority to PCT/US2015/000385 priority Critical patent/WO2017111827A1/fr
Publication of WO2017111827A1 publication Critical patent/WO2017111827A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

Definitions

  • the present disclosure relates generally to the field of displays, and more particularly, to substrates, assemblies, and techniques to enable a nanowire LED pixel.
  • micro LEDs that emit red, green and blue colors are first fabricated on separate wafers. The separate LEDs are then transferred from the wafers to backplanes to make red, green, and blue (RGB) pixels that make the active matrix micro LED display panel.
  • RGB red, green, and blue
  • FIGURE 1 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 2 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 3 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 4 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 5 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 6 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 7 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 8 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 9 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure.
  • FIGURE 10 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 11 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 12 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 13 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 14 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 15 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure.
  • FIGURE 16 is a simplified flowchart illustrating potential operations that may be associated with one embodiment of the present disclosure
  • FIGURE 17 is a simplified process flow diagram illustrating potential operations that may be associated with one embodiment of the present disclosure
  • FIGURE 18 is an interposer implementing one or more of the embodiments disclosed herein.
  • FIGURE 19 is a computing device built in accordance with an embodiment disclosed herein.
  • RGB, RYGB, RRGGBB, etc. pixels on wafers monolithically (i.e., on a single wafer). The pixels may then be transferred all at once, from source wafers to TFT backplanes.
  • various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the embodiments disclosed herein may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the embodiments disclosed herein may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
  • the terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • Implementations of the embodiments disclosed herein may be formed or carried out on a substrate, such as a semiconductor substrate or a sapphire substrate.
  • the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure.
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium
  • micro LED displays can offer an improvement of the charging cycle of a smartphone.
  • GaN-based micro LEDs that emit red, green and blue colors are first fabricated on separate wafers (silicon or sapphire) then transferred from the wafers to thin film transistor (TFT) backplanes to make red, green, and blue (RGB) pixels that make the active matrix micro LED display panel.
  • TFT thin film transistor
  • RGB red, green, and blue
  • One drawback of this process is that the transfer process has to be executed three times for the three colors. This affects the throughput of the transfer process and increases the chance of missing transfers which affect the overall production yield.
  • the production cost of micro LED displays is very sensitive to the transfer tact time of micro LEDs from source wafers to host glass TFT backplanes, especially for large size displays such as tables or notebooks.
  • RGB pixels may be fabricated on wafers
  • the nanowire RGB pixels may then be transferred all at once, from source wafers to TFT backplanes. This process can improve the throughput by three times and the overall production yield of display panels.
  • red, yellow, green, blue (RYGB) pixels may be fabricated on wafers monolithically.
  • the nanowire RYGB pixels may then be transferred all at once, from source wafers to TFT backplanes.
  • red, red, green, green, blue, blue (RRGGBB) pixels (or some other combination) may be fabricated on wafers monolithically.
  • the nanowire RRGGGB pixels (or other combination) may then be transferred all at once, from source wafers to TFT backplanes.
  • a process for making pixels on a wafer can start with a silicon, silicon carbide, or sapphire wafer.
  • a buffer stack can be grown on the silicon or sapphire wafer. The buffer stack should allow good quality EPI growth without
  • an N-type GaN layer can be gown on the buffer layer.
  • the N-type GaN layer may be about lum in thickness.
  • a hard mask e.g., Si3N4
  • CVD chemical vapor deposition
  • PECVD plasma enhanced CVD
  • ALD atomic layer deposition
  • Nanoimprint Lithography (NIL) can be used to pattern and open trenches down to the buffer layer.
  • the trenches may be about 50 to about 300 nm wide. In another example, the trenches may be about 70 to about 150 nm wide.
  • a core of N-type GaN rods may be grown using metal organic chemical vapor phase deposition (MOCVD).
  • MOCVD metal organic chemical vapor phase deposition
  • a Si3N4 hardmask may be deposited using ALD or CVD.
  • the hardmask may be about 5 to about 20 nms thick.
  • Si02 may be deposited using a low
  • Micrometer scale lithography can be used to uncover (e.g., by etching Si02 and Si3N4) areas where blue and green (or some other color) LEDs will be located.
  • MOCVD may be used to grow an InGaN multi quantum well around the exposed N-type GaN core nanorods. The indium composition in InGaN is determined by the diameter of the core N- GaN nanorods. MOCVD may also be used to grow p-type GaN for the contacts in the blue and green LEDs.
  • Si02 can be deposited using CVD or PECVD and CMP may be used to planarize the Si02.
  • Micro-scale lithography techniques may be used to uncover the area of the red (or some other color) LED.
  • MOCVD may be used to grow an InGaN multi-quantum well around the N-GaN nanorods in the red LED region.
  • MOCVD may be used to grow P-type GaN for contacting the red LED.
  • Si02 can be deposited using CVD or PECVD and CMP can be used to planarize.
  • a micro-scale lithograph method may be used to pattern the contacts for red, green and blue LEDs.
  • a metal contact can be deposited and lithography and etch may be used again to make separate contacts to red, green and blue LEDs.
  • FIGURE 1 illustrates one embodiment of a nanowire LED pixel 100.
  • Nanowire LED pixel 100 can include a support substrate 102, a buffer stack 104, a GaN active layer 106, a hard mask 108, a first active emitting region (AER) LED 110, a second AER LED 112, a third AER LED 114, a metal contact 116, and a Si02 layer 122.
  • FIGURE 1 is an illustrative example of three nanowire LEDs (e.g., RGB, YGB, etc.) grown monolithically on the same support substrate 102.
  • Support substrate 102 may be any type of wafer such as sapphire, silicon wafer, silicon carbide wafer, etc.
  • active emitting region or "AER” is to include an active emitting region such as an p-n junction, multi-quantum well (MQW), pin junction, etc.
  • FIGURE 2 illustrates one embodiment of one of the early stages of building a nanowire LED pixel 100.
  • GaN active layer 106 can be deposited on support substrate 102.
  • Buffer stack 104 can help facilitate the process of creating GaN active layer 106 on support substrate 102.
  • buffer stack 104 may be about 3um in thickness.
  • GaN active layer 106 may include n- GaN and be about lum in thickness.
  • FIGURE 3 illustrates one embodiment of one of the early stages of building a nanowire LED pixel 100.
  • hard mask 108 can be deposited or layered onto GaN active layer 106.
  • hard mask 108 may be a Si3N4 mask or some other similar type hard mask.
  • Hard mask 108 may be deposited using CVD/PECVD or ALD.
  • FIGURE 4 illustrates one embodiment of one of the early stages of building a nanowire LED pixel 100.
  • trenches 132 may be created in hard mask 108.
  • Trenches 132 may be created by nanoimprint lithography (NIL) or some other means or method of creating nanometer scale trenches or cavities in hard mask 108.
  • Trenches 132 may be about 50 to about 150 nms wide.
  • FIGURE 5 illustrates one embodiment of one of the early stages of building a nanowire LED pixel 100.
  • a core 118 is grown through each trench 132.
  • Core 118 can be the core shell for first AER LED 110, second AER LED 112, and third AER LED 112.
  • core 118 may be N-type GaN rods grown using MOCVD.
  • FIGURE 6 illustrates one embodiment of one of the early stages of building a nanowire LED pixel 100.
  • a hard mask 120 can be deposited on each core 118.
  • Hard mask 120 may be a Si3N4 hard mask.
  • hard mark 120 may be about 5 to about 20 nm thick.
  • Hard mask 120 can be deposited using ALD or CVD.
  • FIGURE 7 illustrates one embodiment of one of the early stages of building a nanowire LED pixel 100.
  • Si02 layer 122 may be deposited over hard mask 120.
  • Si02 layer 122 can be deposited using a low temperature PECVC process.
  • the temperature may be below about 500 °C or between about 400 °C to about 600 °C.
  • Si02 layer 122 may undergo chemical mechanical polishing to planarize Si02 layer 122.
  • FIGURE 8 illustrates one embodiment of one of the stages of building a nanowire LED pixel 100.
  • Si02 layer 122 and hard mask 120 may be etched from each core 118 that will comprise first AER LED 110 and second AER LED 112.
  • micrometer scale lithography may be used to uncover each core 118 that will comprise first AER LED 110 and second AER LED 112.
  • FIGURE 9 illustrates one embodiment of one of the stages of building a nanowire LED pixel 100.
  • selective AER growth 124 on a portion of exposed cores 118 may be used to create first AER LED 110 and selective AER growth 126 on a portion of exposed cores 118 may be used to create second AER LED 112.
  • MOCVD may be used to grow InGaN AERs around exposed cores 118.
  • the indium composition in InGaN is determined by the diameter of each exposed core 118. For example, with the increase in nanowire diameters from 147 to 270 nm, the emission peak wavelengths shift monotonically from 480 to 632 nm, (i.e., from blue to red color). Such a wide range of emission wavelength tuning is attributed to the increased indium composition with increasing wire diameter.
  • FIGURE 10 illustrates one embodiment of one of the stages of building a nanowire LED pixel 100.
  • Si02 layer 122 may be deposited over first AER LED 110 and second AER LED 112.
  • Si02 layer 122 can be deposited using a low temperature PECVC process.
  • the temperature may be below about 500 °C or between about 400 °C to about 600 °C.
  • Si02 layer 122 may undergo chemical mechanical polishing to planarize Si02 layer 122.
  • FIGURE 11 illustrates one embodiment of one of the stages of building a nanowire LED pixel 100.
  • a photoresist layer 128 may be created on a region of Si02 layer 122 that is over first AER LED 110 and second AER LED 112. Photoresist layer 128 may be created using photolithography. Photoresist layer 128 can be configured to provide first AER LED 110 and second AER LED 112 with photoresist protection from etching that will be used to create a red AER LED.
  • FIGURE 12 illustrates one embodiment of one of the stages of building a nanowire LED pixel 100.
  • Si02 layer 122 and hard mask 120 may be etched from each core 118 that will comprise third AER LED 112.
  • micrometer scale lithography may be used to uncover each core 118 that will comprise third AER LED 112.
  • FIGURE 13 illustrates one embodiment of one of the stages of building a nanowire LED pixel 100.
  • selective AER growth 130 on a portion of exposed cores 118 may be used to create third AER LED 112.
  • MOCVD may be used to grow InGaN AERs around exposed cores 118 to create third AER LED 112.
  • FIGURE 14 illustrates one embodiment of one of the stages of building a nanowire LED pixel 100.
  • Si02 layer 122 may be deposited over third AER LED 112.
  • Si02 layer 122 can be deposited using a low temperature PECVC process.
  • the temperature may be below about 500 °C or between about 400 °C to about 600 °C.
  • Si02 layer 122 may undergo chemical mechanical polishing to planarize Si02 layer 122.
  • FIGURE 15 illustrates one embodiment of one of the stages of building a nanowire LED pixel 100.
  • portions of Si02 layer 122 that are above first AER LED 110, second AER LED 112, and third AER LED 112 are etched away.
  • a micro-scale lithography method is used to pattern etch the areas of Si02 layer 122 that are above first AER LED 110, second AER LED 112, and third AER LED 112.
  • Metal contacts 116 (shown in FIGURE 1) can be deposited into the areas etched away to create contacts for first AER LED 110, second AER LED 112, and third AER LED 112.
  • FIGURE 16 is an example flowchart illustrating possible operations of a flow 1600 that may be associated with a nanowire LED pixel, in accordance with an embodiment.
  • a buffer layer is created on a substrate.
  • a gallium nitride layer is created on the buffer layer.
  • a mask layer is created on the gallium nitride layer.
  • openings are etched in the mask layer.
  • nanowires from the gallium nitride layer are grown through the openings in the mask layer.
  • a mask layer is created over the nanowires.
  • silicon dioxide is planarized over the nanowires.
  • the silicon dioxide undergoes chemical mechanical polishing.
  • silicon dioxide that covers the nanowires that will become a green LED is etched away.
  • a multiple quantum well (or AER) is grown over the exposed nano wires to create a green LED.
  • silicon dioxide is planarized over the green LED.
  • silicon dioxide that covers the nanowires that will become a blue LED is etched away.
  • a multiple quantum well (or AER) is grown over the exposed nanowires to create a blue LED.
  • silicon dioxide is planarized over the blue LED.
  • a photo resist layer is created over the green LED and the blue LED.
  • silicon dioxide that covers the nano wires that will become a red LED is etched away.
  • a multiple quantum well or AER is grown over the exposed nanowires to create a red LED.
  • silicon dioxide is planarized over the red LED.
  • the silicon dioxide undergoes chemical mechanical polishing.
  • contacts over the green LED blue LED and red LED are opened.
  • FIGURE 17 is an example process flow illustrating possible operations of a flow 1700 that may be associated with a nanowire LED pixel, in accordance with an embodiment.
  • a buffer layer may be deposited on a wafer using MOCVD at a temperature of about 1100 °C.
  • a hard mask may be deposited using PECVD at temperatures of about 500 °C to 600°C. Trenches may be formed in the hard mask using NIL and the trenches may be about 50 to about 300 nm wide.
  • the structure may be dried and etched.
  • MOCVD a N-GaN core may be grown.
  • a hard mask can be deposited using ALD at about 300 °C to about 400°C.
  • a layer of Si02 can be deposited using PECVD at about 500 °C to about 600 °C and the layer of Si02 can undergo chemical mechanical planarization and lithography.
  • the Si02 layer can be etched and cleaned.
  • MOCVD at about 500 °C to about 900°C can be used to facilitate blue LED AER growth and green LED AER growth.
  • Si02 can be deposited using CVD or PECVD and CMP may be used to planarize the Si02.
  • the Si02 layer can be etched and cleaned.
  • MOCVD at about 500 °C to about 900°C can be used to facilitate red LED AER growth.
  • Si02 can again be deposited using CVD or PECVD and CMP can be used to planarize the Si02.
  • a micro-scale lithograph method may be used to create contact trenches for the red, green and blue LEDs and a metal deposition can be used to create metal contacts for each LED. Lithography and etch may be used again to make separate contacts for the red, green and blue LEDs
  • RGB pixels may be fabricated on wafers monolithically and the RGB pixels may then be transferred all at once, from source wafers to TFT backplanes and coupled to one or more transistors on a substrate.
  • a plurality of transistors such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate.
  • MOSFET metal-oxide-semiconductor field-effect transistors
  • the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both.
  • Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
  • Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer.
  • the gate dielectric layer may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material.
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high- k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
  • the gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor.
  • the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide.
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.
  • the gate electrode when viewed as a cross-section of the transistor along the source-channel-drain direction, may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack.
  • the sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
  • source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor.
  • the source and drain regions are generally formed using either an implantation/diffusion process or an
  • etching/deposition process In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
  • the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy.
  • one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
  • ILD interlayer dielectrics
  • the ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials.
  • dielectric materials include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as
  • the ILD layers may include pores or air gaps to further reduce their dielectric constant.
  • FIGURE 18 illustrates an interposer 1800 that can include or interact with one or more embodiments disclosed herein.
  • the interposer 1800 is an intervening substrate used to bridge a first substrate 1802 to a second substrate 1804.
  • the first substrate 1802 may be, for instance, an integrated circuit die.
  • the second substrate 1804 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 1800 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 1800 may couple an integrated circuit die to a ball grid array (BGA) 1806 that can subsequently be coupled to the second substrate 1804.
  • BGA ball grid array
  • the first and second substrates 1802/1804 are attached to opposing sides of the interposer 1800. In other embodiments, the first and second substrates 1802/1804 are attached to the same side of the interposer 1800. And in further embodiments, three or more substrates are interconnected by way of the interposer 1800.
  • the interposer 1800 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide.
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
  • the interposer may include metal interconnects 1808 and vias 1810, including but not limited to through-silicon vias (TSVs) 1812.
  • the interposer 1800 may further include embedded devices 1814, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1800.
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 1800.
  • FIGURE 19 illustrates a computing device 1900 in accordance with various embodiments.
  • the computing device 1900 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.
  • the components in the computing device 1900 include, but are not limited to, an integrated circuit die 1902 and at least one communications logic unit 1908.
  • the communications logic unit 1908 is fabricated within the integrated circuit die 1902 while in other implementations the communications logic unit 1908 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 1902.
  • the integrated circuit die 1902 may include a CPU 1904 as well as on-die memory 1906, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STT-MRAM).
  • eDRAM embedded DRAM
  • STTM spin-transfer
  • Computing device 1900 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1910 (e.g., DRAM), non-volatile memory 1912 (e.g., ROM or flash memory), a graphics processing unit 1914 (GPU), a digital signal processor 1916, a crypto processor 1942 (a specialized processor that executes cryptographic algorithms within hardware), a chipset 1920, an antenna 1922, a display or a touchscreen display 1924, a touchscreen controller 1926, a battery 1928 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1928, a compass 1930, a motion coprocessor or sensors 1932 (that may include an accelerometer, a gyroscope, and a compass), a speaker 1934, a camera 1936, user input devices 1938 (such as a keyboard, mouse, stylus, and touchpad), and a mass
  • the communications logic unit 1908 enables wireless communications for the transfer of data to and from the computing device 1900.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communications logic unit 1908 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 1900 may include a plurality of communications logic units 1908. For instance, a first communications logic unit 1908 may be dedicated to shorter range wireless
  • communications such as Wi-Fi and Bluetooth and a second communications logic unit 1908 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1904 of the computing device 1900 can communicate with one or more devices that are formed in accordance with various embodiments.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communications logic unit 1908 may also include one or more devices, such as transistors or metal interconnects, that are in communication with various ones of the embodiments disclosed herein.
  • another component housed within the computing device 1200 may contain one or more devices, such as transistors or metal interconnects, that are formed in accordance with implementations of the embodiments disclosed herein.
  • the computing device 1900 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an
  • the computing device 1900 may be any other electronic device that processes data.
  • Example 1 is a nanowire pixel including a support substrate, an n-type gallium nitride (GaN) layer on the support substrate, where the GaN layer includes a plurality of N- type GaN core nanorods, a first active emitting region (AER) on a first portion of the plurality of N-type GaN core nanorods to create a first AER LED, a second AER on a second portion of the plurality of N-type GaN core nanorods to create a second AER LED, and a third AER on a third portion of the plurality of N-type GaN core nanorods to create a third AER LED.
  • GaN gallium nitride
  • Example 2 the subject matter of Example 1 can optionally include a fourth AER on a fourth portion of the plurality of N-type GaN core nanorods to create a fourth AER LED.
  • Example 3 the subject matter of any one of Examples 1-2 can optionally include where the N-type GaN core nanorods extend from an N-type GaN layer on a buffer layer.
  • Example 4 the subject matter of any one of Examples 1-3 can optionally include where the plurality of N-type GaN core nanorods were grown using metal organic chemical vapor phase deposition (MOCVD).
  • MOCVD metal organic chemical vapor phase deposition
  • Example 5 the subject matter of any one of Examples 1-4 can optionally include where MOCVD is capable of forming an indium GaN multi quantum well around the N-type GaN core nanorods.
  • Example 6 the subject matter of any one of Examples 1-5 can optionally include where the N-type GaN layer is about lum thick.
  • a method can include growing a buffer layer on a support substrate, growing an N-type gallium nitride (GaN) layer on the buffer layer, growing a core of N-type GaN rods from the N-type GaN layer, growing an active emitting region (AER) around a portion of the N-type GaN core nanorods to create a blue AER LED, growing a AER around a portion of the N-type GaN core nanorods to create a green AER LED, and growing a AER around a portion of the N-type GaN core nanorods to create a red AER LED.
  • GaN gallium nitride
  • AER active emitting region
  • Example 8 the subject matter of Example 7 can optionally include where the core of N-type GaN rods may be grown using metal organic chemical vapor phase deposition (MOCVD).
  • MOCVD metal organic chemical vapor phase deposition
  • Example 9 the subject matter of any one of Examples 7-8 can optionally include where MOCVD may be used to grow an indium GaN multi quantum well around the N-type GaN core nanorods.
  • Example 10 the subject matter of any one of Examples 7-9 can optionally include where the N-type GaN layer is about lum thick.
  • Example 11 the subject matter of any one of Examples 7-10 can optionally include depositing a hard mask on the N-type GaN layer using chemical vapor deposition (CVD)/plasma enhanced CVD (PECVD) or atomic layer deposition (ALD), opening trenches through the hard mask and down to the buffer layer, and allowing the core of N-type GaN rods to grow through the trenches from the N-type GaN layer.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced CVD
  • ALD atomic layer deposition
  • Example 12 the subject matter of any one of Examples 7-11 can optionally include where the hard mask is Si3N4.
  • Example 13 the subject matter of any one of Examples7-12 can optionally include where the support substrate is a silicon or sapphire wafer.
  • Example 14 the subject matter of any one of Examples 8-13 can optionally include growing a AER around a portion of the N-type GaN core nanorods to create a yellow AER LED.
  • Example 15 is an apparatus including a micro LED display that includes red, green, and blue (RGB) nanowire pixels, where the RGB nanowire pixels are fabricated on a wafer monolithically and then transferred all at once to a thin film transistor (TFT) backplane.
  • RGB red, green, and blue
  • TFT thin film transistor
  • Example 16 the subject matter of Example 15 can optionally include where the micro LED display includes active matrix micro LED display panels that include gallium nitride (GaN)-based Micro LEDs that emit RGB colors.
  • the micro LED display includes active matrix micro LED display panels that include gallium nitride (GaN)-based Micro LEDs that emit RGB colors.
  • GaN gallium nitride
  • Example 17 the subject matter of Example 15-16 can optionally include where the RGB nanowire pixels were fabricated on the wafers monolithically by growing a buffer layer on a support substrate, growing an N-type gallium nitride (GaN)-layer on the buffer layer, growing a core of N-type GaN rods from the N-type GaN layer, growing an active emitting region (AER) around a portion of the N-type GaN core nanorods to create a blue AER LED, growing a AER around a portion of the N-type GaN core nanorods to create a green AER LED, and growing a AER around a portion of the N-type GaN core nanorods to create a red AER LED.
  • GaN gallium nitride
  • AER active emitting region
  • Example 18 the subject matter of any one of the Examples 15-17 can optionally include where the N-type GaN layer is about lum thick.
  • Example 19 the subject matter of any one of the Examples 15-18 can optionally include where the core of N-type GaN rods may be grown using metal organic chemical vapor phase deposition (MOCVD).
  • MOCVD metal organic chemical vapor phase deposition
  • Example 20 the subject matter of any one of the Examples 15-19 can optionally include where MOCVD may be used to grow an InGaN multi quantum well around the N-type GaN core nanorods.
  • Example 21 is a computing device including a processor mounted on a substrate, a communications logic unit within the processor, a memory within the processor, a graphics processing unit within the computing device, an antenna within the computing device, a display on the computing device, a battery within the computing device, a power amplifier within the processor, and a voltage regulator within the processor, where the display includes, red, green, and blue (RGB) nanowire pixels, where the RGB nanowire pixels are fabricated on a wafer monolithically and then transferred all at once to a thin film transistor (TFT) backplane.
  • RGB red, green, and blue
  • Example 22 the subject matter of Example 21 can optionally include where the micro LED display includes active matrix micro LED display panels that include gallium nitride (GaN)-based Micro LEDs that emit RGB colors.
  • the micro LED display includes active matrix micro LED display panels that include gallium nitride (GaN)-based Micro LEDs that emit RGB colors.
  • GaN gallium nitride
  • Example 23 the subject matter of any one of the Examples 21-22 can optionally include where the RGB nanowire pixels includes a support substrate, an n-type gallium nitride (GaN) layer on the support substrate, where the GaN layer includes a plurality of N-type GaN core nanorods, a blue active emitting region (AER) grown around a blue portion of the plurality of N-type GaN core nanorods to create a blue AER LED, a green AER grown around a green portion of the plurality of N-type GaN core nanorods to create a green AER LED, and a red AER grown around a red portion of the plurality of N-type GaN core nanorods to create a red AER LED.
  • the subject matter of any one of the Examples 21-22 can optionally include where the N-type GaN core nanorods were grown from an N-type GaN layer on a buffer layer.
  • Example 25 the subject matter of any one of the Examples 21-24 can optionally include where the plurality of N-type GaN core nanorods were grown using metal organic chemical vapor phase deposition (MOCVD).
  • MOCVD metal organic chemical vapor phase deposition
  • Example 26 the subject matter of any one of the Examples 21-25 can optionally include where wherein the N-type GaN layer is about lum thick.
  • Example 27 is a nanowire pixel including a support substrate, an n-type gallium nitride (GaN) layer on the support substrate, where the GaN layer includes a plurality of N-type GaN core nanorods, a first active emitting region (AER) grown around a first portion of the plurality of N-type GaN core nanorods to create a first AER LED, a second AER grown around a second portion of the plurality of N-type GaN core nanorods to create a second AER LED, and a third AER grown around a third portion of the plurality of N-type GaN core nanorods to create a third AER LED.
  • AER active emitting region
  • Example 28 the subject matter of Example 27 can optionally include a fourth AER grown around a fourth portion of the plurality of N-type GaN core nanorods to create a fourth AER LED.
  • Example 29 the subject matter of any one of Examples 27-28 can optionally include where the N-type GaN core nanorods were grown from an N-type GaN layer on a buffer layer.
  • Example 30 the subject matter of any one of Examples 27-29 can optionally include where the plurality of N-type GaN core nanorods were grown using metal organic chemical vapor phase deposition (MOCVD).
  • MOCVD metal organic chemical vapor phase deposition
  • Example 31 the subject matter of any one of Examples 27-30 can optionally include where MOCVD may be used to grow an indium GaN multi quantum well around the N-type GaN core nanorods.
  • Example 32 the subject matter of any one of Examples 27-31 can optionally include where the N-type GaN layer is about lum thick.

Abstract

L'invention concerne des substrats, des ensembles et des techniques d'activation d'un pixel de DEL à nanofils. Par exemple, certains modes de réalisation comprennent la croissance d'une couche tampon sur un substrat de support, la croissance d'une couche de GaN de type N sur la couche tampon, la croissance d'un noyau de tiges de GaN de type N à partir de la couche de GaN de type N, la croissance d'une zone active d'émission (AER) autour d'une partie des nanotiges du noyau de GaN de type N afin de créer une DEL AER bleue, la croissance d'une AER autour d'une partie des nanotiges du noyau de GaN de type N afin de créer une DEL AER verte, et la croissance d'une AER autour d'une partie des nanotiges du noyau de GaN de type N afin de créer une DEL AER rouge. Il est ainsi possible de fabriquer des pixels RVB sur des plaquettes de manière monolithique (c'est-à-dire sur une seule plaquette). Les pixels RVB peuvent alors être tous transférés en une seule fois, à partir de plaquettes source vers des panneaux arrière de TFT.
PCT/US2015/000385 2015-12-26 2015-12-26 Pixel de del à nanofils WO2017111827A1 (fr)

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