WO2017111831A1 - Dispositif de commutation empilable - Google Patents

Dispositif de commutation empilable Download PDF

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Publication number
WO2017111831A1
WO2017111831A1 PCT/US2015/000389 US2015000389W WO2017111831A1 WO 2017111831 A1 WO2017111831 A1 WO 2017111831A1 US 2015000389 W US2015000389 W US 2015000389W WO 2017111831 A1 WO2017111831 A1 WO 2017111831A1
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WIPO (PCT)
Prior art keywords
layer
contact area
reaction layer
gate
drain
Prior art date
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PCT/US2015/000389
Other languages
English (en)
Inventor
Elijah V. KARPOV
Prashant Majhi
Uday Shah
Ravi Pillarisetty
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2015/000389 priority Critical patent/WO2017111831A1/fr
Priority to TW105138786A priority patent/TW201733037A/zh
Publication of WO2017111831A1 publication Critical patent/WO2017111831A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/253—Multistable switching devices, e.g. memristors having three or more electrodes, e.g. transistor-like devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides

Definitions

  • the present disclosure relates generally to the field of integrated circuits, and more particularly, to substrates, assemblies, and techniques to enable stackable switching devices.
  • FIGURE 1A is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE IB is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 2 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 3 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 4 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 5 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 6 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 7 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 8 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 9 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure.
  • FIGURE 10 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 11 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 12 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 13 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 14 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure.
  • FIGURE 15 is a simplified flowchart illustrating potential operations that may be associated with one embodiment of the present disclosure
  • FIGURE 16 is an interposer implementing one or more of the embodiments disclosed herein.
  • FIGURE 117 is a computing device built in accordance with an embodiment disclosed herein.
  • a stackable switching device can include a source, a drain, a reaction layer, a contact area, and a gate.
  • the reaction layer is a resistive switching layer and can be an oxide based channel or some other area where oxygen vacancy or hydrogen can be modulated or the resistance of reaction layer can be modulated.
  • the resistance of the reaction layer can be modulated by the gate.
  • the contact area may be a Schottky contact area or barrier or some other similar area configured as a potential energy barrier for electrons formed at a metal-semiconductor junction.
  • Scaling of logic devices is typically accomplished by reducing the size of the logic device.
  • One approach is based on increasing the number of logic elements per unit area.
  • the density of dies needs to be increased and additional logic devices need to be fabricated above the silicon.
  • dies may be stacked on top of each other such that instead of fabricating logic devices in a silicon single crystal layer on top of a silicon wafer, additional logic devices can be fabricated above the silicon.
  • a device may include a source, a drain, and a reaction layer located between the source and the drain.
  • the source, the drain, and the reaction layer can be on top of a support substrate such as a semiconductor substrate and a contact area can modulate the resistance of the reaction layer.
  • the substrate may be a non-silicon flexible substrate.
  • the contact area is a Schottky contact area and the reaction layer is a resistive switching layer.
  • the terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • Implementations of the embodiments disclosed herein may be formed or carried out on a substrate, such as a semiconductor substrate.
  • the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure.
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials.
  • the substrate may be a flexible substrate including 2D materials such as graphene and MoS2, organic materials such as pentacene, transparent oxides such as IGZO poly/amorphous (low temperature of dep) lll-V semiconductors and Ge/Si, and other non-silicon flexible substrates.
  • 2D materials such as graphene and MoS2
  • organic materials such as pentacene
  • transparent oxides such as IGZO poly/amorphous (low temperature of dep) lll-V semiconductors and Ge/Si
  • other non-silicon flexible substrates such as a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a
  • FIGURES 1A and IB illustrate one
  • Stackable switching device 100 can be formed on a support substrate 102.
  • support substrate 102 can include silicon or some other non-metal layer.
  • substrate 102 may be a non- silicon flexible substrate.
  • Stackable switching device 100 can include a source 104, a drain 106, a reaction layer 108, a contact area 110, and a gate 112.
  • source 104 may be a metal source and drain 106 may be a metal drain.
  • Reaction layer 108 is a resistive switching layer and can be an oxide based channel or some other area where oxygen vacancy or hydrogen can be modulated or the resistance of reaction layer 108 can be modulated.
  • the resistance of reaction layer 108 can be modulated by gate 112.
  • Contact area 110 may be a Schottky contact area or barrier or some other similar area configured as a potential energy barrier for electrons formed at a metal-semiconductor junction.
  • Gate 112 may be a metal gate.
  • stackable switching device 100 is illustrated in an "on” configuration.
  • stackable switching device 100 is illustrated in an "off' configuration.
  • contact area 110 can exchange oxygen vacancy or hydrogen ions with reaction layer 108. This causes reaction layer 108 to have an oxygen vacancy or hydrogen reduced "off' state.
  • FIGURE 2 illustrates one embodiment of one of the early stages of building stackable switching device 100.
  • an interconnect dielectric layer 114 can be deposited on support substrate 102.
  • interconnect dielectric layer 114 may be an isolation oxide layer or some other interconnect dielectric layer that can provide a non-conductive base.
  • some of interconnect dielectric layer 114 may include a conductive area/electrode just beneath the gate to be biased with respect to gate 112.
  • Reaction layer 108 can be deposited on interconnect dielectric layer 114 and may be a resistive switching layer that can change conduction based on oxygen vacancy or hydrogen ion mobility effects.
  • reaction layer 108 can be about 0.5 nm to about 5 nms. In other embodiments, other thicknesses that enable the operations and features discussed herein may be used.
  • Contact area 110 can be deposited on reaction layer 108, is a material that has a resistivity similar to metal (e.g., ⁇ 10 mOhmcm, and is conductive.
  • Gate 112 can be deposited on contact area 110. In an example, gate 112 can function as a metal layer etch stop.
  • a hard mask layer 116 can be deposited on gate 112.
  • FIGURE 3 illustrates one embodiment of one of the early stages of building stackable switching device 100.
  • a resist layer 118 can be placed on top of hard mask layer 116. Resist layer 118 can be positioned where the stackable switching device 100 will be located.
  • FIGURE 4 illustrates one embodiment of one of the early stages of building stackable switching device 100.
  • hard mask layer 116 and gate 112 can be etched. The etching can stop at contact area 110.
  • FIGURE 5 illustrates one embodiment of one of the stages of building stackable switching device 100.
  • resist layer 118 can be removed.
  • the exposed surface of contact area 110, gate 112 and hard mask layer 116 can be cleaned.
  • FIGURE 6 illustrates one embodiment of one of the stages of building stackable switching device 100.
  • portions of contact area 110 can be removed.
  • the remaining hard mask layer 116 can protect the area of contact area 110 that will be used in stackable switching device 100 and removal can stop on reaction layer 108.
  • FIGURE 7 illustrates one embodiment of one of the stages of building stackable switching device 100.
  • hard mask layer 116 can be removed. Hard mask layer 116 is removed because it is non-conductive material and could interrupt the connectivity of stackable switching device 100.
  • FIGURE 8 illustrates one embodiment of one of the stages of building stackable switching device 100.
  • a dielectric isolation layer 120 is deposited on reaction layer 108 and over contact area and gate 112.
  • Dielectric isolation layer 120 can be a silicon oxide layer or some other isolation material.
  • One or more resist layers 122 are deposited on dielectric isolation layer 120. The location of one or more resist layers 122 is conditioned upon the desired location of source 104 and drain 106 for stackable switching device 100.
  • FIGURE 9 illustrates one embodiment of one of the stages of building stackable switching device 100.
  • areas of dielectric isolation layer 120 that are not protected by resist layers 122 are etched and removed.
  • the width of dielectric isolation layer 120 is less than the width of contact area 110 to allow for reasonable modulation of layer conductance. The etching can stop at reaction layer 108 and gate 112.
  • FIGURE 10 illustrates one embodiment of one of the stages of building stackable switching device 100.
  • resist layers 122 can be removed.
  • the exposed surface of reaction layer 108 and gate 112 can be cleaned.
  • FIGURE 11 illustrates one embodiment of one of the stages of building stackable switching device 100.
  • reaction layer 108 in the areas where the desired location of source 104 and drain 106 for stackable switching device 100 are located.
  • the exposed surfaces of gate 112 and interconnect dielectric layer 114 can be cleaned.
  • FIGURE 12 illustrates one embodiment of one of the stages of building stackable switching device 100.
  • conductive material 130 can be deposited into the etched areas.
  • conductive material 130 may be metal or metallic.
  • FIGURE 13 illustrates one embodiment of one of the stages of building stackable switching device 100.
  • excessive conductive material 130 is removed.
  • Exposed layers of conductive material 130 (in source 104, drain 106, and reaction layer 108 but not illustrated) and dielectric isolation layer 120 can be polished.
  • FIGURE 14 illustrates one embodiment of a portion of an electronic device that includes one or more stackable switching devices 100.
  • a portion of an electronic device can include a silicon layer 124, a first layer 126, and a second layer 128. Note that while only three layers are illustrated (i.e., two layers stacked on silicon layer 124) many more layers could be stacked onto of silicon layer and the number of layers that can be stacked is only limited by limited by design, total height, and economic limitations.
  • Silicon layer 124 can include various electronic devices (e.g., CMOS, etc.) 140. Silicon layer 124 can be electrically coupled to first layer 126 using one or more ILDs 140. First layer 126 may be a non-silicon layer and can include first layer electronic devices 142 and one or more stackable switching devices 100. First layer electronic devices 142 may be thin-film based electronic devices. First layer 126 can be electrically coupled to second layer 128 using one or more IDLs 144a and 144b. IDLs 144a and 144b may be the same or similar type electrical connector as IDL 140. Second layer 128 may be a non-silicon layer and can include second layer electronic devices 146 and one or more stackable switching devices 100. Second layer electronic devices 146 may be thin-film based electronic devices. Second layer 128 may include the same semiconductor substrate as first layer 126 or may include a different semiconductor substrate.
  • the semiconductor substrate for first layer 126 and second layer 128 may be formed using alternate materials, which may or may not be combined with silicon. This includes, but is not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials.
  • the substrate of any layer may be a flexible substrate including 2D materials such as graphene and MoS2, organic materials such as pentacene, transparent oxides such as IGZO poly/amorphous (low temperature of dep) lll-V semiconductors and Ge/Si, and other non-silicon flexible substrates.
  • FIGURE 15 is an example flowchart illustrating possible operations of a flow 1500 that may be associated with a stackable switching device, in accordance with an embodiment.
  • an isolation layer on a silicon substrate, an isolation layer, a function layer, a conductive layer, a metal layer etch stop, and a hard mask are created.
  • the function layer can be similar to reaction layer 108.
  • a resist layer is created at a desired location of a switching device.
  • portions of the hard mask layer and the metal layer etch stop that are not under the resist layer are etched away.
  • the resist layer is removed.
  • a portion of the conductive layer that is not under the remaining metal layer etch stop is removed.
  • a resistive layer is build.
  • a plurality of dielectric isolation areas are built on the resistive layer.
  • portions of the resistive layer not under the dielectric isolation areas are etched away.
  • the remaining dielectric isolation areas are etched away.
  • a conductive material is deposited and polished.
  • a plurality of transistors such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), that include stackable switching device 100, may be fabricated on the substrate.
  • the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both.
  • Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that various embodiments may also be carried out using nonplanar transistors.
  • Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer.
  • the gate dielectric layer may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material.
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high- k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
  • the gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some
  • the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide.
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.
  • the gate electrode when viewed as a cross-section of the transistor along the source-channel-drain direction, may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack.
  • the sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
  • source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor.
  • the source and drain regions are generally formed using either an implantation/diffusion process or an
  • etching/deposition process In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
  • the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy.
  • one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
  • ILD interlayer dielectrics
  • the ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials.
  • dielectric materials include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as
  • the ILD layers may include pores or air gaps to further reduce their dielectric constant.
  • FIGURE 16 illustrates an interposer 1600 that can include or interact with one or more embodiments disclosed herein.
  • the interposer 1600 is an intervening substrate used to bridge a first substrate 1602 to a second substrate 1604.
  • the first substrate 1602 may be, for instance, an integrated circuit die.
  • the second substrate 1604 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 1600 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 1600 may couple an integrated circuit die to a ball grid array (BGA) 1606 that can subsequently be coupled to the second substrate 1604.
  • BGA ball grid array
  • the first and second substrates 1602/1604 are attached to opposing sides of the interposer 1600. In other embodiments, the first and second substrates 1602/1604 are attached to the same side of the interposer 1600. And in further embodiments, three or more substrates are interconnected by way of the interposer 1600.
  • the interposer 1600 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide.
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
  • the interposer may include metal interconnects 1608 and vias 1610, including but not limited to through-silicon vias (TSVs) 1612.
  • the interposer 1600 may further include embedded devices 1614, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1600.
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 1600.
  • FIGURE 17 illustrates a computing device 1700 in accordance with various embodiments.
  • the computing device 1700 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.
  • SoC system-on-a-chip
  • the components in the computing device 1700 include, but are not limited to, an integrated circuit die 1702 and at least one communications logic unit 1708.
  • the communications logic unit 1708 is fabricated within the integrated circuit die 1702 while in other implementations the communications logic unit 1708 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 1702.
  • the integrated circuit die 1702 may include a CPU 1704 as well as on-die memory 1706, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STT-MRAM).
  • eDRAM embedded DRAM
  • STTM spin-transfer torque memory
  • STT-MRAM spin-transfer torque memory
  • volatile memory 1710 e.g., DRAM
  • non-volatile memory 1712 e.g., ROM or flash memory
  • graphics processing unit 1714 GPU
  • digital signal processor 1716 e.g., a crypto processor 1742 (a specialized processor that executes cryptographic algorithms within hardware)
  • chipset 1720 an antenna 1722, a display or a touchscreen display 1724, a touchscreen controller 1726, a battery 1728 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1728, a compass 1730, a motion coprocessor or sensors 1732 (that may include an accelerometer, a gyroscope, and a compass), a speaker 1734, a camera 1736, user input devices 1738 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 1740 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD),
  • volatile memory 1710 e.
  • the communications logic unit 1708 enables wireless communications for the transfer of data to and from the computing device 1700.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communications logic unit 1708 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 1700 may include a plurality of communications logic units 1708. For instance, a first communications logic unit 1708 may be dedicated to shorter range wireless
  • communications such as Wi-Fi and Bluetooth and a second communications logic unit 1708 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1704 of the computing device 1700 can communicate with one or more devices that are formed in accordance with various embodiments.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communications logic unit 1708 may also include one or more devices, such as transistors or metal interconnects, that are in communication with various ones of the embodiments disclosed herein.
  • another component housed within the computing device 1200 may contain one or more devices, such as transistors or metal interconnects, that are formed in accordance with implementations of the embodiments disclosed herein.
  • the computing device 1700 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an
  • the computing device 1700 may be any other electronic device that processes data.
  • Example 1 is an apparatus including a source, a drain, a reaction layer located between the source and the drain, where the source, the drain, and the reaction layer are on top of a support substrate, and a contact area, where the contact area can modulate the resistance of the reaction layer.
  • Example 2 the subject matter of Example 1 can optionally include where the contact area is a Schottky contact area.
  • Example 3 the subject matter of any one of Examples 1-2 can optionally include where the reaction layer is a resistive switching layer.
  • Example 4 the subject matter of any one of Examples 1-3 can optionally include where the support substrate is a non-metal layer.
  • Example 5 the subject matter of any one of Examples 1-4 can optionally include where a thickness of the reaction layer is between about 0.5 nms to about 5 nms.
  • Example 6 the subject matter of any one of Examples 1-5 can optionally include a gate, wherein the gate can control the contact area to module the resistance of the reaction layer.
  • Example 7 the subject matter of any one of Example 1-6 can optionally include where the gate is a metal gate.
  • a method can include depositing an interconnect dielectric layer on a support substrate, depositing a reaction layer on the interconnect dielectric layer, depositing a contact area on the reaction layer, and depositing a gate on the contact area, wherein the gate can control the contact area to module the resistance of the reaction layer.
  • Example 9 the subject matter of Example 8 can optionally include depositing a hard mask layer on the gate, depositing a resist layer on the hard mask layer, etching a portion of the hark mask layer and a portion of the resist layer down to the contact area, removing the hard mask layer, etching a portion of the contact area down to the reaction layer, and depositing a dielectric isolation layer over the gate and reaction layer.
  • Example 10 the subject matter of any one of Examples 8-9 can optionally include depositing one or more resist layers on the dielectric isolation layer, etching and removing portions of the dielectric isolation layer, and adding conductive material into the etched and removed portions of the dielectric isolation layer to create a source, a drain, and a gate contact.
  • Example 11 the subject matter of any one of Examples 8-10 can optionally include where the support substrate is non-conductive.
  • Example 12 the subject matter of any one of Examples 8-11 can optionally include where the interconnect dielectric layer is an isolation oxide layer.
  • the subject matter of any one of Examples 8-12 can optionally include where the reaction layer has a thickness between about 0.5 nm to about 5 nms.
  • Example 14 the subject matter of any one of Examples 8-13 can optionally include where the contact area has metallic properties and is conductive.
  • Example 15 is a computing device including a processor mounted on a substrate, a communications logic unit within the processor, a memory within the processor, a graphics processing unit within the computing device, an antenna within the computing device, a display on the computing device, a battery within the computing device, a power amplifier within the processor, and a voltage regulator within the processor.
  • the processor can include a source, a drain, a reaction layer located between the source and the drain, where the source, the drain, and the reaction layer are on top of a support substrate, and a contact area, where the contact area can modulate the resistance of the reaction layer.
  • Example 16 the subject matter of Example 15 can optionally include where the contact area is a Schottky contact area.
  • Example 17 the subject matter of Example 15-16 can optionally include where the reaction layer is a resistive switching layer.
  • Example 18 the subject matter of any one of the Examples 15-17 can optionally include where the support substrate is a non-metal layer.
  • Example 19 the subject matter of any one of the Examples 15-18 can optionally include where a thickness of the reaction layer is between about 0.5 nms to about 5 nms.
  • Example 20 the subject matter of any one of the Examples 15-19 can optionally include a gate, wherein the gate can control the contact area to module the resistance of the reaction layer.
  • Example 21 is an integrated circuit (IC) assembly including a substrate, a source on top of the substrate, a drain on top of the substrate a reaction layer located between the source and the drain, and on top of the substrate, and a contact area, where the contact area can modulate the resistance of the reaction layer.
  • IC integrated circuit
  • Example 22 the subject matter of Example 21 can optionally include where the contact area is a Schottky contact area.
  • the subject matter of any one of the Examples 21-22 can optionally include where the reaction layer is a resistive switching layer.
  • Example 24 the subject matter of any one of the Examples 21-22 can optionally include where a thickness of the reaction layer is between about 0.5 nms to about 5 nms.
  • Example 25 the subject matter of any one of the Examples 21-24 can optionally include a gate, wherein the gate can control the contact area to module the resistance of the reaction layer.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

L'invention concerne des substrats, des ensembles et des techniques d'activation d'un dispositif de commutation empilable. Par exemple, dans certains modes de réalisation, un dispositif peut comprendre une source, un drain, et une couche de réaction placée entre la source et le drain. La source, le drain et la couche de réaction peuvent être disposés sur une partie supérieure d'un substrat de support tel qu'un substrat semi-conducteur, et une zone de contact peur moduler la résistance de la couche de réaction. Dans un exemple, la surface de contact est une zone de contact Schottky, et la couche de réaction est une couche de commutation résistive.
PCT/US2015/000389 2015-12-26 2015-12-26 Dispositif de commutation empilable WO2017111831A1 (fr)

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PCT/US2015/000389 WO2017111831A1 (fr) 2015-12-26 2015-12-26 Dispositif de commutation empilable
TW105138786A TW201733037A (zh) 2015-12-26 2016-11-25 可堆疊式切換裝置

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070131985A1 (en) * 2005-11-29 2007-06-14 Kazunori Fujita Semiconductor device and method for manufacturing the same
US20090174435A1 (en) * 2007-10-01 2009-07-09 University Of Virginia Monolithically-Integrated Graphene-Nano-Ribbon (GNR) Devices, Interconnects and Circuits
WO2010014974A2 (fr) * 2008-08-01 2010-02-04 President And Fellows Of Harvard College Dispositifs à transition de phase et dispositifs capacitifs intelligents
US20130026558A1 (en) * 2011-07-29 2013-01-31 Samsung Electronics Co., Ltd. Semiconductor devices including variable resistance material and methods of fabricating the same
US8405124B2 (en) * 2008-01-09 2013-03-26 International Business Machines Corporation Logic element, and integrated circuit or field programmable gate array

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070131985A1 (en) * 2005-11-29 2007-06-14 Kazunori Fujita Semiconductor device and method for manufacturing the same
US20090174435A1 (en) * 2007-10-01 2009-07-09 University Of Virginia Monolithically-Integrated Graphene-Nano-Ribbon (GNR) Devices, Interconnects and Circuits
US8405124B2 (en) * 2008-01-09 2013-03-26 International Business Machines Corporation Logic element, and integrated circuit or field programmable gate array
WO2010014974A2 (fr) * 2008-08-01 2010-02-04 President And Fellows Of Harvard College Dispositifs à transition de phase et dispositifs capacitifs intelligents
US20130026558A1 (en) * 2011-07-29 2013-01-31 Samsung Electronics Co., Ltd. Semiconductor devices including variable resistance material and methods of fabricating the same

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