WO2019132894A1 - Électrode source et électrode drain auto-alignées destinées à des transistors en couches minces - Google Patents

Électrode source et électrode drain auto-alignées destinées à des transistors en couches minces Download PDF

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Publication number
WO2019132894A1
WO2019132894A1 PCT/US2017/068575 US2017068575W WO2019132894A1 WO 2019132894 A1 WO2019132894 A1 WO 2019132894A1 US 2017068575 W US2017068575 W US 2017068575W WO 2019132894 A1 WO2019132894 A1 WO 2019132894A1
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layer
device body
forming
accumulation layer
area
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PCT/US2017/068575
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English (en)
Inventor
Travis LAJOIE
Tahir Ghani
Jack T. Kavalieros
Yih Wang
Allen GARDINER
Van H. Le
Chieh-Jen Ku
Abhishek A. Sharma
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Intel Corporation
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Priority to PCT/US2017/068575 priority Critical patent/WO2019132894A1/fr
Publication of WO2019132894A1 publication Critical patent/WO2019132894A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Definitions

  • Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to transistors.
  • a thin-film transistor is a kind of field-effect transistor in back-end-of-line (BEOL) including a channel layer, a gate electrode, and source and drain electrodes, over a supporting but non-conducting substrate.
  • a TFT differs from a conventional transistor, where a channel of the conventional transistor is typically within a substrate, such as a silicon substrate.
  • TFTs have emerged as an attractive option to fuel Moore’s law by integrating TFTs vertically in the backend, while leaving the silicon substrate areas for high-speed transistors. TFTs hold great potential for large area and flexible electronics, e.g., displays. Other applications of TFTs may include memory arrays.
  • TFTs In order to make TFTs more attractive for memory applications or other applications, it is important to fabricate TFTs with small channel lengths and hence gate lengths. However, it is difficult to control a channel length and a gate length of a TFT in current technology. Furthermore, in current technology, the source electrode and the drain electrode of a TFT may not be self- aligned to an active channel area. Misalignment errors between a source electrode or a drain electrode with an active channel area, in addition to variations of feature sizes, may lead to increased contact resistance for the source electrode and the drain electrode, and reduced drive current.
  • FIG. 1 schematically illustrates a diagram of a thin-film transistor (TFT) having a source electrode and a drain electrode aligned to an edge of a rectangular area of a device body, in accordance with some embodiments.
  • TFT thin-film transistor
  • Figure 2 schematically illustrates a diagram of two TFTs having a source electrode and a drain electrode aligned to an edge of a rectangular area of a device body, in accordance with some embodiments.
  • Figure 3 illustrates a process for forming a TFT having a source electrode and a drain electrode self-aligned with respect to a channel area of a device body of the TFT and aligned to an edge of a rectangular area of the device body, in accordance with some embodiments.
  • FIGS. 4-15 illustrate a process for forming a TFT having a source electrode and a drain electrode self-aligned with respect to a channel area of a device body of the TFT and aligned to an edge of a rectangular area of the device body, in accordance with some embodiments.
  • Figure 16 illustrates another process for forming a TFT having a source electrode and a drain electrode self-aligned with respect to a channel area of a device body of the TFT and aligned to an edge of a rectangular area of the device body, in accordance with some embodiments.
  • FIG 17 schematically illustrates a diagram of a TFT having a source electrode and a drain electrode aligned to an edge of a rectangular area of a device body and formed in back-end- of-line (BEOL) on a substrate, in accordance with some embodiments.
  • BEOL back-end- of-line
  • Figure 18 schematically illustrates an interposer implementing one or more embodiments of the disclosure, in accordance with some embodiments.
  • Figure 19 schematically illustrates a computing device built in accordance with an embodiment of the disclosure, in accordance with some embodiments.
  • TFT thin-film transistor
  • Current technology for fabricating a thin-film transistor may not have a source electrode and a drain electrode of the TFT self-aligned to an active channel area of the TFT.
  • a TFT may have the source electrode and the drain electrode misaligned with a channel area and a device body of the TFT.
  • the TFT may have increased contact resistance for the source electrode and the drain electrode and reduced drive current.
  • Embodiments herein may present a process to form a source electrode and a drain electrode self-aligned with respect to a channel area of a device body of the TFT.
  • a channel area may be first patterned based on a backbone on a hardmask layer. Spaces for a source electrode and a drain electrode may be defined by two spacers around the backbone on the hardmask layer. By controlling the thickness of the spacers to be equal length, a source electrode and a drain electrode may be made of equal length, and not overlapping with the channel area. Because the source electrode and the drain electrode are self-aligned and equal in size, the TFT may have a smaller size overall.
  • a TFT may have a source electrode and a drain electrode aligned to an edge of a rectangular area of a device body.
  • An etching accumulation layer may be used in the process to reduce the opportunity for the channel area and the device body to expose to processing chemicals and external environments, which also improves transistor performance.
  • Embodiments herein may present a semiconductor device including a TFT.
  • the TFT may include a gate electrode above a substrate, a gate dielectric layer above the gate electrode, and a device body above the gate dielectric layer.
  • the device body may include a source area, a drain area, and a channel area between the source area and the drain area.
  • the device body may be of a rectangular shape separated from other devices by isolation areas.
  • a source electrode may be above the source area, aligned to an edge of the device body, while a drain electrode may be above the drain area, and aligned to an edge of the device body.
  • a passivation layer may be above the channel area and between the source electrode and the drain electrode.
  • Embodiments herein may present a method for forming a semiconductor device.
  • the method may include: forming a rectangular area in an etching accumulation layer, surrounded by openings in the etching accumulation layer in a first direction following a shadow of a backbone, a first spacer, and a second spacer on one or more hardmask layers above the etching accumulation layer, and openings in the etching accumulation layer in a second direction orthogonal to the first direction, wherein the first spacer and the second spacer are around the backbone.
  • the method may further include extending the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer into a passivation layer below the etching accumulation layer, and a device body layer below the passivation layer to form a rectangular area in the passivation layer and the device body layer.
  • the method may include forming isolation areas around the rectangular area in the passivation layer and the device body layer, and in the etching accumulation layer, by filling one or more isolation materials into the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer and extended into the passivation layer and the device body layer.
  • Embodiments herein may present a method for forming a semiconductor device.
  • the method may include: forming a gate electrode; forming a device body layer above the gate electrode; forming a passivation layer above the device body layer; forming an etching accumulation layer above the passivation layer; forming one or more hardmask layers above the etching accumulation layer; forming a backbone on the one or more hardmask layers; forming a first spacer and a second spacer around the backbone; and forming openings in the etching accumulation layer in a first direction, by following a shadow of the backbone, the first spacer, and the second spacer.
  • the method may further include forming openings in the etching accumulation layer in a second direction orthogonal to the first direction, wherein the openings in the etching accumulation layer in the first direction and the openings in the etching accumulation layer in the second direction form a rectangular area in the etching accumulation layer.
  • the method may include: extending the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer into the passivation layer and the device body layer to form a rectangular area in the passivation layer and the device body layer; and forming isolation areas around the rectangular area in the passivation layer and the device body layer, and in the etching accumulation layer by filling one or more isolation materials into the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer and extended into the passivation layer and the device body layer.
  • phrase“A and/or B” means (A), (B), or (A and B).
  • phrase“A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
  • the terms“over,”“under,”“between,”“above,” and“on” as used herein may refer to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer“on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening features.
  • “Coupled” may mean one or more of the following.“Coupled” may mean that two or more elements are in direct physical or electrical contact. However,“coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other.
  • the term“directly coupled” may mean that two or more elements are in direct contact.
  • the phrase“a first feature formed, deposited, or otherwise disposed on a second feature” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.
  • circuitry may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality.
  • ASIC Application Specific Integrated Circuit
  • computer-implemented method may refer to any method executed by one or more processors, a computer system having one or more processors, a mobile device such as a smartphone (which may include one or more processors), a tablet, a laptop computer, a set-top box, a gaming console, and so forth.
  • Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate.
  • the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure.
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.
  • MOSFET metal-oxide-semiconductor field-effect transistors
  • the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both.
  • Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
  • Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer.
  • the gate dielectric layer may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material.
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
  • the gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor.
  • the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide.
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a work function that is between about 4.9 eV and about 5.2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a work function that is between about 3.9 eV and about 4.2 eV.
  • the gate electrode when viewed as a cross-section of the transistor along the source-channel-drain direction, may consist of a“U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack.
  • the sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
  • source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor.
  • the source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process.
  • dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions.
  • An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process.
  • the substrate may first be etched to form recesses at the locations of the source and drain regions.
  • the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
  • the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
  • ILD interlayer dielectrics
  • the ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.
  • the ILD layers may include pores or air gaps to further reduce their dielectric constant.
  • FIG. 1 schematically illustrates a diagram of a thin-film transistor (TFT) 100 having a source electrode 111 and a drain electrode 113 aligned to an edge of a rectangular area of a device body 109, in accordance with some embodiments.
  • TFT thin-film transistor
  • FIG. 1 schematically illustrates a diagram of a thin-film transistor (TFT) 100 having a source electrode 111 and a drain electrode 113 aligned to an edge of a rectangular area of a device body 109, in accordance with some embodiments.
  • TFT thin-film transistor
  • one or more of the components within a TFT, a source electrode, a drain electrode, and a device body may include additional and/or varying features from the description below, and may include any device that one having ordinary skill in the art would consider and/or refer to as a TFT, a source electrode, a drain electrode, and a device body.
  • the TFT 100 may include a substrate 101, an ILD layer 103 above the substrate 101, a gate electrode 105 above the ILD layer 103 and the substrate 101, and an ILD layer 115 above the gate electrode 105.
  • a gate dielectric layer 107 may be above the gate electrode 105.
  • the device body 109 may be above the gate electrode 105, and further above the gate dielectric layer 107.
  • the device body 109 may include a source area 191, a drain area 193, and a channel area 195 between the source area 191 and the drain area 193.
  • the device body 109 may be of a rectangular shape separated from other devices by an isolation area 121 and an isolation area 123.
  • the source electrode 111 may be above the source area 191 and aligned to an edge 192 of the device body 109, and the drain electrode 113 may be above the drain area 193 and aligned to an edge 194 of the device body 109.
  • a passivation layer 115 may be above the channel area 195 and between the source electrode 111 and the drain electrode 113.
  • the isolation area 121 may be through the gate dielectric layer 107, next to the edge 192 of the device body 109, and next to an edge of the source electrode 111.
  • the isolation area 123 may be through the gate dielectric layer 107, next to the edge 194 of the device body 109, and next to an edge of the drain electrode 123.
  • the channel area 195 may be patterned first based on a backbone on a hardmask layer, not shown. Spaces for the source electrode 111 and the drain electrode 113 may be defined by two spacers around the backbone on the hardmask layer. By controlling the thickness of the spacers to be equal length, the source electrode 111 and the drain electrode 113 may be made of equal length, or substantially equal length with some differences caused by processing variations. In addition, the source electrode 111 and the drain electrode 113 may not overlap with the channel area 195. Because the source electrode 111 and the drain electrode 113 may be self-aligned and equal in size, the TFT 100 may have a smaller size overall.
  • the substrate 101 may be a silicon substrate, a glass substrate, such as soda lime glass or borosilicate glass, a metal substrate, a plastic substrate, or other suitable substrate.
  • the ILD layer 103 may include a silicon oxide (SiO) film, a silicon nitride (SiN) film, Cb-tetraethylorthosilicate (TEOS), Cb-hexamethyldisiloxane (HMDS), plasma-TEOS oxide layer, or other suitable materials.
  • SiO silicon oxide
  • SiN silicon nitride
  • TEOS Cb-tetraethylorthosilicate
  • HMDS Cb-hexamethyldisiloxane
  • plasma-TEOS oxide layer or other suitable materials.
  • the gate electrode 105, the source electrode 111, or the drain electrode 113 may be formed as a single layer or a stacked layer using one or more conductive films including a conductive material.
  • the gate electrode 105, the source electrode 111, or the drain electrode 113 may include gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), molybdenum (Mo), copper (Cu), tantalum (Ta), tungsten (W), nickel (Ni), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, Mo, Au, Pt, Al Ni, Cu, Cr, TiAlN, HfAlN, or InAlO.
  • the gate electrode 105, the source electrode 111, or the drain electrode 113 may include tantalum nitride (TaN), titanium nitride (TiN), iridium- tantalum alloy (Ir-Ta), indium-tin oxide (ITO), the like, and/or a combination thereof.
  • TaN tantalum nitride
  • TiN titanium nitride
  • Ir-Ta iridium- tantalum alloy
  • ITO indium-tin oxide
  • the gate dielectric layer 107 may include silicon and oxygen, silicon and nitrogen, yttrium and oxygen, silicon, oxygen, and nitrogen, aluminum and oxygen, hafnium and oxygen, tantalum and oxygen, or titanium and oxygen.
  • the gate dielectric layer 107 may include silicon oxide (SiCh), silicon nitride (SiN x ), yttrium oxide (Y2O3), silicon oxynitride (SiCXNy), aluminum oxide (AI2O3), hafnium(IV) oxide (HfCh), tantalum oxide (T ⁇ Qs), titanium dioxide (TiCh), or other materials.
  • the device body 109 may include a material such as: indium doped zinc oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low- temperature poly crystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium- doped zinc oxide (YZO), polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, indium oxide, tin oxide, zinc oxide, gallium oxide, indium gallium zinc oxide (IGZO), copper oxide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, indium antimonide, graphene, graphyne, borophene, germanene, silicene, S12BN, stanene, phosphoren
  • the passivation layer 115 may include oxide or nitride of silicon (Si), germanium (Ge), aluminum (Al), gallium (Ga), zirconium (Zr), yttrium (Y), hafnium (Hf), vanadium (V), magnesium (Mg), calcium (Ca), barium (Ba), strontium (Sr), antimony (Sb), or tantalum (Ta).
  • FIG. 2 schematically illustrates a diagram of two TFTs, e.g., a TFT 210, and a TFT 220, having a source electrode and a drain electrode aligned to an edge of a rectangular area of a device body, e.g., a device body 290, and a device body 280, in accordance with some embodiments.
  • the TFT 210 and the TFT 220 may be similar to the TFT 100 as shown in Figure 1.
  • the TFT 210 may include a substrate 201, an ILD layer 203 above the substrate 201, a gate electrode 205 above the ILD layer 203 and the substrate 201, and an ILD layer 215 above the gate electrode 205.
  • a gate dielectric layer 207 may be above the gate electrode 205.
  • the device body 290 may be above the gate electrode 205, and further above the gate dielectric layer 207.
  • the device body 290 may include a source area 291, a drain area 293, and a channel area 295 between the source area 291 and the drain area 293.
  • the device body 290 may be of a rectangular shape separated from other devices by an isolation area 221 and an isolation area 223.
  • a source electrode 211 may be above the source area 291 and aligned to an edge 292 of the device body 290, and the drain electrode 213 may be above the drain area 293 and aligned to an edge 294 of the device body 290.
  • a passivation layer 215 may be above the channel area 295 and between the source electrode 211 and the drain electrode 213.
  • the isolation area 221 may be through the gate dielectric layer 207, next to the edge 292 of the device body 290, and next to an edge of the source electrode 211.
  • the isolation area 223 may be through the gate dielectric layer 207, next to the edge 294 of the device body 290, and next to an edge of the drain electrode 213.
  • the TFT 220 may include a gate electrode 255 above the ILD layer 203 and the substrate 201.
  • a gate dielectric layer 257 may be above the gate electrode 255.
  • the device body 280 may be above the gate electrode 255, and further above the gate dielectric layer 257.
  • the device body 280 may include a source area 281, a drain area 283, and a channel area 285 between the source area 281 and the drain area 283.
  • the device body 280 may be of a rectangular shape separated from other devices by the isolation area 223 and an isolation area 227.
  • a source electrode 231 may be above the source area 281 and aligned to an edge 282 of the device body 280, and a drain electrode 233 may be above the drain area 283 and aligned to an edge 284 of the device body 280.
  • a passivation layer 225 may be above the channel area 285 and between the source electrode 231 and the drain electrode 233.
  • the isolation area 223 may be through the gate dielectric layer 257, next to the edge 282 of the device body 280, and next to an edge of the source electrode 231.
  • the isolation area 223 may include a first material, and a second material to form an isolation area 225.
  • the isolation area 227 may be through the gate dielectric layer 257, next to the edge 284 of the device body 280, and next to an edge of the drain electrode 233.
  • Figure 3 illustrates a process 300 for forming a TFT having a source electrode and a drain electrode self-aligned with respect to a channel area of a device body of the TFT and aligned to an edge of a rectangular area of the device body, in accordance with some embodiments.
  • Figures 4-15 illustrate a process for forming a TFT having a source electrode and a drain electrode self- aligned with respect to a channel area of a device body of the TFT and aligned to an edge of a rectangular area of the device body, in accordance with some embodiments.
  • the processor 300 may be used to fabricate a TFT similar to the TFT 100 in Figure 1, or the TFT 210 and the TFT 220 in Figure 2.
  • Figures 4-15 may illustrate the details of the process 300 shown in Figure 3.
  • the process 300 may include forming a gate electrode above a substrate.
  • the process 300 may include forming a device body layer above the gate electrode.
  • the process 300 may include forming a passivation layer above the device body layer.
  • the process 300 may include forming an etching accumulation layer above the passivation layer.
  • the process 300 may include forming one or more hardmask layers above the etching accumulation layer.
  • the process 300 may include forming a gate electrode 405 above a substrate 401.
  • the gate electrode 405 may be formed above an ILD layer 403.
  • the process 300 may further include forming a device body layer 409 above the gate electrode 405.
  • the device body layer 409 may be above a gate dielectric layer 407, which is above the gate electrode 405.
  • the process 300 may include forming a passivation layer 415 above the device body layer 409.
  • the process 300 may include forming an etching accumulation layer 421 above the passivation layer 415.
  • the process 300 may include forming one or more hardmask layers, e.g., a hardmask layer 423, and an antireflective layer 425, above the etching accumulation layer 421.
  • etching accumulation layer 421 there may be only one hardmask layer, or more than two hardmask layers, above the etching accumulation layer 421.
  • the etching accumulation layer 421 may protect the device body layer 409 from being exposed to processing chemicals and external environments, which also improves transistor performance.
  • the process 300 may include forming a backbone on the one or more hardmask layers.
  • the process 300 may include forming a first spacer and a second spacer around the backbone.
  • the process 300 may include forming a backbone 431 on the hardmask layer 423 and the antireflective layer 425, and forming a first spacer 433 and a second spacer 435 around the backbone 431.
  • a channel area may be patterned later based on the backbone 431, under a shadow of the backbone 431.
  • Spaces for a source electrode and a drain electrode may be defined by the first spacer 433 and the second spacer 435 around the backbone 431 on the hardmask layer 423 and the antireflective layer 425.
  • a source electrode and a drain electrode may be made of equal length, and not overlapping with the channel area under the shadow of the backbone 431. Because the source electrode and the drain electrode are self-aligned and equal in size, the TFT may have a smaller size overall.
  • the process 300 may form a backbone 441 on the hardmask layer 423 and the antireflective layer 425, and forming a first spacer 443 and a second spacer 445 around the backbone 441.
  • the first spacer 433, the second spacer 435, the first spacer 443, and the second spacer 445 may be separated from each other and from other part of the hardmask layer 423 and the antireflective layer 425 by an opening 451, an opening 453, and an opening 455.
  • the process 300 may include forming openings in the etching accumulation layer in a first direction, by following a shadow of the backbone, the first spacer, and the second spacer.
  • the process 300 may include forming openings, e.g., an opening 452, an opening 454, and an opening 456, in the etching accumulation layer 421 in a first direction, by following a shadow of the backbone 431, the first spacer 433, and the second spacer 435, and a shadow of the backbone 441, the first spacer 443, and the second spacer 445.
  • first spacer 433, and the second spacer 435, the first spacer 443, and the second spacer 445 may be removed after the formation of the opening 452, the opening 454, and the opening 456. Additionally and alternatively, the antireflective layer 425 may be removed as well.
  • the process 300 may include forming openings in the etching accumulation layer in a second direction orthogonal to the first direction, wherein the openings in the etching accumulation layer in the first direction and the openings in the etching accumulation layer in the second direction form a rectangular area in the etching accumulation layer.
  • the process 300 may include forming an opening 461, an opening 463, and an opening 465, in the etching accumulation layer 421 in a second direction orthogonal to the first direction, following the shadow of the backbone 431, or the shadow 441.
  • the openings in the etching accumulation layer 421 in the first direction and the openings in the etching accumulation layer 421 in the second direction form a rectangular area in the etching accumulation layer 421.
  • the opening 452, the opening 454, and the opening 456, in the etching accumulation layer 421 in a first direction, and the opening 461, the opening 463, and the opening 465, in the etching accumulation layer 421 in a second direction orthogonal to the first direction, may form rectangular areas in the etching accumulation layer 421.
  • the process 300 may include extending the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer into the passivation layer and the device body layer to form a rectangular area in the passivation layer and the device body layer.
  • the process 300 may include extending the opening 452, the opening 454, and the opening 456, the opening 461, the opening 463, and the opening 465, in the etching accumulation layer 421 into the passivation layer 415 and the device body layer 409 to form a rectangular area in the passivation layer and the device body layer.
  • the process 300 may include extending the opening 452, the opening 454, and the opening 456, the opening 461, the opening 463, and the opening 465, into the gate dielectric layer 407 as well.
  • the process 300 may include forming isolation areas around the rectangular area in the passivation layer and the device body layer, and in the etching accumulation layer by filling one or more isolation materials into the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer and extended into the passivation layer and the device body layer.
  • the process 300 may include forming isolation areas, e.g., an isolation area 471, an isolation area 473, an isolation area 475, an isolation area 472, an isolation area 474, an isolation area 476, around the rectangular area in the passivation layer 415 and the device body layer 409, and in the etching accumulation layer 421 by filling one or more isolation materials into the openings, e.g., the opening 452, the opening 454, and the opening 456, the opening 461, the opening 463, and the opening 465, in the etching accumulation layer 421 surrounding the rectangular area in the etching accumulation layer 421 and extended into the passivation layer 415, the device body layer 409, and further into the gate dielectric layer 407 as well.
  • the isolation area 471, the isolation area 473, the isolation area 475, the isolation area 472, the isolation area 474, and the isolation area 476 may include one or more isolation materials.
  • the process 300 may include forming openings in the rectangular area in the etching accumulation layer and the passivation layer not covered by the backbone of the one or more hardmask layer, wherein the openings in the rectangular area are above the device body layer and adjacent to the isolation areas.
  • the process 300 may include forming an opening 481, an opening 483, an opening 485, and an opening 487.
  • the opening 481 and the opening 483 may be formed in the etching accumulation layer 421 and the passivation layer 415 not covered by the backbone 431 of the hardmask layer 423.
  • the opening 481 may be above the device body layer 409 and adjacent to the isolation area 471.
  • the opening 483 may be above the device body layer 409 and adjacent to the isolation area 473.
  • the opening 485 and the opening 487 may be formed in the etching accumulation layer 421 and the passivation layer 415 not covered by the backbone 441 of the hardmask layer 423.
  • the opening 485 may be above the device body layer 409 and adjacent to the isolation area 473.
  • the opening 487 may be above the device body layer 409 and adjacent to the isolation area 475.
  • the process 300 may include forming a source electrode and a drain electrode above the device body layer by filling the openings in the rectangular area with conductive materials, wherein the source electrode and the drain electrode are aligned to an edge of the rectangular area in the device body layer.
  • the process 300 may include forming a source electrode 411 and a drain electrode 413 above the device body layer 409 by filling the opening 481 and the opening 483 in the rectangular area with conductive materials, wherein the source electrode 411 and the drain electrode 413 are aligned to an edge of the rectangular area in the device body layer 409.
  • the process 300 may include forming a source electrode 412 and a drain electrode 414 above the device body layer 409 by filling the opening 485 and the opening 487 in the rectangular area with conductive materials, wherein the source electrode 412 and the drain electrode 414 are aligned to an edge of the rectangular area in the device body layer 409.
  • the process 300 may include removing the one or more hardmask layers and the etching accumulation layer above the passivation layer.
  • the process 300 may include removing the hardmask layers 423 and the etching accumulation layer 421 above the passivation layer 415.
  • the process 300 may include polishing a surface of the source electrode, the drain electrode, the isolation area, to be coplanar with the passivation layer.
  • the process 300 may include polishing a surface of the source electrode 411, a surface of the drain electrode 413, a surface of the isolation area 471, and a surface of the isolation area 473, to be coplanar with the passivation layer 415.
  • the process 300 may include polishing a surface of the source electrode 412, a surface of the drain electrode 413, a surface of the isolation area 471, and a surface of the isolation area 473, to be coplanar with the passivation layer 415.
  • Figure 16 illustrates another process 1600 for forming a TFT having a source electrode and a drain electrode self-aligned with respect to a channel area of a device body of the TFT and aligned to an edge of a rectangular area of the device body, in accordance with some embodiments.
  • the process 1600 may be used to fabricate a TFT similar to the TFT 100 in Figure 1, the TFT 210, or the TFT 220 in Figure 2.
  • the process 1600 may be used to make a same TFT made by the process 300, as demonstrated by Figures 4-15.
  • the process 1600 may include forming a rectangular area in an etching accumulation layer, surrounded by openings in the etching accumulation layer in a first direction following a shadow of a backbone, a first spacer, and a second spacer on one or more hardmask layers above the etching accumulation layer, and openings in the etching accumulation layer in a second direction orthogonal to the first direction, wherein the first spacer and the second spacer are around the backbone.
  • the process 1600 may include forming a rectangular area in the etching accumulation layer 421, surrounded by openings in the etching accumulation layer 421 in a first direction, e.g., the opening 452, and the opening 454, following a shadow of the backbone 431, the first spacer 433, and the second spacer 435 on the antireflective layer 425 and the hardmask layer 423 above the etching accumulation layer 421, and the opening 461 and the opening 463 in the etching accumulation layer 421 in a second direction orthogonal to the first direction.
  • a first direction e.g., the opening 452, and the opening 454
  • the process 1600 may include extending the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer into a passivation layer below the etching accumulation layer, and a device body layer below the passivation layer to form a rectangular area in the passivation layer and the device body layer.
  • the process 1600 may include extending the opening 452, the opening 454, the opening 461, and the opening 463 in the etching accumulation layer 421 surrounding the rectangular area in the etching accumulation layer 421 into the passivation layer 415 below the etching accumulation layer 421, and the device body layer 409 below the passivation layer 415 to form a rectangular area in the passivation layer 415 and the device body layer 409.
  • the process 1600 may include forming isolation areas around the rectangular area in the passivation layer and the device body layer, and in the etching accumulation layer, by filling one or more isolation materials into the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer and extended into the passivation layer and the device body layer.
  • the process 1600 may include forming the isolation area 471, the isolation area 473, the isolation area 472, and the isolation area 474, around the rectangular area in the passivation layer 415 and the device body layer 409, and in the etching accumulation layer, by filling one or more isolation materials into the openings, e.g., the opening 452, the opening 454, the opening 461, and the opening 463, in the etching accumulation layer 421 surrounding the rectangular area in the etching accumulation layer 421 and extended into the passivation layer 415 and the device body layer 409.
  • the openings e.g., the opening 452, the opening 454, the opening 461, and the opening 463
  • more operations may be performed to form the source electrode 411 and the drain electrode 413 above the device body layer 409, and to remove the hardmask layers 423 and the etching accumulation layer 421 above the passivation layer 415, as shown in Figures 13-15.
  • FIG 17 schematically illustrates a diagram of a TFT 1710 having a source electrode 1711 and a drain electrode 1713 aligned to an edge of a rectangular area of a device body 1709 and formed in back-end-of-line (BEOL) on a substrate 1751, in accordance with some embodiments.
  • the TFT 1710 may be an example of the TFT 100 in Figure 1.
  • Various layers in the TFT 1710 may be similar to corresponding layers in the TFT 100 in Figure 1.
  • the TFT 1710 may be formed on the substrate 1751.
  • the TFT 1710 may include a gate electrode 1705 above an ILD layer 1753 and the substrate 1751.
  • a gate dielectric layer 1707 may be above the gate electrode 1705.
  • the device body 1709 may be above the gate electrode 1705, and further above the gate dielectric layer 1707.
  • the device body 1709 may include a source area 1791, a drain area 1793, and a channel area 1795 between the source area 1791 and the drain area 1793.
  • the device body 1709 may be of a rectangular shape separated from other devices by an isolation area 1721 and an isolation area 1723.
  • the source electrode 1711 may be above the source area 1791 and aligned to an edge of the device body 1709
  • the drain electrode 1713 may be above the drain area 1793 and aligned to an edge of the device body 1709.
  • a passivation layer 1715 may be above the channel area 1795 and between the source electrode 1711 and the drain electrode 1713.
  • the isolation area 1721 may be through the gate dielectric layer 1707, next to the edge of the device body 1709, and next to an edge of the source electrode 1711.
  • the isolation area 1723 may be through the gate dielectric layer 1707, next to the edge of the device body 1709, and next to an edge of the drain electrode 1713.
  • the TFT 1710 may be formed at the BEOL 1740.
  • the BEOL 1740 may further include a dielectric layer 1760, where one or more vias, e.g., a via 1768, may be connected to one or more interconnect, e.g., an interconnect 1766, and an interconnect 1762 within the dielectric layer 1760.
  • the interconnect 1766 and the interconnect 1762 may be of different metal layers at the BEOL 1740.
  • the BEOL 1740 may be formed on the front-end-of-line (FEOL) 1730.
  • the FEOL 1730 may include the substrate 1751.
  • the FEOL 1730 may include other devices, e.g., a transistor 1764.
  • the transistor 1764 may be a FEOL transistor, including a source 1761, a drain 1763, and a gate 1765, with a channel 1767 between the source
  • the transistor 1764 may be coupled to interconnects, e.g., the interconnect 1762, through a via 1769.
  • FIG 18 illustrates an interposer 1800 that includes one or more embodiments of the disclosure.
  • the interposer 1800 is an intervening substrate used to bridge a first substrate 1802 to a second substrate 1804.
  • the first substrate 1802 may be, for instance, a substrate support for a TFT, e.g., the TFT 100 shown in Figure 1 or the TFT 1710 shown in Figure 17.
  • the second substrate 1804 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 1800 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 1800 may couple an integrated circuit die to a ball grid array (BGA) 1806 that can subsequently be coupled to the second substrate 1804.
  • BGA ball grid array
  • first and second substrates 1802/1804 are attached to opposing sides of the interposer 1800. In other embodiments, the first and second substrates 1802/1804 are attached to the same side of the interposer 1800. And in further embodiments, three or more substrates are interconnected by way of the interposer 1800.
  • the interposer 1800 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide.
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer may include metal interconnects 1808 and vias 1810, including but not limited to through-silicon vias (TSVs) 1812.
  • the interposer 1800 may further include embedded devices 1814, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1800.
  • RF radio-frequency
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 1800.
  • FIG 19 illustrates a computing device 1900 in accordance with one embodiment of the disclosure.
  • the computing device 1900 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as a SoC used for mobile devices.
  • SoC system-on-a-chip
  • the components in the computing device 1900 include, but are not limited to, an integrated circuit die 1902 and at least one communications logic unit 1908.
  • the communications logic unit 1908 is fabricated within the integrated circuit die 1902 while in other implementations the communications logic unit 1908 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 1902.
  • the integrated circuit die 1902 may include a processor 1904 as well as on-die memory 1906, often used as cache memory, which can be provided by technologies such as embedded DRAM (eDRAM), or SRAM.
  • the on-die memory 1906 may include the TFT 100 shown in Figure 1, the TFT 1710 shown in Figure 17, or a TFT formed according to the process 300 shown in Figure 3, or the process 1600 shown in Figure 16.
  • the computing device 1900 may include a display or a touchscreen display 1924, and a touchscreen display controller 1926.
  • a display or the touchscreen display 1924 may include a FPD, an AMOLED display, a TFT LCD, a micro light-emitting diode (pLED) display, or others.
  • the touchscreen display 1924 may include the TFT 100 shown in Figure 1, the TFT 1710 shown in Figure 17, or a TFT formed according to the process 300 shown in Figure 3, or the process 1600 shown in Figure 16.
  • Computing device 1900 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within a SoC die. These other components include, but are not limited to, volatile memory 1910 (e.g., dynamic random access memory (DRAM), non-volatile memory 1912 (e.g., ROM or flash memory), a graphics processing unit 1914 (GPU), a digital signal processor (DSP) 1916, a crypto processor 1942 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 1920, at least one antenna 1922 (in some implementations two or more antenna may be used), a battery 1930 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1928, a compass, a motion coprocessor or sensors 1932 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 1934, a camera 1936, user input devices 1938 (such as a
  • the computing device 1900 may incorporate further transmission, telecommunication, or radio functionality not already described herein.
  • the computing device 1900 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.
  • the computing device 1900 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.
  • the communications logic unit 1908 enables wireless communications for the transfer of data to and from the computing device 1900.
  • the term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communications logic unit 1908 may implement any of a number of wireless standards or protocols, including but not limited to Wi Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 1900 may include a plurality of communications logic units 1908.
  • a first communications logic unit 1908 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 1908 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1904 of the computing device 1900 includes one or more devices, such as transistors.
  • the term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communications logic unit 1908 may also include one or more devices, such as transistors.
  • another component housed within the computing device 1900 may contain one or more devices, such as DRAM, that are formed in accordance with implementations of the current disclosure, e.g., the TFT 100 shown in Figure 1, the TFT 1710 shown in Figure 17, or a TFT formed according to the process 300 shown in Figure 3, or the process 1600 shown in Figure 16.
  • DRAM dynamic random access memory
  • the computing device 1900 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 1900 may be any other electronic device that processes data.
  • Example 1 may include a method for forming a semiconductor device, the method comprising: forming a rectangular area in an etching accumulation layer, surrounded by openings in the etching accumulation layer in a first direction following a shadow of a backbone, a first spacer, and a second spacer on one or more hardmask layers above the etching
  • the etching accumulation layer and openings in the etching accumulation layer in a second direction orthogonal to the first direction, wherein the first spacer and the second spacer are around the backbone; extending the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer into a passivation layer below the etching accumulation layer, and a device body layer below the passivation layer to form a rectangular area in the passivation layer and the device body layer; and forming isolation areas around the rectangular area in the passivation layer and the device body layer, and in the etching accumulation layer, by filling one or more isolation materials into the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer and extended into the passivation layer and the device body layer.
  • Example 2 may include the method of example 1 and/or some other examples herein, further comprising: forming openings in the rectangular area in the etching accumulation layer and the passivation layer not covered by the backbone of the one or more hardmask layer, wherein the openings in the rectangular area are above the device body layer and adjacent to the isolation areas; and forming a source electrode and a drain electrode above the device body layer by filling the openings in the rectangular area with conductive materials, wherein the source electrode and the drain electrode are aligned to an edge of the rectangular area in the device body layer.
  • Example 3 may include the method of example 2 and/or some other examples herein, further comprising: removing the one or more hardmask layers and the etching accumulation layer above the passivation layer; and polishing a surface of the source electrode, the drain electrode, the isolation area, to be coplanar with the passivation layer.
  • Example 4 may include the method of example 1 and/or some other examples herein, further comprising: forming a gate electrode; forming the device body layer above the gate electrode; forming the passivation layer above the device body layer; forming the etching accumulation layer above the passivation layer; forming the one or more hardmask layers above the etching accumulation layer, before forming the rectangular area in the etching accumulation layer.
  • Example 5 may include the method of example 4 and/or some other examples herein, wherein forming the rectangular area in the etching accumulation layer includes: forming the backbone on the one or more hardmask layers; forming the first spacer and the second spacer around the backbone; forming the openings in the etching accumulation layer in the first direction, by following the shadow of the backbone, the first spacer, and the second spacer; and forming the openings in the etching accumulation layer in the second direction orthogonal to the first direction.
  • Example 6 may include the method of any one of examples 1-2 and/or some other examples herein, wherein the extending the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer further includes extending the openings into the passivation layer, the device body layer, and a gate dielectric layer below the device body layer to form the rectangular area in the passivation layer, the device body layer, and the gate dielectric layer; and the forming the isolation areas around the rectangular area further includes filling isolation materials into the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer and extended into the passivation layer, the device body layer, and the gate dielectric layer.
  • Example 7 may include the method of any one of examples 1-2 and/or some other examples herein, wherein the isolation areas includes a first isolation layer with a first isolation material, and a second isolation layer with a second isolation material and around the first isolation layer.
  • Example 8 may include the method of any one of examples 1-2 and/or some other examples herein, wherein the one or more isolation materials include a selected one of silicon and dioxide, silicon and nitride, or a dielectric material.
  • Example 9 may include the method of any one of examples 1-2 and/or some other examples herein, wherein the device body layer includes indium doped zinc oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature poly crystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, indium oxide, tin oxide, zinc oxide, gallium oxide, indium gallium zinc oxide (IGZO), copper oxide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, indium antimonide, graphene, graphyne, borophene, germanene, silic
  • Example 10 may include the method of any one of examples 1-2 and/or some other examples herein, wherein the passivation layer includes oxide or nitride of silicon (Si), germanium (Ge), aluminum (Al), gallium (Ga), zirconium (Zr), yttrium (Y), hafnium (Elf), vanadium (V), magnesium (Mg), calcium (Ca), barium (Ba), strontium (Sr), antimony (Sb), or tantalum (Ta).
  • the passivation layer includes oxide or nitride of silicon (Si), germanium (Ge), aluminum (Al), gallium (Ga), zirconium (Zr), yttrium (Y), hafnium (Elf), vanadium (V), magnesium (Mg), calcium (Ca), barium (Ba), strontium (Sr), antimony (Sb), or tantalum (Ta).
  • Example 11 may include the method of any one of examples 1-2 and/or some other examples herein, wherein the one or more hardmask layers includes an antireflective coating material.
  • Example 12 may include the method of any one of examples 1-2 and/or some other examples herein, wherein the etching accumulation layer includes one of SiN, SiON, SiC,
  • Example 13 may include a semiconductor device including a thin film transistor (TFT), wherein the TFT includes: a gate electrode above a substrate; a gate dielectric layer above the gate electrode; a device body above the gate dielectric layer, wherein the device body includes a source area, a drain area, and a channel area between the source area and the drain area, and the device body is of a rectangular shape separated from other devices by isolation areas; a source electrode above the source area and aligned to an edge of the device body; a drain electrode above the drain area and aligned to an edge of the device body; and a passivation layer above the channel area and between the source electrode and the drain electrode.
  • TFT thin film transistor
  • Example 14 may include the semiconductor device of example 13 and/or some other examples herein, further comprising: a first isolation area through the gate dielectric layer, next to a first edge of the device body, and next to an edge of the source electrode; and a second isolation area through the gate dielectric layer, next to a second edge of the device body, and next to an edge of the drain electrode.
  • Example 15 may include the semiconductor device of any one of examples 13-14 and/or some other examples herein, wherein the TFT is a first TFT, and the semiconductor device further includes a second TFT, the second TFT includes: a second gate dielectric layer above a second gate electrode; a second device body above the second gate dielectric layer, wherein the second device body is of a rectangular shape separated from the first TFT by the first isolation area; a contact above the second device body and aligned to an edge of the second device body, wherein the contact is a source electrode or a drain electrode of the second TFT, and wherein the first isolation area is through the second gate dielectric layer, next to an edge of the second device body, and next to an edge of the contact.
  • the TFT is a first TFT
  • the semiconductor device further includes a second TFT
  • the second TFT includes: a second gate dielectric layer above a second gate electrode; a second device body above the second gate dielectric layer, wherein the second device body is of a rectangular shape separated from the first
  • Example 16 may include the semiconductor device of any one of examples 13-14 and/or some other examples herein, wherein the device body includes indium doped zinc oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature poly crystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, indium oxide, tin oxide, zinc oxide, gallium oxide, indium gallium zinc oxide (IGZO), copper oxide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, indium antimonide, graphene, graphyne, borophene, germanene, silic
  • Example 17 may include the semiconductor device of any one of examples 13-14 and/or some other examples herein, wherein the passivation layer includes oxide or nitride of silicon (Si), germanium (Ge), aluminum (Al), gallium (Ga), zirconium (Zr), yttrium (Y), hafnium (Hf), vanadium (V), magnesium (Mg), calcium (Ca), barium (Ba), strontium (Sr), antimony (Sb), or tantalum (Ta).
  • the passivation layer includes oxide or nitride of silicon (Si), germanium (Ge), aluminum (Al), gallium (Ga), zirconium (Zr), yttrium (Y), hafnium (Hf), vanadium (V), magnesium (Mg), calcium (Ca), barium (Ba), strontium (Sr), antimony (Sb), or tantalum (Ta).
  • Example 18 may include the semiconductor device of any one of examples 13-14 and/or some other examples herein, wherein the source electrode or the drain electrode includes titanium (Ti), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAlN, HfAlN, or InAlO.
  • the source electrode or the drain electrode includes titanium (Ti), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAlN, HfAlN, or InAlO.
  • Example 19 may include a method for forming a semiconductor device, the method comprising: forming a gate electrode above a substrate; forming a device body layer above the gate electrode; forming a passivation layer above the device body layer; forming an etching accumulation layer above the passivation layer; forming one or more hardmask layers above the etching accumulation layer; forming a backbone on the one or more hardmask layers; forming a first spacer and a second spacer around the backbone; forming openings in the etching accumulation layer in a first direction, by following a shadow of the backbone, the first spacer, and the second spacer; forming openings in the etching accumulation layer in a second direction orthogonal to the first direction, wherein the openings in the etching accumulation layer in the first direction and the openings in the etching accumulation layer in the second direction form a rectangular area in the etching accumulation layer; extending the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer into the
  • Example 20 may include the method of example 19 and/or some other examples herein, further comprising: forming openings in the rectangular area in the etching accumulation layer and the passivation layer not covered by the backbone of the one or more hardmask layer, wherein the openings in the rectangular area are above the device body layer and adjacent to the isolation areas; and forming a source electrode and a drain electrode above the device body layer by filling the openings in the rectangular area with conductive materials, wherein the source electrode and the drain electrode are aligned to an edge of the rectangular area in the device body layer.
  • Example 21 may include the method of example 20 and/or some other examples herein, further comprising: removing the one or more hardmask layers and the etching accumulation layer above the passivation layer; and polishing a surface of the source electrode, the drain electrode, the isolation area, to be coplanar with the passivation layer.
  • Example 22 may include the method of any one of examples 19-20 and/or some other examples herein, wherein the one or more isolation materials include a selected one of silicon and dioxide, silicon and nitride, or a dielectric material.
  • Example 23 may include the method of any one of examples 19-20 and/or some other examples herein, wherein the device body layer includes indium doped zinc oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature poly crystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, indium oxide, tin oxide, zinc oxide, gallium oxide, indium gallium zinc oxide (IGZO), copper oxide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, indium antimonide, graphene, graphyne, borophene, germanene, silic
  • Example 24 may include the method of any one of examples 19-20 and/or some other examples herein, wherein the passivation layer includes oxide or nitride of silicon (Si), germanium (Ge), aluminum (Al), gallium (Ga), zirconium (Zr), yttrium (Y), hafnium (Elf), vanadium (V), magnesium (Mg), calcium (Ca), barium (Ba), strontium (Sr), antimony (Sb), or tantalum (Ta).
  • the passivation layer includes oxide or nitride of silicon (Si), germanium (Ge), aluminum (Al), gallium (Ga), zirconium (Zr), yttrium (Y), hafnium (Elf), vanadium (V), magnesium (Mg), calcium (Ca), barium (Ba), strontium (Sr), antimony (Sb), or tantalum (Ta).
  • Example 25 may include the method of any one of examples 19-20 and/or some other examples herein, wherein the etching accumulation layer includes one of SiN, SiON, SiC, SiCN, SiOCN, SiOC, SiBN, SiBCN, or combinations thereof.
  • Example 26 may include one or more computer-readable media having instructions for forming a semiconductor device, upon execution of the instructions by one or more processors, to perform the method of any one of examples 1-12.
  • Example 27 may include an apparatus for forming a semiconductor device, the apparatus comprising: means for forming a rectangular area in an etching accumulation layer, surrounded by openings in the etching accumulation layer in a first direction following a shadow of a backbone, a first spacer, and a second spacer on one or more hardmask layers above the etching accumulation layer, and openings in the etching accumulation layer in a second direction orthogonal to the first direction, wherein the first spacer and the second spacer are around the backbone; means for extending the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer into a passivation layer below the etching accumulation layer, and a device body layer below the passivation layer to form a rectangular area in the passivation layer and the device body layer; and means for forming isolation areas
  • Example 28 may include the apparatus of example 27 and/or some other examples herein, further comprising: means for forming openings in the rectangular area in the etching accumulation layer and the passivation layer not covered by the backbone of the one or more hardmask layer, wherein the openings in the rectangular area are above the device body layer and adjacent to the isolation areas; and means for forming a source electrode and a drain electrode above the device body layer by filling the openings in the rectangular area with conductive materials, wherein the source electrode and the drain electrode are aligned to an edge of the rectangular area in the device body layer.
  • Example 29 may include the apparatus of example 28 and/or some other examples herein, further comprising: means for removing the one or more hardmask layers and the etching accumulation layer above the passivation layer; and means for polishing a surface of the source electrode, the drain electrode, the isolation area, to be coplanar with the passivation layer.
  • Example 30 may include the apparatus of example 27 and/or some other examples herein, further comprising: means for forming a gate electrode; means for forming the device body layer above the gate electrode; means for forming the passivation layer above the device body layer; means for forming the etching accumulation layer above the passivation layer; means for forming the one or more hardmask layers above the etching accumulation layer, before forming the rectangular area in the etching accumulation layer.
  • Example 31 may include the apparatus of example 30 and/or some other examples herein, wherein the means for forming the rectangular area in the etching accumulation layer includes: means for forming the backbone on the one or more hardmask layers; means for forming the first spacer and the second spacer around the backbone; means for forming the openings in the etching accumulation layer in the first direction, by following the shadow of the backbone, the first spacer, and the second spacer; and means for forming the openings in the etching accumulation layer in the second direction orthogonal to the first direction.
  • the means for forming the rectangular area in the etching accumulation layer includes: means for forming the backbone on the one or more hardmask layers; means for forming the first spacer and the second spacer around the backbone; means for forming the openings in the etching accumulation layer in the first direction, by following the shadow of the backbone, the first spacer, and the second spacer; and means for forming the openings in the etching accumulation layer in the second direction orthogonal to
  • Example 32 may include the apparatus of any one of examples 27-28 and/or some other examples herein, wherein the means for extending the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer further includes means for extending the openings into the passivation layer, the device body layer, and a gate dielectric layer below the device body layer to form the rectangular area in the passivation layer, the device body layer, and the gate dielectric layer; and the means for forming the isolation areas around the rectangular area further includes means for filling isolation materials into the openings in the etching accumulation layer surrounding the rectangular area in the etching accumulation layer and extended into the passivation layer, the device body layer, and the gate dielectric layer.
  • Example 33 may include the apparatus of any one of examples 27-28 and/or some other examples herein, wherein the isolation areas includes a first isolation layer with a first isolation material, and a second isolation layer with a second isolation material and around the first isolation layer.
  • Example 34 may include the apparatus of any one of examples 27-28 and/or some other examples herein, materials include a selected one of silicon and dioxide, silicon and nitride, or a dielectric material.
  • Example 35 may include the apparatus of any one of examples 27-28 and/or some other examples herein, wherein the device body layer includes indium doped zinc oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature poly crystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, indium oxide, tin oxide, zinc oxide, gallium oxide, indium gallium zinc oxide (IGZO), copper oxide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, indium antimonide, graphene, graphyne, borophene, germanene, si
  • Example 36 may include the apparatus of any one of examples 27-28 and/or some other examples herein, wherein the passivation layer includes oxide or nitride of silicon (Si), germanium (Ge), aluminum (Al), gallium (Ga), zirconium (Zr), yttrium (Y), hafnium (Hf), vanadium (V), magnesium (Mg), calcium (Ca), barium (Ba), strontium (Sr), antimony (Sb), or tantalum (Ta).
  • the passivation layer includes oxide or nitride of silicon (Si), germanium (Ge), aluminum (Al), gallium (Ga), zirconium (Zr), yttrium (Y), hafnium (Hf), vanadium (V), magnesium (Mg), calcium (Ca), barium (Ba), strontium (Sr), antimony (Sb), or tantalum (Ta).
  • Example 37 may include the apparatus of any one of examples 27-28 and/or some other examples herein, wherein the one or more hardmask layers includes an antireflective coating material.
  • Example 38 may include the apparatus of any one of examples 27-28 and/or some other examples herein, wherein the etching accumulation layer includes one of SiN, SiON, SiC,
  • Various embodiments may include any suitable combination of the above-described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the“and” may be“and/or”). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above- described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.

Abstract

La présente invention concerne, selon certains modes de réalisation, des techniques destinées à un transistor en couches minces (TFT), qui peuvent comprendre une électrode de grille au-dessus d'un substrat, une couche diélectrique de grille au-dessus de l'électrode de grille, et un corps de dispositif au-dessus de la couche diélectrique de grille. Le corps de dispositif peut comprendre une zone source, une zone drain et une zone de canal entre la zone source et la zone drain. Le corps de dispositif peut présenter une forme rectangulaire séparée d'autres dispositifs par des zones d'isolation. Une électrode source peut être située au-dessus de la zone source, alignée sur un bord du corps de dispositif, en même temps qu'une électrode drain peut être située au-dessus de la zone drain, et alignée sur un bord du corps de dispositif. L'invention peut également comprendre d'autres modes de réalisation compris dans la description et/ou dans les revendications.
PCT/US2017/068575 2017-12-27 2017-12-27 Électrode source et électrode drain auto-alignées destinées à des transistors en couches minces WO2019132894A1 (fr)

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