WO2018045613A1 - 薄膜晶体管阵列基板及其制造方法 - Google Patents

薄膜晶体管阵列基板及其制造方法 Download PDF

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WO2018045613A1
WO2018045613A1 PCT/CN2016/101611 CN2016101611W WO2018045613A1 WO 2018045613 A1 WO2018045613 A1 WO 2018045613A1 CN 2016101611 W CN2016101611 W CN 2016101611W WO 2018045613 A1 WO2018045613 A1 WO 2018045613A1
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layer
thin film
film transistor
gate electrode
substrate
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French (fr)
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谢露露
熊彬
韩云
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/211—Gated diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of flexible or folded printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/051—Manufacture or treatment of Schottky diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 

Definitions

  • the invention belongs to the field of wafer fabrication and flat panel display technology. In particular, it relates to a thin film transistor array substrate and a method of fabricating the same.
  • the liquid crystal panel module includes a liquid crystal panel, a driver integrated circuit (DIC, Driver Integrated Circuit), and Flexible printed circuit board.
  • the FPCA functions to connect the mobile phone motherboard and the LCD panel module, and transmits the driving signal, image display data and power voltage of the AP (Application Processor) on the mobile phone motherboard to the DIC, and then the DIC displays the input signals and images. Through complex operations and digital conversion, various analog voltages are finally output to the liquid crystal panel, so that the liquid crystal panel can present different visual images to the user.
  • the FPCA serves as a bridge for connection and transmission, some passive electronic components such as resistors, capacitors, and Schottky diodes are placed according to the requirements of the DIC.
  • the circuit diagram is shown in Figure 2.
  • Schottky diodes are usually required to be fabricated in the FPCA, in order to prevent the latch-up effect between the AVEE (VSN, the operating voltage supplied by the system board to the IC) and the VGL (the voltage generated by the IC that controls the TFT being turned off) (Latch). Up).
  • VSN the operating voltage supplied by the system board to the IC
  • VGL the voltage generated by the IC that controls the TFT being turned off
  • the present invention provides a novel liquid crystal drive wiring structure, which replaces the Diode on the FPCA to make the FPCA thinner, and reduces the manufacturing cost of the FPCA.
  • a thin film transistor array substrate including a substrate and a substrate package is provided a display area and a non-display area, the non-display area surrounding the display area and including a Schottky diode, wherein the Schottky diode comprises: an anode layer and a cathode layer formed on the substrate; and a gate insulating layer formed on the substrate And covering the anode layer and the cathode layer; a first gate electrode formed on the gate insulating layer and laminated on the anode layer and the cathode; an interlayer insulating layer formed on the gate insulating layer and covering the first gate electrode, and including A contact hole for exposing the anode layer and the cathode layer; a first external voltage and a second external voltage are formed on the interlayer insulating layer, and are respectively connected to the anode layer and the cathode layer through the contact holes.
  • the Schottky diode comprises: an anode layer and a cathode layer formed on the
  • a display region includes a thin film transistor, wherein the thin film transistor includes: an active layer formed on a substrate; a second gate electrode insulated from the active layer; a source electrode and a drain electrode, and electricity Connect to the active layer.
  • the anode layer and the cathode layer are disposed on the same layer as the active layer.
  • the first gate electrode and the second gate electrode are disposed on the same layer.
  • the first external voltage and the second external voltage are disposed on the same layer as the source and drain electrodes.
  • the active layer includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the anode layer includes the same material as the source region and the drain region, and the cathode layer includes The same material as the channel region.
  • the thin film transistor array substrate further includes a pad located in a non-display area.
  • a method of manufacturing a thin film transistor array substrate comprising: forming an active layer of a thin film transistor in a display region of a substrate, and forming a Schottky in a non-display region of the substrate An anode layer and a cathode layer of the diode; a gate insulating layer is formed on the substrate to cover the active layer of the thin film transistor and the anode layer and the cathode layer of the Schottky diode;
  • a second gate electrode of the thin film transistor and a first gate electrode of the Schottky diode on the gate insulating layer Forming a second gate electrode of the thin film transistor and a first gate electrode of the Schottky diode on the gate insulating layer, the second gate electrode is stacked on the active layer, and the first gate electrode is stacked on the anode layer and the cathode;
  • An interlayer insulating layer is formed on the insulating layer to cover the first gate electrode and the second gate electrode; an active layer for exposing the thin film transistor and an anode layer of the Schottky diode are formed in the interlayer insulating layer and the gate insulating layer a contact hole of the cathode layer; a source electrode and a drain electrode of the thin film transistor and a first external voltage and a second external voltage of the Schottky diode formed on the interlayer insulating layer, the source electrode, the drain electrode, the first external voltage, and the second The external voltage is connected to the active layer,
  • the active layer includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the anode layer includes the same material as the source region and the drain region, and the cathode layer includes The same material as the channel region.
  • the forming of the first gate electrode and the second gate electrode includes simultaneously forming the first gate electrode and the second gate electrode using the same process.
  • the material cost and the cost of printing the diode can be saved, and the area of the FPCA is saved, the thickness of the FPCA is greatly reduced, and the liquid crystal module can be thinned, thereby Promote the slimming of the whole mobile phone.
  • the Schottky diode of the present invention is formed on the substrate together with the thin film transistor, and therefore, an additional process is not required, thereby simplifying the manufacturing process.
  • FIG. 1 is a schematic structural view of a liquid crystal module including a Schottky diode according to the prior art
  • Figure 2 shows a circuit diagram of a flexible printed circuit board according to the prior art
  • FIG. 3 is a schematic view showing a driving structure of a region where a Schottky diode of the prior art is located;
  • FIG. 4 is a schematic diagram showing a driving structure of a thin film transistor array substrate according to an exemplary embodiment of the present invention
  • 5 through 11 illustrate a flow chart of fabricating a thin film transistor array substrate in accordance with an exemplary embodiment of the present invention.
  • FIG. 4 is a schematic diagram showing a driving structure of a thin film transistor array substrate according to an exemplary embodiment of the present invention.
  • 5 through 11 illustrate a flow chart of fabricating a thin film transistor array substrate in accordance with an exemplary embodiment of the present invention.
  • a first semiconductor 210 and a second semiconductor 220 spaced apart from the first semiconductor 210 are formed on the substrate 100.
  • the first semiconductor 210 may be formed in the display region 101 of the substrate 100, and the second semiconductor 220 may be formed in the non-display region 102 of the substrate 100.
  • the substrate 100 may be formed of a transparent glass material containing SiO 2 as a main component, but is not limited thereto.
  • the first semiconductor 210 and the second semiconductor 220 are formed by a physical vapor deposition (PVD) method.
  • PVD physical vapor deposition
  • the materials of the first semiconductor 210 and the second semiconductor 220 may be the same.
  • a buffer layer (not shown) may be formed between the first semiconductor 210 and the second semiconductor 220 and the substrate, but the invention is not limited thereto.
  • the first semiconductor 210 and the second semiconductor 220 are doped to form a source region 211, a drain region 212 of the active layer of the thin film transistor, and between the source region 211 and the drain region 212.
  • the first semiconductor 210 and the second semiconductor 220 may be doped with the same impurities, so that the source region 211 and the drain region 212 of the active layer of the thin film transistor are the same as the anode layer 221 of the Schottky diode, and the channel region of the thin film transistor 213 is the same as the cathode layer 222 of the Schottky diode.
  • the step of doping the first semiconductor 210 and the second semiconductor 220 may be performed using the same process.
  • the Schottky diode can be simultaneously fabricated in the fabrication of the TFT, an additional process is not required, which simplifies the manufacturing process.
  • a gate insulating layer 300 is formed on the substrate 100 to cover the first semiconductor 210 and the second semiconductor 220.
  • a second gate electrode 310 of the thin film transistor and a first gate electrode 320 of the Schottky diode are formed on the gate insulating layer 300, and the second gate electrode 310 overlaps the channel region 213, first The gate electrode 320 overlaps a portion of the anode layer 221 and the cathode layer 222.
  • the second gate electrode 310 and the first gate electrode 320 may be formed by the same process.
  • an interlayer insulating layer 400 is formed on the gate insulating layer 300 to cover the second The gate electrode 310 and the first gate electrode 320.
  • contacts for exposing the source region 211 and the drain region 212 of the thin film transistor and the anode layer 221 and the cathode layer 222 of the Schottky diode are formed in the gate insulating layer 300 and the interlayer insulating layer 400. Hole H.
  • the source electrode 510 and the drain electrode 520 of the thin film transistor and the first external voltage (for example, VGL) 530 of the Schottky diode and the second external voltage are formed on the interlayer insulating layer 400 (for example, The AVEE) 540, and the source electrode 510, the drain electrode 520, the first external voltage 530, and the second external voltage 540 are connected to the source region 211, the drain region 212, the anode layer 221, and the cathode layer 222 through the contact holes H, respectively.
  • the process and the manufacturing cost can be simplified by simultaneously forming a Schottky diode in forming a thin film transistor (TFT).
  • TFT thin film transistor
  • the area of the FPCA can be saved, the thickness of the FPCA can be greatly reduced, and the thinning of the liquid crystal module can be realized, thereby promoting the slimming of the whole mobile phone.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Engineering & Computer Science (AREA)
  • Thin Film Transistor (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种薄膜晶体管阵列基板及其制造方法。薄膜晶体管阵列基板包括：基底（100），包括显示区域（101）和非显示区域（102），非显示区域围绕显示区域并且包括肖特基二极管，其中，肖特基二极管包括：阳极层（221）和阴极层（222），形成基底上；栅极绝缘层（300），形成在基底上并且覆盖阳极层和阴极层；第一栅电极（320），形成在栅极绝缘层上并且与阳极层和阴极层叠置；层间绝缘层（400），形成在栅极绝缘层上并且覆盖第一栅电极，并且包括用于暴露阳极层和阴极层的接触孔（H）；第一外接电压（530）和第二外接电压（540），形成在层间绝缘层上，并且分别通过接触孔连接到阳极层和阴极层。肖特基二极管与薄膜晶体管一同形成在基底上，因此，不需要额外增加工序，从而简化了制造工艺。

Description

薄膜晶体管阵列基板及其制造方法 技术领域
本发明属于晶圆制造和平板显示技术领域。具体地讲，涉及一种薄膜晶体管阵列基板及其制造方法。
背景技术
现有的面板制造业在面板出货的时候产品都是以模组的形式出货，如图1和3所示，液晶面板模组包括液晶面板、驱动集成电路(DIC,Driver Integrated Circuit)和柔性印刷电路板。其中，FPCA起到连接手机主板与液晶面板模组的作用，将手机主板上AP(Application Processor)的驱动信号、图像显示资料和电源电压传递到DIC，然后DIC将这些输入的信号和图像显示资料通过复杂运算和数位转换，最终输出各种模拟电压到液晶面板，从而使得液晶面板能够呈现给用户不同的视觉图像。FPCA作为桥梁起到连接传递的同时，还会根据DIC的需求放置一些被动电子元器件，例如电阻、电容、肖特基二极管等，电路图如图2所示。
目前在制造FPCA时通常需要放置肖特基二极管，其目的是防止AVEE(VSN,系统板提供给IC的工作电压)与VGL(IC产生的，控制TFT关闭的电压)之间闩锁效应(Latch Up)。但是随着技术的发展和产品性能需求的提高，手机越来越倾向于纤薄化，从而在FPC上放置Diode时，不仅占用了FPC上的空间使FPC的外形足够大，Diode的自身高度也影响了FPCA在手机模组里面安装时需求的空间，使得手机无法做到纤薄化。
发明内容
为了解决上述现有技术的不足，本发明提供一种新的液晶驱动走线架构，取代FPCA上的Diode使FPCA更加纤薄化，并且降低FPCA的制造成本的薄膜晶体管阵列基板及其制造方法。
根据本发明的一方面，提供一种薄膜晶体管阵列基板，包括基底，基底包 括显示区域和非显示区域，非显示区域围绕显示区域并且包括肖特基二极管，其中，所述肖特基二极管包括：阳极层和阴极层，形成基底上；栅极绝缘层，形成在基底上并且覆盖阳极层和阴极层；第一栅电极，形成在栅极绝缘层上并且与阳极层和阴极层叠置；层间绝缘层，形成在栅极绝缘层上并且覆盖第一栅电极，并且包括用于暴露阳极层和阴极层的接触孔；第一外接电压和第二外接电压，形成在层间绝缘层上，并且分别通过接触孔连接到阳极层和阴极层。
根据本发明的示例性实施例，显示区域包括薄膜晶体管，其中，所述薄膜晶体管包括：有源层，形成在基底上；第二栅电极，与有源层绝缘；源电极和漏电极，电连接到有源层。
根据本发明的示例性实施例，阳极层和阴极层与有源层设置在同一层上。
根据本发明的示例性实施例，第一栅电极与第二栅电极设置在同一层上。
根据本发明的示例性实施例，第一外接电压和第二外接电压与源电极和漏电极设置在同一层上。
根据本发明的示例性实施例，有源层包括源区、漏区和位于源区和漏区之间的沟道区，其中，阳极层包括与源区和漏区相同的材料，阴极层包括与沟道区相同的材料。
根据本发明的示例性实施例，所述薄膜晶体管阵列基板还包括焊盘，所述焊盘位于非显示区域中。
根据本发明的另一方面，提供一种制造薄膜晶体管阵列基板的方法，所述方法包括：在基底的显示区域中形成薄膜晶体管的有源层，并且在基底的非显示区域中形成肖特基二极管的阳极层和阴极层；在基底上形成栅极绝缘层以覆盖薄膜晶体管的有源层和肖特基二极管的阳极层和阴极层；
在栅极绝缘层上形成薄膜晶体管的第二栅电极和肖特基二极管的第一栅电极，第二栅电极与有源层叠置，第一栅电极与阳极层和阴极层叠置；在栅极绝缘层上形成层间绝缘层以覆盖第一栅电极和第二栅电极；在层间绝缘层和栅极绝缘层中形成用于暴露薄膜晶体管的有源层以及肖特基二极管的阳极层和阴极层的接触孔；在层间绝缘层上形成薄膜晶体管的源电极和漏电极以及肖特基二极管的第一外接电压和第二外接电压，源电极、漏电极、第一外接电压和第二外接电压分别通过接触孔连接到有源层、阳极层和阴极层。
根据本发明的示例性实施例，有源层包括源区、漏区和位于源区和漏区之间的沟道区，其中，阳极层包括与源区和漏区相同的材料，阴极层包括与沟道区相同的材料。
根据本发明的示例性实施例，形成第一栅电极和第二栅电极的步骤包括：使用同一工艺同时形成第一栅电极和第二栅电极。
根据本发明的薄膜晶体管阵列基板及其制造方法，能够节约购买二极管的物料成本和打件费用，而且还节约了FPCA的面积，大大降低了FPCA的厚度，能够实现液晶模组纤薄化，从而促进手机整机的纤薄化。此外，本发明的肖特基二极管与薄膜晶体管一同形成在基底上，因此，不需要额外增加工序，从而简化了制造工艺。
附图说明
图1示出了根据现有技术的包括肖特基二极管的液晶模组的结构示意图；
图2示出了根据现有技术的柔性印刷电路板的电路图；
图3示出了现有技术的肖特基二极管打件所处区域的驱动架构示意图；
图4示出了根据本发明的示例性实施例的薄膜晶体管阵列基板的驱动架构示意图；
图5至图11示出了根据本发明的示例性实施例的制造薄膜晶体管阵列基板的流程示意图。
具体实施方式
下面将参照附图详细地描述本发明的示例性实施例。
以下将结合附图来详细描述本发明的示例性实施例，然而，附图只是示意性地示出了本发明的具体示例，且不具有限制作用。然而，本领域技术人员应理解的是，在不脱离本发明的权利要求所限定的保护范围的情况下，可以对其进行各种修改和变形。
在下文中，将通过参照附图解释本发明的示例性实施例来详细描述本发明。
图4示出了根据本发明的示例性实施例的薄膜晶体管阵列基板的驱动架构示意图。图5至图11示出了根据本发明的示例性实施例的制造薄膜晶体管阵列基板的流程示意图。
如图4和图5中所示，在基底100上形成第一半导体210和与第一半导体210分隔开的第二半导体220。第一半导体210可以形成在基底100的显示区域101中，第二半导体220可以形成在基底100的非显示区域102中。基底100可以由含有SiO2作为主要成分的透明玻璃材料形成，但是不限于此。
通常，通过物理气相沉积(PVD)法形成第一半导体210和第二半导体220。在本发明的非限制性实施例中，第一半导体210和第二半导体220的材料可以相同。
此外，还可以在第一半导体210和第二半导体220与基底之间形成缓冲层(未示出)，然而本发明不限于此。
接着，如图6中所示，对第一半导体210和第二半导体220进行掺杂，以形成薄膜晶体管的有源层的源区211、漏区212和位于源区211和漏区212之间的沟道区213以及肖特基二极管的阳极层221和阴极层222。可以采用相同的杂质来掺杂第一半导体210和第二半导体220，从而薄膜晶体管的有源层的源区211和漏区212与肖特基二极管的阳极层221相同，薄膜晶体管的沟道区213与肖特基二极管的阴极层222相同。此外，可以采用同一工艺执行掺杂第一半导体210和第二半导体220的步骤。在本发明中，由于在制造TFT时可以同时制造肖特基二极管，从而不需要额外增加工序，简化了制造工艺。
然后，如图7中所示，在基底100上形成栅极绝缘层300，以覆盖第一半导体210和第二半导体220。
接着，参照图8，在栅极绝缘层300上形成薄膜晶体管的第二栅电极310和肖特基二极管的第一栅电极320，并且第二栅电极310与沟道区213叠置，第一栅电极320与阳极层221和阴极层222的一部分叠置。在本发明的实施例中，可以通过同一工艺来形成第二栅电极310和第一栅电极320。
然后，参照图9，在栅极绝缘层300上形成层间绝缘层400，以覆盖第二 栅电极310和第一栅电极320。接着，如图10所示，在栅极绝缘层300和层间绝缘层400中形成用于暴露薄膜晶体管的源区211和漏区212以及肖特基二极管的阳极层221和阴极层222的接触孔H。
最后，如图11所示，在层间绝缘层400上形成薄膜晶体管的源电极510和漏电极520以及肖特基二极管的第一外接电压(例如，VGL)530和第二外接电压(例如，AVEE)540，并且源电极510、漏电极520、第一外接电压530和第二外接电压540分别通过接触孔H连接到源区211、漏区212、阳极层221和阴极层222。
根据本发明，通过在形成薄膜晶体管(TFT)时同时形成肖特基二极管能够简化工艺以及制造成本。
此外，根据本发明提供的薄膜晶体管阵列基板及其制造方法，能够节约FPCA的面积，大大降低FPCA的厚度，能够实现液晶模组纤薄化，从而促进手机整机的纤薄化。
以上描述了根据本发明的示例性实施例的制造薄膜晶体管阵列基板的方法，但本发明的保护范围并不限制于上述特定实施例。

Claims (10)

  1. 一种薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：
    基底，包括显示区域和非显示区域，非显示区域围绕显示区域并且包括肖特基二极管，
    其中，所述肖特基二极管包括：
    阳极层和阴极层，形成基底上；
    栅极绝缘层，形成在基底上并且覆盖阳极层和阴极层；
    第一栅电极，形成在栅极绝缘层上并且与阳极层和阴极层叠置；
    层间绝缘层，形成在栅极绝缘层上并且覆盖第一栅电极，并且包括用于暴露阳极层和阴极层的接触孔；
    第一外接电压和第二外接电压，形成在层间绝缘层上，并且分别通过接触孔连接到阳极层和阴极层。
  2. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述显示区域包括薄膜晶体管，
    其中，所述薄膜晶体管包括：
    有源层，形成在基底上；
    第二栅电极，与有源层绝缘；
    源电极和漏电极，电连接到有源层。
  3. 根据权利要求2所述的薄膜晶体管阵列基板，其中，阳极层和阴极层与所述有源层设置在同一层上。
  4. 根据权利要求2所述的薄膜晶体管阵列基板，其中，第一栅电极与第二栅电极设置在同一层上。
  5. 根据权利要求2所述的薄膜晶体管阵列基板，其中，第一外接电压和 第二外接电压与源电极和漏电极设置在同一层上。
  6. 根据权利要求2所述的薄膜晶体管阵列基板，其中，有源层包括源区、漏区和位于源区和漏区之间的沟道区，
    其中，阳极层包括与源区和漏区相同的材料，阴极层包括与沟道区相同的材料。
  7. 根据权利要求2所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板还包括焊盘，所述焊盘位于非显示区域中。
  8. 一种制造薄膜晶体管阵列基板的方法，其中，所述方法包括：
    在基底的显示区域中形成薄膜晶体管的有源层，并且在基底的非显示区域中形成肖特基二极管的阳极层和阴极层；
    在基底上形成栅极绝缘层以覆盖薄膜晶体管的有源层和肖特基二极管的阳极层和阴极层；
    在栅极绝缘层上形成薄膜晶体管的第二栅电极和肖特基二极管的第一栅电极，第二栅电极与有源层叠置，第一栅电极与阳极层和阴极层叠置；
    在栅极绝缘层上形成层间绝缘层以覆盖第一栅电极和第二栅电极；
    在层间绝缘层和栅极绝缘层中形成用于暴露薄膜晶体管的有源层以及肖特基二极管的阳极层和阴极层的接触孔；
    在层间绝缘层上形成薄膜晶体管的源电极和漏电极以及肖特基二极管的第一外接电压和第二外接电压，源电极、漏电极、第一外接电压和第二外接电压分别通过接触孔连接到有源层、阳极层和阴极层。
  9. 根据权利要求8所述的方法，其中，有源层包括源区、漏区和位于源区和漏区之间的沟道区，
    其中，阳极层包括与源区和漏区相同的材料，阴极层包括与沟道区相同的材料。
  10. 根据权利要求8所述的方法，其中，形成第一栅电极和第二栅电极的 步骤包括：使用同一工艺同时形成第一栅电极和第二栅电极。
PCT/CN2016/101611 2016-09-07 2016-10-10 薄膜晶体管阵列基板及其制造方法 Ceased WO2018045613A1 (zh)

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