WO2018040475A1 - 一种薄膜晶体管及其制造方法 - Google Patents

一种薄膜晶体管及其制造方法 Download PDF

Info

Publication number
WO2018040475A1
WO2018040475A1 PCT/CN2017/070829 CN2017070829W WO2018040475A1 WO 2018040475 A1 WO2018040475 A1 WO 2018040475A1 CN 2017070829 W CN2017070829 W CN 2017070829W WO 2018040475 A1 WO2018040475 A1 WO 2018040475A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
metal
metal layer
thin film
film transistor
Prior art date
Application number
PCT/CN2017/070829
Other languages
English (en)
French (fr)
Inventor
石龙强
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/328,945 priority Critical patent/US10367066B2/en
Publication of WO2018040475A1 publication Critical patent/WO2018040475A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/441—Deposition of conductive or insulating materials for electrodes
    • H01L21/443—Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor and a method of fabricating the same.
  • IGZO is an abbreviation for indium gallium zinc oxide, which is a channel layer material used in next-generation thin film transistor technology. It is a thin film transistor technology and refers to TFT-LCD. Above the active layer, a layer of metal oxide is applied. Simply put, in fact, IGZO is only a channel layer material, not a new panel technology, and IPS, SVA, OLED is not a hierarchical concept, IGZO is still in the scope of TFT-LCD. The IGZO material was first proposed by the Tokyo Institute of Technology in Japan, and was applied in the TFT industry. The IGZO-TFT technology was first produced in Japan at Sharp Corporation.
  • a TFT Thin Film Transistor refers to a thin film transistor which is located in a pixel driving module in a lower glass substrate of a liquid crystal panel, and has a film shape and is embedded in the driving module together with the pixel element.
  • a TFT liquid crystal screen means that each liquid crystal pixel on the liquid crystal panel is driven by a thin film transistor integrated therein.
  • the characteristics of the TFT are substantially the same as those of the semiconductor transistor, the driving current charges the pixel capacitance, and the pixel conversion device is lit, and the IGZO material is used on the TFT.
  • the semiconductor band is bent at the interface to form a barrier.
  • the presence of the barrier results in a large interfacial resistance such that the source 3 and the drain 4 form a Schottky diode contact with the IGZO layer 4, respectively.
  • the Schottky resistor causes the on-state current of the TFT element to be insufficient, the Subthreshold Swing (SS) is too large, and the component stability is degraded, which may affect the picture display quality.
  • reducing the contact resistance of metal and IGZO to form an ohmic contact is an important factor in determining the performance of a semiconductor device.
  • One of the methods for forming good ohmic contact is to perform N-type doping (n+IGZO) in the semiconductor region in contact with the metal, so that the depletion region of the interface is narrowed, and electrons have more opportunities for direct tunneling (tunneling effect). .
  • the existing N+IGZO (ie, N-type doping) method adopts doping, that is, after IGZO is finished, the IGZO is implanted with heavy metal or H+; the process is complicated and the time is long, which greatly increases the production. cost.
  • the technical problem to be solved by the present invention is to reduce the contact resistance of metal and IGZO to form an ohmic contact.
  • the present application proposes a thin film transistor and a method of fabricating the same.
  • the thin film transistor of the present invention is provided with a gate layer, a gate insulating layer, an indium gallium zinc oxide layer, a source and a drain in this order from the inside to the outside, wherein the source and the drain are respectively arranged first and second from the inside to the outside a metal layer, a second metal layer, and a third metal layer, wherein the first metal layer is in contact with the indium gallium zinc oxide layer.
  • the source and the drain respectively adopt three metal layers, and the first metal layer diffuses into the indium gallium zinc oxide layer at the contact surface with the indium gallium zinc oxide layer, and reduces source, drain and indium gallium zinc oxidation. Contact resistance of the layer.
  • the first metal layer is metal indium (In)
  • the second metal layer is one of metal molybdenum (Mo) or titanium (Ti)
  • the third metal layer is one of metal copper or aluminum.
  • the first metal layer is a metal indium
  • indium is a silver-gray, extremely soft fusible metal having a melting point of 156.61 ° C and high conductivity, so that indium is more easily diffused into the indium gallium zinc oxide layer during the fabrication process.
  • the contact resistance of the first metal layer and the indium gallium zinc oxide layer is lowered.
  • a passivation layer is disposed above the source, the drain, and the indium gallium zinc oxide layer.
  • the passivation layer is a silicon oxide film.
  • the indium gallium zinc oxide layer has a metal diffusion layer in contact with the first metal layer, and the metal diffusion layer reduces contact resistance between the source, the drain and the indium gallium zinc oxide layer to achieve ohmic contact. .
  • the method for fabricating a thin film transistor proposed by the present invention comprises the following steps:
  • Step 1 sequentially forming a gate layer, a gate insulating layer and an indium gallium zinc oxide layer on the substrate;
  • Step 2 fabricating a source and a drain on the basis of the previous step, and sequentially forming a first metal layer, a second metal layer, and a third metal layer on the upper portion of the gate insulating layer and the indium gallium zinc oxide layer;
  • Step 3 making a passivation (PV) layer on the basis of the previous step
  • Step 4 performing a high temperature annealing treatment on the passivation layer on the basis of the previous step, the metal indium in the first metal layer diffuses to the indium gallium zinc oxide layer to form a metal diffusion layer, so that the indium gallium zinc oxide layer and the source and the drain The pole contact interface forms an ohmic contact.
  • the high temperature annealing in step 4 not only eliminates the internal stress generated during the fabrication process, but more importantly, the high temperature causes the metal indium in the first metal layer in contact with the indium gallium zinc oxide layer to melt and diffuse into the indium gallium zinc oxide layer. Medium, thereby forming an ohmic contact between the first metal layer and the indium gallium zinc oxide layer.
  • the source and the drain are respectively provided with a first metal layer, a second metal layer and a third metal layer, wherein the first metal layer is metal indium, and the second metal layer is metal molybdenum or titanium.
  • the third metal layer is one of metallic copper or aluminum.
  • first metal layer, the second metal layer and the third metal layer are sequentially deposited by physical vapor deposition.
  • the thin film transistor structure is obtained by etching.
  • the passivation layer is obtained by depositing a silicon oxide film by chemical vapor deposition.
  • the invention has the following advantages:
  • the invention adopts a structure of a first metal layer, a second metal layer and a third metal layer at the source and the drain, the first metal layer is a metal In layer, the second metal layer is a metal Mo or Ti layer, and the third metal layer It is a metal Cu or Al layer, wherein the first metal layer is a bottom layer, that is, a contact layer with the IGZO layer.
  • the In element in IGZO acts as a conductor, and an increase in the In content causes IGZO to become an N+IGZO region.
  • the portion In of the source and drain of the present invention diffuses into IGZO in a subsequent heating process to form N+IGZO to form an ohmic contact.
  • FIG. 1 is a flow chart showing a method of fabricating a thin film transistor of the present invention
  • 2 shows a schematic view of a metal and indium gallium zinc oxide layer forming a Schottky diode contact; wherein, in the figure, 1 indicates that the source or the drain forms a Schottky diode contact with IGZO; and 2 is an S pole (source); 3 is a D pole (drain); 4 is an IGZO layer; 5 is a gate insulating layer; 6 is a source layer; 7 is a substrate;
  • FIG. 3 is a schematic structural view of a thin film transistor of the present invention; wherein 10 is a PV layer, 11 is a third metal layer; 12 is a second metal layer; 13 is a first metal layer; 4 is an IGZO layer; and 8 is a metal diffusion layer.
  • 5 is a gate insulating layer; 6 is a gate layer; 7 is a substrate;
  • FIG. 4 is a schematic view showing the structure obtained in the second step of the first embodiment; wherein 11 is a third metal layer; 12 is a second metal layer; 13 is a first metal layer; 4 is an IGZO layer; 5 is a gate insulating layer; a gate layer; 7 is a substrate;
  • 5 is a schematic view showing the structure obtained in the third step of the first embodiment; wherein 10 is a passivation layer, 11 is a third metal layer; 12 is a second metal layer; 13 is a first metal layer; 4 is an IGZO layer; 5 is a gate insulating layer; 6 is a gate layer; 7 is a substrate;
  • 6 is a schematic view showing the structure obtained in the fourth step of the first embodiment; wherein 10 is a PV layer, 11 is a third metal layer; 12 is a second metal layer; 13 is a first metal layer; 4 is an IGZO layer; a metal diffusion layer; 5 is a gate insulating layer; 6 is a gate layer; and 7 is a substrate.
  • the first metal layer 13, the second metal layer 12, and the third metal layer 11 are used in the source and drain electrodes.
  • the first metal layer 13 is a metal indium layer
  • the second metal layer 12 is a metal molybdenum or titanium layer
  • the third metal layer 11 is a metal copper or aluminum layer
  • the first metal layer 13 is a bottom layer, that is, a contact layer with the IGZO layer; by the above change, the portion of the source and drain electrodes is in a subsequent heating process
  • the medium diffuses into the IGZO layer 4 to form a metal diffusion layer N+IGZO region 8, thereby forming an ohmic contact.
  • FIG. 3 of the present invention constitutes a drain
  • first metal layer 13 and the second metal layer on the right side. 12 and the third metal layer 11 constitute a source
  • FIGS. 4 to 6 are the same as FIG.
  • the gate layer, the gate insulating layer and the IGZO layer are first formed;
  • a gate layer 6, a gate insulating layer 5, and an IGZO layer 4 are sequentially deposited on the substrate 7;
  • the selected substrate is a glass substrate, but is not limited to a glass substrate;
  • a gate layer (Gate) 6 is deposited on a glass substrate by a plasma chemical vapor deposition method on a glass substrate, that is, the substrate 7 of FIG. 4, and then a gate insulating layer (GI) 5 is deposited by PECVD.
  • the IGZO layer 4 is deposited by vapor deposition, and after the reactive ion etching, the Gate, GI and IGZO structures are obtained;
  • PECVD plasma enhanced chemical vapor deposition
  • the present embodiment sequentially deposits a first metal layer 13 (ie, a metal In layer) and a second metal layer 12 by adding a diffusion layer at a source and a drain, that is, using a PVD suppter film formation.
  • Metal molybdenum or titanium layer and third metal layer 11 (ie, metal copper or aluminum layer), then yellow light, etching to obtain a design pattern; in the process of adding a diffusion layer, ensuring the metal indium layer as a bottom layer and IGZO layer 4 In contact, the indium element in IGZO 4 acts as a conductor, and an increase in the indium content causes IGZO to form an N+IGZO region 8.
  • Part of the indium of the source and drain of the present invention will diffuse into the IGZO in the subsequent heating process, thereby forming the N+IGZO region 8 in the following step, and finally forming an ohmic contact; compared with the conventional injection of heavy metal or H+ for the IGZO.
  • N+IGZO is obtained.
  • indium is added to the source and drain to diffuse into IGZO in subsequent heating, which simplifies the process, shortens the manufacturing process time, and reduces production. Cost, and can play a role in improving ohmic contact and improving component characteristics.
  • a surface oxygen protective layer may be formed on the IGZO layer, and the protective layer is formed because the IGZO layer preparation process also includes some non-vacuum processes, such as photoresist coating, Exposure, development, etc., there will be a certain amount of H atoms in these processes. In addition, some H atoms will exist in the subsequent PECVD SiOx plating process. These H atoms are likely to affect the performance of the IGZO layer. Therefore, by forming a surface oxygen protective layer on the IGZO layer, the influence of the H atoms on the IGZO layer is effectively blocked, and the H atoms are prevented from converting the IGZO layer from a semiconductor to a conductor.
  • a surface oxygen protective layer on the IGZO layer Forming a surface oxygen protective layer on the IGZO layer, and forming a surface oxygen protective layer by inverting the target and forming O 2 under the film formation of the IGZO layer, wherein the flow rate of O 2 is 10-20 sccm, The time is 1 to 10 seconds. It is also possible to form a surface oxygen protective layer by introducing a mixed gas of O 2 and Ar having a flow ratio of 1:10 to 1:100 after film formation of the IGZO layer, and the introduction time of the mixed gas of O 2 and Ar is 1 to 10 second.
  • the PV layer 10 fabricated in the previous step is subjected to a high temperature annealing treatment, and the indium portion of the source and drain electrodes is diffused to the interface between the IGZO layer 4 and the source and drain contacts to form an ohmic contact, as shown in FIG. Structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种薄膜晶体管及其制造方法，所述薄膜晶体管的源极和漏极分别具有第一金属层（13）、第二金属层（12）、第三金属层（11），第一金属层（13）与铟镓锌氧化物层（4）相接触，并在接触面处设置有金属扩散层（8）。该薄膜晶体管的制造方法，依次沉积得到第一金属层（13）、第二金属层（12）、第三金属层（11），然后得到PV层（10），对PV层（10）进行高温退火处理，使得第一金属层（13）中的金属扩散到铟镓锌氧化物层（4）形成金属扩散层（8），该金属扩散层（8）使得第一金属层（13）和铟镓锌氧化物层（4）形成欧姆接触，降低源极、漏极与铟镓锌氧化物层（4）的接触电阻。

Description

一种薄膜晶体管及其制造方法
相关申请的交叉引用
本申请要求享有于2016年8月31日提交的名称为“一种薄膜晶体管及其制造方法”的中国专利申请CN201610793911.3的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管及其制造方法。
背景技术
IGZO是铟镓锌氧化物(indium gallium zinc oxide)的缩写，非晶IGZO材料是用于新一代薄膜晶体管技术中的沟道层材料，它是一种薄膜电晶体技术，是指在TFT-LCD主动层之上，打上一层金属氧化物。简单说，其实IGZO只是沟道层材料，而并不是一种新的面板技术，和IPS、SVA、OLED并不是一个层级的概念，总得来说IGZO还在TFT-LCD的范畴之内。IGZO材料由日本东京工业大学细野秀雄最先提出并在TFT行业中应用，IGZO-TFT技术最先在日本夏普公司实现大量生产。
TFT(Thin Film Transistor)是指薄膜晶体管，TFT位于液晶面板的下方玻璃基板中的像素驱动模组中，其形态为薄膜状，与像素元件一起嵌入在这个驱动模组当中。TFT液晶屏幕就是指液晶面板上的每一液晶象素点都是由集成在其后的薄膜晶体管来驱动。通常而言，TFT的特征与半导体电晶体基本相同，其驱动电流对像素电容充电，并点亮像素的电器转换装置，而IGZO材料则使用在TFT上。
如图2，金属和IGZO相接触时，在界面处半导体能带弯曲，形成势垒。势垒的存在会导致大的界面电阻，使得源极3、漏极4分别与IGZO层4形成肖特基二极管(Schottky)接触。Schottky电阻会导致TFT元件开态电流不足，亚阈值摆幅(Subthreshold Swing，SS)过大，元件稳定性下降，从而会影响画面显示品质。
所以，降低金属和IGZO的接触电阻，形成欧姆接触，是决定半导体元件性能好坏的一个重要因素。良好的欧姆接触形成的方法之一是在与金属接触的半导体区域进行N型掺杂(n+IGZO)，使得界面的空乏区变窄，电子有更多的机会直穿隧(穿隧效应)。
现有的N+IGZO(即N型掺杂)的方法都是采用掺杂，即在IGZO做完之后，对IGZO进行重金属或者H+等的注入；这样做工艺复杂，时间长，大大增加了生产成本。
发明内容
本发明所要解决的技术问题是降低金属和IGZO的接触电阻，形成欧姆接触，为了解决该技术问题，本申请提出了一种薄膜晶体管及其制造方法。
本发明提出的薄膜晶体管，由内向外依次设置栅极层、栅绝缘层、铟镓锌氧化物层、源极和漏极，其中，在源极和漏极分别由内向外依次设置有第一金属层、第二金属层和第三金属层，其中，所述第一金属层与铟镓锌氧化物层接触。
源极和漏极分别采用三个金属层，第一个金属层在与铟镓锌氧化物层接触面处会扩散到铟镓锌氧化物层中，降低源极、漏极与铟镓锌氧化物层的接触电阻。
进一步，所述的第一金属层为金属铟(In)，第二金属层为金属钼(Mo)或钛(Ti)中的一种，第三金属层为金属铜或铝中的一种。
由于第一金属层为金属铟，铟是一种银灰色，质地极软的易熔金属，熔点156.61℃，具有高导电性，所以在制作过程中，铟更容易扩散到铟镓锌氧化物层中，降低第一金属层与铟镓锌氧化物层的接触电阻。
进一步，在所述源极、所述漏极和所述铟镓锌氧化物层的上方设置有钝化层。
进一步，所述钝化层为氧化硅薄膜。
进一步，所述铟镓锌氧化物层与所述第一金属层接触处有金属扩散层，金属扩散层使得源极、漏极与铟镓锌氧化物层之间的接触电阻降低，达到欧姆接触。
本发明提出的薄膜晶体管制作方法，包括以下步骤：
步骤一、在基板上依次制作栅极层、栅绝缘层和铟镓锌氧化物层；
步骤二、在上一步基础上制作源极和漏极，在栅绝缘层和铟镓锌氧化物层的上部分别依次制作第一金属层、第二金属层和第三金属层；
步骤三、在上一步基础上制作钝化(PV)层；
步骤四、在上一步基础上对钝化层进行高温退火处理，第一金属层中的金属铟扩散到铟镓锌氧化物层形成金属扩散层，使得铟镓锌氧化物层与源极和漏极接触界面形成欧姆接触。
步骤四中采用高温退火，不仅消除了制作过程中产生的内应力，更重要的是高温使得与铟镓锌氧化物层接触的第一金属层中的金属铟融化扩散到铟镓锌氧化物层中，从而使第一金属层与铟镓锌氧化物层之间形成欧姆接触。
进一步，所述源极和所述漏极分别设置有第一金属层、第二金属层和第三金属层，所述的第一金属层为金属铟，第二金属层为金属钼或钛中的一种，第三金属层为金属铜或铝中的一种。
进一步，所述第一金属层、所述第二金属层和所述第三金属层是通过物理气相沉积方式依次沉积得到。
进一步，在第一金属层、第二金属层和第三金属层进行沉积后，进行黄光制程，刻蚀得到所述薄膜晶体管结构。
进一步，所述钝化层通过化学气相沉积方式沉积氧化硅薄膜得到。
本发明与现有技术相比，具有如下优势：
本发明在源极和漏极采用第一金属层、第二金属层和第三金属层的结构，第一金属层为金属In层，第二金属层为金属Mo或Ti层，第三金属层为金属Cu或Al层，其中，第一金属层为底层，即与IGZO层接触层。IGZO中In元素起到导电作用，In含量的增加会导致IGZO变成N+IGZO区域。本发明源漏极的部分In在后续加热的制程中会扩散到IGZO中，形成N+IGZO从而形成欧姆接触。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1显示了本发明薄膜晶体管制造方法的流程图；
图2显示了金属和铟镓锌氧化物层形成肖特基二极管接触的示意图；其中，图中1表示源极或漏极与IGZO形成肖特基二极管接触；2为S极(源极)；3为D极(漏极)；4为IGZO层；5为栅绝缘层；6为源极层；7为基底；
图3显示了本发明的薄膜晶体管结构示意图；其中，10为PV层，11为第三金属层；12为第二金属层；13为第一金属层；4为IGZO层；8为金属扩散层；5为栅绝缘层；6为栅极层；7为基底；
图4显示了实施例一中步骤二得到的结构示意图；其中，11为第三金属层；12为第二金属层；13为第一金属层；4为IGZO层；5为栅绝缘层；6为栅极层；7为基底；
图5显示了实施例一中步骤三得到的的结构示意图；其中，10为钝化层，11为第三金属层；12为第二金属层；13为第一金属层；4为IGZO层；5为栅绝缘层；6为栅极层；7为基底；
图6显示了实施例一中步骤四得到的结构示意图；其中，10为PV层，11为第三金属层；12为第二金属层；13为第一金属层；4为IGZO层；8为金属扩散层；5为栅绝缘层；6为栅极层；7为基底。
具体实施方式
下面将结合附图对本发明作进一步说明。
实施例一
为了解决金属和IGZO相接触时，在界面处半导体能带弯曲，形成势垒，导致大的界面电阻，即肖特基二极管接触的问题，如图2所示，本实施例提供了一种形成欧姆接触的方式，如图3所示。
如图3所示，本实施例在源漏极采用第一金属层13、第二金属层12和第三金属层11的结构，第一金属层13为金属铟层，第二金属层12为金属钼或钛层，第三金属层11为金属铜或铝层，其中，第一金属层13为底层，即与IGZO层接触层；通过上述改变，源漏极的部分In在后续加热的制程中会扩散到IGZO层4中，形成金属扩散层N+IGZO区域8，从而形成欧姆接触。
需要说明的是，本发明中图3中所表明的左侧第一金属层13、第二金属层12和第三金属层11构成漏极，右侧的第一金属层13、第二金属层12和第三金属层11构成源极，图4至图6同图3。
具体过程为：
一、首先制作栅极层、栅绝缘层和IGZO层；
依次在基板7上沉积栅极层6、栅绝缘层5和IGZO层4；所选择的基板为玻璃基板，但不限于玻璃基板；
首先，在玻璃基板即图4的基底7上采用等离子体化学气相沉积方法在玻璃基板沉积栅极层(Gate)6，然后PECVD沉积备栅极绝缘层(GI)5，再采用化 学气相沉积法沉积IGZO层4，经过反应离子刻蚀后，得到Gate、GI和IGZO结构；
所采用的等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)成膜不会损害到IGZO沟道，有助于改善欧姆接触，提高元件特性。
二、进行漏极和源极的制作；
如图4所示，在此步骤中，本实施例通过在源漏极加入扩散层，即利用PVD suppter成膜依次沉积第一金属层13(即金属In层)、第二金属层12(即金属钼或钛层)和第三金属层11(即金属铜或铝层)，然后进行黄光，刻蚀得到设计图形；在加入扩散层过程中，保证金属铟层在作为底层与IGZO层4接触，IGZO 4中铟元素起到导电作用，铟含量的增加会导致IGZO形成N+IGZO区域8。本发明源漏极的部分铟在后续加热的制程中会扩散到IGZO中，从而在下面步骤中形成N+IGZO区域8，最终形成欧姆接触；相比较常规的对IGZO进行重金属或者H+等的注入方式，即N掺杂的方式获取N+IGZO，本实施例采用源漏极加入铟，使其在后续加热中扩散到IGZO中，有效地简化了工艺过程，使得制作工艺时间缩短，降低了生产成本，并能起到改善欧姆接触，提高元件特性的作用。
三、PV层的制作；
如图5所示，采用PECVD方法进行SiOx成膜，得到PV层10；
此步骤中，在制作PV层前，可以在IGZO层上形成表面氧保护层，制作保护层的目的是因为IGZO层制备过程中，还包括一些非真空工艺，例如光致抗蚀剂涂布、曝光、显影等，这些工艺中会存在一定量的H原子，此外后续PECVD镀SiOx的过程中也会有部分H原子存在，这些H原子极有可能影响IGZO层的性能。因此，通过在IGZO层上形成表面氧保护层，有效地阻挡H原子对IGZO层的影响，避免H原子将IGZO层由半导体转变为导体。
所述的在IGZO层上形成表面氧保护层，可通过在IGZO层的成膜后将靶材反转同时通入O2形成表面氧保护层，其中O2的流量为10～20sccm，通入时间为1～10秒。也可通过在IGZO层的成膜后通入流量比为1:10至1:100的O2和Ar混合气体来形成表面氧保护层，O2和Ar混合气体的通入时间为1～10秒。
四、金属扩散层制作
如图6所示，对上一步骤制作的PV层10进行高温退火处理，源漏极的铟部分会扩散到IGZO层4和源漏极接触的界面，形成欧姆接触，得到如图6所示的结构。
虽然在本文中参照了特定的实施方式来描述本发明，但是应该理解的是，这些实施例仅仅是本发明的原理和应用的示例，可以对示例性的实施例进行许多修改，只要不偏离所附权利要求所限定的本发明的精神和范围，均在本发明的权利要求保护范围之内。

Claims (10)

  1. 一种薄膜晶体管，由内向外依次设置栅极层、栅绝缘层、铟镓锌氧化物层、源极和漏极，其中，在源极和漏极分别由内向外依次设置有第一金属层、第二金属层和第三金属层，其中，所述第一金属层与所述铟镓锌氧化物层接触。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述的第一金属层为金属铟，第二金属层为金属钼或钛中的一种，第三金属层为金属铜或铝中的一种。
  3. 根据权利要求1所述的薄膜晶体管，其中，在所述源极、所述漏极和所述铟镓锌氧化物层的上方设置有钝化层。
  4. 根据权利要求3所述的薄膜晶体管，其中，所述钝化层为氧化硅膜。
  5. 根据权利要求1所述的薄膜晶体管，其中，所述铟镓锌氧化物层与所述第一金属层接触处设置有金属扩散层。
  6. 一种薄膜晶体管的制造方法，
    所述薄膜晶体管由内向外依次设置栅极层、栅绝缘层、铟镓锌氧化物层、源极和漏极，在源极和漏极分别由内向外依次设置有第一金属层、第二金属层和第三金属层，所述第一金属层与所述铟镓锌氧化物层接触，
    所述制造方法包括以下步骤：
    步骤一、在基板上依次制作栅极层、栅绝缘层和铟镓锌氧化物层；
    步骤二、制作源极和漏极，在栅绝缘层和铟镓锌氧化物层的上部分别依次制作第一金属层、第二金属层和第三金属层；
    步骤三、制作钝化层；
    步骤四、对钝化层进行高温退火处理，第一金属层中的铟扩散到铟镓锌氧化物层形成金属扩散层，使得铟镓锌氧化物层与源极和漏极接触界面形成欧姆接触。
  7. 根据权利要求6所述的薄膜晶体管的制造方法，其中，所述源极和所述漏极分别设置有第一金属层、第二金属层和第三金属层，所述的第一金属层为金属铟，第二金属层为金属钼或钛中的一种，第三金属层为金属铜或铝中的一种。
  8. 根据权利要求6所述的薄膜晶体管的制造方法，其中，所述第一金属层、所述第二金属层和所述第三金属层是通过物理气相沉积方式依次沉积得到。
  9. 根据权利要求8所述的薄膜晶体管的制造方法，其中，在沉积得到第一 金属层、第二金属层和第三金属层后，进行黄光制程，刻蚀得到所述薄膜晶体管结构。
  10. 根据权利要求6所述的薄膜晶体管的制造方法，其中，所述钝化层由基于化学气相沉积方式沉积氧化硅薄膜得到。
PCT/CN2017/070829 2016-08-31 2017-01-11 一种薄膜晶体管及其制造方法 WO2018040475A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/328,945 US10367066B2 (en) 2016-08-31 2017-01-11 Thin film transistor and method for manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610793911.3A CN106229260A (zh) 2016-08-31 2016-08-31 一种薄膜晶体管及其制造方法
CN201610793911.3 2016-08-31

Publications (1)

Publication Number Publication Date
WO2018040475A1 true WO2018040475A1 (zh) 2018-03-08

Family

ID=58074195

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/070829 WO2018040475A1 (zh) 2016-08-31 2017-01-11 一种薄膜晶体管及其制造方法

Country Status (3)

Country Link
US (1) US10367066B2 (zh)
CN (1) CN106229260A (zh)
WO (1) WO2018040475A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106229260A (zh) 2016-08-31 2016-12-14 深圳市华星光电技术有限公司 一种薄膜晶体管及其制造方法
CN111244034A (zh) * 2020-01-17 2020-06-05 Tcl华星光电技术有限公司 阵列基板及其制造方法
CN111769188A (zh) * 2020-07-31 2020-10-13 佛山紫熙慧众科技有限公司 一种新型的紫外led芯片电极制备方法
CN113707559B (zh) * 2021-08-02 2023-12-01 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管的制备方法、薄膜晶体管及显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002026335A (ja) * 2000-07-13 2002-01-25 Fujitsu Ltd 薄膜トランジスタ及びその製造方法
US20020109797A1 (en) * 2001-02-12 2002-08-15 Woo-Suk Chung TFT LCD device having multi-layered pixel electrodes
CN1534742A (zh) * 2003-03-27 2004-10-06 友达光电股份有限公司 金属斜角蚀刻结构、源极/漏极与栅极结构及其制造方法
CN101013670A (zh) * 2007-01-17 2007-08-08 友达光电股份有限公司 薄膜晶体管的制造方法及液晶显示器用的下基板
CN101645418A (zh) * 2009-09-07 2010-02-10 上海广电光电子有限公司 薄膜晶体管阵列基板制造方法
CN102598284A (zh) * 2009-11-06 2012-07-18 株式会社半导体能源研究所 半导体器件
CN106229260A (zh) * 2016-08-31 2016-12-14 深圳市华星光电技术有限公司 一种薄膜晶体管及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9722049B2 (en) * 2013-12-23 2017-08-01 Intermolecular, Inc. Methods for forming crystalline IGZO with a seed layer
US20150311345A1 (en) * 2014-04-28 2015-10-29 Boe Technology Group Co., Ltd. Thin film transistor and method of fabricating the same, display substrate and display device
US10483285B2 (en) * 2016-06-01 2019-11-19 Innolux Corporation Element substrate and display device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002026335A (ja) * 2000-07-13 2002-01-25 Fujitsu Ltd 薄膜トランジスタ及びその製造方法
US20020109797A1 (en) * 2001-02-12 2002-08-15 Woo-Suk Chung TFT LCD device having multi-layered pixel electrodes
CN1534742A (zh) * 2003-03-27 2004-10-06 友达光电股份有限公司 金属斜角蚀刻结构、源极/漏极与栅极结构及其制造方法
CN101013670A (zh) * 2007-01-17 2007-08-08 友达光电股份有限公司 薄膜晶体管的制造方法及液晶显示器用的下基板
CN101645418A (zh) * 2009-09-07 2010-02-10 上海广电光电子有限公司 薄膜晶体管阵列基板制造方法
CN102598284A (zh) * 2009-11-06 2012-07-18 株式会社半导体能源研究所 半导体器件
CN106229260A (zh) * 2016-08-31 2016-12-14 深圳市华星光电技术有限公司 一种薄膜晶体管及其制造方法

Also Published As

Publication number Publication date
CN106229260A (zh) 2016-12-14
US20180337237A1 (en) 2018-11-22
US10367066B2 (en) 2019-07-30

Similar Documents

Publication Publication Date Title
US9793377B2 (en) Thin film transistor, thin film transistor array panel including the same, and manufacturing method thereof
US10615266B2 (en) Thin-film transistor, manufacturing method thereof, and array substrate
WO2018054180A1 (zh) 一种阵列基板及其制备方法、显示装置
WO2018040475A1 (zh) 一种薄膜晶体管及其制造方法
JP2007220817A (ja) 薄膜トランジスタ及びその製法
JP2019511831A5 (zh)
KR101872629B1 (ko) 저온폴리실리콘 박막 트랜지스터 및 그 제조방법
TW465113B (en) Thin film transistor, liquid crystal display device and method of fabricating the thin film transistor
WO2016008226A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示设备
WO2018152875A1 (zh) 薄膜晶体管的制作方法、薄膜晶体管及显示器
US10615282B2 (en) Thin-film transistor and manufacturing method thereof, array substrate, and display apparatus
WO2015043220A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
WO2018149027A1 (zh) 一种薄膜晶体管及其制备方法
US10121883B2 (en) Manufacturing method of top gate thin-film transistor
CN110729357A (zh) 薄膜晶体管及其制造方法
US10192903B2 (en) Method for manufacturing TFT substrate
WO2019085096A1 (zh) 一种柔性oled显示面板的制备方法及柔性oled显示面板
US6166400A (en) Thin film transistor of liquid crystal display with amorphous silicon active layer and amorphous diamond ohmic contact layers
US10205026B2 (en) Thin film transistor having a composite metal gate layer
WO2019095408A1 (zh) 阵列基板及其制作方法、显示面板
US10115745B2 (en) TFT array substrate and method of forming the same
US9257290B2 (en) Low temperature poly-silicon thin film transistor and manufacturing method thereof
WO2019015004A1 (zh) 一种阵列基板、显示装置及其制作方法
WO2019071670A1 (zh) N型薄膜晶体管及其制备方法、oled显示面板的制备方法
CN106206745B (zh) 一种高迁移率金属氧化物tft的制作方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15328945

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17844786

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17844786

Country of ref document: EP

Kind code of ref document: A1