WO2018040340A1 - 一种阵列基板 - Google Patents

一种阵列基板 Download PDF

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Publication number
WO2018040340A1
WO2018040340A1 PCT/CN2016/108185 CN2016108185W WO2018040340A1 WO 2018040340 A1 WO2018040340 A1 WO 2018040340A1 CN 2016108185 W CN2016108185 W CN 2016108185W WO 2018040340 A1 WO2018040340 A1 WO 2018040340A1
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Prior art keywords
pixels
data lines
lines
gate
data
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English (en)
French (fr)
Inventor
邢振周
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/323,973 priority Critical patent/US10290274B2/en
Publication of WO2018040340A1 publication Critical patent/WO2018040340A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to an array substrate.
  • Liquid crystal display Liquid Crystal Display
  • LCD and other flat display devices are widely used in mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, desktop computers, etc. due to their high image quality, power saving, thin body and wide application range.
  • Various consumer electronic products have become the mainstream in display devices.
  • Most of the liquid crystal display devices on the market are backlight type liquid crystal displays, which include a liquid crystal display panel (TFT-LCD) and a backlight module (backlight) Module).
  • TFT-LCD liquid crystal display panel
  • backlight backlight module
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates, and the liquid crystal molecules are controlled to change direction by energizing or not, and the light of the backlight module is changed. Refracted to produce a picture.
  • the driving structure of the conventional liquid crystal display driving circuit is as shown in FIG. 1 , that is, one pixel electrode 4 is respectively connected with a data line 2 and a gate line 1 through the thin film transistor 3, which can well control each gate.
  • the number of data lines 2 and the number of gate lines 1 also increases, thereby affecting the transmittance and affecting the display effect.
  • one data line is divided into three data lines by a demultiplexing controller, and respectively connected to 3 of a row of pixels.
  • this architecture consumes more power in the case of commonly used column inversion displays. This situation needs to be changed.
  • An object of the present invention is to provide an array substrate to solve the problem in the prior art, as the resolution of the screen increases and the resolution increases, the number of data lines and gate lines also increases, thereby affecting the transmittance. A problem that affects the display effect.
  • An array substrate comprising a gate driver, a data driver and a driving circuit structure, the driving circuit structure comprising a plurality of driving circuit units, each of the driving circuit units comprising:
  • a pixel matrix including a plurality of pixels for displaying an image signal
  • each of the second gate lines for driving a row of pixels of the pixel matrix
  • a plurality of demultiplexing controllers for dividing each of the first data lines into a plurality of second data lines, and respectively controlling the opening and closing thereof;
  • the gate driver is provided with a plurality of first gate lines, each of the first gate lines is divided into a plurality of the second gate lines, and the plurality of the second gate lines are respectively corresponding to each other.
  • the data driver is provided with the plurality of first data lines, and each of the first data lines is divided into a plurality of the first by a plurality of the demultiplexing controllers
  • the second data lines are connected one by one, and the two demultiplexing controllers correspond to different first data lines;
  • Each of the first gate lines is divided into two of the second gates, and each of the demultiplexing controllers divides each of the first data lines into six of the second data lines.
  • the data driver is correspondingly provided with four first data lines, and two of the first data lines are respectively disposed on the left side and the right side of the driving circuit unit.
  • two of the demultiplexing controllers corresponding to the plurality of second data lines connected in one-to-one correspondence with each row of pixels are respectively disposed on one of the left and right sides of each of the driving circuit units The first data line is described.
  • each of the second data lines output by each of the demultiplexing controllers independently inputs different or the same gray scale signals to corresponding pixels.
  • each pixel is not adjacent to each other.
  • the two second gate lines originating from the same first gate line respectively drive adjacent two rows of pixels in the pixel matrix.
  • the two second gate lines originating from the same first gate line respectively drive two rows of pixels in the pixel matrix that are not adjacent.
  • the number of pixels in each row of the pixel matrix is 12, and the pixels of the pixel matrix include RGB three-color pixels or RGBW four-color pixels.
  • An array substrate comprising a gate driver, a data driver and a driving circuit structure, the driving circuit structure comprising a plurality of driving circuit units, each of the driving circuit units comprising:
  • a pixel matrix including a plurality of pixels for displaying an image signal
  • each of the second gate lines for driving a row of pixels of the pixel matrix
  • a plurality of demultiplexing controllers for dividing each of the first data lines into a plurality of second data lines, and respectively controlling the opening and closing thereof;
  • the gate driver is provided with a plurality of first gate lines, each of the first gate lines is divided into a plurality of the second gate lines, and the plurality of the second gate lines are respectively corresponding to each other.
  • the data driver is provided with the plurality of first data lines, and each of the first data lines is divided into a plurality of the first by a plurality of the demultiplexing controllers
  • the second data lines are connected one by one, and the two demultiplexing controllers correspond to different first data lines.
  • each of the first gate lines is divided into two of the second gate lines.
  • each of the demultiplexing controllers divides each of the first data lines into six of the second data lines.
  • the data driver is correspondingly provided with four of the first data lines, wherein two of the first data lines are respectively disposed on the left side and the right side of the driving circuit unit. .
  • two of the demultiplexing controllers corresponding to the plurality of second data lines connected in one-to-one correspondence with each row of pixels are respectively disposed on one of the left and right sides of each of the driving circuit units The first data line is described.
  • each of the second data lines output by each of the demultiplexing controllers independently inputs different or the same gray scale signals to corresponding pixels.
  • each pixel is not adjacent to each other.
  • the two second gate lines originating from the same first gate line respectively drive adjacent two rows of pixels in the pixel matrix.
  • the two second gate lines originating from the same first gate line respectively drive two rows of pixels in the pixel matrix that are not adjacent.
  • the number of pixels in each row of the pixel matrix is 12, and the pixels of the pixel matrix include RGB three-color pixels or RGBW four-color pixels.
  • An array substrate of the present invention divides a first data line into a plurality of second data lines by a demultiplexing controller, and connects them one by one to a row of pixels, thereby solving the prior art, along with the screen As the resolution increases and the resolution increases, the number of data lines and gate lines also increases, thereby affecting the transmittance and affecting the display effect.
  • FIG. 1 is a schematic overall structural diagram of a driving circuit unit of an array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic overall structural diagram of a driving circuit unit of another array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a circuit driving structure of an array substrate of the prior art
  • FIG. 4 is a schematic diagram showing display control timing of a driving circuit unit of an array substrate according to an embodiment of the present invention.
  • FIG. 1 is a schematic diagram showing the overall structure of a driving circuit unit of an array substrate according to an embodiment of the present invention.
  • an array substrate of the present invention includes a gate driver, a data driver, and A driving circuit structure, the driving circuit structure comprising a plurality of driving circuit units, each of the driving circuit units comprising:
  • the pixel matrix includes a plurality of pixels 60 for displaying image signals.
  • a plurality of second gate lines 50 each of the second gate lines 50 for driving a row of pixels 60 of the pixel matrix.
  • the plurality of demultiplexing controllers 30 are configured to divide each of the first data lines 10 into a plurality of second data lines 20 and respectively control the opening and closing thereof.
  • the gate driver is provided with a plurality of first gate lines 40, and each of the first gate lines 40 is divided into a plurality of the second gate lines 50 and a plurality of the second gate lines. 50 respectively driving the pixels 60 of the pixel matrix one by one, the data driver is provided with the plurality of first data lines 10, and each of the first data lines 10 is controlled by a plurality of the demultiplexing
  • the device 30 is divided into a plurality of the second data lines 20, and each of the demultiplexing controllers 30 outputs a plurality of the second data lines 20 and one-to-one correspondingly connects half of the pixels 60 of one row of pixels 60, each row of pixels
  • the plurality of the second data lines 20 outputted by the two demultiplexing controllers 30 are connected in one-to-one correspondence, and the two demultiplexing controllers 30 correspond to different first data lines 10 .
  • each of the first gate lines 40 is preferably divided into two of the second gate lines 50.
  • each of the demultiplexing controllers 30 preferably divides each of the first data lines 10 into six of the second data lines 20.
  • the data driver is provided with four first data lines 10, wherein the left and right sides of the driving circuit unit are provided with two The first data line 10.
  • two of the demultiplexing controllers 30 corresponding to the plurality of second data lines 20 connected in one-to-one correspondence with each row of pixels 60 are respectively disposed in each of the driving circuit units.
  • each of the second data lines 20 output by each of the demultiplexing controllers 30 independently inputs different or the same gray scale signals to the corresponding pixels 60.
  • the signal of each output port can be independently controlled by the demultiplexing controller 30, and different gray scale signals can be output according to actual needs for display.
  • one of the plurality of second data lines 20 outputted by the demultiplexing controller 30 is correspondingly connected to a row of pixels 60, and each pixel 60 is between two Not adjacent.
  • the two second gate lines 50 originating from the same first gate line 40 respectively drive adjacent two rows of pixels 60 in the pixel matrix.
  • the two second gate lines 50 originating from the same first gate line 40 respectively drive two rows of pixels 60 that are not adjacent in the pixel matrix.
  • 2 is a schematic view showing the overall structure of a driving circuit unit of another array substrate according to an embodiment of the present invention. 2 is the same as FIG. 1 in that the first data line 10 of FIG. 2 is also divided into a plurality of second data lines 20 by a plurality of demultiplexing controllers 30, and connected to the pixels 60 of the respective rows in the same manner. Go up. The difference is that the rows of pixels 60 connected by the plurality of second gate lines 50 divided by the first gate line 40 of FIG. 2 are not adjacent.
  • the number of pixels 60 in each row of the pixel matrix is 12, and the pixels 60 of the pixel matrix include an RGB three-color pixel matrix or an RGBW four-color pixel matrix. (The schematic diagram of the RGBW four-color pixel matrix is not shown).
  • the pixel matrix is an RGB three-color pixel matrix
  • one row of pixels 60 of one of the driving circuit units includes four pixel units, and each pixel unit includes RGB. 3 pixels 60.
  • the pixel matrix is an RGBW four-color pixel matrix
  • one row of pixels 60 of one of the driving circuit units includes three pixel units, and each pixel unit includes RGBW 4 pixels 60.
  • FIG. 4 is a schematic diagram of display control timing of a driving circuit unit of an array substrate according to an embodiment of the present invention.
  • VSYN is also called V The sync signal, which is a frame sync signal.
  • HSYN is also called the H sync signal, which is a line sync signal.
  • VBP is V sync The back porch is used to transmit some audio signals, etc. (where VACT delivers video signals within one frame time).
  • VFP is a V sync front porch with a blank time zone to prepare for the delivery of content in the next frame.
  • VS V Sync Low pulse.
  • VACT is the effective width of V sync.
  • HBP is the H sync back gallery, which is used to transmit some audio signals (HACT delivers video signals in one line).
  • HFP is H Sync front porch, blank time zone, ready to deliver content for the next frame.
  • HS is a H sync low pulse.
  • HACT is H Sync effective width.
  • DEN is the enable signal.
  • the 2to12 of the present invention Two circuit configurations of the De-mux driving architecture, wherein each of the first gate lines 40 simultaneously controls the opening and closing of the two second gate lines 50, as one of the first gate lines 40 (as shown in the figure) Gate n) When opened, there are 2 second gate lines 50 (Gate line1 and Gate in the figure) Line2) is opened, and the four first data lines 10 (such as Data1 (a), Data1 (b), Data 2 (a), and Data 2 (b) in the figure) are given two second data lines through the twelve second data lines 20, respectively.
  • each of the first gate lines 40 simultaneously controls the opening and closing of the two second gate lines 50, as one of the first gate lines 40 (as shown in the figure) Gate n)
  • there are 2 second gate lines 50 Gate line1 and Gate in the figure) Line2
  • the four first data lines 10 such as Data1 (a), Data1 (b), Data 2 (a), and Data 2 (b) in the figure
  • Gate line 50 (Gate in the figure) The pixel 60 on line1 and Gate line2) is charged; when the other first gate line 40 (Gate(n+1) in the figure) is turned on (Gate at this time) n off), then the other two second gate lines 50 (Gate line3 and Gate in the figure) The gate on line 4) is opened, and the four first data lines 10 (Data1(a), Data1(b), Data2(a), and Data2(b) in the figure) are respectively given through 12 second data lines 20 Second gate line 50 (Gate in the figure) Line3 and Gate The pixel 60 on line 4) is charged.
  • the De-mux driver architecture will reduce the number of gate lines by half, which is beneficial to reduce the area of the GOA control unit, thus facilitating the implementation of narrow borders.
  • 2to12 The number of data lines in the De-mux driver architecture remains the same as the number of data lines in the 2to6 De-mux driver architecture.
  • the first data line 10 is divided into a plurality of second data lines 20 by a demultiplexing controller 30, and connected to a row of pixels 60 in a one-to-one correspondence, which solves the prior art.
  • the present invention reduces the power consumption of the liquid crystal display panel, which is 2to12 De-mux (that is, a 2-pair 12-demultiplexer controller, specifically a data line connecting six pairs of pixels 60 that are not adjacent to each other) is introduced into the In cell under the driving architecture.
  • the touch panel ie, one substrate of the touch panel is disposed in the liquid crystal panel
  • 1to6 De-mux that is, a 1-to-6 demultiplexing controller, specifically a data line connecting six adjacent two adjacent pixels 60
  • the touch panel architecture is achievable, and at the same time, the liquid crystal display panel achieves a narrow frame, in 1to6 Under the De-mux combined RGBW driving scheme, the charging rate of the pixel 60 is improved, and at the same time, a narrow bezel is facilitated.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种阵列基板，包括栅极驱动器、数据驱动器及一驱动电路结构，驱动电路结构包括多个驱动电路单元，每个驱动电路单元包括：像素矩阵；多条第二栅极线（50）；多条第一数据线（10）；多个解多工控制器（30）。解决了现有技术中，由于数据线和栅极线条数增加导致的穿透率低、显示效果差的问题。

Description

一种阵列基板 技术领域
本发明涉及液晶显示领域，特别涉及一种阵列基板。
 背景技术
液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板(TFT-LCD)及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
传统液晶显示驱动电路的驱动结构如图1所示，即一个像素电极4上通过薄膜晶体管3分别接有一条数据线2和一条栅极线1，这种做法可以很好地控制每条栅极线1上栅极的打开、每条数据线2上数据的输入。但是，随着屏幕解析度的增加和分辨率的增加，数据线2和栅极线1的条数也会增加，从而影响穿透率、影响显示效果。为了保证屏幕解析度和穿透率不变，同时减少数据线的条数，现有技术中，有将1条数据线通过解多工控制器分成3条数据线，分别连接一行像素中的3个不同的像素，但是这种架构在常用的列反转显示情况下功耗较高。这种情况亟待改变。
 技术问题
本发明的目的在于提供一种阵列基板，以解决现有技术中，随着屏幕解析度的增加和分辨率的增加，数据线和栅极线的条数也会增加，从而影响穿透率、影响显示效果的问题。
 技术解决方案
本发明的技术方案如下：
一种阵列基板，其包括栅极驱动器、数据驱动器及一驱动电路结构，所述驱动电路结构包括多个驱动电路单元，每个所述驱动电路单元包括：
像素矩阵，包括多个像素，用于显示图像信号；
多条第二栅极线，每条所述第二栅极线用于驱动所述像素矩阵的一行像素；
多条第一数据线，与所述多条第二栅极线相垂直，其中一半设在所述像素矩阵的左边，另一半设在所述像素矩阵的右边，用于向对应的像素输入数据信号；
多个解多工控制器，用于将每一条所述第一数据线分为多条第二数据线，并分别对其进行开启与关闭的控制；
其中所述栅极驱动器设有多条第一栅极线，每条所述第一栅极线分为多条所述第二栅极线，多条所述第二栅极线分别一一对应地驱动所述像素矩阵的各行像素，所述数据驱动器设有所述多条第一数据线，每条所述第一数据线通过多个所述解多工控制器分为多条所述第二数据线，每个所述解多工控制器输出多条所述第二数据线并一一对应连接一行像素的一半像素，每行像素与2个所述解多工控制器输出的多条所述第二数据线一一对应连接，且该2个所述解多工控制器对应不同的所述第一数据线；
其中每条所述第一栅极线分为2条所述第二栅极，每个所述解多工控制器将每条所述第一数据线分为6条所述第二数据线。
优选地，其中在一个所述驱动电路单元中，所述数据驱动器对应设有4条所述第一数据线，所述驱动电路单元的左边与右边各设有2条所述第一数据线。
优选地，其中与每行像素一一对应连接的多条所述第二数据线所对应的2个所述解多工控制器，分别设在每个所述驱动电路单元的左右两边的一条所述第一数据线上。
优选地，其中每个所述解多工控制器输出的各条所述第二数据线，各自独立地输入不同或相同的灰阶信号到对应的像素上。
优选地，其中在一个所述驱动电路单元中，一个所述解多工控制器输出的多条所述第二数据线对应连接的一行像素中，各个像素两两之间不相邻。
优选地，其中源于同一条所述第一栅极线的2条所述第二栅极线，分别驱动所述像素矩阵中相邻的两行像素。
优选地，其中源于同一条所述第一栅极线的2条所述第二栅极线，分别驱动所述像素矩阵中不相邻的两行像素。
优选地，其中在一个所述驱动电路单元中，所述像素矩阵的每行像素个数为12个，所述像素矩阵的像素包括RGB三色像素或RGBW四色像素。
一种阵列基板，其包括栅极驱动器、数据驱动器及一驱动电路结构，所述驱动电路结构包括多个驱动电路单元，每个所述驱动电路单元包括：
像素矩阵，包括多个像素，用于显示图像信号；
多条第二栅极线，每条所述第二栅极线用于驱动所述像素矩阵的一行像素；
多条第一数据线，与所述多条第二栅极线相垂直，其中一半设在所述像素矩阵的左边，另一半设在所述像素矩阵的右边，用于向对应的像素输入数据信号；
多个解多工控制器，用于将每一条所述第一数据线分为多条第二数据线，并分别对其进行开启与关闭的控制；
其中所述栅极驱动器设有多条第一栅极线，每条所述第一栅极线分为多条所述第二栅极线，多条所述第二栅极线分别一一对应地驱动所述像素矩阵的各行像素，所述数据驱动器设有所述多条第一数据线，每条所述第一数据线通过多个所述解多工控制器分为多条所述第二数据线，每个所述解多工控制器输出多条所述第二数据线并一一对应连接一行像素的一半像素，每行像素与2个所述解多工控制器输出的多条所述第二数据线一一对应连接，且该2个所述解多工控制器对应不同的所述第一数据线。
优选地，其中每条所述第一栅极线分为2条所述第二栅极线。
优选地，其中每个所述解多工控制器将每条所述第一数据线分为6条所述第二数据线。
优选地，其中在一个所述驱动电路单元中，所述数据驱动器对应设有4条所述第一数据线，其中所述驱动电路单元的左边与右边各设有2条所述第一数据线。
优选地，其中与每行像素一一对应连接的多条所述第二数据线所对应的2个所述解多工控制器，分别设在每个所述驱动电路单元的左右两边的一条所述第一数据线上。
优选地，其中每个所述解多工控制器输出的各条所述第二数据线，各自独立地输入不同或相同的灰阶信号到对应的像素上。
优选地，其中在一个所述驱动电路单元中，一个所述解多工控制器输出的多条所述第二数据线对应连接的一行像素中，各个像素两两之间不相邻。
优选地，其中源于同一条所述第一栅极线的2条所述第二栅极线，分别驱动所述像素矩阵中相邻的两行像素。
优选地，其中源于同一条所述第一栅极线的2条所述第二栅极线，分别驱动所述像素矩阵中不相邻的两行像素。
优选地，其中在一个所述驱动电路单元中，所述像素矩阵的每行像素个数为12个，所述像素矩阵的像素包括RGB三色像素或RGBW四色像素。
 有益效果
本发明的一种阵列基板，通过解多工控制器将将第一数据线分为多条第二数据线，并一一对应地连接到一行像素上，解决了现有技术中，随着屏幕解析度的增加和分辨率的增加，数据线和栅极线的条数也会增加，从而影响穿透率、影响显示效果的问题。
 附图说明
图1为本发明实施例的一种阵列基板的一个驱动电路单元的整体结构示意图；
图2为本发明实施例的另一种阵列基板的一个驱动电路单元的整体结构示意图；
图3为现有技术的一种阵列基板的电路驱动结构示意图；
图4为本发明实施例的阵列基板的一个驱动电路单元的显示控制时序示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
实施例一
请参考图1，图1为本发明实施例的一种阵列基板的一个驱动电路单元的整体结构示意图，从图1可以看到，本发明的一种阵列基板，包括栅极驱动器、数据驱动器及一驱动电路结构，所述驱动电路结构包括多个驱动电路单元，每个所述驱动电路单元包括：
像素矩阵，包括多个像素60，用于显示图像信号。
多条第二栅极线50，每条所述第二栅极线50用于驱动所述像素矩阵的一行像素60。
多条第一数据线10，与所述多条第二栅极线50相垂直，其中一半设在所述像素矩阵的左边，另一半设在所述像素矩阵的右边，用于向对应的像素60输入数据信号。
多个解多工控制器30，用于将每一条所述第一数据线10分为多条第二数据线20，并分别对其进行开启与关闭的控制。
其中，所述栅极驱动器设有多条第一栅极线40，每条所述第一栅极线40分为多条所述第二栅极线50，多条所述第二栅极线50分别一一对应地驱动所述像素矩阵的各行像素60，所述数据驱动器设有所述多条第一数据线10，每条所述第一数据线10通过多个所述解多工控制器30分为多条所述第二数据线20，每个所述解多工控制器30输出多条所述第二数据线20并一一对应连接一行像素60的一半像素60，每行像素60与2个所述解多工控制器30输出的多条所述第二数据线20一一对应连接，且该2个所述解多工控制器30对应不同的所述第一数据线10。
在本实施例中，优选每条所述第一栅极线40分为2条所述第二栅极线50。
在本实施例中，优选每个所述解多工控制器30将每条所述第一数据线10分为6条所述第二数据线20。
在本实施例中，在一个所述驱动电路单元中，优选所述数据驱动器对应设有4条所述第一数据线10，其中所述驱动电路单元的左边与右边各设有2条所述第一数据线10。
在本实施例中，与每行像素60一一对应连接的多条所述第二数据线20所对应的2个所述解多工控制器30，分别设在每个所述驱动电路单元的左右两边的一条所述第一数据线10上。这种分配方式可以使得电路结构更加均匀合理。
在本实施例中，每个所述解多工控制器30输出的各条所述第二数据线20，各自独立地输入不同或相同的灰阶信号到对应的像素60上。这样就可以通过解多工控制器30独立地控制其每个输出口的信号，根据实际需要输出不同灰阶信号来进行显示。
在本实施例中，在一个所述驱动电路单元中，一个所述解多工控制器30输出的多条所述第二数据线20对应连接的一行像素60中，各个像素60两两之间不相邻。
在本实施例中，源于同一条所述第一栅极线40的2条所述第二栅极线50，分别驱动所述像素矩阵中相邻的两行像素60。
在本实施例中，源于同一条所述第一栅极线40的2条所述第二栅极线50，分别驱动所述像素矩阵中不相邻的两行像素60，这里请参考图2，图2为本发明实施例的另一种阵列基板的一个驱动电路单元的整体结构示意图。图2与图1的相同之处在于，图2的第一数据线10也通过多个解多工控制器30分为多条第二数据线20，并按照同样的方式连接到各行的像素60上去。不同之处在于，图2的第一栅极线40分成的多条第二栅极线50连接的各行像素60是不相邻的。
在本实施例中，在一个所述驱动电路单元中，所述像素矩阵的每行像素60的个数为12个，所述像素矩阵的像素60包括RGB三色像素矩阵或RGBW四色像素矩阵（RGBW四色像素矩阵的示意图未示出）。当所述像素矩阵的为RGB三色像素矩阵时，一个所述驱动电路单元的一行像素60中，包含4个像素单元，每个像素单元包含RGB 3个像素60。当所述像素矩阵的为RGBW四色像素矩阵时，一个所述驱动电路单元的一行像素60中，包含3个像素单元，每个像素单元包含RGBW 4个像素60。
如图4所示，图4为本发明实施例的阵列基板的一个驱动电路单元的显示控制时序示意图。其中，VSYN也叫 V sync信号，其为帧同步信号。HSYN也叫H sync信号，其为行同步信号。VBP为V sync 后廊，用来传递一些音频信号等(其中VACT传递的是一帧时间内的视频信号)。VFP为V sync 前廊，空白时间区域，可为下帧传递内容做些准备。VS为V sync 低电平脉冲。VACT为V sync有效宽度。HBP为H sync 后廊，用来传递一些音频信号等(其中HACT传递的是一行时间内视频信号)。HFP为H sync 前廊，空白时间区域，可为下帧传递内容做些准备。HS为H sync 低电平脉冲。HACT为H sync有效宽度。DEN为使能有效信号。CLK为晶振时钟。
本发明的工作过程如下：
如图1和图2所示，分别为本发明的2to12 De-mux驱动架构的两种电路结构形式，其中每条第一栅极线40同时控制两条第二栅极线50的开与关，当1条第一栅极线40（如图中的Gate n）打开时，则2条第二栅极线50（如图中的Gate line1和Gate line2）打开，4条第一数据线10（如图中的Data1(a)、Data1(b)、Data2(a)和Data2(b)）分别通过12条第二数据线20给2条第二栅极线50（如图中的Gate line1与 Gate line2）上的像素60充电；当另一条第一栅极线40（如图中的Gate( n+1)）打开时（此时Gate n关闭），则另2条第二栅极线50（如图中的Gate line3和Gate line4）上的栅极被打开，4条第一数据线10（如图中的Data1(a)、Data1(b)、Data2(a)和Data2(b)）分别通过12第二数据线20给第二栅极线50（如图中的Gate line3与 Gate line4）上的像素60充电。其中，每次充电的时候，每条第二数据线20对与其连接的像素60进行独立的充电控制，并非所有第二数据线20同时对相关的像素60进行充电，而是一部分充电另一部分不充电。本发明的2to12 De-mux驱动架构相较于现有技术的2to6 De-mux驱动架构会缩减栅极线的条数为原来的一半，有益于缩减GOA控制单元的面积，从而有利于窄边框的实现，另外2to12 De-mux驱动架构的数据线条数依然保持与2to6 De-mux驱动架构的数据线条数相同。
现有技术中，以将1条数据线通过解多工控制器30分成3条数据线，分别连接一行像素60中的3个不同的像素60的技术方案为例，这种驱动电路共有1080条数据线，1920条栅极线，一帧充电显示时间为16.7ms,则每条栅极线的充电时间约为(16.7/1920)ms, 这样的话，其中每个像素60的充电时间大约为 (16.7/1920)/(1080*3)ms。而本发明的技术方案中，一帧充电显示的时间大约为16.7ms,则每条栅极线的充电时间约为16.7/(1920/2)ms，这样的话，其中每个像素60的充电时间约为16.7/(1920/2)/(1080*3)ms，即每个像素60的充电时间增加。由于充电时间的增加，为在本发明的技术方案提供了时间保证，从而使本发明的技术方案能变为现实。
本发明的一种阵列基板，通过解多工控制器30将将第一数据线10分为多条第二数据线20，并一一对应地连接到一行像素60上，解决了现有技术中，随着屏幕解析度的增加和分辨率的增加，数据线和栅极线的条数也会增加，从而影响穿透率、影响显示效果的问题。另外，本发明降低了液晶显示面板的功耗，为2to12 De-mux（即2对12解多工控制器，具体来说是一条数据线连接6个两两不相邻的像素60）驱动架构下引入In cell 触控面板（即触控面板的一个基板设置在液晶面板中），提供了充电时间的保证，使1to6 De-mux（即1对6解多工控制器，具体来说是一条数据线连接6个两两相邻的像素60）组合In cell 触控面板架构具有可实现性，同时使液晶显示面板实现窄边框化，在1to6 De-mux组合RGBW驱动方案下，提升了像素60的充电率，同时有利于实现窄边框。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种阵列基板，其包括栅极驱动器、数据驱动器及一驱动电路结构，所述驱动电路结构包括多个驱动电路单元，每个所述驱动电路单元包括：
    像素矩阵，包括多个像素，用于显示图像信号；
    多条第二栅极线，每条所述第二栅极线用于驱动所述像素矩阵的一行像素；
    多条第一数据线，与所述多条第二栅极线相垂直，其中一半设在所述像素矩阵的左边，另一半设在所述像素矩阵的右边，用于向对应的像素输入数据信号；
    多个解多工控制器，用于将每一条所述第一数据线分为多条第二数据线，并分别对其进行开启与关闭的控制；
    其中所述栅极驱动器设有多条第一栅极线，每条所述第一栅极线分为多条所述第二栅极线，多条所述第二栅极线分别一一对应地驱动所述像素矩阵的各行像素，所述数据驱动器设有所述多条第一数据线，每条所述第一数据线通过多个所述解多工控制器分为多条所述第二数据线，每个所述解多工控制器输出多条所述第二数据线并一一对应连接一行像素的一半像素，每行像素与2个所述解多工控制器输出的多条所述第二数据线一一对应连接，且该2个所述解多工控制器对应不同的所述第一数据线；
    其中每条所述第一栅极线分为2条所述第二栅极，每个所述解多工控制器将每条所述第一数据线分为6条所述第二数据线。
  2. 根据权利要求1所述的阵列基板，其中在一个所述驱动电路单元中，所述数据驱动器对应设有4条所述第一数据线，所述驱动电路单元的左边与右边各设有2条所述第一数据线。
  3. 根据权利要求1所述的阵列基板，其中与每行像素一一对应连接的多条所述第二数据线所对应的2个所述解多工控制器，分别设在每个所述驱动电路单元的左右两边的一条所述第一数据线上。
  4. 根据权利要求1所述的阵列基板，其中每个所述解多工控制器输出的各条所述第二数据线，各自独立地输入不同或相同的灰阶信号到对应的像素上。
  5. 根据权利要求1所述的阵列基板，其中在一个所述驱动电路单元中，一个所述解多工控制器输出的多条所述第二数据线对应连接的一行像素中，各个像素两两之间不相邻。
  6. 根据权利要求1所述的阵列基板，其中源于同一条所述第一栅极线的2条所述第二栅极线，分别驱动所述像素矩阵中相邻的两行像素。
  7. 根据权利要求1所述的阵列基板，其中源于同一条所述第一栅极线的2条所述第二栅极线，分别驱动所述像素矩阵中不相邻的两行像素。
  8. 根据权利要求1所述的阵列基板，其中在一个所述驱动电路单元中，所述像素矩阵的每行像素个数为12个，所述像素矩阵的像素包括RGB三色像素或RGBW四色像素。
  9. 一种阵列基板，其包括栅极驱动器、数据驱动器及一驱动电路结构，所述驱动电路结构包括多个驱动电路单元，每个所述驱动电路单元包括：
    像素矩阵，包括多个像素，用于显示图像信号；
    多条第二栅极线，每条所述第二栅极线用于驱动所述像素矩阵的一行像素；
    多条第一数据线，与所述多条第二栅极线相垂直，其中一半设在所述像素矩阵的左边，另一半设在所述像素矩阵的右边，用于向对应的像素输入数据信号；
    多个解多工控制器，用于将每一条所述第一数据线分为多条第二数据线，并分别对其进行开启与关闭的控制；
    其中所述栅极驱动器设有多条第一栅极线，每条所述第一栅极线分为多条所述第二栅极线，多条所述第二栅极线分别一一对应地驱动所述像素矩阵的各行像素，所述数据驱动器设有所述多条第一数据线，每条所述第一数据线通过多个所述解多工控制器分为多条所述第二数据线，每个所述解多工控制器输出多条所述第二数据线并一一对应连接一行像素的一半像素，每行像素与2个所述解多工控制器输出的多条所述第二数据线一一对应连接，且该2个所述解多工控制器对应不同的所述第一数据线。
  10. 根据权利要求9所述的阵列基板，其中每条所述第一栅极线分为2条所述第二栅极线。
  11. 根据权利要求9所述的阵列基板，其中每个所述解多工控制器将每条所述第一数据线分为6条所述第二数据线。
  12. 根据权利要求9所述的阵列基板，其中在一个所述驱动电路单元中，所述数据驱动器对应设有4条所述第一数据线，其中所述驱动电路单元的左边与右边各设有2条所述第一数据线。
  13. 根据权利要求9所述的阵列基板，其中与每行像素一一对应连接的多条所述第二数据线所对应的2个所述解多工控制器，分别设在每个所述驱动电路单元的左右两边的一条所述第一数据线上。
  14. 根据权利要求9所述的阵列基板，其中每个所述解多工控制器输出的各条所述第二数据线，各自独立地输入不同或相同的灰阶信号到对应的像素上。
  15. 根据权利要求9所述的阵列基板，其中在一个所述驱动电路单元中，一个所述解多工控制器输出的多条所述第二数据线对应连接的一行像素中，各个像素两两之间不相邻。
  16. 根据权利要求9所述的阵列基板，其中源于同一条所述第一栅极线的2条所述第二栅极线，分别驱动所述像素矩阵中相邻的两行像素。
  17. 根据权利要求9所述的阵列基板，其中源于同一条所述第一栅极线的2条所述第二栅极线，分别驱动所述像素矩阵中不相邻的两行像素。
  18. 根据权利要求9所述的阵列基板，其中在一个所述驱动电路单元中，所述像素矩阵的每行像素个数为12个，所述像素矩阵的像素包括RGB三色像素或RGBW四色像素。
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