WO2018035689A1 - 一种高效率高宽带的谐波功率放大电路及射频功率放大器 - Google Patents

一种高效率高宽带的谐波功率放大电路及射频功率放大器 Download PDF

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WO2018035689A1
WO2018035689A1 PCT/CN2016/096274 CN2016096274W WO2018035689A1 WO 2018035689 A1 WO2018035689 A1 WO 2018035689A1 CN 2016096274 W CN2016096274 W CN 2016096274W WO 2018035689 A1 WO2018035689 A1 WO 2018035689A1
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transmission line
matching network
transistor
amplifying circuit
network
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PCT/CN2016/096274
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English (en)
French (fr)
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朱守奎
丁庆
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深圳市华讯方舟微电子科技有限公司
华讯方舟科技有限公司
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Priority to PCT/CN2016/096274 priority Critical patent/WO2018035689A1/zh
Priority to US16/327,483 priority patent/US11552599B2/en
Priority to EP16913713.0A priority patent/EP3503388A4/en
Publication of WO2018035689A1 publication Critical patent/WO2018035689A1/zh

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217Class D power amplifiers; Switching amplifiers
    • H03F3/2176Class E amplifiers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/36Circuit design at the analogue level
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42Modifications of amplifiers to extend the bandwidth
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56Modifications of input or output impedances, not otherwise provided for
    • H03F1/565Modifications of input or output impedances, not otherwise provided for using inductive elements
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217Class D power amplifiers; Switching amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217Class D power amplifiers; Switching amplifiers
    • H03F3/2171Class D power amplifiers; Switching amplifiers with field-effect devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H03F3/601Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators using FET's, e.g. GaAs FET's
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/165A filter circuit coupled to the input of an amplifier
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/171A filter circuit coupled to the output of an amplifier
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/222A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/387A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/423Amplifier output adaptation especially for transmission line coupling purposes, e.g. impedance adaptation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/451Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the invention belongs to the field of radio frequency communication, and particularly relates to a high efficiency and high bandwidth harmonic power amplifying circuit and a radio frequency power amplifier.
  • High-efficiency, high-bandwidth power amplifiers are generally designed based on the structure of a class-E power amplifier structure and a harmonic control-type power amplifier.
  • the class E power amplifier has a simple structure and high efficiency, since the class E power amplifier theoretically has an upper operating frequency limit, it limits the further application of the class E power amplifier in a higher frequency range;
  • harmonic control power amplifiers that are suitable for higher operating frequencies, such as Class F power amplifiers and inverse Class F power amplifiers, not only accurate harmonic impedance control at the transistor drain but also narrow bandwidth is required to expand the bandwidth.
  • a continuous harmonic control type power amplifier has been developed, including a continuous class F power amplifier and a continuous inverse class F power amplifier, but a continuous class F power amplifier and a continuous inverse F Class-type power amplifiers need to satisfy the impedance conditions of the second harmonic and the third harmonic simultaneously within a certain bandwidth when providing more than 70% efficiency and a relative bandwidth greater than 50%, which brings great challenges to the design of the matching circuit, and Its complex matching circuit deteriorates efficiency to some extent.
  • An object of the embodiments of the present invention is to provide a high efficiency and high bandwidth harmonic power amplifier circuit. In solving the problem that the existing power amplifying circuit cannot simultaneously achieve high efficiency, high bandwidth, and easy harmonic impedance matching.
  • Input matching network transistor and output matching network
  • An input end of the input matching network is an input end of the harmonic power amplifying circuit, an output end of the input matching network is connected to a gate of the transistor, and a drain of the transistor is matched with the output matching network
  • the input terminal is connected, the source of the transistor is grounded, and the output end of the output matching network is an output end of the harmonic power amplifying circuit;
  • the output matching network causes the lower sideband of the harmonic power amplifying circuit to operate in a continuous inverse F-type amplification mode, so that the sideband of the harmonic power amplifying circuit operates in a continuous F-type amplification mode;
  • the output matching network forms a low pass filter with the parasitic network of the transistor.
  • Another object of embodiments of the present invention is to provide a radio frequency power amplifier using the above-described high efficiency and high bandwidth harmonic power amplifying circuit.
  • Another object of the present invention is to provide a method for designing an output matching network in a high-efficiency and high-bandwidth harmonic power amplifying circuit, the method comprising:
  • the third-order low-pass network prototype parameters are obtained by looking up the table, and the frequency and impedance transformation are performed according to the third-order low-pass network prototype parameters, design frequency and reference impedance, and a real impedance-real impedance transformer is obtained.
  • the embodiment of the invention combines a continuous class F power amplifier with a continuous inverse class F power amplifier, and expands the single continuous type by the operation mode of the continuous inverse class F power amplifier to the continuous operation mode of the class F power amplifier.
  • the design space of the harmonic control type power amplifier effectively increases the efficiency of the continuous harmonic control type power amplifier to more than 60%, increases the relative bandwidth to more than 80%, and the harmonic impedance matching is simple and easy to implement.
  • FIG. 1 is a structural diagram of a high efficiency and high bandwidth harmonic power amplifying circuit according to an embodiment of the present invention
  • Figure 2 is a Smith chart of a continuous class F power amplifier
  • Figure 3 is a Smith chart of a continuous inverse class F power amplifier
  • FIG. 4 is a topological structural diagram of a third-order low-pass filter formed by an output matching network and a parasitic network of a transistor in a high-efficiency and high-bandwidth harmonic power amplifier circuit according to an embodiment of the present invention
  • FIG. 5 is a parasitic network diagram of a transistor in a high efficiency and high bandwidth harmonic power amplifier circuit according to an embodiment of the present invention
  • FIG. 6 is a schematic flowchart of a method for designing an output matching network in a high-efficiency and high-bandwidth harmonic power amplifying circuit according to an embodiment of the present invention.
  • Embodiments of the present invention combine a continuous class F power amplifier with a continuous inverse class F power amplifier
  • the operation mode of the continuous type F power amplifier is extended to the continuous type F power amplifier, and the design space of a single continuous harmonic control type power amplifier is broadened, and the continuous harmonic control power is effectively
  • the efficiency of the amplifier is increased to more than 60%, the relative bandwidth is increased to more than 80%, and the harmonic impedance matching is simple and easy to implement.
  • FIG. 1 shows the structure of a high efficiency and high bandwidth harmonic power amplifying circuit according to an embodiment of the present invention. For the convenience of description, only parts related to the present invention are shown.
  • the high efficiency and high bandwidth harmonic power amplifying circuit can be applied to any radio frequency power amplifier, including:
  • Input matching network 11 transistor M and output matching network 12;
  • the input end of the input matching network 11 is connected to the input end of the harmonic power amplifier circuit and the end of the capacitor C i in the bias unit, and the other end of the capacitor C i is the RF input end, and the output end of the input matching network 11 and the transistor M
  • the gate is connected, the drain of the transistor M is connected to the input of the output matching network 12, the source of the transistor M is grounded, and the output of the output matching network 12 is the output of the harmonic power amplifying circuit and the capacitor in the biasing unit.
  • One end of C o is connected, and the other end of the capacitor C o is a radio frequency output end, and the bias end of the input matching network 11 is connected to the gate-source voltage V GS through the inductor L G and the capacitor C b1 in the bias unit to output the matching network 12
  • the bias terminal is connected to the drain-source voltage V DS through the inductor L D and the capacitor C b2 in the bias unit;
  • the output matching network 12 enables the lower sideband of the harmonic power amplifier circuit to operate in the continuous inverse class F amplification mode, so that the sidebands of the harmonic power amplifier circuit operate in the continuous class F amplification mode;
  • the output matching network 12 forms a low pass filter with the parasitic network of transistor M.
  • the current waveform of the continuous type F power amplifier is half sinusoidal, and the voltage waveform is not unique.
  • the normalized voltage expression is as follows :
  • the range of ⁇ is: -1 ⁇ ⁇ ⁇ 1.
  • the current waveform is not unique, and its normalized expression is as follows:
  • n the order of the harmonic components.
  • R opt is the optimal impedance of a standard Class B power amplifier with short-circuits of higher harmonics.
  • the expression (5) constitutes the design space of the continuous class F power amplifier, and the normalized impedance of the Smith chart is set to R opt , so that the design space of the continuous class F power amplifier is expressed on the Smith chart.
  • Figure 2 shows.
  • Expression (6) constitutes the design space of the continuous inverse class F power amplifier.
  • the normalized impedance of the Smith chart is also set to R opt , so that the design space of the continuous inverse class F power amplifier is on the Smith chart.
  • the representation is shown in Figure 3.
  • the lower sideband of the harmonic power amplifying circuit operates in a continuous inverse class F amplification mode
  • the upper sideband operates in a continuous class F amplification mode through a continuous inverse class F power amplifier operating mode.
  • the excessive operation mode of the continuous class F power amplifier broadens the design space of a single continuous harmonic control class power amplifier, effectively improving efficiency and relative bandwidth.
  • the input matching network 11 can be configured as a fourth-order low pass filter that effectively reduces the area of the input matching network relative to the multi-section impedance transformer.
  • the transistor M can be selected from Cree's GaN transistor CGH40010F, which operates at a frequency of 0-6 GHz and has a typical output power of 10 W.
  • the output matching network 12 forms a third-order low-pass filter with the parasitic network of the transistor, which reduces design difficulty, and the design method can be flexibly adapted to different operating frequencies and different characteristic impedances.
  • the input end of the parasitic network of the transistor is connected to the intrinsic drain of the transistor, and the output end of the parasitic network of the transistor is connected to the input end of the output matching network.
  • the topology of the third-order low-pass filter is shown in Figure 4, including:
  • One end of the inductor L1 is the input end of the parasitic network, the other end of the inductor L1 is grounded through the capacitor C1, the other end of the inductor L1 is also connected to one end of the inductor L2, and the other end of the inductor L2 is grounded through the capacitor C2, and the other end of the inductor L2 is also Connected to one end of the inductor L3, the other end of the inductor L3 is the output of the parasitic network grounded through the capacitor C3.
  • the flow structure of the design method of the output matching network 12 is shown in FIG. 6, and specifically includes the following steps:
  • step S101 the APS loadpull simulation tool is used to obtain the optimal fundamental impedance of the continuous inverse F-class amplification mode of the harmonic power amplifier circuit at the operating frequency f1 and the continuous F class at the operating frequency f2.
  • the optimal fundamental impedance of the amplification mode
  • step S102 the third-order low-pass network prototype parameters are obtained by looking up the table, and the frequency and impedance transformation are performed according to the third-order low-pass network prototype parameters, the design frequency and the reference impedance, to obtain a real impedance-real impedance transformer;
  • step S103 the real impedance-real impedance transformer is optimized to a real impedance-complex impedance converter by ADS in combination with a parasitic network parameter of the transistor, the complex impedance being equal to the optimal fundamental impedance;
  • step S104 a topology is established according to the third-order low-pass network prototype parameters, and the capacitance and inductance in the topology are replaced with transmission lines.
  • the inductor can be replaced with a high impedance transmission line that is replaced with a low impedance open stub transmission line.
  • the method further includes:
  • Step S105 after the topology is connected to the transistor, the length of the transmission line is adjusted by HB simulation to maximize the efficiency.
  • an output matching network is used, and 1 is a star transmission line structure, including:
  • One end of the first transmission line TL1 is an input end of the output matching network, and the other end of the first transmission line TL1 is simultaneously connected to one end of the second transmission line TL2, the third transmission line TL3, and the fourth transmission line TL4, and the other end of the second transmission line TL2 is an output.
  • the other end of the fourth transmission line TL4 is connected to one end of the fifth transmission line TL5, the sixth transmission line TL6, and the seventh transmission line TL7, and the other end of the seventh transmission line TL7 is simultaneously connected to the eighth transmission line TL8 and the ninth transmission line.
  • One end of the TL9 and the tenth transmission line TL10, and the other end of the tenth transmission line TL10 is an output end of the output matching network.
  • f1 is the center frequency of the lower half band
  • f2 is the center frequency of the upper half band
  • Another object of embodiments of the present invention is to provide a radio frequency power amplifier using the above-described high efficiency and high bandwidth harmonic power amplifying circuit.

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  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种高效率高宽带的谐波功率放大电路及射频功率放大器,该电路包括:输入匹配网络(11)、晶体管(M)及输出匹配网络(12);晶体管(M)的栅极连接输入匹配网络(11)的输出端,晶体管(M)的漏极连接输出匹配网络(12)的输入端,晶体管(M)的源极接地;输出匹配网络(12)使谐波功率放大电路下边带工作在连续型逆F类放大模式,使上边带工作在连续型F类放大模式;输出匹配网络(12)与晶体管(M)的寄生网络形成低通滤波器。通过连续型逆F类功率放大器工作模式向连续型F类功率放大器工作模式的过度,有效地将连续型谐波控制类功率放大器的效率提高到大于60%,将相对带宽提高到大于80%,并且谐波阻抗匹配简单、容易实现。

Description

一种高效率高宽带的谐波功率放大电路及射频功率放大器 技术领域
本发明属于射频通信领域,尤其涉及一种高效率高宽带的谐波功率放大电路及射频功率放大器。
背景技术
目前第五代移动通信系统对通信标准的兼容性要求越来越强大,从而对射频功率放大器的带宽要求也越来越高,同时,随着绿色经济的进一步发展,市场对功率放大器的效率也要求越来越高。而高效率、高宽带的功率放大器一般主要基于E类功率放大器结构和谐波控制类功率放大器的结构进行设计。
然而,E类功率放大器虽然结构简单,效率高,但是由于E类功率放大器理论上存在工作频率上限,从而限制了E类功率放大器在较高频率范围的进一步应用;
而对于适用于较高工作频率的谐波控制类功率放大器,例如F类功率放大器和逆F类功率放大器,不仅需要在晶体管漏极进行精确的谐波阻抗的控制,而且带宽窄,为了扩展带宽,基于谐波控制类功率放大器结构发展出了连续型谐波控制类功率放大器,包括连续型F类功率放大器和连续型逆F类功率放大器,但是,连续型F类功率放大器和连续型逆F类功率放大器在提供大于70%的效率和大于50%的相对带宽时需要在一定的带宽内同时满足二次谐波和三次谐波的阻抗条件,给匹配电路的设计带来了巨大挑战,并且其复杂的匹配电路在一定程度上恶化了效率。
技术问题
本发明实施例的目的在于提供一种高效率高宽带的谐波功率放大电路,旨 在解决现有功率放大电路无法同时实现高效率、高宽带,并且谐波阻抗匹配容易的问题。
技术解决方案
本发明实施例是这样实现的,一种高效率高宽带的谐波功率放大电路,所述谐波功率放大电路包括:
输入匹配网络、晶体管及输出匹配网络;
所述输入匹配网络的输入端为所述谐波功率放大电路的输入端,所述输入匹配网络的输出端与所述晶体管的栅极连接,所述晶体管的漏极与所述输出匹配网络的输入端连接,所述晶体管的源极接地,所述输出匹配网络的输出端为所述谐波功率放大电路的输出端;
所述输出匹配网络使所述谐波功率放大电路下边带工作在连续型逆F类放大模式,使所述谐波功率放大电路上边带工作在连续型F类放大模式;
所述输出匹配网络与所述晶体管的寄生网络形成低通滤波器。
本发明实施例的另一目的在于,提供一种采用上述高效率高宽带的谐波功率放大电路的射频功率放大器。
本发明实施例的另一目的在于,提供一种上述高效率高宽带的谐波功率放大电路中输出匹配网络的设计方法,所述方法包括:
运用仿真工具分别获取所述谐波功率放大电路在工作频率f1下的连续型逆F类放大模式的最优基波阻抗和在工作频率f2下的连续型F类放大模式的最优基波阻抗;
通过查表得到三阶低通网络原型参数,并根据三阶低通网络原型参数、设计频率和参考阻抗进行频率和阻抗变换,得到实数阻抗-实数阻抗变换器;
结合晶体管的寄生网络参数,将实数阻抗-实数阻抗变换器优化为实数阻抗-复数阻抗变换器,所述复数阻抗等于所述最优基波阻抗;
根据三阶低通网络原型参数建立拓扑结构,并将所述拓扑结构中的电容和 电感替换为传输线。
有益效果
本发明实施例将连续型F类功率放大器和连续型逆F类功率放大器结合起来,通过连续型逆F类功率放大器工作模式向连续型F类功率放大器工作模式的过度,拓宽了单一的连续型谐波控制类功率放大器的设计空间,有效地将连续型谐波控制类功率放大器的效率提高到大于60%,将相对带宽提高到大于80%,并且谐波阻抗匹配简单、容易实现。
附图说明
图1为本发明实施例提供的高效率高宽带的谐波功率放大电路的结构图;
图2为连续型F类功率放大器的Smith圆图;
图3为连续型逆F类功率放大器的Smith圆图;
图4为本发明实施例提供的高效率高宽带的谐波功率放大电路中输出匹配网络与晶体管的寄生网络形成的三阶低通滤波器的拓扑结构图;
图5为本发明实施例提供的高效率高宽带的谐波功率放大电路中晶体管的寄生网络图;
图6为本发明实施例提供的高效率高宽带的谐波功率放大电路中输出匹配网络的设计方法的流程结构。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。此外,下面所描述的本发明各个实施方式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。
本发明实施例将连续型F类功率放大器和连续型逆F类功率放大器结合起 来,通过连续型逆F类功率放大器工作模式向连续型F类功率放大器工作模式的过度,拓宽了单一的连续型谐波控制类功率放大器的设计空间,有效地将连续型谐波控制类功率放大器的效率提高到大于60%,将相对带宽提高到大于80%,并且谐波阻抗匹配简单、容易实现。
以下结合具体实施例对本发明的实现进行详细描述:
图1示出了本发明实施例提供的高效率高宽带的谐波功率放大电路的结构,为了便于说明,仅示出了与本发明相关的部分。
作为本发明一实施例,该高效率高宽带的谐波功率放大电路可以应用于任何射频功率放大器中,包括:
输入匹配网络11、晶体管M及输出匹配网络12;
输入匹配网络11的输入端为谐波功率放大电路的输入端与偏置单元中的电容Ci的一端连接,电容Ci的另一端为射频输入端,输入匹配网络11的输出端与晶体管M的栅极连接,晶体管M的漏极与输出匹配网络12的输入端连接,晶体管M的源极接地,输出匹配网络12的输出端为谐波功率放大电路的输出端与偏置单元中的电容Co的一端连接,电容Co的另一端为射频输出端,输入匹配网络11的偏置端通过偏置单元中的电感LG和电容Cb1连接栅源电压VGS,输出匹配网络12的偏置端通过偏置单元中的电感LD和电容Cb2连接漏源电压VDS
输出匹配网络12使谐波功率放大电路下边带工作在连续型逆F类放大模式,使谐波功率放大电路上边带工作在连续型F类放大模式;
输出匹配网络12与晶体管M的寄生网络形成低通滤波器。
在本发明实施例中,根据波形设计理论,连续型F类功率放大器的电流波形为半正弦,而电压波形并不唯一,在只考虑三次谐波的情况下,归一化的电压表达式如下:
Figure PCTCN2016096274-appb-000001
因为负电压的出现会恶化效率,所以为了保证电压非负,γ的取值范围为:-1≤γ≤1。当γ=0时,便得到标准的F类功率放大器电压波形。
对连续型逆F类功率放大器来说,由于它和F类功率放大器互为对偶关系,因此,在只考虑三次谐波的情况下,连续型逆F类功率放大器的电压唯一确定,它的归一化表达式如下:
Figure PCTCN2016096274-appb-000002
而电流波形不唯一,它的归一化表达式如下:
Figure PCTCN2016096274-appb-000003
其中,iDC=0.37,i1=0.43,i3=0.06。为了保证电流波形的非负,ξ的取值范围是:-1≤ξ≤1。当ξ=0时,便得到标准的逆F类功率放大器电压波形。
根据公式:
Figure PCTCN2016096274-appb-000004
其中,n表示谐波分量的阶次。由连续型F类功率放大器的电压波形和电流波形表达式,我们能够得出连续型F类功率放大器的阻抗条件:
Figure PCTCN2016096274-appb-000005
Figure PCTCN2016096274-appb-000006
Z3,F=∞            (5)
其中,Ropt为高次谐波均短路的标准B类功率放大器的最优阻抗。
类似的,我们能够推导出连续型逆F类功率放大器的阻抗条件,为了表示的方便,我们采用导纳的表达形式:
Figure PCTCN2016096274-appb-000007
Figure PCTCN2016096274-appb-000008
Figure PCTCN2016096274-appb-000009
其中,Gopt=1/Ropt。
表达式(5)构成了连续型F类功率放大器的设计空间,把Smith圆图的归一化阻抗设为Ropt,这样连续型F类功率放大器的设计空间在Smith圆图上的表示便如图2所示。表达式(6)构成了连续型逆F类功率放大器的设计空间,同样把Smith圆图的归一化阻抗设为Ropt,这样连续型逆F类功率放大器的设计空间在Smith圆图上的表示便如图3所示。
由于基波阻抗在圆点附近,而二次谐波阻抗和三次谐波阻抗都位于圆边上,因此需要一个低通滤波器作为输出匹配。
那么通过设计一个输出匹配网络12,使该谐波功率放大电路下边带工作在连续型逆F类放大模式,上边带工作在连续型F类放大模式,通过连续型逆F类功率放大器工作模式向连续型F类功率放大器工作模式的过度,拓宽了单一的连续型谐波控制类功率放大器的设计空间,有效地提高效率和相对带宽。
优选地,输入匹配网络11可以设置为四阶低通滤波器,相对于多节阻抗变换器,有效地减小了输入匹配网络的面积。
优选地,晶体管M可以选用Cree公司的GaN晶体管CGH40010F,它的工作频率为0-6GHz,典型输出功率是10W。
优选地,输出匹配网络12与晶体管的寄生网络形成三阶低通滤波器,降低了设计难度,并且这种设计方法能够灵活适用于不同工作频率和不同的特征阻抗。其中,晶体管的寄生网络的输入端连接晶体管的固有漏极,晶体管的寄生网络的输出端连接输出匹配网络的输入端。
三阶低通滤波器的拓扑结构参见图4,包括:
电感L1、电感L2、电感L3、电容C1、电容C2、电容C3;
电感L1的一端为寄生网络的输入端,电感L1的另一端通过电容C1接地,电感L1的另一端还与电感L2的一端连接,电感L2的另一端通过电容C2接地,电感L2的另一端还与电感L3的一端连接,电感L3的另一端为寄生网络的输出端通过电容C3接地。
晶体管的寄生网络参见图5,包括:
电感Lp、电容Cds和电容Cp
电感Lp的一端为寄生网络的输入端与电容Cds的一端连接,电感Lp的另一端为寄生网络的输出端与电容Cp的一端连接,电容Cp的另一端与电容Cds的另一端连接。
输出匹配网络12的设计方法的流程结构参见图6,具体包括下述步骤:
在步骤S101中,运用ADS的loadpull仿真工具分别获取所述谐波功率放大电路在工作频率f1下的连续型逆F类放大模式的最优基波阻抗和在工作频率f2下的连续型F类放大模式的最优基波阻抗;
在步骤S102中,通过查表得到三阶低通网络原型参数,并根据三阶低通网络原型参数、设计频率和参考阻抗进行频率和阻抗变换,得到实数阻抗-实数阻抗变换器;
在步骤S103中,结合晶体管的寄生网络参数,通过ADS将实数阻抗-实数阻抗变换器优化为实数阻抗-复数阻抗变换器,所述复数阻抗等于所述最优基波阻抗;
在步骤S104中,根据三阶低通网络原型参数建立拓扑结构,并将所述拓扑结构中的电容和电感替换为传输线。
作为本发明一实施例,可以将所述电感替换为高阻抗传输线,将所述电容替换为低阻抗开路枝节传输线。
优选地,在步骤S104后还可以进一步包括:
步骤S105,将所述拓扑结构与晶体管连接后,通过HB仿真,调节所述传输线的长度,使效率达到最大。
作为本发明一实施例,结合图1,输出匹配网络,1为星型传输线结构,包括:
第一传输线TL1、第二传输线TL2、第三传输线TL3、第四传输线TL4、第五传输线TL5、第六传输线TL6、第七传输线TL7、第八传输线TL8、第九传输线TL9、第十传输线TL10;
第一传输线TL1的一端为输出匹配网络的输入端,第一传输线TL1的另一端同时与第二传输线TL2、第三传输线TL3、第四传输线TL4的一端连接,第二传输线TL2的另一端为输出匹配网络的偏置端,第四传输线TL4的另一端同时连接第五传输线TL5、第六传输线TL6、第七传输线TL7的一端,第七传输线TL7的另一端同时连接第八传输线TL8、第九传输线TL9、第十传输线TL10的一端,第十传输线TL10的另一端为输出匹配网络的输出端。
在本发明实施例中,设f1为下半边带的中心频率,f2为上半边带的中心频率,f1和f2存在这样的近似关系:f1=2/3f2。由于设计输出匹配网络使下边带工作在连续型逆F类模式,使上边带工作在连续型F类模式,那么在f1这个频点上谐波功率放大电路工作在标准的逆F类模式,而在f2这个频点上谐波功率放大电路工作在标准的F类模式。
将连续型F类功率放大器和连续型逆F类功率放大器结合起来,通过连续型逆F类功率放大器工作模式向连续型F类功率放大器工作模式的过度,拓宽了单一的连续型谐波控制类功率放大器的设计空间,有效地将连续型谐波控制类功率放大器的效率提高到大于60%,将相对带宽提高到大于80%,并且谐波阻抗匹配简单、容易实现。
本发明实施例的另一目的在于,提供一种采用上述高效率高宽带的谐波功率放大电路的射频功率放大器。
以上仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种高效率高宽带的谐波功率放大电路,其特征在于,所述谐波功率放大电路包括:
    输入匹配网络、晶体管及输出匹配网络;
    所述输入匹配网络的输入端为所述谐波功率放大电路的输入端,所述输入匹配网络的输出端与所述晶体管的栅极连接,所述晶体管的漏极与所述输出匹配网络的输入端连接,所述晶体管的源极接地,所述输出匹配网络的输出端为所述谐波功率放大电路的输出端;
    所述输出匹配网络使所述谐波功率放大电路下边带工作在连续型逆F类放大模式,使所述谐波功率放大电路上边带工作在连续型F类放大模式;
    所述输出匹配网络与所述晶体管的寄生网络形成低通滤波器。
  2. 如权利要求1所述的谐波功率放大电路,其特征在于,所述输入匹配网络为四阶低通滤波器。
  3. 如权利要求1所述的谐波功率放大电路,其特征在于,所述谐波功率放大电路下边带的中心频率与上半边带的中心频率关系为:
    f1=2/3f2,其中f1为下半边带的中心频率,f2为上半边带的中心频率。
  4. 如权利要求1所述的谐波功率放大电路,其特征在于,所述晶体管为GaN晶体管,所述晶体管的工作频率为0-6GHz,所述晶体管的输出功率为10W。
  5. 如权利要求1所述的谐波功率放大电路,其特征在于,所述输出匹配网络与所述晶体管的寄生网络形成三阶低通滤波器,所述晶体管的寄生网络的输入端连接晶体管的固有漏极,所述晶体管的寄生网络的输出端连接所述输出匹配网络的输入端;
    所述三阶低通滤波器的拓扑结构包括:
    电感L1、电感L2、电感L3、电容C1、电容C2、电容C3;
    所述电感L1的一端为所述寄生网络的输入端,所述电感L1的另一端通过所述电容C1接地,所述电感L1的另一端还与所述电感L2的一端连接,所述 电感L2的另一端通过所述电容C2接地,所述电感L2的另一端还与所述电感L3的一端连接,所述电感L3的另一端为所述寄生网络的输出端通过所述电容C3接地。
  6. 如权利要求1所述的谐波功率放大电路,其特征在于,所述输出匹配网络为星型传输线结构,包括:
    第一传输线、第二传输线、第三传输线、第四传输线、第五传输线、第六传输线、第七传输线、第八传输线、第九传输线、第十传输线;
    所述第一传输线的一端为所述输出匹配网络的输入端,所述第一传输线的另一端同时与所述第二传输线、所述第三传输线、所述第四传输线的一端连接,所述第二传输线的另一端为所述输出匹配网络的偏置端,所述第四传输线的另一端同时连接所述第五传输线、所述第六传输线、所述第七传输线的一端,所述第七传输线的另一端同时连接所述第八传输线、所述第九传输线、所述第十传输线的一端,所述第十传输线的另一端为所述输出匹配网络的输出端。
  7. 一种射频功率放大器,其特征在于,所述射频功率放大器包括如权利要求1-6任一项所述的谐波功率放大电路。
  8. 一种输出匹配网络的设计方法,所述输出匹配网络为如权利要求1-6任一项所述的谐波功率放大电路中的输出匹配网络,其特征在于,所述方法包括:
    运用仿真工具分别获取所述谐波功率放大电路在工作频率f1下的连续型逆F类放大模式的最优基波阻抗和在工作频率f2下的连续型F类放大模式的最优基波阻抗;
    通过查表得到三阶低通网络原型参数,并根据三阶低通网络原型参数、设计频率和参考阻抗进行频率和阻抗变换,得到实数阻抗-实数阻抗变换器;
    结合晶体管的寄生网络参数,将实数阻抗-实数阻抗变换器优化为实数阻抗-复数阻抗变换器,所述复数阻抗等于所述最优基波阻抗;
    根据三阶低通网络原型参数建立拓扑结构,并将所述拓扑结构中的电容和电感替换为传输线。
  9. 如权利要求8所述的方法,其特征在于,将所述电感替换为高阻抗传输线,将所述电容替换为低阻抗开路枝节传输线。
  10. 如权利要求8所述的方法,其特征在于,所述根据三阶低通网络原型参数建立拓扑结构,并将所述拓扑结构中的电容和电感替换为传输线的步骤之后还包括:
    将所述拓扑结构与晶体管连接后,通过仿真调节所述传输线的长度,使效率达到最大。
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