WO2018032518A1 - 一种ldpc码的基矩阵生成方法、编译码方法及设备 - Google Patents

一种ldpc码的基矩阵生成方法、编译码方法及设备 Download PDF

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Publication number
WO2018032518A1
WO2018032518A1 PCT/CN2016/096112 CN2016096112W WO2018032518A1 WO 2018032518 A1 WO2018032518 A1 WO 2018032518A1 CN 2016096112 W CN2016096112 W CN 2016096112W WO 2018032518 A1 WO2018032518 A1 WO 2018032518A1
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matrix
row
ldpc code
receiving end
base matrix
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PCT/CN2016/096112
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English (en)
French (fr)
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马亮
魏岳军
郑晨
曾歆
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华为技术有限公司
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Priority to EP16913274.3A priority Critical patent/EP3477865B1/en
Priority to PCT/CN2016/096112 priority patent/WO2018032518A1/zh
Priority to CN201680087813.6A priority patent/CN109478894B/zh
Publication of WO2018032518A1 publication Critical patent/WO2018032518A1/zh
Priority to US16/279,551 priority patent/US10826530B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
    • H03M13/6393—Rate compatible low-density parity check [LDPC] codes

Definitions

  • the embodiments of the present invention relate to the field of communications, and in particular, to a base matrix generation method, a coding and decoding method, and a device for an LDPC code.
  • a low density parity check (LDPC) code is a linear block code with a sparse check matrix, and has been used because of its low complexity, low error leveling, and full parallel decoding. Widely used in channel coding in the fields of worldwide interoperability for microwave access (Wimax), optical network, wireless fidelity (Wi-Fi), etc., to ensure the information transmitted in the channel. Reliability and effectiveness.
  • Wimax worldwide interoperability for microwave access
  • Wi-Fi wireless fidelity
  • HARQ technology includes two schemes: casset combining (CC) and incremental redundancy (IR).
  • CC casset combining
  • IR incremental redundancy
  • the retransmission data is identical to the initial transmission data, and there is only one redundancy version.
  • the receiving end performs soft combining and retransmission of the retransmitted data and the initial transmission data.
  • each retransmission includes Different incremental redundancy check bits are used, and the codewords received twice are first combined in decoding, and then decoded as a codeword with a lower code rate. Since the IR scheme can obtain the energy gain and the coding gain at the same time, in actual use, the IR scheme is mostly used to implement HARQ.
  • the transmitting end can adjust the bit rate of the LDPC code by using a puncturing method, and send the punctured LDPC code to the receiving end to adapt to different channel environments.
  • the receiving end decodes the received punctured LDPC code, firstly, the confidence level of the punctured bit needs to be set to 0, and then Row decoding, but this decoding method has the disadvantages of high computational complexity, slow convergence, and degraded decoding performance.
  • the prior art provides a decoding method.
  • the specific solution is: after receiving the LDPC code, the receiving end first determines whether the LDPC code is a punctured codeword, and if so, the receiving end needs to The initial check matrix (the transmitting end is encoded by the initial check matrix) performs a row merge and a column delete transform operation to obtain a modified check matrix (corresponding to the column deleted during the initial check matrix deformation process) The position of the punctured bit in the entire codeword, the modified check matrix is consistent with the received LDPC code rate, and then the LDPC code is decoded according to the obtained modified check matrix. .
  • the embodiment of the invention provides a base matrix generation method, a coding and decoding method and a device for an LDPC code, which solves the problem that the performance of the parity check matrix after the deformation is not guaranteed due to the difference of the punch pattern, and the probability of decoding error increases.
  • the problem is not limited to the performance of the parity check matrix after the deformation.
  • the embodiment of the present invention adopts the following technical solutions:
  • a first aspect of the embodiments of the present invention provides a method for generating a base matrix of an LDPC code, including:
  • the initial matrix having dual pairs
  • the matrix of the angular structure is m ⁇ m
  • the check digit is the k-th transform matrix H k obtained by k-transforming the initial matrix
  • the k-th transform matrix H k is 2 k m ⁇ 2 k
  • the matrix of m, k satisfies 2 k-1 m ⁇ T ⁇ 2 k m
  • T is the size of the check bit portion
  • the information bit portion of the base matrix is determined according to the check bit portion, and finally, according to the determined check bit Part and information bit parts get the base matrix.
  • the i-th transform process in the k-th transform process is specifically:
  • the first non-negative element of the a-th row is filled to the b-th position of the 2ath row of the split matrix S i , and the second row of the a-th row nonnegative elements filled into the c-th position of the first division line 2a-1 of the matrix S i, S i the matrix elements split the remaining positions -1, to obtain a split matrix S i; wherein splitting of the matrix S i A matrix of size 2 i m ⁇ 2 i-1 m, i is an integer less than or equal to k and greater than 0.
  • the i-1 order transformation matrix H i-1 is an initial matrix; the a -th behavior Any row of the i-1 order transformation matrix H i-1 , b is the position of the first non-negative element of the a-th row at the a-th row, and c is the second non-negative element of the a-th row at the a-th row Position, a, b, c are integers greater than 0;
  • a d,e represents an element of the d-th row and the e- th column of the supplementary matrix A i
  • d is an integer less than 2 i m and greater than 0, and e is less than 2 i-1 m and greater than An integer of 0;
  • the base matrix generation method of the LDPC code provided by the embodiment of the present invention firstly determines the size of the check bit portion of the base matrix according to the required minimum code rate, and performs the initial matrix according to the determined size of the check bit portion. After the k-th transform process, the check bit portion of the base matrix is obtained, and the information bit portion of the base matrix is determined according to the check bit portion. Finally, the base matrix is obtained according to the determined check bit portion and the information bit portion, thus generating The base matrix has a fixed puncturing pattern, thereby ensuring the performance of the transformation matrix obtained by the receiving end deforming the base matrix according to the fixed puncturing pattern, thereby reducing the probability of decoding errors.
  • a second aspect of the embodiments of the present invention provides a decoding method, which is applied to a receiving end, where the receiving end is pre-configured with the base matrix according to the first aspect, and the method may include: receiving, receiving, and receiving by the receiving end The initial transmission LDPC code sent by the initial transmission rate, and determining that the received initial transmission LDPC code includes the punctured bits, and the receiving end determines the column to be deleted in the parity portion of the base matrix according to the lowest code rate and the initial transmission rate.
  • the first transformation matrix is started by the last column of the check bit portion of the base matrix, and the x column of the check bit portion is deleted, and each column is deleted and merged a matrix obtained after the row corresponding to the column, and then using the obtained first transformation matrix
  • the initial transmission LDPC code is decoded.
  • the receiving end when the receiving end determines that the initial transmission LDPC code sent by the transmitting end includes the punctured bit, it first determines that the check bit portion of the base matrix needs to be deleted according to the lowest code rate and the initial transmission code rate.
  • the number of columns x then start from the last column of the check digit portion of the base matrix, delete the x column, and delete each row, merge the rows corresponding to the column, and obtain the first transformation matrix with the code rate equal to the initial transmission rate, and finally
  • the first transform matrix is used to decode the initial LDPC code, and the receiving end performs the check according to the fixed puncturing pattern according to the last column of the check bit portion of the base matrix.
  • the corresponding number of columns in the bit portion, and each time a column is deleted, the transformation matrix obtained by morphing the base matrix in a manner corresponding to the row of the column ensures the performance of the transformation matrix, thereby reducing the probability of decoding errors.
  • the receiving end pre-stores the correspondence between the column and the row corresponding to the column.
  • a second j m-1 column of the check bit portion and a second k m-2 k-j+1 line of the base matrix, a second k m-2 k-j+1 -1 line, and a second k m-2 k-j+1 -2 lines, ... corresponds to the 2k m-2 k-j+2 line;
  • the second j-1 m+1 column of the check bit portion corresponds to the 2 k-j+1 row, ..., the 2nd row and the 1st row of the base matrix; j is less than k and greater than 0 Integer.
  • the decoding method may further include: if the receiving end determines that the received LDPC code sent by the sending end does not include the punched hole Bits, the soft values of the possible repeated bits can be merged first, and then no conversion processing is performed on the pre-configured base matrix, and the pre-configured base matrix is directly used to decode the initial transmission LDPC code.
  • the initial LDPC code is decoded by using the pre-configured base matrix at the receiving end, it can be determined whether the decoding of the initial LDPC code is successful, and if it is determined that the initial LDPC code is successfully decoded, Send an acknowledgement (ACK) instruction to the sender to complete the data transmission; If the decoding of the initial LDPC code fails, the non-acknowledgment (NACK) command is sent to the transmitting end, so that the transmitting end performs retransmission until the receiving end decodes successfully or the number of repeated transmissions reaches a preset threshold.
  • ACK acknowledgement
  • NACK non-acknowledgment
  • the decoding method may further include: determining by the receiving end Whether the decoding of the initial transmission LDPC code is successful, if it is determined that the decoding of the initial transmission LDPC code is successful, an ACK instruction is sent to the transmitting end to complete the data transmission; if it is determined that the initial transmission LDPC code is decoded If the failure occurs, the receiving end sends a NACK command to the transmitting end, so that the transmitting end constructs and sends a retransmission bit according to the NACK command.
  • the receiving end receives the retransmission bit sent by the transmitting end, and needs to first determine whether the retransmission code rate is greater than the lowest code. Rate, if the retransmission code rate is greater than the lowest code rate, it indicates that the first LDPC code obtained by splicing the received retransmission bits and all the bits included in the initial transmission LDPC code still includes the puncturing bits, and the receiving end can Directly splicing all the bits included in the retransmission bit and the initial transmission LDPC code to obtain a first LDPC code whose code rate and retransmission code rate are equal, and then the receiving end determines the base according to the lowest code rate and the retransmission code rate.
  • the retransmission code rate is lower than the lowest code rate, it indicates that the retransmission bit includes a bit that overlaps with the bit included in the initial transmission LDPC code.
  • the retransmission bit and the bit included in the initial transmission LDPC code may be represented first. The soft values of the same bits are combined, and then spliced with the remaining bits to obtain a first LDPC code, and the first LDPC code is directly decoded using the base matrix.
  • the retransmission bit and all the bits included in the initial transmission LDPC code may be directly spliced to obtain a first LDPC code, and then the first LDPC code is directly decoded by using the base matrix.
  • the receiving end needs to determine again whether the decoding of the first LDPC code is successful, and when it is determined that the decoding is successful, the sending is performed.
  • the terminal sends an ACK command, and the data transmission is completed.
  • the NACK command needs to be sent to the transmitting end, so that the transmitting end can construct and send the first retransmitting bit to the receiving end again, and the receiving end receives the first
  • all bits of the first received initial LDPC code and all retransmitted retransmission bits are combined to construct a second LDPC code until the decoding of the LDPC code is successful or repeated. The number of times reaches the preset threshold to complete the data transmission.
  • a third aspect of the embodiments of the present invention provides an encoding method, which is applied to a transmitting end, where the transmitting end is pre-configured with the base matrix according to the first aspect, and the method may include: the transmitting end encodes the information to be transmitted by using the base matrix. Obtaining an LDPC code, and determining whether the preset initial transmission code rate is greater than the lowest code rate. If it is determined that the initial transmission code rate is greater than the lowest code rate, the transmitting end determines the bit to be punctured according to the initial transmission code rate and the lowest code rate. The number of bits is then punctured from the last bit of the LDPC code to generate an initial transmission LDPC code according to the number of bits to be punctured. Finally, the initial transmission LDPC code is transmitted to the receiving end by using the initial transmission rate.
  • the transmitting end determines the number of bits of the bits to be repeated according to the initial transmission rate and the lowest code rate, and then repeats the bits of the encoded LDPC code one by one from the first bit. Adding to the end of the LDPC code to generate an initial transmission LDPC code, and transmitting the initial transmission LDPC code to the receiving end by using an initial transmission rate. If it is determined that the initial transmission code rate is equal to the lowest code rate, the transmitting end directly uses the coded LDPC code as the initial transmission LDPC code, and sends the initial transmission LDPC code to the receiving end by using the initial transmission rate.
  • the initial transmission code rate is less than or equal to the lowest code rate
  • the ACK command sent by the receiving end is received, it indicates that the receiving end decodes the initial transmission LDPC code. If the data transmission is completed, the NACK command sent by the receiving end indicates that the receiving end fails to decode the initial LDPC code. At this time, the transmitting end needs to retransmit until receiving the ACK sent by the receiving end. The number of instructions or repeated transmissions reaches a preset threshold.
  • the transmitting end uses the base matrix to encode the information to be transmitted to obtain an LDPC code, and when determining that the initial transmission code rate is greater than the lowest code rate, determining the bit to be punctured according to the initial transmission rate and the lowest code rate.
  • the number of bits then puncturing the LDPC code from the last bit of the LDPC code, based on the number of bits of the bit to be punctured
  • the initial transmission LDPC code is generated, and the initial transmission LDPC code is sent to the receiving end by using the initial transmission rate.
  • the LDPC code is punctured from the last bit of the LDPC code to generate the initial transmission LDPC code, so that the receiving end can be fixed according to the fixed Punching the pattern, that is, by using the last column of the check bit portion of the base matrix, deleting the corresponding number of columns in the check bit portion of the base matrix according to x, and deleting each row to merge the rows corresponding to the columns
  • the transformation matrix obtained by the deformation of the basis matrix ensures the performance of the transformation matrix, thereby reducing the probability of decoding errors at the receiving end.
  • the encoding method may further include: receiving by the transmitting end
  • the NACK command sent by the receiving end indicates that the receiving end fails to decode the initial LDPC code.
  • the transmitting end can generate a retransmission bit according to the preset retransmission code rate, and send the retransmitted bit to the receiving end.
  • the retransmitted bits include some or all of the punctured bits, or the retransmitted bits include all punctured bits, and bits that are repeated one by one from the first bit of the LDPC code.
  • the transmitting end receives the ACK command sent by the receiving end, it indicates that the receiving end successfully decodes the initial LDPC code, and the data transmission is completed.
  • the method further includes: if the sending end receives the NACK command sent by the receiving end again, the sending end may regenerate and send the first The bit is retransmitted to the receiving end until the number of times the ACK command or retransmission sent by the receiving end is received reaches a preset threshold.
  • a fourth aspect of the embodiments of the present invention provides a base matrix generating device for an LDPC code, including:
  • a determining unit configured to determine a size of a check bit portion of the base matrix according to a required minimum code rate, and determine a check bit portion of the base matrix according to the size of the check bit portion and an initial matrix;
  • the initial matrix is a matrix of size m ⁇ m having a double diagonal structure
  • the check bit portion is a k-th order transformation matrix H k obtained by performing k-th transform processing on the initial matrix, the k-order
  • the transformation matrix H k is a matrix of size 2 k m ⁇ 2 k m, k satisfies 2 k-1 m ⁇ T ⁇ 2 k m, T is the size of the check bit portion; and according to the check bit portion Determining an information bit portion of the base matrix;
  • a processing unit configured to determine the check digit portion according to the determining unit
  • the information bit portion obtains the base matrix
  • the determining unit is specifically configured to:
  • the first non-negative element of the a-th row is filled to the b-th position of the 2a-th row of the split matrix S i
  • the a-th row is the second non-negative elements to fill the c-th division 2a-1 position of the first row of the matrix S i of the matrix elements split the remaining S i -1 position, to give the split matrix S i
  • the split matrix S i is a matrix of size 2 i m ⁇ 2 i-1 m
  • the order transformation matrix H i-1 is the initial matrix
  • the a-th is an arbitrary row of the i-1 order transformation matrix H i-1
  • the b is the first non-negative element of the a-th row
  • the c is the position of the second non-negative element of the
  • a d,e represents an element of the d-th row and the e- th column of the supplementary matrix A i , the d being an integer less than 2 i m and greater than 0, and the e is less than 2 i-1 m, and an integer greater than 0;
  • a fifth aspect of the embodiments of the present invention provides a receiving end, where the receiving end is pre-configured with the base matrix according to the first aspect, and the receiving end includes:
  • the receiving unit is configured to receive an initial transmission LDPC code sent by the sending end by using a preset initial transmission rate
  • a determining unit configured to determine that the initial transmission LDPC code received by the receiving unit includes a punctured bit, and determine, according to the lowest code rate and the initial transmission code rate, a parity bit portion of the base matrix The number of columns to be deleted x;
  • a transform unit configured to transform the base matrix to obtain a first transform matrix, where a code rate of the first transform matrix is equal to the initial code rate, and the first transform matrix is used by the base matrix
  • the last column of the check digit portion begins, the x column of the check digit portion is deleted, and each row is deleted, and the row corresponding to the column is merged to obtain Matrix
  • a decoding unit configured to decode the initial transmission LDPC code by using the first transformation matrix obtained by the transformation unit transformation.
  • the receiving end further includes: a storage unit;
  • a second j m-1 column of the check bit portion and a second k m-2 k-j+1 line of the base matrix, a second k m-2 k-j+1 -1 line, and a second k m-2 k-j+1 -2 lines, ... corresponds to the 2k m-2 k-j+2 line;
  • the second j-1 m+1 column of the check bit portion corresponds to the 2 k-j+1 row, ..., the 2nd row and the 1st row of the base matrix; j is less than k and greater than 0 Integer.
  • the receiving end further includes: a sending unit and a merging unit;
  • the determining unit is further configured to determine that the decoding unit fails to decode the initial transmission LDPC code
  • the sending unit is configured to send a non-acknowledgment NACK command to the sending end;
  • the receiving unit is further configured to receive a retransmission bit sent by the sending end;
  • a splicing unit configured to splicing the retransmission bits received by the receiving unit and all bits included in the initial transmission LDPC code to obtain a first LDPC code, if the retransmission rate is greater than the lowest code rate;
  • the code rate of the first LDPC code is equal to the retransmission code rate;
  • the determining unit is further configured to determine, according to the lowest code rate and the retransmission code rate, the number of columns y to be deleted in the check bit portion of the base matrix;
  • the transforming unit is further configured to transform the base matrix to obtain a second transform matrix, where the second transform matrix is started by a last column of a check bit portion of the base matrix, and the checksum is The y column of the bit portion is deleted, and each time a column is deleted, a matrix obtained after merging the row corresponding to the column, the code rate of the second transformation matrix and the The retransmission code rate is equal;
  • the decoding unit is further configured to decode the first LDPC code by using the second transform matrix transformed by the transform unit.
  • a sixth aspect of the embodiments of the present invention provides a transmitting end, where the sending end is configured with a base matrix as described in the first aspect, where the sending end includes:
  • a coding unit configured to encode the information to be transmitted by using the base matrix to obtain an LDPC code
  • a determining unit configured to determine, according to the initial transmission code rate and the lowest code rate, a bit number of bits to be punctured according to the preset initial transmission code rate being greater than the lowest code rate
  • a puncturing unit configured to punct the LDPC code from a last bit of the LDPC code obtained by the coding unit according to the number of bits of the bit to be punctured determined by the determining unit Generate an initial transmission LDPC code
  • a sending unit configured to send the initial transmission LDPC code to the receiving end by using the initial transmission rate.
  • the method further includes: a receiving unit and a generating unit;
  • a receiving unit configured to receive a non-acknowledgment NACK command sent by the receiving end
  • a generating unit configured to generate a retransmission bit according to the preset retransmission code rate in response to the NACK instruction received by the receiving unit, where the retransmitted bit includes some or all of the punctured bits, Or the retransmitted bits include all punctured bits, and bits repeated one by one from the first bit of the LDPC code;
  • the sending unit is further configured to send the retransmission bit generated by the generating unit to the receiving end.
  • the generating unit is further configured to regenerate the first retransmission bit if the NACK command sent by the receiving end is received again;
  • the sending unit is further configured to send the first retransmission generated by the generating unit Bits to the receiving end until the number of times the acknowledgment ACK command or retransmission sent by the receiving end is received reaches a preset threshold.
  • a seventh aspect of the embodiments of the present invention provides a base matrix generating device for an LDPC code, including: at least one processor, a memory, a system bus, and a communication interface;
  • the memory is configured to store a computer execution instruction
  • the processor is coupled to the memory through the system bus, and when the base matrix generating device of the LDPC code is running, the processor performs the memory storage
  • the computer executes instructions to cause the base matrix generating device of the LDPC code to perform the base matrix generating method of the LDPC code as described in the first aspect.
  • An eighth aspect of the present invention provides a receiving end, where the receiving end is pre-configured with the base matrix according to the first aspect, and the receiving end comprises: at least one processor, a memory, a system bus, and a communication interface;
  • the memory is configured to store a computer execution instruction
  • the processor is connected to the memory through the system bus, and when the receiving end is running, the processor executes the computer execution instruction stored in the memory to The receiving end is caused to perform the decoding method according to any of the second aspect or the possible implementation of the second aspect.
  • a ninth aspect of the embodiments of the present invention provides a transmitting end, wherein the transmitting end is pre-configured with the base matrix according to the first aspect, and the transmitting end comprises: at least one processor, a memory, and a system bus. And communication interface;
  • the memory is configured to store a computer execution instruction
  • the processor is connected to the memory through the system bus, and when the transmitting end is running, the processor executes the computer execution instruction stored in the memory to The transmitting end is caused to perform the encoding method as described in any of the third aspect or the possible implementation of the third aspect.
  • FIG. 1 is a simplified schematic diagram of a wireless communication system to which an embodiment of the present invention is applied according to an embodiment of the present invention
  • FIG. 2 is a flowchart of a method for generating a base matrix of an LDPC code according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of initial matrix transformation according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of another initial matrix transformation according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of a decoding method according to an embodiment of the present invention.
  • FIG. 6 is a flowchart of an encoding method according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of a method for encoding and decoding according to an embodiment of the present invention.
  • FIG. 8 is a flowchart of another method for encoding and decoding according to an embodiment of the present invention.
  • FIG. 9 is a flowchart of still another method for encoding and decoding according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a base matrix according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a unit matrix and a permutation matrix according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram of a transformation matrix according to an embodiment of the present invention.
  • FIG. 13 is a schematic structural diagram of a base matrix generating device for an LDPC code according to an embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram of a receiving end according to an embodiment of the present invention.
  • FIG. 15 is a schematic structural diagram of another receiving end according to an embodiment of the present invention.
  • FIG. 16 is a schematic structural diagram of a sending end according to an embodiment of the present invention.
  • FIG. 17 is a schematic structural diagram of another sending end according to an embodiment of the present invention.
  • FIG. 18 is a schematic structural diagram of another base matrix generating device for an LDPC code according to an embodiment of the present invention.
  • FIG. 19 is a schematic structural diagram of another receiving end according to an embodiment of the present invention.
  • FIG. 20 is a schematic structural diagram of another sending end according to an embodiment of the present invention.
  • FIG. 21 is a schematic structural diagram of another base matrix generating device for an LDPC code according to an embodiment of the present invention.
  • FIG. 22 is a schematic structural diagram of another receiving end according to an embodiment of the present invention.
  • FIG. 23 is a schematic structural diagram of another sending end according to an embodiment of the present invention.
  • the embodiment of the present invention provides a method for generating a base matrix of an LDPC code, which is basically used, because the quality of the punctured pattern has a large impact on the performance of the modified check matrix.
  • the principle is: the base matrix generating device of the LDPC code determines the size of the check bit portion of the base matrix according to the required minimum code rate, and determines the check bit portion of the base matrix according to the determined size of the check bit portion and the initial matrix.
  • the initial matrix is a matrix of size m ⁇ m having a double diagonal structure
  • the check digit portion is a k-th order transformation matrix H k obtained by performing k-th transform processing on the initial matrix
  • the k-th order transformation matrix H k For a matrix of size 2 k m ⁇ 2 k m, k satisfies 2 k-1 m ⁇ T ⁇ 2 k m, T is the size of the check bit portion, and the information bit portion of the base matrix is determined according to the check bit portion
  • the base matrix can be obtained according to the determined check bit portion and the information bit portion, so that the generated base matrix has a fixed punch pattern, thereby ensuring that the receiving end deforms the base matrix according to the fixed punch pattern. Obtained transformation moment Performance, thereby reducing the probability of decoding error.
  • the transmitting end and the receiving end can perform information interaction through a wireless channel by using a wireless communication technology.
  • the transmitting end may encode and transmit the information to be transmitted that needs to be transmitted to obtain a transmission signal suitable for wireless channel transmission, and send the transmission signal to the receiving end, and the receiving end receives the received signal transmitted through the wireless channel, and then demodulates and decodes the received signal to obtain The information to be transmitted that the sender needs to transmit.
  • the information to be transmitted may be a symbol, for example, a text or a language, or may be a signal such as an image or an audio or the like.
  • the sender may be a user experience (UE) or a base station.
  • the receiving end can be a UE or a base station.
  • FIG. 1 shows a simplified schematic diagram of a wireless communication system to which embodiments of the present invention may be applied.
  • the wireless communication system may include a bit input unit, a channel coding unit, a transmission processing unit, a channel, a reception processing unit, a channel decoding unit, and a bit output unit.
  • the channel coding unit includes an LDPC encoder and a punching device.
  • the channel decoding unit includes an LDPC decoder and a de-punching device.
  • the transmission processing unit includes a device such as a modulator that needs to process the transmitted bit information.
  • the receiving processing unit includes a device such as a demodulator that needs to process the received transmitted bit information.
  • the LDPC encoder stores a base matrix of the LDPC code, and is used for LDPC encoding the information to be transmitted generated by the source to be transmitted to obtain an LDPC code.
  • a punching device for puncturing an LDPC code to obtain an LDPC code of a desired code rate.
  • the modulator is configured to modulate the LDPC code after punching through the punching device to obtain a signal suitable for channel transmission. Channel for transmitting signals to the sink.
  • a demodulator for demodulating a signal transmitted over a channel.
  • the punching device is configured to perform puncturing on the punched LDPC code.
  • the LDPC decoder stores a base matrix of the LDPC code, and performs LDPC decoding on the demodulated signal of the demodulator to obtain information to be transmitted that needs to be transmitted. a bit output unit for outputting information to be transmitted.
  • the transmitting end may include a bit input unit, a channel coding unit, and a transmission processing unit.
  • the receiving end may include a receiving processing unit, a channel decoding unit, and a bit output unit.
  • the wireless communication system may further include: a base matrix generating device of the LDPC code.
  • the base matrix generating device of the LDPC code is used to generate a base matrix of the LDPC code.
  • FIG. 2 is a flowchart of a method for generating a base matrix of an LDPC code according to an embodiment of the present invention. As shown in FIG. 2, the method may include:
  • the device for performing the base matrix generation method of the LDPC code may be an electronic device such as a computer.
  • the parity matrix of the LDPC code can be obtained by performing a spreading process on the base matrix of the LDPC code, and the LDPC code can be uniquely determined according to the check matrix of the LDPC code.
  • Base matrix package for LDPC codes The information bit portion and the check bit portion are included in the embodiment of the present invention to implement the generation of the base matrix of the LDPC code by the following steps.
  • the lowest code rate is preset according to the requirements of the actual application scenario. Since the code rate is equal to the ratio of the bit number of the information bits included in the LDPC code to the total number of bits of the LDPC code, and the LDPC code is encoded according to the base matrix to be transmitted, it is assumed that the base matrix is expanded to be verified.
  • the spreading factor used in the matrix is z, then the bit number of the information bit and the check bit in the LDPC code obtained by encoding the information to be transmitted using the parity check matrix corresponding to the base matrix is equal to the product of the expansion factor and the length of the base matrix.
  • the bit number of the information bits included in the obtained LDPC code is equal to the difference between the length and the width of the base matrix multiplied by the expansion factor. Therefore, the code rate can be determined by the length and width of the base matrix, and the check bit portion of the base matrix It is a matrix, so that the size of the check bit portion of the base matrix can be determined according to the preset minimum code rate.
  • the initial matrix is a matrix of size m ⁇ m having a double diagonal structure.
  • the row weight of the initial matrix (the row weight refers to the number of elements greater than or equal to 0 contained in a row of the matrix) and the column weight (the column weight refers to the number of elements greater than or equal to 0 contained in one column of the matrix)
  • the number is 2.
  • m can usually be set to 2 or 3.
  • it can also be set to other values, just ensure that the initial matrix is a square matrix with a double diagonal structure.
  • the embodiment of the present invention does not specifically limit the value of m.
  • the initial matrix is a 2 ⁇ 2 square matrix.
  • all elements of the initial matrix are 0.
  • the initial matrix is a 3 ⁇ 3 square matrix.
  • the initial matrix satisfies the requirements of the double diagonal structure.
  • the number of transforms k required to transform from the initial matrix to the check bit portion of the base matrix can also be determined.
  • the size of the known check bit portion is T ⁇ T
  • the size of the initial matrix is m ⁇ m
  • the number of times of transformation k is a positive integer
  • finding k satisfies the following formula:
  • the matrix obtained after k times of change is the check digit part of the final generated base matrix.
  • T ⁇ 2 k m the matrix structure is first changed by k times, and then 2 is completed.
  • the k mT sub-matrix row combining operation obtains that the check bit portion of the finally generated base matrix will satisfy the size of T ⁇ T.
  • the initial matrix may be subjected to k-transform processing to obtain a k-th order transformation matrix H k , and the k-th order transformation matrix H k is the check bit portion of the base matrix, and the k-th order transformation matrix H k is a matrix having a size of 2 k m ⁇ 2 k m .
  • the i-th transform process in the k-th transform process is implemented by performing the following steps:
  • Step 1 For the a-th row of the i- 1th-order transformation matrix H i-1 , the first non-negative element of the a-th row is filled to the b-th position of the 2a-th row of the split matrix S i , and the a-th row is the second non-negative elements to fill the c-th position of the first division line 2a-1 of the matrix S i, S i the elements of the matrix to split the remaining positions -1, to obtain a split matrix S i.
  • the split matrix S i is a matrix of size 2 i m ⁇ 2 i-1 m, i is less than or equal to k, and is an integer greater than 0.
  • the i-1 order transformation matrix H i-1 is Initial matrix.
  • the a-th row is an arbitrary row of the i-1 order transformation matrix H i-1
  • b is the position of the first non-negative element of the a-th row at the a-th row
  • c is the second non-negative element of the a-th row at the The position of a line, a, b, and c are integers greater than zero.
  • the first element of a non-negative initial row of the first matrix to the second division filled matrix 1 S
  • the first position of the 2 rows fills the second non-negative element of the first row to the second position of the first row of the split matrix S 1 ; and the first non-negative element of the second row of the initial matrix filled into a first position of the break line 4 matrix S 1, the second non-filled negative elements of the second row to the second row position of the third division matrix S 1, S 1 splitting the rest of the matrix
  • the element of the position is -1 to obtain the split matrix S 1 as shown in FIG.
  • a non-negative element of the first row of the first matrix initial matrix S is filled into the second division 1
  • the first position of the row fills the second non-negative element of the first row to the second position of the first row of the split matrix S 1 ; and fills the first non-negative element of the second row of the initial matrix
  • the second non-negative element of the second row is filled to the third position of the third row of the split matrix S 1 ; and the third row of the initial matrix the first non-negative element to the first position filling split line 6 matrix S 1, the padding element of the second non-negative in the third row to the third position of the break line 5 matrix S 1, splitting the remaining elements of the location in the matrix S -1. 1, to obtain a split matrix S 41 shown in FIG.
  • the split matrix S 2 as shown in FIG. 4 can be obtained by the second transform process.
  • Step 2 According to Generate a supplementary matrix A i .
  • a d,e represents an element of the d-th row and the e- th column of the supplementary matrix A i
  • d is an integer less than 2 i m and greater than
  • e is an integer less than 2 i-1 m and greater than 0.
  • step 1 constructed split matrix S i can matrix supplemented matrix A i S i according to the formula the configuration of the split, the number of rows the number of rows of the supplementary matrix A i and a number of columns of the split matrix S i and column The numbers are the same, and the complement matrix A i has a row weight of 1, a column weight of 2, and 0 elements are distributed on the diagonal line with an offset factor of 2 in the longitudinal direction.
  • the supplementary matrix A 1 and the supplementary matrix A 2 as shown in FIG. 3 can be obtained according to the above formula.
  • the supplementary matrix A 1 and the supplementary matrix A 2 as shown in Fig. 4 can be obtained according to the above equation.
  • the first-order transformation matrix H 1 and the second-order transformation matrix H 2 shown in FIG. 3 can be obtained according to the above formula.
  • the first-order transformation matrix H 1 and the second-order transformation matrix H 2 shown in FIG. 4 can be obtained according to the above formula.
  • a k-th order transformation matrix H k that satisfies the size of the check bit portion can be obtained, that is, the check bit portion of the base matrix can be obtained.
  • the information bit portion of the base matrix can be determined according to a check digit portion, a density evolution (DE) theory, and a progressive edge growth (PEG) method.
  • DE density evolution
  • PEG progressive edge growth
  • the base matrix obtained according to the above steps 201-204 has a fixed punch pattern, and the punch pattern is shown in Table 1:
  • M represents the number of rows of the base matrix
  • N represents the number of columns of the base matrix
  • M is an integer greater than or equal to 1
  • N is an integer greater than or equal to 1.
  • the LDPC matrix having the diagonal structure may be first constructed, and then the row and column exchange of the LDPC matrix is performed to satisfy the step 204.
  • the basis of the structure of the base matrix described in the embodiment of the present invention is obtained.
  • the base matrix generation method of the LDPC code provided by the embodiment of the present invention firstly determines the size of the check bit portion of the base matrix according to the required minimum code rate, and performs the initial matrix according to the determined size of the check bit portion. After the k-th transform process, the check bit portion of the base matrix is obtained, and the information bit portion of the base matrix is determined according to the check bit portion. Finally, the base matrix is obtained according to the determined check bit portion and the information bit portion, thus generating The base matrix has a fixed puncturing pattern, thereby ensuring the performance of the transformation matrix obtained by the receiving end deforming the base matrix according to the fixed puncturing pattern, thereby reducing the probability of decoding errors.
  • FIG. 5 is a flowchart of a decoding method according to an embodiment of the present disclosure. The method is applied to a receiving end, where the receiving end is pre-configured with a base matrix in the embodiment as described in FIG.
  • the lowest code rate, as shown in Figure 5, the method can include:
  • the receiving end receives an initial transmission LDPC code sent by the sending end by using a preset initial transmission rate.
  • the receiving end determines that the initial transmission LDPC code includes the punctured bit.
  • the transmitting end may, according to the embodiment in FIG.
  • the base matrix is encoded. After the transmitting end encodes the transmission information according to the base matrix in the embodiment as described in FIG. 1, the code rate of the obtained LDPC code is equal to the lowest code rate, and the transmitting end transmits the encoded LDPC. Before the code, it is determined whether the LDPC code obtained by coding needs to be punctured according to the initial code rate.
  • the receiving end may first determine whether the initial transmission LDPC code includes the punctured bit according to whether the initial transmission code rate is greater than the lowest code rate, if the initial transmission code rate is greater than the lowest code Rate, to determine that the initial transmission LDPC code includes the punctured bits, perform the following step 303, if the initial transmission rate is not greater than the lowest code rate, it can be determined that the initial transmission LDPC code does not include the punctured bits, Repetitive bit soft value of the receiving end may be present may be first combined and then the base matrix without any pre-configured transformation process, but directly using the initial transmission of the base matrix of the LDPC code decoding.
  • the receiving end determines, according to the lowest code rate and the initial transmission code rate, the number of columns x to be deleted in the check digit portion of the base matrix.
  • the receiving end When it is determined that the initial transmission LDPC code includes the punctured bits, the receiving end needs to transform the base matrix to obtain a transformation matrix, and then decode the initial transmission LDPC code according to the transformation matrix. At this time, the receiving end may first Determining the number of bits to be punctured according to the lowest code rate and the initial transmission code rate of the initial transmission LDPC code sent by the transmitting end, that is, determining the base that needs to be deleted by the transformation matrix whose code rate is equal to the initial transmission code rate. The number of columns x of the check digit portion of the matrix.
  • the receiving end transforms the base matrix to obtain a first transform matrix.
  • the code rate of the first transform matrix is equal to the initial code rate.
  • the x column may be deleted from the last column of the check bit portion of the base matrix according to the determined x, and each deletion is performed. For one column, it is necessary to merge the rows corresponding to the column to obtain the first transformation matrix. among them, Merging the row corresponding to the column means that the elements between the rows corresponding to the column are modulo 2 added according to the corresponding position.
  • the receiving end decodes the initial transmission LDPC code by using a first transform matrix.
  • the first transformation matrix After the first transformation matrix is transformed by the receiving end, the first transformation matrix can be used to decode the initial transmission LDPC code, so as to obtain the information to be transmitted that the transmitting end needs to transmit to itself.
  • the receiving end when the receiving end determines that the initial transmission LDPC code sent by the transmitting end includes the punctured bit, it first determines that the check bit portion of the base matrix needs to be deleted according to the lowest code rate and the initial transmission code rate.
  • the number of columns x then start from the last column of the check digit portion of the base matrix, delete the x column, and delete each row, merge the rows corresponding to the column, and obtain the first transformation matrix with the code rate equal to the initial transmission rate, and finally
  • the first transform matrix is used to decode the initial LDPC code, and the receiving end performs the check according to the fixed puncturing pattern according to the last column of the check bit portion of the base matrix.
  • the corresponding number of columns in the bit portion, and each time a column is deleted, the transformation matrix obtained by morphing the base matrix in a manner corresponding to the row of the column ensures the performance of the transformation matrix, thereby reducing the probability of decoding errors.
  • FIG. 6 is a flowchart of an encoding method according to an embodiment of the present disclosure. The method is applied to a sending end, where the sending end is pre-configured with a base matrix in the embodiment as described in FIG. 1 , where the base matrix corresponds to a preset minimum
  • the code rate as shown in FIG. 6, the method may include:
  • the transmitting end encodes the information to be transmitted by using a base matrix to obtain an LDPC code.
  • the transmitting end may, according to the embodiment in FIG.
  • the base matrix is encoded to obtain an LDPC code suitable for channel transmission, and the code rate of the LDPC code is equal to the lowest code rate.
  • the transmitting end may first transform the check bit portion of the base matrix into an equivalent double diagonal matrix by using row and column transformation, and then implement the information to be transmitted by using a simplified dual diagonal encoding algorithm.
  • Quick coding if the transmitting end uses the method to implement the encoding of the information to be transmitted, the receiving end may pre-record the order in which the transmitting end performs the row-column transformation, and then, after receiving the LDPC code, first The order of the column transformation of the transmitting end adjusts the order of the LDPC codes to obtain the order before the conversion, and then performs decoding.
  • the sending end determines that the preset initial transmission code rate is greater than the lowest code rate.
  • the LDPC code After the LDPC code is encoded by the transmitting end to obtain the LDPC code, it can be determined whether the preset initial transmission rate is greater than the lowest code rate. If the initial transmission rate is greater than the lowest code rate, the following step 403 is performed.
  • the transmitting end may directly send the LDPC code as the initial transmission LDPC code to the receiving end. If the initial transmission rate is less than the lowest code rate, the transmitting end according to the initial transmission rate and the lowest code rate. Determining the number of bits of the bits to be repeated, and then adding the bits of the encoded LDPC code to the end of the LDPC code one by one from the first bit to generate an initial transmission LDPC code, and transmitting the initial transmission LDPC code to the reception end.
  • the transmitting end determines, according to the initial transmission rate and the lowest code rate, the number of bits of the bit to be punctured.
  • the sending end determines that the initial transmission code rate is greater than the lowest code rate, it indicates that the LDPC code needs to be punctured. At this time, the transmitting end can determine the number of bits to be punctured according to the initial transmission rate and the lowest code rate. .
  • the transmitting end punctifies the LDPC code to generate an initial transmission LDPC code according to the number of bits of the bit to be punctured from the last bit of the LDPC code.
  • the LDPC code can be punctured from the last bit of the LDPC code to generate an initial LDPC code according to the number of bits to be punctured.
  • the sending end sends the initial transmission LDPC code to the receiving end by using an initial transmission rate.
  • the transmitting end uses the base matrix to encode the information to be transmitted to obtain an LDPC code, and when determining that the initial transmission code rate is greater than the lowest code rate, determining the bit to be punctured according to the initial transmission rate and the lowest code rate.
  • the number of bits is then punctured from the last bit of the LDPC code to generate an initial transmission LDPC code according to the number of bits to be punctured.
  • the initial transmission LDPC code is transmitted to the receiving end using the initial transmission rate.
  • the LDPC code is punctured from the last bit of the LDPC code to generate an initial LDPC code, so that the receiving end can adopt a fixed puncturing pattern, that is, by adopting Starting from the last column of the check bit portion of the base matrix, the corresponding number of columns in the check bit portion of the base matrix are deleted according to x, and each row is deleted, and the transform corresponding to the column is merged to transform the base matrix.
  • the matrix ensures the performance of the transformation matrix, thereby reducing the probability of decoding errors at the receiving end.
  • FIG. 7-9 are flowcharts of a method for encoding and decoding according to an embodiment of the present invention.
  • the method is applied to a wireless communication system, where the wireless communication system includes at least a transmitting end and a receiving end, and the transmitting end and the receiving end are pre-configured.
  • the base matrix corresponds to a preset minimum code rate, and assuming that the base matrix pre-configured at the transmitting end and the receiving end is as shown in FIG. 10, then the lowest code rate at this time is equal to 0.5, and assume that the initial pass rate is 0.7.
  • the method can include:
  • the initial transmission process may be completed by using steps 501 to 513 as shown in FIG. 7 , specifically:
  • the transmitting end encodes the information to be transmitted by using a base matrix to obtain an LDPC code.
  • the transmitting end may encode the information to be transmitted according to the base matrix as shown in FIG. 10 to obtain an LDPC code, and the code rate of the LDPC code is equal to the minimum. Rate rate.
  • the specific coding process has been defined in the communication standard, and the embodiments of the present invention will not be described in detail herein.
  • the transmitting end may first expand the base matrix as shown in FIG. 10 to obtain a corresponding check matrix, and then use the obtained check matrix to encode the information to be transmitted to obtain an LDPC code.
  • all the elements with a value of -1 in the base matrix are extended to obtain an all-zero matrix of z ⁇ z size, and other elements are expanded to obtain a permutation matrix of z ⁇ z size, and z is the actual expansion factor.
  • the permutation matrix may be obtained by cyclically shifting an identity matrix according to a corresponding number of displacements, and the number of displacements corresponds to the value of the element.
  • the element value can be transformed according to the following formula (1) to obtain the number of displacements.
  • z f is the actual expansion factor
  • p (i, j) is the value of the element of the i-th row and the j-th column in the base matrix. Indicates rounding down, p(f, i, j) indicates the number of shifts.
  • the corresponding permutation matrix can be obtained by cyclically shifting the unit matrix to the right 7 times.
  • the unit matrix and the resulting permutation matrix are shown in Figure 11.
  • the information to be transmitted is 0000 1100 11110001 0101 0101 0100 0111 1011 0111 1000 0001 1100 0001 10010011
  • the LDPC obtained by encoding the check matrix obtained by the base matrix expansion as shown in FIG. 10 is used.
  • the code is 0000 1100 1111 0001 0101 0101 0100 0111 1011 01111000 0001 1100 0001 1001 0011 0101 1110 0101 1101 0110 00100000 0100 0001 0011 1010 0011 0011 1001 0011 1011
  • the code rate of the LDPC code is 0.5.
  • the sending end determines whether the preset initial transmission code rate is greater than a minimum code rate.
  • the LDPC code After the LDPC code is encoded by the transmitting end to obtain the LDPC code, it can be determined whether the preset initial transmission rate is greater than the lowest code rate. If the initial transmission rate is greater than the lowest code rate, perform the following steps 503-505; If the initial code rate is equal to the lowest code rate, step 506 is performed. If the initial code rate is less than the lowest code rate, step 507 is performed.
  • the transmitting end determines, according to the initial transmission rate and the lowest code rate, the number of bits of the bit to be punctured.
  • the sending end determines that the initial transmission code rate is greater than the lowest code rate, it indicates that the LDPC code needs to be punctured. At this time, the transmitting end can determine the number of bits to be punctured according to the initial transmission rate and the lowest code rate. .
  • the determined number of bits to be punctured is 4. It should be noted that when the number of bits to be punched calculated according to the initial code rate and the lowest code rate is a decimal, the actual bit to be punched may be determined according to the rule of rounding up or down. number. The present invention is hereby exemplified by upward rounding.
  • the transmitting end punctifies the LDPC code to generate an initial transmission LDPC code according to the number of bits of the bit to be punctured from the last bit of the LDPC code.
  • puncturing from the last bit of the LDPC code generates an initial transmission LDPC code of 0000 1100 1111 00010101 0101 0100 0111 1011 0111 1000 0001 1100 0001 1001 0011 01011110 0101 1101 0110 0010 0000 0100 0001 0011 1010 0011 0011 10010011.
  • the sending end sends the initial transmission LDPC code to the receiving end by using an initial transmission rate.
  • the transmitting end sends the LDPC code as an initial transmission LDPC code to the receiving end by using an initial transmission rate.
  • the transmitting end determines, according to the initial code rate and the lowest code rate, the number of bits of the bit to be repeated, and then adds the bit of the coded LDPC code to the end of the LDPC code one by one from the first bit to generate the initial
  • the LDPC code is transmitted, and the initial transmission LDPC code is sent to the receiving end by using the initial transmission rate.
  • the receiving end receives an initial transmission LDPC code sent by the sending end by using a preset initial transmission rate.
  • the receiving end determines whether the initial transmission LDPC code includes the punctured bit.
  • the receiving end may determine whether the initial LDPC code includes the punctured bit. If the initial LDPC code includes the punctured bit, perform the following steps 510-512. If the transmitted LDPC code does not contain the punctured bits, then the following step 513 is performed.
  • the receiving end determines, according to the lowest code rate and the initial transmission code rate, the number of columns x to be deleted in the parity bit portion of the base matrix.
  • the receiving end When it is determined that the initial transmission LDPC code includes the punctured bits, the receiving end needs to transform the base matrix to obtain a transformation matrix, and then decode the initial transmission LDPC code according to the transformation matrix. At this time, the receiving end may first Determining, according to the lowest code rate and the initial transmission rate of the initial transmission LDPC code sent by the transmitting end, the number of columns x of the parity bit portion of the base matrix to be deleted by the transformation matrix whose code rate is equal to the initial transmission code rate is obtained by the base matrix deformation.
  • the number of columns x of the check bit portion of the base matrix to be deleted can be obtained to be equal to 4. It should be noted that when the number of columns of the check bit portion of the base matrix to be deleted is calculated according to the initial code rate and the lowest code rate, When it is a decimal, the number of columns of the check digit part of the base matrix that needs to be deleted can be determined according to the rule of rounding up or down. The present invention is hereby exemplified by upward rounding.
  • the receiving end transforms the base matrix to obtain a first transform matrix.
  • the x column may be deleted from the last column of the check bit portion of the base matrix according to the determined x, and Each time a column is deleted, the row corresponding to the column needs to be merged to obtain the first transformation matrix. For each column in the check bit portion of the base matrix, the receiving end pre-stores the correspondence between the column and the row corresponding to the column.
  • the 2 k mth column of the check bit portion corresponds to the 2 k m row and the 2 k m-1 row of the base matrix
  • the 2 k m-1 column of the check bit portion is The 2 k m-2 row and the 2 k m-3 row of the base matrix correspond, and so on, the 2 k-1 m+1 column of the check bit portion and the 2nd of the base matrix
  • the line corresponds to the first line.
  • the m-7 row corresponds to, and so on, the 2 k-2 m+1 column of the check bit portion corresponds to the 4th row, the 3rd row, the 2nd row, and the 1st row of the base matrix.
  • j a 2 j mth column of the check bit portion and a 2 k m row, a 2 k m-1 row, a 2 k m-2 row, ... and a 2 k m-2 k- of the base matrix j + 1 +1 rows corresponding to the parity bit portion of column j m-1 K 2 of the second base matrix m-2 k-j + 1 th line, 2 k m-2 k-j +1 -1 rows, k m-2 k-j + 1 -2 row 2, ..., and k m-2 k-j + 2 corresponding to the second row, and so on, and the second parity bit portion
  • the j-1 m+1 column corresponds to the 2 k-j+1th row, ..., the 2nd row, and the 1st row of the base matrix; j is an integer less than k and greater than 0.
  • the check bit portion of the base matrix is obtained by three transformation processes according to the initial matrix, and the initial matrix is a square matrix of 2*2 size
  • the parity bit The last column of the portion corresponds to the 15th row and the 16th row of the base matrix
  • the second column of the reciprocal of the parity bit portion corresponds to the 13th row and the 14th row of the base matrix
  • the third column and the base of the check digit portion The 11th row and the 12th row of the matrix correspond
  • the 4th column of the reciprocal of the check digit portion corresponds to the 9th row and the 10th row of the base matrix, and so on
  • the 8th column of the reciprocal of the check bit portion and the base matrix 1 row corresponds to row 2
  • the ninth column of the reciprocal of the check digit portion corresponds to the 13th to 16th rows of the base matrix
  • the 10th column of the reciprocal of the check digit portion corresponds to the 9th-12th row of the base matrix, and so on.
  • the 12th column of the reciprocal of the check digit portion corresponds to the 1-4th row of the base matrix; the 13th column of the reciprocal of the check digit portion corresponds to the 9th to 16th rows of the base matrix, and the reciprocal 14th column of the check digit portion Corresponds to lines 1-8 of the base matrix. According to such a correspondence, the receiving end can start from the last column of the check bit portion of the base matrix, delete the corresponding number of columns in the check bit portion of the base matrix according to x, and merge the rows corresponding to the columns for each column deleted. To get the first transformation matrix.
  • the number of columns to be deleted is 4, then referring to FIG. 10, deleting the last four columns of the check digit portion, and merging the rows corresponding to the four columns, that is, deleting the last column.
  • the elements between the 15th row and the 16th row of the corresponding base matrix of the last column are modulo 2 added according to the corresponding positions, the second column of the last number is deleted, and the 13th row and the 14th of the base matrix corresponding to the second column of the last column are added.
  • the elements between the lines are modulo 2 plus according to the corresponding positions, and the third column of the last number is deleted, and the elements between the 11th line and the 12th line of the base matrix corresponding to the third column of the reciprocal are modulo 2 added according to the corresponding positions, and the countdown is deleted. 4 columns, and the elements between the 9th row and the 10th row of the base matrix corresponding to the fourth column of the reciprocal are modulo 2 added according to the corresponding positions to obtain the first transformation matrix.
  • the 2 k m column to the 2 k-1 m+1 column may be deleted first, and the rows corresponding to the columns are merged. After obtaining a transformation matrix smaller than the base matrix, and then deleting the 2 k-1 mth column to the 2 k-2 m+1 column on the basis of the transformation matrix smaller than the base matrix, and merging the columns The line, and so on.
  • the 9th column to the 16th column of the check bit portion may be deleted first, and the corresponding row of each column is merged to obtain a transformation matrix as shown in FIG. Then, based on the transformation matrix as shown in FIG. 12, the last column (the eighth column corresponding to the base matrix of the last column) and the second to last column (the seventh column of the base matrix corresponding to the second to last column) are deleted and merged. The row corresponding to each column.
  • the receiving end decodes the initial transmission LDPC code by using a first transform matrix.
  • the receiving end combines the soft values of the possible repeated bits, and then directly uses the base matrix to decode the initial transmission LDPC code.
  • the initial transmission process from the transmitting end to the receiving end is completed. Further, if the receiving end determines that the initial transmission fails, the following steps 514-526 can be performed.
  • Retransmission Specifically, as shown in FIG. 8, for the case where the initial transmission LDPC code includes the punctured bits, the retransmission process includes the following steps 514-525. As shown in FIG. 9, for the case where the initial transmission LDPC code does not include the punctured bits, the retransmission process includes the following steps 514-step 516, and steps 525-526.
  • the receiving end determines whether the decoding of the initial transmission LDPC code is successful.
  • the initial LDPC code After the initial LDPC code is decoded by the receiving end, it can be determined whether the decoding of the initial LDPC code is successful. If the decoding of the initial LDPC code fails, the following steps 515-524 can be performed. If the decoding of the initial transmission LDPC code is successful, the following step 525 is performed.
  • the receiving end sends a NACK command to the sending end.
  • the sending end receives the NACK command sent by the receiving end.
  • the sending end In response to the NACK command, the sending end generates a retransmission bit according to the preset retransmission code rate.
  • the retransmitted bits include some or all of the punctured bits, or the retransmitted bits include all punctured bits, and the bits are repeated one by one from the first bit of the LDPC code.
  • the transmitting end may form part or all of the punctured bits into retransmission bits, and when the number of punctured bits does not satisfy the retransmission code rate When required, the transmitting end may compose all the punctured bits and the bits that are repeated one by one from the first bit of the LDPC code.
  • the sending end sends the retransmitted bit to the receiving end.
  • the receiving end receives the retransmission bit sent by the sending end.
  • the receiving end determines that the retransmission code rate is greater than the lowest code rate.
  • the receiving end After receiving the retransmission bit sent by the transmitting end, the receiving end needs to determine whether the retransmission code rate is greater than the lowest code rate. If the retransmission code rate is greater than the lowest code rate, it indicates that the retransmitted bit and the initial transmission LDPC are received.
  • the first LDPC code obtained after all the bits included in the code are spliced (the splicing of all the bits included in the retransmission bit and the initial transmission LDPC code refers to adding the retransmission bits after all the bits included in the initial transmission LDPC code)
  • the puncturing bit is included, and the receiving end may perform the following steps 521 to 524.
  • the retransmission code rate is lower than the lowest code rate, it indicates that the retransmission bit includes a bit that is repeated with the bit included in the initial transmission LDPC code.
  • the retransmission bit may be first combined with the soft value representing the same bit in the bits included in the initial transmission LDPC code, and then spliced with the remaining bits to obtain the first LDPC code, and the first LDPC code is directly used by the base matrix. Perform decoding. If the retransmission code rate is equal to the lowest code rate, the retransmission bit and all the bits included in the initial transmission LDPC code may be directly spliced to obtain a first LDPC code, and then the first LDPC code is directly decoded by using the base matrix.
  • the receiving end splices all the bits included in the retransmission bit and the initial transmission LDPC code to obtain a first LDPC code.
  • the retransmitted retransmission bit and the initial transmission LDPC code may be spliced to obtain the first LDPC code.
  • the code rate of the first LDPC code is equal to the retransmission code rate.
  • the receiving end determines, according to the lowest code rate and the retransmission code rate, the number of columns y to be deleted in the check digit portion of the base matrix.
  • the retransmission code rate since the retransmission code rate is greater than the lowest code rate, it indicates that the first LDPC code includes the punctured bits. In this case, the base matrix needs to be transformed again to obtain a transformation matrix. Therefore, the receiving end needs to be based on the lowest code rate and retransmitted.
  • the code rate determines the number of columns y to be deleted in the check digit portion of the base matrix.
  • the receiving end transforms the base matrix to obtain a second transform matrix.
  • the receiving end may start from the last column of the check bit portion of the base matrix, delete the y column, and merge each row with the column to obtain a second transform matrix.
  • the code rate of the second transform matrix is equal to the retransmission code rate.
  • the receiving end decodes the first LDPC code by using a second transform matrix.
  • the receiving end may first extend the second transform matrix to obtain a check matrix corresponding to the second transform matrix, and then decode the first LDPC code by using the obtained check matrix.
  • the expansion process reference may be made to the corresponding description in the step 501 in the embodiment of the present invention, and details are not described herein again.
  • the receiving end may continue to determine whether the decoding of the first LDPC code is successful. If the decoding fails to decode the first LDPC code, The NACK command needs to be sent to the sending end again. If the sending end receives the NACK command sent by the receiving end again, the transmitting end needs to regenerate and send the second retransmitting bit to the receiving end until receiving the acknowledgement ACK command sent by the receiving end or The number of retransmissions reaches a preset threshold.
  • the receiving end sends an ACK command to the sending end.
  • the transmitting end performs retransmission until the number of times that the ACK command sent by the receiving end or the repeated transmission is received reaches a preset threshold.
  • the sending end receives the NACK command sent by the receiving end, it indicates that the receiving end fails to decode the initial LDPC code. At this time, the transmitting end performs retransmission until receiving the ACK command or repeated transmission sent by the receiving end. The number of times reaches the preset threshold.
  • the transmitting end uses a base matrix to be transmitted.
  • the information is encoded to obtain an LDPC code.
  • the number of bits to be punctured is determined according to the initial transmission rate and the lowest code rate, and then according to the number of bits to be punctured,
  • the last bit of the LDPC code starts to punctify the LDPC code to generate the initial LDPC code, and finally sends the initial LDPC code to the receiving end by using the initial transmission rate, and punctifies the LDPC code by starting from the last bit of the LDPC code.
  • the receiving end can delete a corresponding number of columns in the parity bit portion of the base matrix according to the fixed perforation pattern, that is, by using the last column of the parity bit portion of the base matrix, and Each time a column is deleted, the transformation matrix obtained by morphing the row corresponding to the column is modified to ensure the performance of the transformation matrix, thereby reducing the probability of decoding error at the receiving end.
  • each network element such as a base matrix generating device, a receiving end, and a transmitting end of the LDPC code, in order to implement the above functions, includes hardware structures and/or software modules corresponding to performing respective functions.
  • a network element such as a base matrix generating device, a receiving end, and a transmitting end of the LDPC code
  • each network element includes hardware structures and/or software modules corresponding to performing respective functions.
  • the present invention can be implemented in a combination of hardware or hardware and computer software in combination with the algorithm steps of the various examples described in the embodiments disclosed herein. Whether a function is implemented in hardware or computer software to drive hardware depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods for implementing the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.
  • the embodiment of the present invention may divide the function module of the base matrix generating device, the receiving end, and the transmitting end of the LDPC code according to the foregoing method.
  • each functional module may be divided according to each function, or two or more of the functional modules may be divided.
  • the functions are integrated in one processing module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of the module in the embodiment of the present invention is schematic, and is only a logical function division, and the actual implementation may have another division manner.
  • FIG. 13 shows a possible structure of a base matrix generating device of the LDPC code involved in the above embodiment, in the case where each functional module is divided by corresponding functions.
  • the base matrix generating device of the LDPC code may include: a determining unit 61 and a processing unit 62.
  • the determining unit 61 is configured to support step 201, step 202, and step 203 in the base matrix generating method of the LDPC code shown in FIG. 2, which is used by the base matrix generating device that supports the LDPC code.
  • the processing unit 62 is configured to support step 204 in the base matrix generating method of the LDPC code shown in FIG. 2 by the base matrix generating device supporting the LDPC code.
  • the base matrix generating device of the LDPC code provided by the embodiment of the present invention is configured to perform the base matrix generating method of the LDPC code, so that the same effect as the base matrix generating method of the LDPC code can be achieved.
  • FIG. 14 is a schematic diagram showing a possible structure of the receiving end involved in the foregoing embodiment, where the receiving end is pre-configured with the base matrix in the embodiment as described in FIG. As shown in FIG. 14, the receiving end may include: a receiving unit 71, a determining unit 72, a transforming unit 73, and a decoding unit 74.
  • the receiving unit 71 is configured to support the receiving end to perform step 301 in the decoding method shown in FIG. 5, step 508 in the encoding and decoding method shown in FIG. 7, and step 519 in the encoding and decoding method shown in FIG. .
  • the determining unit 72 is configured to support the receiving end to perform step 302, step 303 in the decoding method shown in FIG. 5, step 509 in the encoding and decoding method shown in FIG. 7, step 510, and the encoding and decoding method shown in FIG. Step 514, step 520, step 522, step 514 in the codec method shown in FIG.
  • the transforming unit 73 is configured to support the receiving end to perform step 304 in the decoding method shown in FIG. 5, step 511 in the encoding and decoding method shown in FIG. 7, and step 523 in the encoding and decoding method shown in FIG.
  • the decoding unit 74 is configured to support the receiving end to perform step 305 in the decoding method shown in FIG. 5, step 512 and step 513 in the encoding and decoding method shown in FIG. 7, in the encoding and decoding method shown in FIG. Step 524.
  • the receiving end may further include: a storage unit 75.
  • the correspondence relationship between the column and the row corresponding to the column is previously stored in the storage unit 75.
  • the second j m column of the check bit portion and the second k m row, the second k m-1 row, the second k m-2 row, ... and the 2 k m-2 of the base matrix k-j + 1 +1 row corresponds; bit portion of the check j m-1 and column 2 of the base matrix k m-2 k-j + 1 , line 2, 2 k m-2 k line -j + 1 -1, k m-2 k-j + 1 -2 row 2, ..., and k m-2 k-j + 2 corresponding to the second row; and so on; the check-bit portion
  • the second j-1 m+1 column corresponds to the 2 k-j+1th row, ..., the 2nd row, and the 1st row of the base matrix; j is an integer less than k and greater than 0.
  • the receiving end may further include: a sending unit 76 and a splicing unit 77.
  • the sending unit 76 is configured to support the receiving end to perform steps 515 and 525 in the encoding and decoding method shown in FIG. 8 and steps 515 and 525 in the encoding and decoding method shown in FIG. 9.
  • the splicing unit 77 is configured to support the receiving end to perform step 521 in the encoding and decoding method shown in FIG. 8.
  • the receiving end provided by the embodiment of the present invention is configured to perform the above decoding method, so that the same effect as the above decoding method can be achieved.
  • FIG. 16 is a schematic diagram showing a possible structure of the transmitting end involved in the foregoing embodiment, where the transmitting end is pre-configured with a base matrix in the embodiment as described in FIG.
  • the transmitting end may include: an encoding unit 81, a determining unit 82, a punching unit 83, and a transmitting unit 84.
  • the encoding unit 81 is configured to support the transmitting end to perform step 401 in the encoding method shown in FIG. 6 and step 501 in the encoding and decoding method shown in FIG. 7.
  • the determining unit 82 is configured to support the sending end to perform step 402 and step 403 in the encoding method shown in FIG. 6 and step 502 and step 503 in the encoding and decoding method shown in FIG. 7 .
  • the puncturing unit 83 is configured to support the transmitting end to perform step 404 in the encoding method shown in FIG. 6, step 504 in the encoding and decoding method shown in FIG.
  • the sending unit 84 is configured to support the sending end to perform step 405 in the encoding method shown in FIG. 6, step 505, step 506, and step 507 in the encoding and decoding method shown in FIG. 7, in the encoding and decoding method shown in FIG. Step 518.
  • the transmitting end may further include: a receiving unit 85 and a generating unit 86.
  • the receiving unit 85 is configured to support the sending end to perform step 516 in the encoding and decoding method shown in FIG. 8.
  • the generating unit 86 is configured to support the sending end to perform step 517 in the encoding and decoding method shown in FIG. 8.
  • the transmitting end provided by the embodiment of the present invention is used to execute the foregoing encoding method, so that the same effect as the above encoding method can be achieved.
  • FIG. 18 shows a possible structural diagram of a base matrix generating device of the LDPC code involved in the above embodiment.
  • the base matrix generating device of the LDPC code includes a processing module 91 and a communication module 92.
  • the processing module 91 is configured to perform control on the operation of the base matrix generating device of the LDPC code.
  • the processing module 91 is configured to support the base matrix generating device of the LDPC code to perform step 201, step 202, step 203, and step 204 in FIG. 2 .
  • the communication module 92 is for supporting communication between the base matrix generating device of the LDPC code and other network entities, such as communication with the functional modules or network entities shown in FIG. 1, FIG. 14, FIG. 15, FIG. 16, or FIG.
  • the base matrix generating device of the LDPC code may further include a storage module 93 for storing program codes and data of the base matrix generating device of the LDPC code.
  • the processing module 91 can be a processor or a controller. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure.
  • the processor may also be a combination of computing functions, for example comprising one or more micro Processor combination, combination of DSP and microprocessor, etc.
  • the communication module 92 can be a transceiver, a transceiver circuit, a communication interface, or the like.
  • the storage module 93 can be a memory.
  • the base matrix generating device of the LDPC code may be a base matrix generating device of the LDPC code shown in FIG. 21. .
  • FIG. 19 shows a possible structural diagram of the receiving end involved in the above embodiment.
  • the receiving end includes: a processing module 1001 and a communication module 1002.
  • the processing module 1001 is configured to control and control the action of the receiving end.
  • the processing module 1001 is configured to support the receiving end to perform step 302, step 303, step 304, step 305 in FIG. 5, step 509, step 510 in FIG. Step 511, step 512, step 513, step 514, step 520, step 521, step 522, step 523, step 524 in FIG. 8, step 514 in FIG. 9, and/or other techniques for the techniques described herein process.
  • the communication module 1002 is configured to support communication between the receiving end and other network entities, such as communication with the functional modules or network entities shown in FIG. 1, FIG. 13, FIG. 16, or FIG.
  • the receiving end may further include a storage module 1003 for storing program codes and data of the receiving end.
  • the storage module 1003 is configured to store the correspondence between the column and the row corresponding to the column. Wherein the second j m column of the check bit portion and the second k m row, the second k m-1 row, the second k m-2 row, ...
  • the second j-1 m+1 column corresponds to the 2 k-j+1th row, ..., the 2nd row, and the 1st row of the base matrix; j is an integer less than k and greater than 0.
  • the processing module 1001 can be a processor or a controller. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure.
  • the processor may also be a combination of computing functions, for example, including one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like.
  • the communication module 1002 can be a transceiver, a transceiver circuit, a communication interface, or the like.
  • the storage module 1003 can be a memory.
  • the processing module 1001 is a processor
  • the communication module 1002 is a transceiver
  • the storage module 1003 is a memory
  • the receiving end of the embodiment of the present invention may be the receiving end shown in FIG.
  • FIG. 20 shows a possible structural diagram of the transmitting end involved in the above embodiment.
  • the transmitting end includes a processing module 1101 and a communication module 1102.
  • the processing module 1101 is configured to perform control and management on the action of the sending end.
  • the processing module 1101 is configured to support the sending end to perform step 401, step 402, step 403, and step 404 in FIG. 6, step 501, step 502 in FIG. Step 503, step 504, step 517 in Figure 8, and/or other processes for the techniques described herein.
  • the communication module 1102 is configured to support communication between the sender and other network entities, such as communication with the functional modules or network entities shown in FIG. 1, FIG. 13, FIG. 14, or FIG.
  • the sending end may further include a storage module 1103 for storing program code and data of the transmitting end.
  • the storage module 1103 is configured to store the correspondence between the column and the row corresponding to the column.
  • the second j-1 m+1 column corresponds to the 2 k-j+1th row, ..., the 2nd row, and the 1st row of the base matrix; j is an integer less than k and greater than 0.
  • the processing module 1101 can be a processor or a controller. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure.
  • the processor may also be a combination of computing functions, for example, including one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like.
  • the communication module 1102 can be a transceiver, a transceiver circuit, a communication interface, or the like.
  • the storage module 1103 can be a memory.
  • the processing module 1101 is a processor
  • the communication module 1102 is a transceiver
  • the storage module 1103 is a memory
  • the transmitting end of the embodiment of the present invention may be the transmitting end shown in FIG.
  • FIG. 21 is a schematic diagram of a base matrix generating device for an LDPC code according to an embodiment of the present invention.
  • the base matrix generating device of the LDPC code may include at least one processor 1201, a memory 1202, a system bus 1203, and a communication interface 1204.
  • the memory 1202 is configured to store computer execution instructions, and the processor 1201 is connected to the memory 1202 through the system bus 1203.
  • the processor 1201 performs the The computer stored in the memory 1202 executes an instruction to cause the base matrix generating device of the LDPC code to perform a base matrix generating method of the LDPC code as described in FIG. 2 to implement the base matrix generating device of the LDPC code shown in FIG.
  • the function of the unit 61 and the processing unit 62 is determined.
  • the processor 1201 executes the computer-executed instructions stored by the memory 1202 to cause the base matrix generating device of the LDPC code to perform step 201 in the base matrix generation method of the LDPC code as described in FIG. 2 to implement
  • the base matrix generating device of the LDPC code shown in FIG. 13 includes the function of the determining unit 61.
  • the processor 1201 executes the computer execution instruction stored by the memory 1202, so that the base matrix generating device of the LDPC code performs step 202 in the base matrix generating method of the LDPC code as described in FIG.
  • the function of the determining unit 61 included in the base matrix generating device of the LDPC code shown in FIG. 13 is realized.
  • the processor 1201 executes the computer execution instruction stored by the memory 1202, so that the base matrix generating device of the LDPC code performs step 204 in the base matrix generation method of the LDPC code as described in FIG.
  • the function of the processing unit 62 included in the base matrix generating device of the LDPC code shown in FIG. 13 is realized.
  • the embodiment further provides a storage medium, which may include the memory 1202.
  • the processor 1201 may be a central processing unit (CPU).
  • the processor 1201 can also be a general-purpose processor, a digital signal processing (DSP), an application specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). ) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and the like.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the processor 1201 may be a dedicated processor, and the dedicated processor may include at least one of a baseband processing chip, a radio frequency processing chip, and the like.
  • the memory 1202 may include a volatile memory, such as a random-access memory (RAM); the memory 1202 may also include a non-volatile memory, such as only Read-only memory (ROM), flash memory, hard disk drive (HDD) or solid-state drive (SSD); the memory 1202 may also include the above-described type of memory The combination.
  • RAM random-access memory
  • non-volatile memory such as only Read-only memory (ROM), flash memory, hard disk drive (HDD) or solid-state drive (SSD); the memory 1202 may also include the above-described type of memory The combination.
  • the system bus 1203 may include a data bus, a power bus, a control bus, a signal status bus, and the like. For the sake of clarity in the present embodiment, various buses are illustrated as the system bus 1203 in FIG.
  • the communication interface 1204 may specifically be a transceiver on a base matrix generating device of the LDPC code.
  • the transceiver can be a wireless transceiver.
  • the wireless transceiver may be an antenna of a base matrix generating device of an LDPC code or the like.
  • the processor 1201 performs data transmission and reception with the other device, for example, between the transmitting end and the receiving end through the communication interface 1204.
  • each step in the method flow shown in FIG. 2 above may be implemented by the processor 1201 in hardware form executing a computer-executed instruction in the form of software stored in the memory 1202. To avoid repetition, we will not repeat them here.
  • the base matrix generating device of the LDPC code provided by the embodiment of the present invention is configured to perform the base matrix generating method of the LDPC code, so that the same effect as the base matrix generating method of the LDPC code can be achieved.
  • FIG. 22 is a schematic structural diagram of another receiving end according to an embodiment of the present invention.
  • the receiving end is pre-configured with a base matrix in the embodiment as shown in FIG. 1.
  • the receiving end may include: at least one processor 1301.
  • the memory 1302 is configured to store a computer execution instruction, and the processor 1301 Connected to the memory 1302 through the system bus 1303, when the receiving end is running, the processor 1301 executes the computer execution instruction stored by the memory 1302, so that the receiving end performs as shown in FIG. a decoding method, or a corresponding step in the encoding and decoding method according to any one of FIG. 7 to FIG. 9, to correspondingly implement the receiving unit 71, the determining unit 72, and the transform in the receiving end as described in FIG. 14 or FIG.
  • the processor 1301 executes the computer-executed instructions stored by the memory 1302 to cause the receiving end to perform step 301 in the decoding method as described in FIG. 5 to implement the receiving as shown in FIG. 14 or FIG.
  • the function of the receiving unit 71 included in the terminal For another example, the processor 1301 executes the computer execution instruction stored by the memory 1302, so that the receiving end performs step 511 in the encoding and decoding method as described in FIG. 7 to implement the method shown in FIG. 14 or FIG.
  • the processor 1301 executes the computer execution instruction stored by the memory 1302, so that the receiving end performs step 520 in the encoding and decoding method as described in FIG. 8 to implement the receiving end shown in FIG.
  • the function of the splicing unit 77 For example, the processor 1301 executes the computer-executed instructions stored by the memory 1302 to cause the receiving end to perform step 301 in the decoding method as described in FIG. 5 to implement the receiving as shown in
  • the embodiment further provides a storage medium, which may include the memory 1302.
  • the processor 1301 can be a CPU.
  • the processor 1301 can also be other general purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and the like.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the processor 1301 may be a dedicated processor, and the dedicated processor may include at least one of a baseband processing chip, a radio frequency processing chip, and the like.
  • the memory 1302 may include a volatile memory such as a RAM; the memory 1302 may also include a non-volatile memory such as a ROM, a flash memory, an HDD or an SSD; and the memory 1302 may further include a combination of the above types of memories.
  • a volatile memory such as a RAM
  • the memory 1302 may also include a non-volatile memory such as a ROM, a flash memory, an HDD or an SSD
  • the memory 1302 may further include a combination of the above types of memories.
  • the system bus 1303 can include a data bus, a power bus, a control bus, and a signal status bus. In the present embodiment, for the sake of clarity, various buses will be shown in FIG. All are indicated as system bus 1303.
  • the transceiver 1304 can be a wireless transceiver.
  • the wireless transceiver can be an antenna at the receiving end or the like.
  • the processor 1301 performs data transmission and reception between the transceiver 1304 and other devices, for example, with the transmitting end.
  • the corresponding steps in the method flow shown in FIG. 5 and FIG. 7 to FIG. 9 can be implemented by the processor 1301 in the hardware form to execute the computer-executed instructions in the form of software stored in the memory 1302. To avoid repetition, we will not repeat them here.
  • the receiving end provided by the embodiment of the present invention is configured to perform the above decoding method, so that the same effect as the above decoding method can be achieved.
  • FIG. 23 is a schematic structural diagram of another transmitting end according to an embodiment of the present invention.
  • the transmitting end is pre-configured with a base matrix in the embodiment as shown in FIG. 1.
  • the transmitting end may include: at least one processor 1401. , a memory 1402, a system bus 1403, and a transceiver 1404.
  • the memory 1402 is configured to store computer execution instructions
  • the processor 1401 is connected to the memory 1402 via the system bus 1403, and when the transmitting end is running, the processor 1401 executes the storage stored by the memory 1402.
  • the computer executes instructions to enable the transmitting end to perform the encoding method as described in FIG. 6, or the encoding and decoding method described in any of FIGS. 7-9, to correspondingly implement the transmission as described in FIG. 16 or FIG.
  • the processor 1401 executes the computer execution instructions stored by the memory 1402 to cause the transmitting end to perform step 401 in the encoding method as described in FIG. 6 to implement the transmitting end shown in FIG. 16 or FIG.
  • the processor 1401 executes the computer execution instruction stored by the memory 1402, so that the sending end performs step 504 in the encoding and decoding method as described in FIG.
  • the function of the punching unit 83 included in the transmitting end shown in Fig. 16 or Fig. 17 is now shown.
  • the processor 1401 executes the computer execution instructions stored by the memory 1402 to cause the transmitting end to perform step 526 in the encoding and decoding method as described in FIG. 9 to implement the method shown in FIG. 16 or FIG.
  • the embodiment further provides a storage medium, which may include the memory 1402.
  • the processor 1401 can be a CPU.
  • the processor 1401 can also be other general purpose processors, DSPs, ASICs, FPGAs, or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and the like.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the processor 1401 may be a dedicated processor, and the dedicated processor may include at least one of a baseband processing chip, a radio frequency processing chip, and the like.
  • the memory 1402 may include a volatile memory such as a RAM; the memory 1402 may also include a non-volatile memory such as a ROM, a flash memory, an HDD or an SSD; and the memory 1402 may further include a combination of the above types of memories.
  • a volatile memory such as a RAM
  • the memory 1402 may also include a non-volatile memory such as a ROM, a flash memory, an HDD or an SSD
  • the memory 1402 may further include a combination of the above types of memories.
  • the system bus 1403 can include a data bus, a power bus, a control bus, and a signal status bus. For the sake of clarity in the present embodiment, various buses are illustrated as the system bus 1403 in FIG.
  • the transceiver 1404 can be a wireless transceiver.
  • the wireless transceiver can be an antenna of the transmitting end or the like.
  • the processor 1401 performs data transmission and reception with the other device, for example, and the receiving end, through the transceiver 1404.
  • the corresponding steps in the method flow shown in FIG. 6 to FIG. 9 can be implemented by the processor 1401 in the hardware form executing the computer-executed instructions in the form of software stored in the memory 1402. To avoid repetition, we will not repeat them here.
  • each function module in the sending end may refer to the specific description of the corresponding process in the method embodiment, which is not described in detail herein.
  • the sending end provided by the embodiment of the present invention is configured to execute the foregoing encoding method, and thus In order to achieve the same effect as the above encoding method.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the modules or units is only a logical function division.
  • there may be another division manner for example, multiple units or components may be used.
  • the combination may be integrated into another device, or some features may be ignored or not performed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may be one physical unit or multiple physical units, that is, may be located in one place, or may be distributed to multiple different places. . Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a readable storage medium.
  • the technical solution of the present invention may contribute to the prior art or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium.
  • the foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

Abstract

本发明公开了一种LDPC码的基矩阵生成方法、编译码方法及设备，涉及通信领域，解决了由于打孔图样差使得变形后的校验矩阵的性能得不到保证，导致的译码出错的概率增加的问题。具体方案为：根据所需的最低码率确定基矩阵的校验位部分的大小，根据初始矩阵及校验位部分的大小确定基矩阵的校验位部分，初始矩阵为具备双对角结构的、大小为m×m的矩阵，校验位部分为对初始矩阵进行k次变换处理后得到的k阶变换矩阵Hk，k满足2k-1m＜T≤2km，T为所述校验位部分的大小，根据校验位部分确定基矩阵的信息位部分，根据校验位部分和信息位部分得到基矩阵。本发明用于编译码过程中。

Description

一种LDPC码的基矩阵生成方法、编译码方法及设备 技术领域
本发明实施例涉及通信领域，尤其涉及一种LDPC码的基矩阵生成方法、编译码方法及设备。
背景技术
目前，在频率资源有限的无线通信网络中，信息在信道中传输的可靠性和有效性影响无线通信网络的服务质量。低密度奇偶校验(low density parity check，LDPC)码是一种具有稀疏校验矩阵的线性分组码，且由于其具有低复杂度、低错误平层、能够全并行译码等优点，已被广泛应用于全球微波互联接入(worldwide interoperability for microwave access，Wimax)、光网络、无线保真(wireless fidelity，Wi-Fi)等领域的信道编码中，以用来确保在信道中传输的信息的可靠性和有效性。
众所周知的，由于信道环境复杂多变，信道编码需要采用混合自动重传请求(hybrid automatic repeat request，HARQ)技术实现码字的重传，以提升通信系统的性能。HARQ技术包括蔡司合并(chase combining，CC)和增量冗余(incremental redundancy，IR)两种方案。在CC方案中，重传数据和初传数据完全相同，只有一种冗余版本，接收端将重传数据和初传数据进行软合并后进行译码；在IR方案中，每次重传包含了不同的增量冗余校验位，译码时先将两次收到的码字进行合并，再将其当作一个码率更低的码字进行译码。由于IR方案可以同时获得能量增益和编码增益，因此在实际使用中大多会使用IR方案实现HARQ。
采用IR方案实现HARQ时，发送端可以采用打孔的方法对LDPC码的码率做出调整，并将打孔后的LDPC码发送至接收端，以适应不同的信道环境。相应的，接收端在对接收到的打孔后的LDPC码进行译码时，先需要将被打孔的比特的置信度置为0，然后再进 行译码，但这种译码方法会出现计算复杂度高，收敛速度慢，译码性能恶化等缺点。为了解决这一问题，现有技术提供一种译码方法，其具体方案为，接收端在接收到LDPC码后，先判断该LDPC码是否为被打孔码字，若是，则接收端需对初始校验矩阵(发送端是采用该初始校验矩阵进行编码的)进行行合并和列删除的变形操作，以得到变形后的校验矩阵(在对初始校验矩阵变形过程中删除的列对应被打孔比特在整个码字中的位置，该变形后的校验矩阵与接收到的LDPC码的码率一致)，然后，再根据得到的变形后的校验矩阵对该LDPC码进行译码。
现有技术中至少存在如下问题：现有技术在对初始校验矩阵进行行合并和列删除时，需根据发送端进行打孔时的打孔图样进行相应的变形操作，而打孔图样的好坏会对变形后的校验矩阵的性能产生较大的影响，也就是说，若根据较差的打孔图样对初始校验矩阵进行变形操作，则会使得变形后的校验矩阵的性能得不到保证，从而导致译码出错的概率增加。
发明内容
本发明实施例提供一种LDPC码的基矩阵生成方法、编译码方法及设备，解决了由于打孔图样差使得变形后的校验矩阵的性能得不到保证，导致的译码出错的概率增加的问题。
为达到上述目的，本发明实施例采用如下技术方案：
本发明实施例的第一方面，提供一种LDPC码的基矩阵生成方法，包括：
首先，根据所需的最低码率确定基矩阵的校验位部分的大小，并根据确定出的校验位部分的大小及初始矩阵确定基矩阵的校验位部分，该初始矩阵为具备双对角结构的、大小为m×m的矩阵，校验位部分为对初始矩阵进行k次变换处理后得到的k阶变换矩阵Hk，k阶变换矩阵Hk为大小为2km×2km的矩阵，k满足2k-1m<T≤2km，T为校验位部分的大小，并根据校验位部分确定基矩阵的信息位部分，最后，根据确定出的校验位部分和信息位部分得到基矩阵。
其中，k次变换处理中的第i次变换处理具体为：
针对i-1阶变换矩阵Hi-1的第a行，将第a行的第一个非负元素填充到分裂矩阵Si的第2a行的第b个位置，将第a行的第二个非负元素填充到分裂矩阵Si的第2a-1行的第c个位置，分裂矩阵Si中的其余位置的元素为-1，以得到分裂矩阵Si；其中，分裂矩阵Si为大小为2im×2i-1m的矩阵，i为小于或等于k，且大于0的整数，当i＝1时，i-1阶变换矩阵Hi-1为初始矩阵；第a行为i-1阶变换矩阵Hi-1的任意一行，b为第a行的第一个非负元素在第a行的位置，c为第a行的第二个非负元素在第a行的位置，a，b，c均为大于0的整数；
根据
Figure PCTCN2016096112-appb-000001
生成补充矩阵Ai；其中，Ad,e表示补充矩阵Ai第d行第e列的元素，d为小于2im，且大于0的整数，e为小于2i-1m，且大于0的整数；
拼接分裂矩阵Si和补充矩阵Ai以获得i阶变换矩阵Hi＝[Si,Ai]。
本发明实施例提供的LDPC码的基矩阵生成方法，首先，根据所需的最低码率确定基矩阵的校验位部分的大小，并根据确定出的校验位部分的大小，对初始矩阵进行k次变换处理后得到基矩阵的校验位部分，并根据校验位部分确定基矩阵的信息位部分，最后，根据确定出的校验位部分和信息位部分得到基矩阵，这样，生成的基矩阵具有固定的打孔图样，进而保证了接收端根据该固定的打孔图样对基矩阵进行变形得到的变换矩阵的性能，从而降低了译码出错的概率。
本发明实施例的第二方面，提供一种译码方法，应用于接收端，该接收端预先配置有如第一方面所述的基矩阵，该方法可以包括：接收端接收发送端采用预设的初传码率发送的初传LDPC码，并确定接收到的初传LDPC码包含被打孔比特，接收端根据最低码率和初传码率确定基矩阵的校验位部分中需删除的列数x，并对基矩阵进行变换得到的第一变换矩阵，该第一变换矩阵是由基矩阵的校验位部分的最后一列开始，将检验位部分的x列删除，并每删除一列，合并与列对应的行之后得到的矩阵，然后采用得到的第一变换矩阵 对初传LDPC码进行译码。
本发明实施例提供的译码方法，接收端在确定发送端发送的初传LDPC码包含被打孔比特时，首先根据最低码率和初传码率确定基矩阵的校验位部分中需删除的列数x，然后由基矩阵的校验位部分的最后一列开始，删除x列，并每删除一列，合并与列对应的行，得到码率与初传码率相等第一变换矩阵，最后采用得到的第一变换矩阵对初传LDPC码进行译码，通过接收端根据固定的打孔图样，即通过采用由基矩阵的校验位部分的最后一列开始，根据x删除基矩阵的校验位部分中相应数量的列，并每删除一列，合并与列对应的行的方式对基矩阵进行变形得到的变换矩阵，确保了变换矩阵的性能，从而降低了译码出错的概率。
结合第二方面，在一种可能的实现方式中，针对基矩阵的校验位部分中的每列，该接收端预先存储有该列和与该列对应的行的对应关系。
其中，所述校验位部分的第2jm列与所述基矩阵的第2km行、第2km-1行、第2km-2行，…和第2km-2k-j+1+1行对应；
所述校验位部分的第2jm-1列与所述基矩阵的第2km-2k-j+1行、第2km-2k-j+1-1行、第2km-2k-j+1-2行，…和第2km-2k-j+2行对应；
以此类推；
所述校验位部分的第2j-1m+1列与所述基矩阵的第2k-j+1行、…、第2行和第1行对应；j为小于k且大于0的整数。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，该译码方法还可以包括：若接收端确定接收到的发送端发送的初传的LDPC码不包含被打孔比特，则可以先将可能存在的重复比特的软值合并，然后无需对预先配置的基矩阵进行任何变换处理，而是直接采用该预先配置的基矩阵对初传LDPC码进行译码。
另外，在接收端采用预先配置的基矩阵对初传LDPC码进行译码之后，可以判断对该初传LDPC码的译码是否成功，若判断得到对该初传LDPC码的译码成功，则向发送端发送确认(acknowledgement，ACK)指令，以便完成此次数据传输；若判断 得到对该初传LDPC码的译码失败，则向发送端发送非确认(negative acknowledgement，NACK)指令，以便发送端进行重传，直到接收端译码成功或重复传输的次数达到预设阈值。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，在接收端采用第一变换矩阵对初传LDPC码进行译码之后，该译码方法还可以包括：接收端判断对初传LDPC码的译码是否成功，若判断得到对初传LDPC码的译码成功，则向发送端发送ACK指令，以便完成此次数据传输；若判断得到对初传LDPC码的译码失败，则接收端向发送端发送NACK指令，以便发送端根据NACK指令构造并发送重传比特，此时接收端接收发送端发送的重传比特，并需要先判断重传码率是否大于最低码率，若重传码率大于最低码率，则表明将接收到的重传比特和初传LDPC码包括的所有比特进行拼接后得到的第一LDPC码仍包含打孔比特，此时接收端可以直接将重传比特和初传LDPC码包括的所有比特进行拼接，得到码率与重传码率相等第一LDPC码，然后接收端根据最低码率和重传码率确定基矩阵的校验位部分中需删除的列数y，并对基矩阵进行变换得到第二变换矩阵；其中，第二变换矩阵是由基矩阵的校验位部分的最后一列开始，将校验位部分的y列删除，并每删除一列，合并与列对应的行之后得到的矩阵，第二变换矩阵的码率与重传码率相等，最后采用第二变换矩阵对第一LDPC码进行译码。
若重传码率小于最低码率，则表明重传比特中包含有与初传LDPC码中包括的比特重复的比特，此时可以先将重传比特和初传LDPC码中包含的比特中代表相同比特的软值合并，然后与剩余的比特进行拼接以得到第一LDPC码，并直接采用基矩阵对该第一LDPC码进行译码。
若重传码率等于最低码率，则可以直接将重传比特和初传LDPC码包括的所有比特进行拼接，得到第一LDPC码，然后直接采用基矩阵对该第一LDPC码进行译码。
当然，接收端在对第一LDPC码进行译码之后，还需再次判断对该第一LDPC码的译码是否成功，并在确定译码成功时，向发送 端发送ACK指令，此次数据传输完成，当确定译码失败时，需向发送端发送NACK指令，以便发送端可以再次构造并发送第一重传比特至接收端，此时接收端接收到了第一重传比特之后，需将第一次接收到的初始LDPC码的所有比特，以及所有重传的重传比特合并，构造出第二LDPC码，直到对LDPC码的译码成功或重复传输的次数达到预设阈值，完成此次数据传输。
本发明实施例的第三方面，提供一种编码方法，应用于发送端，该发送端预先配置有如第一方面所述的基矩阵，该方法可以包括：发送端采用基矩阵对待传输信息进行编码得到LDPC码，并判断预设的初传码率是否大于最低码率，若判断得到初传码率大于最低码率，则发送端根据初传码率和最低码率确定需打孔的比特的位数，然后根据需打孔的比特的位数，从LDPC码的最后一个比特开始对LDPC码进行打孔生成初传LDPC码，最后采用初传码率将初传LDPC码发送至接收端。
若判断得到初传码率小于最低码率，则发送端根据初传码率和最低码率确定需要重复的比特的位数，然后从第一个比特开始将编码得到的LDPC码的比特逐个重复添加到该LDPC码的末尾，以生成初传LDPC码，并采用初传码率将该初传LDPC码发送至接收端。若判断得到初传码率等于最低码率，则发送端直接将编码得到的LDPC码作为初传LDPC码，并采用初传码率将该初传LDPC码发送至接收端。另外，在初传码率小于或等于最低码率的情况下，将初传LDPC码发送至接收端之后，若接收到接收端发送的ACK指令，则表明接收端对初传LDPC码的译码成功，此时数据传输完成；若接收到接收端发送的NACK指令，则表明接收端对初传LDPC码的译码失败，此时，发送端需进行重传，直到接收到接收端发送的ACK指令或重复传输的次数达到预设阈值。
本发明实施例提供的编码方法，发送端采用基矩阵对待传输信息进行编码得到LDPC码，在确定初传码率大于最低码率时，根据初传码率和最低码率确定需打孔的比特的位数，然后根据需打孔的比特的位数，从LDPC码的最后一个比特开始对LDPC码进行打孔 生成初传LDPC码，最后采用初传码率将初传LDPC码发送至接收端，通过从LDPC码的最后一个比特开始对LDPC码进行打孔生成初传LDPC码，使得接收端可以根据固定的打孔图样，即通过采用由基矩阵的校验位部分的最后一列开始，根据x删除基矩阵的校验位部分中相应数量的列，并每删除一列，合并与列对应的行的方式对基矩阵进行变形得到的变换矩阵，确保了变换矩阵的性能，从而降低了接收端译码出错的概率。
结合第三方面和上述可能的实现方式，在另一种可能的实现方式中，在发送端采用初传码率将初传LDPC码发送至接收端之后，该编码方法还可以包括：发送端接收接收端发送的NACK指令，表明接收端对初传LDPC码的译码失败，此时发送端可以根据预设的重传码率生成重传比特，并将重传比特发送至接收端；其中，该重传比特中包括部分或全部被打孔的比特，或重传比特中包括全部被打孔的比特，以及从LDPC码的第一个比特开始逐个重复的比特。
另外，若发送端接收到接收端发送的ACK指令，则表明接收端对初传LDPC码的译码成功，则此次数据传输完成。
结合第三方面和上述可能的实现方式，在另一种可能的实现方式中，所述方法还包括：若发送端再次接收到接收端发送的NACK指令，则发送端可以重新生成并发送第一重传比特至接收端，直到接收到接收端发送的ACK指令或重传的次数达到预设的阈值。
本发明实施例的第四方面，提供一种LDPC码的基矩阵生成设备，包括：
确定单元，用于根据所需的最低码率确定基矩阵的校验位部分的大小，并根据所述校验位部分的大小及初始矩阵确定所述基矩阵的校验位部分；其中，所述初始矩阵为具备双对角结构的、大小为m×m的矩阵，所述校验位部分为对所述初始矩阵进行k次变换处理后得到的k阶变换矩阵Hk，所述k阶变换矩阵Hk为大小为2km×2km的矩阵，k满足2k-1m<T≤2km，T为所述校验位部分的大小；并根据所述校验位部分确定所述基矩阵的信息位部分；
处理单元，用于根据所述确定单元确定出的所述校验位部分和 所述信息位部分得到所述基矩阵；
其中，针对k次变换处理中的第i次变换处理，所述确定单元具体用于：
针对i-1阶变换矩阵Hi-1的第a行，将第a行的第一个非负元素填充到分裂矩阵Si的第2a行的第b个位置，将所述第a行的第二个非负元素填充到所述分裂矩阵Si的第2a-1行的第c个位置，所述分裂矩阵Si中的其余位置的元素为-1，以得到所述分裂矩阵Si；其中，所述分裂矩阵Si为大小为2im×2i-1m的矩阵，所述i为小于或等于k，且大于0的整数，当i＝1时，所述i-1阶变换矩阵Hi-1为所述初始矩阵；所述第a行为所述i-1阶变换矩阵Hi-1的任意一行，所述b为所述第a行的第一个非负元素在所述第a行的位置，所述c为所述第a行的第二个非负元素在所述第a行的位置，所述a，所述b，所述c均为大于0的整数；
根据
Figure PCTCN2016096112-appb-000002
生成补充矩阵Ai；其中，Ad,e表示补充矩阵Ai第d行第e列的元素，所述d为小于2im，且大于0的整数，所述e为小于2i-1m，且大于0的整数；
拼接所述分裂矩阵Si和所述补充矩阵Ai以获得i阶变换矩阵Hi＝[Si,Ai]。
本发明实施例的第五方面，提供一种接收端，所述接收端预先配置有如第一方面所述的基矩阵，所述接收端包括：
接收单元，用于接收发送端采用预设的初传码率发送的初传LDPC码；
确定单元，用于确定所述接收单元接收到的所述初传LDPC码包含被打孔比特，并根据所述最低码率和所述初传码率确定所述基矩阵的校验位部分中需删除的列数x；
变换单元，用于对所述基矩阵进行变换得到第一变换矩阵；其中，所述第一变换矩阵的码率与所述初传码率相等，所述第一变换矩阵是由所述基矩阵的校验位部分的最后一列开始，将所述检验位部分的x列删除，并每删除一列，合并与所述列对应的行之后得到 的矩阵；
译码单元，用于采用所述变换单元变换得到的所述第一变换矩阵对所述初传LDPC码进行译码。
结合第五方面，在一种可能的实现方式中，所述接收端还包括：存储单元；
针对所述基矩阵的校验位部分中的每列，所述存储单元中预先存储有该列和与该列对应的行的对应关系；
其中，所述校验位部分的第2jm列与所述基矩阵的第2km行、第2km-1行、第2km-2行，…和第2km-2k-j+1+1行对应；
所述校验位部分的第2jm-1列与所述基矩阵的第2km-2k-j+1行、第2km-2k-j+1-1行、第2km-2k-j+1-2行，…和第2km-2k-j+2行对应；
以此类推；
所述校验位部分的第2j-1m+1列与所述基矩阵的第2k-j+1行、…、第2行和第1行对应；j为小于k且大于0的整数。
结合第五方面和上述可能的实现方式，在另一种可能的实现方式中，所述接收端还包括：发送单元和合并单元；
所述确定单元，还用于确定所述译码单元对所述初传LDPC码的译码失败；
所述发送单元，用于向所述发送端发送非确认NACK指令；
所述接收单元，还用于接收所述发送端发送的重传比特；
拼接单元，用于若重传码率大于所述最低码率，则将所述接收单元接收到的所述重传比特和所述初传LDPC码包括的所有比特进行拼接得到第一LDPC码；所述第一LDPC码的码率与所述重传码率相等；
所述确定单元，还用于根据所述最低码率和所述重传码率确定所述基矩阵的校验位部分中需删除的列数y；
所述变换单元，还用于对所述基矩阵进行变换得到第二变换矩阵；其中，所述第二变换矩阵是由所述基矩阵的校验位部分的最后一列开始，将所述校验位部分的y列删除，并每删除一列，合并与所述列对应的行之后得到的矩阵，所述第二变换矩阵的码率与所述 重传码率相等；
所述译码单元，还用于采用所述变换单元变换得到的所述第二变换矩阵对所述第一LDPC码进行译码。
具体的实现方式可以参考第二方面或第二方面的可能的实现方式提供的译码方法中接收端的行为功能，在此不再详细赘述。
本发明实施例的第六方面，提供一种发送端，所述发送端预先配置有如第一方面所述的基矩阵，所述发送端包括：
编码单元，用于采用所述基矩阵对待传输信息进行编码得到LDPC码；
确定单元，用于若预设的初传码率大于所述最低码率，则根据所述初传码率和所述最低码率确定需打孔的比特的位数；
打孔单元，用于根据所述确定单元确定出的所述需打孔的比特的位数，从所述编码单元编码得到的所述LDPC码的最后一个比特开始对所述LDPC码进行打孔生成初传LDPC码；
发送单元，用于采用所述初传码率将所述初传LDPC码发送至接收端。
结合第六方面，在一种可能的实现方式中，还包括：接收单元和生成单元；
接收单元，用于接收所述接收端发送的非确认NACK指令；
生成单元，用于响应于所述接收单元接收到的所述NACK指令，根据预设的重传码率生成重传比特；其中，所述重传比特中包括部分或全部被打孔的比特，或所述重传比特中包括全部被打孔的比特，以及从所述LDPC码的第一个比特开始逐个重复的比特；
所述发送单元，还用于将所述生成单元生成的所述重传比特发送至所述接收端。
结合第六方面和上述可能的实现方式，在另一种可能的实现方式中，
所述生成单元，还用于若再次接收到所述接收端发送的所述NACK指令，则重新生成第一重传比特；
所述发送单元，还用于发送所述生成单元生成的所述第一重传 比特至所述接收端，直到接收到所述接收端发送的确认ACK指令或重传的次数达到预设的阈值。
具体的实现方式可以参考第三方面或第三方面的可能的实现方式提供的编码方法中发送端的行为功能，在此不再详细赘述。
本发明实施例的第七方面，提供一种LDPC码的基矩阵生成设备，包括：至少一个处理器、存储器、系统总线和通信接口；
所述存储器用于存储计算机执行指令，所述处理器与所述存储器通过所述系统总线连接，当所述LDPC码的基矩阵生成设备运行时，所述处理器执行所述存储器存储的所述计算机执行指令，以使所述LDPC码的基矩阵生成设备执行如第一方面所述的LDPC码的基矩阵生成方法。
本发明实施例的第八方面，提供一种接收端，所述接收端预先配置有如第一方面所述的基矩阵，所述接收端包括：至少一个处理器、存储器、系统总线和通信接口；
所述存储器用于存储计算机执行指令，所述处理器与所述存储器通过所述系统总线连接，当所述接收端运行时，所述处理器执行所述存储器存储的所述计算机执行指令，以使所述接收端执行如第二方面或第二方面的可能的实现方式中任一所述的译码方法。
本发明实施例的第九方面，提供一种发送端，其特征在于，所述发送端预先配置有如第一方面所述的基矩阵，所述发送端包括：至少一个处理器、存储器、系统总线和通信接口；
所述存储器用于存储计算机执行指令，所述处理器与所述存储器通过所述系统总线连接，当所述发送端运行时，所述处理器执行所述存储器存储的所述计算机执行指令，以使所述发送端执行如第三方面或第三方面的可能的实现方式中任一所述的编码方法。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可 以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种应用本发明实施例的无线通信系统的简化示意图；
图2为本发明实施例提供的一种LDPC码的基矩阵生成方法的流程图；
图3为本发明实施例提供的一种初始矩阵变换示意图；
图4为本发明实施例提供的另一种初始矩阵变换示意图；
图5为本发明实施例提供的一种译码方法的流程图；
图6为本发明实施例提供的一种编码方法的流程图；
图7为本发明实施例提供的一种编译码方法的流程图；
图8为本发明实施例提供的另一种编译码方法的流程图；
图9为本发明实施例提供的又一种编译码方法的流程图；
图10为本发明实施例提供的一种基矩阵的示意图；
图11为本发明实施例提供的一种单位矩阵和置换矩阵的示意图；
图12为本发明实施例提供的一种变换矩阵的示意图；
图13为本发明实施例提供一种LDPC码的基矩阵生成设备的结构示意图；
图14为本发明实施例提供一种接收端的结构示意图；
图15为本发明实施例提供另一种接收端的结构示意图；
图16为本发明实施例提供一种发送端的结构示意图；
图17为本发明实施例提供另一种发送端的结构示意图；
图18为本发明实施例提供另一种LDPC码的基矩阵生成设备的结构示意图；
图19为本发明实施例提供另一种接收端的结构示意图；
图20为本发明实施例提供另一种发送端的结构示意图；
图21为本发明实施例提供另一种LDPC码的基矩阵生成设备的结构示意图；
图22为本发明实施例提供另一种接收端的结构示意图；
图23为本发明实施例提供另一种发送端的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
由于打孔图样的好坏会对变形后的校验矩阵的性能产生较大的影响，因此为了减小译码出错的概率，本发明实施例提供一种LDPC码的基矩阵生成方法，其基本原理是：LDPC码的基矩阵生成设备根据所需的最低码率确定基矩阵的校验位部分的大小，并根据确定出的校验位部分的大小以及初始矩阵确定基矩阵的校验位部分，其中，初始矩阵为具备双对角结构的、大小为m×m的矩阵，校验位部分为对初始矩阵进行k次变换处理后得到的k阶变换矩阵Hk，k阶变换矩阵Hk为大小为2km×2km的矩阵，k满足2k-1m<T≤2km，T为校验位部分的大小，并根据校验位部分确定基矩阵的信息位部分，最后，根据确定出的校验位部分和信息位部分便可以得到基矩阵，这样，生成的基矩阵具有固定的打孔图样，进而保证了接收端根据该固定的打孔图样对基矩阵进行变形得到的变换矩阵的性能，从而降低了译码出错的概率。
下面将结合附图对本发明实施例的实施方式进行详细描述。
目前，发送端和接收端可以利用无线通信技术通过无线信道进行信息交互。发送端可以将需要传输的待传输信息经过编码调制得到适合无线信道传输的发送信号，向接收端发送该发送信号，接收端接收通过无线信道传输的接收信号，再将接收信号解调解码，得到发送端需要传输的待传输信息。其中，待传输信息可以是符号，例如，文字或语言等，也可以是信号，例如图像或声响等等。发送端可以是用户设备(user experience，UE)或者基站。接收端可以是UE或者基站。
如图1所示，图1示出的是可以应用本发明实施例的无线通信系统的简化示意图。该无线通信系统可以包括：比特输入单元、信道编码单元、发送处理单元、信道、接收处理单元、信道译码单元和比特输出单元。其中，信道编码单元包括LDPC编码器和打孔装置。信道译码单元包括LDPC译码器和解打孔装置。发送处理单元包括调制器等需要对传输的比特信息进行处理的一些设备。接收处理单元包括解调器等需要对接收到的传输的比特信息进行处理的一些设备。
比特输入单元，用于获取需要传输的待传输信息。LDPC编码器，存储有LDPC码的基矩阵，用于将信源生成的需要传输的待传输信息进行LDPC编码得到LDPC码。打孔装置，用于对LDPC码进行打孔得到期望的码率的LDPC码。调制器，用于将经过打孔装置打孔后得到LDPC码进行调制得到适合信道传输的信号。信道，用于向信宿传输信号。解调器，用于对经过信道传输的信号进行解调。解打孔装置，用于对打孔后的LDPC码进行解打孔。LDPC译码器，存储有LDPC码的基矩阵，用于对解调器解调后的信号进行LDPC译码，得到需要传输的待传输信息。比特输出单元，用于输出待传输信息。
其中，发送端可以包括比特输入单元、信道编码单元和发射处理单元。接收端可以包括接收处理单元、信道译码单元和比特输出单元。
进一步的，无线通信系统还可以包括：LDPC码的基矩阵生成设备。该LDPC码的基矩阵生成设备用于生成LDPC码的基矩阵。
图2为本发明实施例提供的一种LDPC码的基矩阵生成方法的流程图，如图2所示，该方法可以包括：
需要说明的是，执行本发明实施例的LDPC码的基矩阵生成方法的设备可以是计算机等电子设备。另外，可以知道的是，将LDPC码的基矩阵进行扩展处理，可以得到该LDPC码的校验矩阵，根据该LDPC码的校验矩阵可以唯一确定LDPC码。LDPC码的基矩阵包 括信息位部分和校验位部分，本发明实施例通过以下步骤实现LDPC码的基矩阵的生成。
201、根据所需的最低码率确定基矩阵的校验位部分的大小。
其中，最低码率是根据实际应用场景的需求预先设置的。由于码率等于LDPC码中包括的信息位的比特位数与LDPC码的总比特位数之比，并且LDPC码是根据基矩阵对待传输信息进行编码得到的，假设对基矩阵进行扩展得到校验矩阵时采用的扩展因子为z，那么采用该基矩阵对应的校验矩阵对待传输信息进行编码得到的LDPC码中包含信息位和校验位的比特位数等于拓展因子与基矩阵的长度的乘积，得到的LDPC码中包括的信息位的比特位数等于基矩阵的长度和宽度之差乘以拓展因子，因此，码率可以由基矩阵的长度和宽度确定，而基矩阵的校验位部分为一方阵，这样，根据预设的最低码率便可以确定出基矩阵的校验位部分的大小。
202、根据初始矩阵及校验位部分的大小确定基矩阵的校验位部分。
其中，初始矩阵为具备双对角结构的、大小为m×m的矩阵。初始矩阵的行重(行重指的是矩阵的一行中包含的大于或等于0的元素的个数)和列重(列重指的是矩阵的一列中包含的大于或等于0的元素的个数)均为2。示例性的，m通常可以设置为2或3。当然，也可以设置为其他值，只需保证初始矩阵为具备双对角结构的方阵即可。本发明实施例在此对m的取值不做具体限制。例如，当m＝2时，初始矩阵为一2×2的方阵，如图3所示，该初始矩阵的所有元素均为0。再例如，当m＝3时，初始矩阵为一3×3的方阵，如图4所示，该初始矩阵满足双对角结构的要求。
其中，在已知初始矩阵的大小的情况下，根据校验位部分的大小，还可以确定出由初始矩阵变换到基矩阵的校验位部分所需的变换次数k。示例性的，假设，已知校验位部分的大小为T×T，初始矩阵的大小为m×m，变换次数k为正整数，找到k满足如下式：
2k-1m<T≤2km
当T＝2km时，k次变化后得到的矩阵即是最终生成的基矩阵的校验位部分，当T<2km时，先按k次变化进行矩阵构造，完成后再进行2km-T次矩阵行合并操作，得到最终生成的基矩阵的校验位部分将满足大小为T×T。
确定出由初始矩阵变换到基矩阵的校验位部分所需的变换次数k之后，便可以对初始矩阵进行k次变换处理，以得到k阶变换矩阵Hk，并将该k阶变换矩阵Hk作为基矩阵的校验位部分，k阶变换矩阵Hk为大小为2km×2km的矩阵。
具体的，k次变换处理中的第i次变换处理通过执行以下步骤实现：
步骤1：针对i-1阶变换矩阵Hi-1的第a行，将第a行的第一个非负元素填充到分裂矩阵Si的第2a行的第b个位置，将第a行的第二个非负元素填充到分裂矩阵Si的第2a-1行的第c个位置，分裂矩阵Si中的其余位置的元素为-1，以得到分裂矩阵Si。
其中，分裂矩阵Si为大小为2im×2i-1m的矩阵，i小于或等于k，且大于0的整数，当i＝1时，i-1阶变换矩阵Hi-1为初始矩阵。第a行为i-1阶变换矩阵Hi-1的任意一行，b为第a行的第一个非负元素在第a行的位置，c为第a行的第二个非负元素在第a行的位置，a，b，c均为大于0的整数。
示例性的，按照如图3所示的初始矩阵，在执行步骤1时，在第1次变换处理中，将初始矩阵的第1行的第一个非负元素填充到分裂矩阵S1的第2行的第1个位置，将第1行的第二个非负元素填充到分裂矩阵S1的第1行的第2个位置；并将初始矩阵的第2行的第一个非负元素填充到分裂矩阵S1的第4行的第1个位置，将第2行的第二个非负元素填充到分裂矩阵S1的第3行的第2个位置，分裂矩阵S1中的其余位置的元素为-1，以得到如图3所示的分裂矩阵S1。同理，在第2次变换处理中，将如图3所示的1阶变换矩阵H1的第1行的第一个非负元素填充到分裂矩阵S2的第2行的第2个位置，将第1行的第二个非负元素填充到分裂矩阵S2的第1行的第3个位置； 并将1阶变换矩阵H1的第2行的第一个非负元素填充到分裂矩阵S2的第4行的第1个位置，将第2行的第二个非负元素填充到分裂矩阵S1的第3行的第3个位置；…；将1阶变换矩阵H1的第4行的第一个非负元素填充到分裂矩阵S2的第8行的第1个位置，将第4行的第二个非负元素填充到分裂矩阵S1的第7行的第4个位置，分裂矩阵S2中的其余位置的元素为-1，以得到如图3所示的分裂矩阵S2。
同样的，按照如图4所述的初始矩阵，在执行步骤1时，在第1次变换处理中，将初始矩阵的第1行的第一个非负元素填充到分裂矩阵S1的第2行的第1个位置，将第1行的第二个非负元素填充到分裂矩阵S1的第1行的第2个位置；并将初始矩阵的第2行的第一个非负元素填充到分裂矩阵S1的第4行的第2个位置，将第2行的第二个非负元素填充到分裂矩阵S1的第3行的第3个位置；并将初始矩阵的第3行的第一个非负元素填充到分裂矩阵S1的第6行的第1个位置，将第3行的第二个非负元素填充到分裂矩阵S1的第5行的第3个位置，分裂矩阵S1中的其余位置的元素为-1，以得到如图4所示的分裂矩阵S1。同理，通过第2次的变换处理，便可以得到如图4所述的分裂矩阵S2。
步骤2：根据
Figure PCTCN2016096112-appb-000003
生成补充矩阵Ai。
其中，Ad,e表示补充矩阵Ai第d行第e列的元素，d为小于2im，且大于0的整数，e为小于2i-1m，且大于0的整数。在根据步骤1构造出分裂矩阵Si之后，便可以根据上式构造该分裂矩阵Si的补充矩阵Ai，该补充矩阵Ai的行数和列数与分裂矩阵Si的行数和列数相同，且该补充矩阵Ai的行重为1，列重为2，0元素在纵向以2为偏移因子分布在对角线上。
示例性的，按照如图3所示的初始矩阵，根据上式便可以得到如图3所示的补充矩阵A1和补充矩阵A2。
示例性的，按照如图4所示的初始矩阵，根据上式便可以得到 如图4所示的补充矩阵A1和补充矩阵A2。
步骤3：拼接分裂矩阵Si和补充矩阵Ai以获得i阶变换矩阵Hi＝[Si,Ai]。
其中，在得到分裂矩阵Si和补充矩阵Ai之后，便可以将分裂矩阵Si和补充矩阵Ai进行拼接，以获得i阶变换矩阵Hi＝[Si,Ai]。
示例性的，按照如图3所示的初始矩阵，根据上式便可以得到如图3所示的1阶变换矩阵H1和2阶变换矩阵H2。
示例性的，按照如图4所示的初始矩阵，根据上式便可以得到如图4所示的1阶变换矩阵H1和2阶变换矩阵H2。
将步骤1-步骤3重复执行k次，便可以得到满足校验位部分大小的k阶变换矩阵Hk，也就是说，可以得到基矩阵的校验位部分。
203、根据校验位部分确定的基矩阵的信息位部分。
示例性的，可以根据校验位部分、密度演化(density evolution，DE)理论和边增长算法(progressive edge growth，PEG)方法确定基矩阵的信息位部分。具体的生成过程在通信标准已经进行了规定，本发明实施例在此不再详细赘述。
204、根据校验位部分和信息位部分得到基矩阵。
其中，在得到校验位部分和信息位部分之后，便可以将校验位部分和信息位部分进行拼接，以得到基矩阵。例如，校验位部分为P，信息位部分为Q，那么将校验位部分和信息位部分进行拼接得到的基矩阵＝[Q，P]。
其中，按照上述步骤201-步骤204得到的基矩阵具有固定的打孔图样，其打孔图样参见表1：
表1
Figure PCTCN2016096112-appb-000004
表1中，M表示基矩阵的行数，N表示基矩阵的列数，且M为大于或等于1整数，N为大于或等于1的整数。
另外，需要说明的是，针对本发明实施例中生成的基矩阵，还可以通过先构造具备对角结构的LDPC矩阵，然后通过对该LDPC矩阵进行行列交换使得进行行列交换后的矩阵满足步骤204中所述的基矩阵的结构的方式获得本发明实施例中所述的基矩阵。
本发明实施例提供的LDPC码的基矩阵生成方法，首先，根据所需的最低码率确定基矩阵的校验位部分的大小，并根据确定出的校验位部分的大小，对初始矩阵进行k次变换处理后得到基矩阵的校验位部分，并根据校验位部分确定基矩阵的信息位部分，最后，根据确定出的校验位部分和信息位部分得到基矩阵，这样，生成的基矩阵具有固定的打孔图样，进而保证了接收端根据该固定的打孔图样对基矩阵进行变形得到的变换矩阵的性能，从而降低了译码出错的概率。
图5为本发明实施例提供的一种译码方法的流程图，该方法应用于接收端，该接收端预先配置有如图1所述的实施例中的基矩阵，该基矩阵对应预设的最低码率，如图5所示，该方法可以包括：
301、接收端接收发送端采用预设的初传码率发送的初传LDPC码。
302、接收端确定初传LDPC码包含被打孔比特。
其中，在发送端需向接收端发送待传输信息时，为了提高该待传输信息在信道中传输的可靠性和有效性，发送端可以将待传输信息按照如图1所述的实施例中的基矩阵进行编码，当发送端对待传输信息按照如图1所述的实施例中的基矩阵进行编码之后，得到的LDPC码的码率是等于最低码率的，发送端在发送编码得到的LDPC码之前，会根据初传码率确定是否需要对编码得到的LDPC码进行打孔，若是，则会将编码得到的LDPC码进行打孔处理得到初传LDPC码，然后将初传LDPC码发送至接收端，因此，在接收端接收到初传LDPC码之后，可以先根据初传码率是否大于最低码率来判断该初传LDPC码是否包含被打孔比特，若初传码率大于最低码率，便可以确定初传LDPC码包含被打孔比特，则执行以下步骤303，若初传码率不大于最低码率，便可以确定初传LDPC码不包含打孔比特，则接收端可以先将可能存在的重复比特的软值合并，然后无需对预先配置的基矩阵进行任何变换处理，而是直接采用该基矩阵对初传LDPC码进行译码。
303、接收端根据最低码率和初传码率确定基矩阵的校验位部分中需删除的列数x。
其中，当确定初传LDPC码包含被打孔比特时，则接收端需要先对基矩阵进行变换得到变换矩阵，然后根据变换矩阵对该初传LDPC码进行译码，此时，接收端可以先根据最低码率和发送端发送初传LDPC码的初传码率确定出被打孔的比特位数，即确定出由基矩阵变形得到码率与初传码率相等的变换矩阵需要删除的基矩阵的校验位部分的列数x。
304、接收端对基矩阵进行变换得到第一变换矩阵。
其中，第一变换矩阵的码率与初传码率相等。在接收端确定出基矩阵的校验位部分中需删除的列数x之后，则可以根据确定出的x，由基矩阵的校验位部分的最后一列开始，删除x列，并且，每删除一列，需要合并与该列对应的行，以得到第一变换矩阵。其中， 合并该列对应的行指的是，将该列对应的行之间元素按照对应位置做模2加。
305、接收端采用第一变换矩阵对初传LDPC码进行译码。
其中，在接收端变换得到第一变换矩阵之后，便可以采用第一变换矩阵对初传LDPC码进行译码处理，以便得到发送端需传输给自身的待传输信息。
本发明实施例提供的译码方法，接收端在确定发送端发送的初传LDPC码包含被打孔比特时，首先根据最低码率和初传码率确定基矩阵的校验位部分中需删除的列数x，然后由基矩阵的校验位部分的最后一列开始，删除x列，并每删除一列，合并与列对应的行，得到码率与初传码率相等第一变换矩阵，最后采用得到的第一变换矩阵对初传LDPC码进行译码，通过接收端根据固定的打孔图样，即通过采用由基矩阵的校验位部分的最后一列开始，根据x删除基矩阵的校验位部分中相应数量的列，并每删除一列，合并与列对应的行的方式对基矩阵进行变形得到的变换矩阵，确保了变换矩阵的性能，从而降低了译码出错的概率。
图6为本发明实施例提供的一种编码方法的流程图，该方法应用于发送端，该发送端预先配置有如图1所述的实施例中的基矩阵，该基矩阵对应预设的最低码率，如图6所示，该方法可以包括：
401、发送端采用基矩阵对待传输信息进行编码得到LDPC码。
其中，在发送端需向接收端发送待传输信息时，为了提高该待传输信息在信道中传输的可靠性和有效性，发送端可以将待传输信息按照如图1所述的实施例中的基矩阵进行编码得到适合信道传输的LDPC码，该LDPC码的码率是等于最低码率的。
另外，在本发明实施例中，发送端也可以先通过行列变换将基矩阵的校验位部分变形成一个等价的双对角矩阵，然后利用简化的双对角编码算法实现对待传输信息的快速编码。相应的，若发送端采用该方法实现对待传输信息的编码时，接收端可以预先记录下发送端进行行列变换的顺序，然后在接收到LDPC码之后，先按照发 送端的列变换顺序对LDPC码的顺序进行调整，以得到变换前的顺序，然后再进行译码。
402、发送端确定预设的初传码率大于最低码率。
其中，在发送端对待传输信息进行编码得到LDPC码之后，可以判断预设的初传码率是否大于最低码率，若初传码率大于最低码率，则执行以下步骤403。
若初传码率等于最低码率，则发送端可以直接将LDPC码作为初传LDPC码发送至接收端，若初传码率小于最低码率，则发送端根据初传码率和最低码率确定需要重复的比特的位数，然后从第一个比特开始将编码得到的LDPC码的比特逐个重复添加到该LDPC码的末尾，以生成初传LDPC码，并将初传LDPC码发送至接收端。
403、发送端根据初传码率和最低码率确定需打孔的比特的位数。
其中，若发送端判断得到初传码率大于最低码率，则表明需要对LDPC码进行打孔处理，此时发送端可以根据初传码率和最低码率确定出需打孔的比特位数。
404、发送端根据需打孔的比特的位数，从LDPC码的最后一个比特开始对LDPC码进行打孔生成初传LDPC码。
其中，发送端在确定出需打孔的比特位数之后，便可以根据需打孔的比特的位数，从LDPC码的最后一个比特开始对LDPC码进行打孔生成初传LDPC码。
405、发送端采用初传码率将初传LDPC码发送至接收端。
本发明实施例提供的编码方法，发送端采用基矩阵对待传输信息进行编码得到LDPC码，在确定初传码率大于最低码率时，根据初传码率和最低码率确定需打孔的比特的位数，然后根据需打孔的比特的位数，从LDPC码的最后一个比特开始对LDPC码进行打孔生成初传LDPC码，最后采用初传码率将初传LDPC码发送至接收端，通过从LDPC码的最后一个比特开始对LDPC码进行打孔生成初传LDPC码，使得接收端可以根据固定的打孔图样，即通过采用 由基矩阵的校验位部分的最后一列开始，根据x删除基矩阵的校验位部分中相应数量的列，并每删除一列，合并与列对应的行的方式对基矩阵进行变形得到的变换矩阵，确保了变换矩阵的性能，从而降低了接收端译码出错的概率。
图7-9为本发明实施例提供的一种编译码方法的流程图，该方法应用于无线通信系统，该无线通信系统至少包括发送端和接收端，该发送端和接收端中均预先配置有如图1所述的实施例中的基矩阵，该基矩阵对应预设的最低码率，且假设预先配置在发送端和接收端的基矩阵如图10所示，那么此时的最低码率等于0.5，并假设初传码率为0.7。如图7-9所示，该方法可以包括：
当发送端需向接收端发送待传输信息时，可以采用如图7所示的步骤501-步骤513，完成初传过程，具体为：
501、发送端采用基矩阵对待传输信息进行编码得到LDPC码。
其中，为了提高该待传输信息在信道中传输的可靠性和有效性，发送端可以将待传输信息按照如图10所示的基矩阵进行编码得到LDPC码，该LDPC码的码率是等于最低码率的。具体的编码过程在通信标准已经进行了规定，本发明实施例在此不再详细赘述。
具体的，发送端可以先将如图10所示的基矩阵进行扩展得到对应的校验矩阵，然后，采用得到的校验矩阵对待传输信息进行编码得到LDPC码。其中，基矩阵中所有值为-1的元素进行扩展后得到一个z×z大小的全0矩阵，其他元素进行扩展后得到一个z×z大小的置换矩阵，z为实际的扩展因子。所述的置换矩阵可以由一个单位矩阵根据相应的位移次数进行循环位移获得，位移次数与该元素的值相对应。具体的可根据下述公式(1)对该元素值进行变换，得到位移次数。
Figure PCTCN2016096112-appb-000005
在公式(1)中，z0＝96为扩展因子的最大值，zf为实际的扩展 因子，p(i,j)为基矩阵中第i行第j列的元素的值，
Figure PCTCN2016096112-appb-000006
表示向下取整，p(f,i,j)表示位移次数。
例如，如图10所示的基矩阵中第8行第17个元素为7，假设实际的扩展因子z＝12，那么则可以通过对单位矩阵向右循环位移7次，得到对应的置换矩阵，单位矩阵和得到的置换矩阵如图11所示。
示例性的，假设扩展因子为4，待传输信息为0000 1100 11110001 0101 0101 0100 0111 1011 0111 1000 0001 1100 0001 10010011，采用经如图10所示的基矩阵扩展得到的校验矩阵进行编码得到的LDPC码为0000 1100 1111 0001 0101 0101 0100 0111 1011 01111000 0001 1100 0001 1001 0011 0101 1110 0101 1101 0110 00100000 0100 0001 0011 1010 0011 0011 1001 0011 1011，该LDPC码的码率为0.5。
502、发送端判断预设的初传码率是否大于最低码率。
其中，在发送端对待传输信息进行编码得到LDPC码之后，可以判断预设的初传码率是否大于最低码率，若初传码率大于最低码率，则执行以下步骤503-步骤505；若初传码率等于最低码率，则执行步骤506，若初传码率小于最低码率，则执行步骤507。
503、发送端根据初传码率和最低码率确定需打孔的比特的位数。
其中，若发送端判断得到初传码率大于最低码率，则表明需要对LDPC码进行打孔处理，此时发送端可以根据初传码率和最低码率确定出需打孔的比特位数。
示例性的，根据初传码率为0.7和最低码率为0.5，则确定出的需打孔的比特位数为4。需要说明的是，当根据初传码率和最低码率计算出的需打孔的比特位数为小数时，可以按照向上取整或向下取整的规则确定出实际需打孔的比特位数。本发明在此以向上取整为例。
504、发送端根据需打孔的比特的位数，从LDPC码的最后一个比特开始对LDPC码进行打孔生成初传LDPC码。
示例性的，根据确定出的需打孔的比特位数4，从LDPC码的最后一个比特开始打孔生成初传LDPC码为0000 1100 1111 00010101 0101 0100 0111 1011 0111 1000 0001 1100 0001 1001 0011 01011110 0101 1101 0110 0010 0000 0100 0001 0011 1010 0011 0011 10010011。
505、发送端采用初传码率将初传LDPC码发送至接收端。
506、发送端采用初传码率将LDPC码作为初传LDPC码发送至接收端。
507、发送端根据初传码率和最低码率确定需要重复的比特的位数，然后从第一个比特开始将编码得到的LDPC码的比特逐个重复添加到该LDPC码的末尾，以生成初传LDPC码，并采用初传码率将初传LDPC码发送至接收端。
508、接收端接收发送端采用预设的初传码率发送的初传LDPC码。
509、接收端判断初传LDPC码是否包含被打孔比特。
其中，在接收端接收到初传LDPC码之后，可以先判断该初传LDPC码是否包含被打孔比特，若初传LDPC码包含被打孔比特，则执行以下步骤510-步骤512，若初传LDPC码不包含被打孔比特，则执行以下步骤513。
510、接收端根据最低码率和初传码率确定基矩阵的校验位部分中需删除的列数x。
其中，当确定出初传LDPC码包含被打孔比特时，则接收端需要先对基矩阵进行变换得到变换矩阵，然后根据变换矩阵对该初传LDPC码进行译码，此时，接收端可以先根据最低码率和发送端发送初传LDPC码的初传码率确定出由基矩阵变形得到码率与初传码率相等的变换矩阵需要删除的基矩阵的校验位部分的列数x。
示例性的，根据初传码率0.7和最低码率0.5可以得到需要删除的基矩阵的校验位部分的列数x等于4。需要说明的是，当根据初传码率和最低码率计算出的需要删除的基矩阵的校验位部分的列数 为小数时，可以按照向上取整或向下取整的规则确定出实际需要删除的基矩阵的校验位部分的列数。本发明在此以向上取整为例。
511、接收端对基矩阵进行变换得到第一变换矩阵。
其中，在接收端确定出基矩阵的校验位部分中需删除的列数x之后，则可以根据确定出的x，由基矩阵的校验位部分的最后一列开始，删除x列，并且，每删除一列，需要合并与该列对应的行，以得到第一变换矩阵。针对所述基矩阵的校验位部分中的每列，接收端预先存储有该列和与该列对应的行的对应关系。
其中，所述校验位部分的第2km列与所述基矩阵的第2km行和第2km-1行对应，所述校验位部分的第2km-1列与所述基矩阵的第2km-2行和第2km-3行对应，以此类推，所述校验位部分的第2k-1m+1列与所述基矩阵的第2行和第1行对应。
所述校验位部分的第2k-1m列与所述基矩阵的第2km行、第2km-1行、第2km-2行和第2km-3行对应，所述校验位部分的第2k-1m-1列与所述基矩阵的第2km-4行、第2km-5行、第2km-6行和第2km-7行对应，以此类推，所述校验位部分的第2k-2m+1列与所述基矩阵的第4行、第3行、第2行和第1行对应。
所述校验位部分的第2jm列与所述基矩阵的第2km行、第2km-1行、第2km-2行，…和第2km-2k-j+1+1行对应，所述校验位部分的第2jm-1列与所述基矩阵的第2km-2k-j+1行、第2km-2k-j+1-1行、第2km-2k-j+1-2行，…和第2km-2k-j+2行对应，以此类推，所述校验位部分的第2j-1m+1列与所述基矩阵的第2k-j+1行、…、第2行和第1行对应；j为小于k且大于0的整数。
所述校验位部分的第22m列与所述基矩阵的第2km行、第2km-1行、第2km-2行、…和第2km-2k-1+1行对应，所述校验位部分的第22m-1列与所述基矩阵的第2km-2k-1行、第2km-2k-1-1行、第2km-2k-1-2行，…和第2km-2k行对应，以此类推，所述校验位部分的第21m+1列与所述基矩阵的第2k-1行、…、第2行和第1行对应。
所述校验位部分的第21m列与所述基矩阵的第2km行、第2km-1行、 第2km-2行、…和第2km-2k+1行对应，所述校验位部分的第21m-1列与所述基矩阵的第2km-2k行、第2km-2k-1行、第2km-2k-2行，…和第2km-2k+1行对应，以此类推，所述校验位部分的第20m+1列与所述基矩阵的第2k行、…、第2行和第1行对应。
示例性的，按照如图10所示的基矩阵(该基矩阵的校验位部分是根据初始矩阵经过3次变换处理得到的，初始矩阵为一2*2大小的方阵)，校验位部分的最后一列与基矩阵的第15行和第16行对应，校验位部分的倒数第2列与基矩阵的第13行和第14行对应，校验位部分的倒数第3列与基矩阵的第11行和第12行对应，校验位部分的倒数第4列与基矩阵的第9行和第10行对应，依次类推，校验位部分的倒数第8列与基矩阵的第1行和第2行对应；校验位部分的倒数第9列与基矩阵的第13-16行对应，校验位部分的倒数第10列与基矩阵的第9-12行对应，依次类推，校验位部分的倒数第12列与基矩阵的第1-4行对应；校验位部分的倒数第13列与基矩阵的第9-16行对应，校验位部分的倒数第14列与基矩阵的第1-8行对应。按照这样的对应关系，接收端便可以由基矩阵的校验位部分的最后一列开始，根据x删除基矩阵的校验位部分中相应数量的列，并每删除一列，合并与列对应的行，以得到第一变换矩阵。
示例性的，按照步骤510中的例子，需删除的列数是4，那么可以参考图10，删除校验位部分的最后四列，并合并与该四列对应的行，即删除最后一列，并将最后一列对应的基矩阵的第15行和第16行之间元素按对应位置做模2加，删除倒数第2列，并将倒数第2列对应的基矩阵的第13行和第14行之间元素按对应位置做模2加，删除倒数第3列，并将倒数第3列对应的基矩阵的第11行和第12行之间元素按对应位置做模2加，删除倒数第4列，并将倒数第4列对应的基矩阵的第9行和第10行之间元素按对应位置做模2加，以得到第一变换矩阵。
其中，需要说明的是，在进行删除列，和合并与列对应的行的过程中，可以先删除第2km列至第2k-1m+1列，并将这些列对应的行合 并完，得到一个小于基矩阵的变换矩阵之后，然后再在该小于基矩阵的变换矩阵的基础上，删除第2k-1m列至第2k-2m+1列，并合并这些列对应的行，以此类推。
示例性的，假设需删除的列数为10列，那么可以先将检验位部分的第9列至第16列删除，并合并每个列对应的行，得到如图12所示的变换矩阵，然后再在如图12所述的变换矩阵的基础上，删除最后一列(最后一列对应基矩阵的第8列)和倒数第二列(倒数第二列对应基矩阵的第7列)，并合并每个列对应的行。
512、接收端采用第一变换矩阵对初传LDPC码进行译码。
513、接收端将可能存在的重复比特的软值合并，然后直接采用基矩阵对初传LDPC码进行译码。
其中，需要说明的是，具体的译码过程在通信标准已经进行了规定，本发明实施例在此不再详细赘述。
在执行了如图7所示的步骤501-步骤513之后，便完成了发送端至接收端的初传过程，进一步的，接收端若确定出初传失败，则可以通过执行以下步骤514-步骤526进行重传。具体的，如图8所示，针对初传LDPC码包含被打孔比特的情况，重传过程包括以下步骤514-步骤525。如图9所示，针对初传LDPC码不包含被打孔比特的情况，重传过程包括以下步骤514-步骤516，以及步骤525-步骤526。
514、接收端判断对初传LDPC码的译码是否成功。
其中，在接收端对初传LDPC码进行译码之后，可以判断对该初传LDPC码的译码是否成功，若对初传LDPC码的译码失败，则可以执行以下步骤515-步骤524，若对初传LDPC码的译码成功，则执行以下步骤525。
515、接收端向发送端发送NACK指令。
516、发送端接收接收端发送的NACK指令。
517、响应于NACK指令，发送端根据预设的重传码率生成重传比特。
其中，重传比特中包括部分或全部被打孔的比特，或重传比特中包括全部被打孔的比特，以及从LDPC码的第一个比特开始逐个重复的比特。当被打孔的比特的个数满足重传码率的需求时，发送端可以将部分或全部被打孔的比特组成重传比特，当被打孔的比特的个数不满足重传码率的需求时，发送端可以将全部被打孔比特以及从LDPC码的第一个比特开始逐个重复的比特组成重传比特。
518、发送端将重传比特发送至接收端。
519、接收端接收发送端发送的重传比特。
520、接收端确定重传码率大于最低码率。
当接收端接收到发送端发送的重传比特之后，需先判断重传码率是否大于最低码率，若重传码率大于最低码率，则表明将接收到的重传比特和初传LDPC码包括的所有比特进行拼接(将重传比特和初传LDPC码包括的所有比特进行拼接指的就是将重传比特添加在初传LDPC码包括的所有比特之后)后得到的第一LDPC码仍包含打孔比特，此时接收端可以执行以下步骤521-步骤524，若重传码率小于最低码率，则表明重传比特中包含有与初传LDPC码中包括的比特重复的比特，此时可以先将重传比特和初传LDPC码中包含的比特中代表相同比特的软值合并，然后与剩余的比特进行拼接以得到第一LDPC码，并直接采用基矩阵对该第一LDPC码进行译码。若重传码率等于最低码率，则可以直接将重传比特和初传LDPC码包括的所有比特进行拼接，得到第一LDPC码，然后直接采用基矩阵对该第一LDPC码进行译码。
521、接收端将重传比特和初传LDPC码包括的所有比特进行拼接，得到第一LDPC码。
其中，在接收端接收到发送端重传的重传比特，并确定重传码率大于最低码率之后，可以将重传的重传比特与初传LDPC码进行拼接，得到第一LDPC码，第一LDPC码的码率与重传码率相等。
522、接收端根据最低码率和重传码率确定基矩阵的校验位部分中需删除的列数y。
其中，由于重传码率大于最低码率，因此表明第一LDPC码中包含被打孔比特，此时需再次对基矩阵进行变换得到变换矩阵，因此，接收端需根据最低码率和重传码率确定基矩阵的校验位部分中需删除的列数y。
523、接收端对基矩阵进行变换得到第二变换矩阵。
接收端可以由基矩阵的校验位部分的最后一列开始，删除y列，并每删除一列，合并与列对应的行，得到第二变换矩阵。其中，所述第二变换矩阵的码率与所述重传码率相等。
需要说明的是，本发明实施例中的步骤523的具体变换过程与步骤511的具体变换过程类似，具体描述可以参考步骤511的描述，本发明实施例在此不再详细赘述。
524、接收端采用第二变换矩阵对第一LDPC码进行译码。
具体的，接收端可以先将第二变换矩阵进行扩展得到与该第二变换矩阵对应的校验矩阵，然后采用得到的校验矩阵对第一LDPC码进行译码。扩展过程可以参考本发明实施例中步骤501中对应的描述，本发明实施例在此不再赘述。
其中，在接收端采用了第二变换矩阵对第一LDPC码进行译码之后，可以继续判断对该第一LDPC码的译码是否成功，若判断得到对第一LDPC码的译码失败，则需再次向发送端发送NACK指令，若发送端再次接收到接收端发送的NACK指令，则发送端需重新生成并发送第二重传比特至接收端，直到接收到接收端发送的确认ACK指令或重传的次数达到预设的阈值。
525、接收端向发送端发送ACK指令。
526、发送端进行重传，直到接收到接收端发送的ACK指令或重复传输的次数达到预设阈值。
其中，若发送端接收到接收端发送的NACK指令，则表明接收端对初传LDPC码的译码失败，此时，发送端进行重传，直到接收到接收端发送的ACK指令或重复传输的次数达到预设阈值。
本发明实施例提供的编译码方法，发送端采用基矩阵对待传输 信息进行编码得到LDPC码，在确定初传码率大于最低码率时，根据初传码率和最低码率确定需打孔的比特的位数，然后根据需打孔的比特的位数，从LDPC码的最后一个比特开始对LDPC码进行打孔生成初传LDPC码，最后采用初传码率将初传LDPC码发送至接收端，通过从LDPC码的最后一个比特开始对LDPC码进行打孔生成初传LDPC码，使得接收端可以根据固定的打孔图样，即通过采用由基矩阵的校验位部分的最后一列开始，根据x删除基矩阵的校验位部分中相应数量的列，并每删除一列，合并与列对应的行的方式对基矩阵进行变形得到的变换矩阵，确保了变换矩阵的性能，从而降低了接收端译码出错的概率。
上述主要从各个网元之间交互的角度对本发明实施例提供的方案进行了介绍。可以理解的是，各个网元，例如LDPC码的基矩阵生成设备、接收端、发送端为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的算法步骤，本发明能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
本发明实施例可以根据上述方法示例对LDPC码的基矩阵生成设备、接收端、发送端进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本发明实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在采用对应各个功能划分各个功能模块的情况下，图13示出了上述实施例中涉及的LDPC码的基矩阵生成设备的一种可能的结构 示意图，如图13所示，该LDPC码的基矩阵生成设备可以包括：确定单元61、处理单元62。
其中，确定单元61用于支持LDPC码的基矩阵生成设备执行图2所示的LDPC码的基矩阵生成方法中的步骤201、步骤202、步骤203。
处理单元62用于支持LDPC码的基矩阵生成设备执行图2所示的LDPC码的基矩阵生成方法中的步骤204。
需要说明的是，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
本发明实施例提供的LDPC码的基矩阵生成设备，用于执行上述LDPC码的基矩阵生成方法，因此可以达到与上述LDPC码的基矩阵生成方法相同的效果。
在采用对应各个功能划分各个功能模块的情况下，图14示出了上述实施例中涉及的接收端的一种可能的结构示意图，接收端预先配置有如图1所述的实施例中的基矩阵，如图14所示，该接收端可以包括：接收单元71、确定单元72、变换单元73、译码单元74。
其中，接收单元71，用于支持接收端执行图5所示的译码方法中的步骤301，图7所示的编译码方法中的步骤508，图8所示的编译码方法中的步骤519。
确定单元72，用于支持接收端执行图5所示的译码方法中的步骤302、步骤303、图7所示的编译码方法中的步骤509、步骤510，图8所示的编译码方法中的步骤514、步骤520、步骤522，图9所示的编译码方法中的步骤514。
变换单元73，用于支持接收端执行图5所示的译码方法中的步骤304，图7所示的编译码方法中的步骤511，图8所示的编译码方法中的步骤523。
译码单元74，用于支持接收端执行图5所示的译码方法中的步骤305，图7所示的编译码方法中的步骤512、步骤513，图8所示的编译码方法中的步骤524。
在本发明实施例中，进一步的，如图15所示，所述的接收端还可以包括：存储单元75。
针对基矩阵的校验位部分中的每列，所述存储单元75中预先存储有该列和与该列对应的行的对应关系。
其中，所述校验位部分的第2jm列与所述基矩阵的第2km行、第2km-1行、第2km-2行，…和第2km-2k-j+1+1行对应；所述校验位部分的第2jm-1列与所述基矩阵的第2km-2k-j+1行、第2km-2k-j+1-1行、第2km-2k-j+1-2行，…和第2km-2k-j+2行对应；以此类推；所述校验位部分的第2j-1m+1列与所述基矩阵的第2k-j+1行、…、第2行和第1行对应；j为小于k且大于0的整数。
在本发明实施例中，进一步的，所述接收端还可以包括：发送单元76和拼接单元77。
所述发送单元76，用于支持接收端执行图8所示的编译码方法中的步骤515、步骤525，图9所示的编译码方法中的步骤515、步骤525。
所述拼接单元77，用于支持接收端执行图8所示的编译码方法中的步骤521。
需要说明的是，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
本发明实施例提供的接收端，用于执行上述译码方法，因此可以达到与上述译码方法相同的效果。
在采用对应各个功能划分各个功能模块的情况下，图16示出了上述实施例中涉及的发送端的一种可能的结构示意图，发送端预先配置有如图1所述的实施例中的基矩阵，如图16所示，该发送端可以包括：编码单元81、确定单元82、打孔单元83、发送单元84。
其中，编码单元81，用于支持发送端执行图6所示的编码方法中的步骤401，图7所示的编译码方法中的步骤501。
确定单元82，用于支持发送端执行图6所示的编码方法中的步骤402、步骤403，图7所示的编译码方法中的步骤502、步骤503。
打孔单元83，用于支持发送端执行图6所示的编码方法中的步骤404，图7所示的编译码方法中的步骤504。
发送单元84，用于支持发送端执行图6所示的编码方法中的步骤405，图7所示的编译码方法中的步骤505、步骤506、步骤507，图8所示的编译码方法中的步骤518。
在本发明实施例中，进一步的，如图17所示，该发送端还可以包括：接收单元85和生成单元86。
接收单元85，用于支持发送端执行图8所示的编译码方法中的步骤516。
生成单元86，用于支持发送端执行图8所示的编译码方法中的步骤517。
需要说明的是，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
本发明实施例提供的发送端，用于执行上述编码方法，因此可以达到与上述编码方法相同的效果。
在采用集成的单元的情况下，图18示出了上述实施例中所涉及的LDPC码的基矩阵生成设备的一种可能的结构示意图。如图18所示，该LDPC码的基矩阵生成设备包括：处理模块91和通信模块92。
处理模块91用于对LDPC码的基矩阵生成设备的动作进行控制管理，例如，处理模块91用于支持LDPC码的基矩阵生成设备执行图2中的步骤201、步骤202、步骤203、步骤204，和/或用于本文所描述的技术的其它过程。通信模块92用于支持LDPC码的基矩阵生成设备与其他网络实体的通信，例如与图1、图14、图15、图16或图17中示出的功能模块或网络实体之间的通信。LDPC码的基矩阵生成设备还可以包括存储模块93，用于存储LDPC码的基矩阵生成设备的程序代码和数据。
其中，处理模块91可以是处理器或控制器。其可以实现或执行结合本发明公开内容所描述的各种示例性的逻辑方框，模块和电路。所述处理器也可以是实现计算功能的组合，例如包含一个或多个微 处理器组合，DSP和微处理器的组合等等。通信模块92可以是收发器、收发电路或通信接口等。存储模块93可以是存储器。
当处理模块91为处理器，通信模块92为通信接口，存储模块93为存储器时，本发明实施例所涉及的LDPC码的基矩阵生成设备可以为图21所示的LDPC码的基矩阵生成设备。
在采用集成的单元的情况下，图19示出了上述实施例中所涉及的接收端的一种可能的结构示意图。如图19所示，该接收端包括：处理模块1001和通信模块1002。
处理模块1001用于对接收端的动作进行控制管理，例如，处理模块1001用于支持接收端执行图5中的步骤302、步骤303、步骤304、步骤305，图7中的步骤509、步骤510、步骤511、步骤512、步骤513，图8中的步骤514、步骤520、步骤521、步骤522、步骤523、步骤524，图9中的步骤514，和/或用于本文所描述的技术的其它过程。通信模块1002用于支持接收端与其他网络实体的通信，例如与图1、图13、图16、或图17中示出的功能模块或网络实体之间的通信。
接收端还可以包括存储模块1003，用于存储接收端的程序代码和数据。例如，针对基矩阵的校验位部分中的每列，存储模块1003用于存储该列和与该列对应的行的对应关系。其中，所述校验位部分的第2jm列与所述基矩阵的第2km行、第2km-1行、第2km-2行，…和第2km-2k-j+1+1行对应；所述校验位部分的第2jm-1列与所述基矩阵的第2km-2k-j+1行、第2km-2k-j+1-1行、第2km-2k-j+1-2行，…和第2km-2k-j+2行对应；以此类推；所述校验位部分的第2j-1m+1列与所述基矩阵的第2k-j+1行、…、第2行和第1行对应；j为小于k且大于0的整数。
其中，处理模块1001可以是处理器或控制器。其可以实现或执行结合本发明公开内容所描述的各种示例性的逻辑方框，模块和电路。所述处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，DSP和微处理器的组合等等。通信模块1002可以是收发器、收发电路或通信接口等。存储模块1003可以是存储器。
当处理模块1001为处理器，通信模块1002为收发器，存储模块1003为存储器时，本发明实施例所涉及的接收端可以为图22所示的接收端。
在采用集成的单元的情况下，图20示出了上述实施例中所涉及的发送端的一种可能的结构示意图。如图20所示，该发送端包括：处理模块1101和通信模块1102。
处理模块1101用于对发送端的动作进行控制管理，例如，处理模块1101用于支持发送端执行图6中的步骤401、步骤402、步骤403、步骤404，图7中的步骤501、步骤502、步骤503、步骤504，图8中的步骤517，和/或用于本文所描述的技术的其它过程。通信模块1102用于支持发送端与其他网络实体的通信，例如与图1、图13、图14或图15中示出的功能模块或网络实体之间的通信。发送端还可以包括存储模块1103，用于存储发送端的程序代码和数据。例如，针对基矩阵的校验位部分中的每列，存储模块1103用于存储该列和与该列对应的行的对应关系。其中，所述校验位部分的第2jm列与所述基矩阵的第2km行、第2km-1行、第2km-2行，…和第2km-2k-j+1+1行对应；所述校验位部分的第2jm-1列与所述基矩阵的第2km-2k-j+1行、第2km-2k-j+1-1行、第2km-2k-j+1-2行，…和第2km-2k-j+2行对应；以此类推；所述校验位部分的第2j-1m+1列与所述基矩阵的第2k-j+1行、…、第2行和第1行对应；j为小于k且大于0的整数。
其中，处理模块1101可以是处理器或控制器。其可以实现或执行结合本发明公开内容所描述的各种示例性的逻辑方框，模块和电路。所述处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，DSP和微处理器的组合等等。通信模块1102可以是收发器、收发电路或通信接口等。存储模块1103可以是存储器。
当处理模块1101为处理器，通信模块1102为收发器，存储模块1103为存储器时，本发明实施例所涉及的发送端可以为图23所示的发送端。
图21为本发明实施例提供一种LDPC码的基矩阵生成设备的结 构示意图，如图21所示，该LDPC码的基矩阵生成设备可以包括：至少一个处理器1201、存储器1202、系统总线1203和通信接口1204。
所述存储器1202用于存储计算机执行指令，所述处理器1201与所述存储器1202通过所述系统总线1203连接，当所述LDPC码的基矩阵生成设备运行时，所述处理器1201执行所述存储器1202存储的所述计算机执行指令，以使所述LDPC码的基矩阵生成设备执行如图2所述的LDPC码的基矩阵生成方法，以实现图13所示的LDPC码的基矩阵生成设备中确定单元61和处理单元62的功能。
例如，处理器1201执行所述存储器1202存储的所述计算机执行指令，以使所述LDPC码的基矩阵生成设备执行如图2所述的LDPC码的基矩阵生成方法中的步骤201，以实现图13所示的LDPC码的基矩阵生成设备包括的确定单元61的功能。再例如，处理器1201执行所述存储器1202存储的所述计算机执行指令，以使所述LDPC码的基矩阵生成设备执行如图2所述的LDPC码的基矩阵生成方法中的步骤202，以实现图13所示的LDPC码的基矩阵生成设备包括的确定单元61的功能。再例如，处理器1201执行所述存储器1202存储的所述计算机执行指令，以使所述LDPC码的基矩阵生成设备执行如图2所述的LDPC码的基矩阵生成方法中的步骤204，以实现图13所示的LDPC码的基矩阵生成设备包括的处理单元62的功能。
本实施例还提供一种存储介质，该存储介质可以包括所述存储器1202。
所述处理器1201可以为中央处理器(central processing unit，CPU)。所述处理器1201还可以为其他通用处理器、数字信号处理器(digital signal processing，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
所述处理器1201可以为专用处理器，该专用处理器可以包括基带处理芯片、射频处理芯片等中的至少一个。
所述存储器1202可以包括易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)；所述存储器1202也可以包括非易失性存储器(non-volatile memory)，例如只读存储器(read-only memory，ROM)，快闪存储器(flash memory)，硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)；所述存储器1202还可以包括上述种类的存储器的组合。
所述系统总线1203可以包括数据总线、电源总线、控制总线和信号状态总线等。本实施例中为了清楚说明，在图21中将各种总线都示意为系统总线1203。
所述通信接口1204具体可以是LDPC码的基矩阵生成设备上的收发器。该收发器可以为无线收发器。例如，无线收发器可以是LDPC码的基矩阵生成设备的天线等。所述处理器1201通过所述通信接口1204与其他设备，例如与发送端或接收端之间进行数据的收发。
在具体实现过程中，上述如图2所示的方法流程中的各步骤均可以通过硬件形式的处理器1201执行存储器1202中存储的软件形式的计算机执行指令实现。为避免重复，此处不再赘述。
需要说明的是，本发明实施例提供的LDPC码的基矩阵生成设备中各功能模块的具体工作过程可以参考方法实施例中对应过程的具体描述，本发明实施例在此不再详细赘述。
本发明实施例提供的LDPC码的基矩阵生成设备，用于执行上述LDPC码的基矩阵生成方法，因此可以达到与上述LDPC码的基矩阵生成方法相同的效果。
图22为本发明实施例提供另一种接收端的结构示意图，接收端预先配置有如图1所述的实施例中的基矩阵，如图22所示，该接收端可以包括：至少一个处理器1301、存储器1302、系统总线1303和收发器1304。
所述存储器1302用于存储计算机执行指令，所述处理器1301 与所述存储器1302通过所述系统总线1303连接，当所述接收端运行时，所述处理器1301执行所述存储器1302存储的所述计算机执行指令，以使所述接收端执行如图5所述的译码方法，或图7-图9中任一所述的编译码方法中的相应步骤，以对应实现如图14或图15所述的接收端中接收单元71、确定单元72、变换单元73、译码单元74、存储单元75、发送单元76和拼接单元77的功能。
例如，处理器1301执行所述存储器1302存储的所述计算机执行指令，以使所述接收端执行如图5所述的译码方法中的步骤301，以实现图14或图15所示的接收端包括的接收单元71的功能。再例如，处理器1301执行所述存储器1302存储的所述计算机执行指令，以使所述接收端执行如图7所述的编译码方法中的步骤511，以实现图14或图15所示的接收端包括的变换矩阵73的功能。再例如，处理器1301执行所述存储器1302存储的所述计算机执行指令，以使所述接收端执行如图8所述的编译码方法中的步骤520，以实现图15所示的接收端包括的拼接单元77的功能。
本实施例还提供一种存储介质，该存储介质可以包括所述存储器1302。
所述处理器1301可以为CPU。所述处理器1301还可以为其他通用处理器、DSP、ASIC、FPGA或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
所述处理器1301可以为专用处理器，该专用处理器可以包括基带处理芯片、射频处理芯片等中的至少一个。
所述存储器1302可以包括volatile memory，例如RAM；所述存储器1302也可以包括non-volatile memory，例如ROM，flash memory，HDD或SSD；所述存储器1302还可以包括上述种类的存储器的组合。
所述系统总线1303可以包括数据总线、电源总线、控制总线和信号状态总线等。本实施例中为了清楚说明，在图22中将各种总线 都示意为系统总线1303。
所述收发器1304可以为无线收发器。例如，无线收发器可以是接收端的天线等。所述处理器1301通过所述收发器1304与其他设备，例如与发送端之间进行数据的收发。
在具体实现过程中，上述如图5、图7-图9所示的方法流程中的相应步骤均可以通过硬件形式的处理器1301执行存储器1302中存储的软件形式的计算机执行指令实现。为避免重复，此处不再赘述。
需要说明的是，本发明实施例提供的接收端中各功能模块的具体工作过程可以参考方法实施例中对应过程的具体描述，本发明实施例在此不再详细赘述。
本发明实施例提供的接收端，用于执行上述译码方法，因此可以达到与上述译码方法相同的效果。
图23为本发明实施例提供另一种发送端的结构示意图，发送端预先配置有如图1所述的实施例中的基矩阵，如图23所示，该发送端可以包括：至少一个处理器1401、存储器1402、系统总线1403和收发器1404。
所述存储器1402用于存储计算机执行指令，所述处理器1401与所述存储器1402通过所述系统总线1403连接，当所述发送端运行时，所述处理器1401执行所述存储器1402存储的所述计算机执行指令，以使所述发送端执行如图6所述的编码方法，或图7-图9中任一所述的编译码方法，以对应实现如图16或图17所述的发送端中编码单元81、确定单元82、打孔单元83、发送单元84、接收单元85和生成单元86的功能。
例如，处理器1401执行所述存储器1402存储的所述计算机执行指令，以使所述发送端执行如图6所述的编码方法中的步骤401，以实现图16或图17所示的发送端包括的编码单元81的功能。再例如，处理器1401执行所述存储器1402存储的所述计算机执行指令，以使所述发送端执行如图7所述的编译码方法中的步骤504，以实 现图16或图17所示的发送端包括的打孔单元83的功能。再例如，处理器1401执行所述存储器1402存储的所述计算机执行指令，以使所述发送端执行如图9所述的编译码方法中的步骤526，以实现图16或图17所示的发送端包括的发送单元84的功能。
本实施例还提供一种存储介质，该存储介质可以包括所述存储器1402。
所述处理器1401可以为CPU。所述处理器1401还可以为其他通用处理器、DSP、ASIC、FPGA或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
所述处理器1401可以为专用处理器，该专用处理器可以包括基带处理芯片、射频处理芯片等中的至少一个。
所述存储器1402可以包括volatile memory，例如RAM；所述存储器1402也可以包括non-volatile memory，例如ROM，flash memory，HDD或SSD；所述存储器1402还可以包括上述种类的存储器的组合。
所述系统总线1403可以包括数据总线、电源总线、控制总线和信号状态总线等。本实施例中为了清楚说明，在图23中将各种总线都示意为系统总线1403。
所述收发器1404可以为无线收发器。例如，无线收发器可以是发送端的天线等。所述处理器1401通过所述收发器1404与其他设备，例如与接收端之间进行数据的收发。
在具体实现过程中，上述如图6-图9所示的方法流程中的相应步骤均可以通过硬件形式的处理器1401执行存储器1402中存储的软件形式的计算机执行指令实现。为避免重复，此处不再赘述。
需要说明的是，本发明实施例提供的发送端中各功能模块的具体工作过程可以参考方法实施例中对应过程的具体描述，本发明实施例在此不再详细赘述。
本发明实施例提供的发送端，用于执行上述编码方法，因此可 以达到与上述编码方法相同的效果。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是一个物理单元或多个物理单元，即可以位于一个地方，或者也可以分布到多个不同地方。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该软件产品存储在一个存储介质中，包括若干指令用以使得一个设备(可以是单片机，芯片等)或处理器(processor)执行本发明各 个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种低密度奇偶校验LDPC码的基矩阵生成方法，其特征在于，包括：
    根据所需的最低码率确定基矩阵的校验位部分的大小；
    根据初始矩阵及所述校验位部分的大小确定所述基矩阵的校验位部分；其中，所述初始矩阵为具备双对角结构的、大小为m×m的矩阵，所述校验位部分为对所述初始矩阵进行k次变换处理后得到的k阶变换矩阵Hk，所述k阶变换矩阵Hk为大小为2km×2km的矩阵，k满足2k-1m<T≤2km，T为所述校验位部分的大小；
    根据所述校验位部分确定所述基矩阵的信息位部分；
    根据所述校验位部分和所述信息位部分得到所述基矩阵；
    其中，k次变换处理中的第i次变换处理具体为：
    针对i-1阶变换矩阵Hi-1的第a行，将所述第a行的第一个非负元素填充到分裂矩阵Si的第2a行的第b个位置，将所述第a行的第二个非负元素填充到所述分裂矩阵Si的第2a-1行的第c个位置，所述分裂矩阵Si中的其余位置的元素为-1，以得到所述分裂矩阵Si；其中，所述分裂矩阵Si为大小为2im×2i-1m的矩阵，所述i为小于或等于k，且大于0的整数，当i＝1时，所述i-1阶变换矩阵Hi-1为所述初始矩阵；所述第a行为所述i-1阶变换矩阵Hi-1的任意一行，所述b为所述第a行的第一个非负元素在所述第a行的位置，所述c为所述第a行的第二个非负元素在所述第a行的位置，所述a，所述b，所述c均为大于0的整数；
    根据
    Figure PCTCN2016096112-appb-100001
    生成补充矩阵Ai；其中，Ad,e表示补充矩阵Ai第d行第e列的元素，所述d为小于2im，且大于0的整数，所述e为小于2i-1m，且大于0的整数；
    拼接所述分裂矩阵Si和所述补充矩阵Ai以获得i阶变换矩阵Hi＝[Si,Ai]。
  2. 一种译码方法，其特征在于，应用于接收端，所述接收端预 先配置有如权利要求1所述的基矩阵，所述方法包括：
    所述接收端接收发送端采用预设的初传码率发送的初传低密度奇偶校验LDPC码；
    所述接收端确定所述初传LDPC码包含被打孔比特；
    所述接收端根据所述最低码率和所述初传码率确定所述基矩阵的校验位部分中需删除的列数x；
    所述接收端对所述基矩阵进行变换得到第一变换矩阵；其中，所述第一变换矩阵的码率与所述初传码率相等，所述第一变换矩阵是由所述基矩阵的校验位部分的最后一列开始，将所述检验位部分的x列删除，并每删除一列，合并与所述列对应的行之后得到的矩阵；
    所述接收端采用所述第一变换矩阵对所述初传LDPC码进行译码。
  3. 根据权利要求2所述的方法，其特征在于，针对所述基矩阵的校验位部分中的每列，所述接收端预先存储有该列和与该列对应的行的对应关系；
    其中，所述校验位部分的第2jm列与所述基矩阵的第2km行、第2km-1行、第2km-2行，…和第2km-2k-j+1+1行对应；
    所述校验位部分的第2jm-1列与所述基矩阵的第2km-2k-j+1行、第2km-2k-j+1-1行、第2km-2k-j+1-2行，…和第2km-2k-j+2行对应；
    以此类推；
    所述校验位部分的第2j-1m+1列与所述基矩阵的第2k-j+1行、…、第2行和第1行对应；j为小于k且大于0的整数。
  4. 根据权利要求2或3所述的方法，其特征在于，在所述接收端采用所述第一变换矩阵对所述初传LDPC码进行译码之后，还包括：
    所述接收端确定对所述初传LDPC码的译码失败；
    所述接收端向所述发送端发送非确认NACK指令；
    所述接收端接收所述发送端发送的重传比特；
    若重传码率大于所述最低码率，则所述接收端将所述重传比特和所述初传LDPC码包括的所有比特进行拼接得到第一LDPC码；所述 第一LDPC码的码率与所述重传码率相等；
    所述接收端根据所述最低码率和所述重传码率确定所述基矩阵的校验位部分中需删除的列数y；
    所述接收端对所述基矩阵进行变换得到第二变换矩阵；其中，所述第二变换矩阵是由所述基矩阵的校验位部分的最后一列开始，将所述校验位部分的y列删除，并每删除一列，合并与所述列对应的行之后得到的矩阵，所述第二变换矩阵的码率与所述重传码率相等；
    所述接收端采用所述第二变换矩阵对所述第一LDPC码进行译码。
  5. 一种编码方法，其特征在于，应用于发送端，所述发送端预先配置有如权利要求1所述的基矩阵，所述方法包括：
    所述发送端采用所述基矩阵对待传输信息进行编码得到低密度奇偶校验LDPC码；
    若预设的初传码率大于所述最低码率，则所述发送端根据所述初传码率和所述最低码率确定需打孔的比特的位数；
    所述发送端根据所述需打孔的比特的位数，从所述LDPC码的最后一个比特开始对所述LDPC码进行打孔生成初传LDPC码；
    所述发送端采用所述初传码率将所述初传LDPC码发送至接收端。
  6. 根据权利要求5所述的方法，其特征在于，在所述发送端采用所述初传码率将所述初传LDPC码发送至接收端之后，还包括：
    所述发送端接收所述接收端发送的非确认NACK指令；
    响应于所述NACK指令，所述发送端根据预设的重传码率生成重传比特；其中，所述重传比特中包括部分或全部被打孔的比特，或所述重传比特中包括全部被打孔的比特，以及从所述LDPC码的第一个比特开始逐个重复的比特；
    所述发送端将所述重传比特发送至所述接收端。
  7. 根据权利要求6所述的方法，其特征在于，所述方法还包括：
    若所述发送端再次接收到所述接收端发送的所述NACK指令， 则所述发送端重新生成并发送第一重传比特至所述接收端，直到接收到所述接收端发送的确认ACK指令或重传的次数达到预设的阈值。
  8. 一种低密度奇偶校验LDPC码的基矩阵生成设备，其特征在于，包括：
    确定单元，用于根据所需的最低码率确定基矩阵的校验位部分的大小，并根据所述校验位部分的大小及初始矩阵确定所述基矩阵的校验位部分；其中，所述初始矩阵为具备双对角结构的、大小为m×m的矩阵，所述校验位部分为对所述初始矩阵进行k次变换处理后得到的k阶变换矩阵Hk，所述k阶变换矩阵Hk为大小为2km×2km的矩阵，k满足2k-1m<T≤2km，T为所述校验位部分的大小；并根据所述校验位部分确定所述基矩阵的信息位部分；
    处理单元，用于根据所述确定单元确定出的所述校验位部分和所述信息位部分得到所述基矩阵；
    其中，针对k次变换处理中的第i次变换处理，所述确定单元具体用于：
    针对i-1阶变换矩阵Hi-1的第a行，将所述第a行的第一个非负元素填充到分裂矩阵Si的第2a行的第b个位置，将所述第a行的第二个非负元素填充到所述分裂矩阵Si的第2a-1行的第c个位置，所述分裂矩阵Si中的其余位置的元素为-1，以得到所述分裂矩阵Si；其中，所述分裂矩阵Si为大小为2im×2i-1m的矩阵，所述i为小于或等于k，且大于0的整数，当i＝1时，所述i-1阶变换矩阵Hi-1为所述初始矩阵；所述第a行为所述i-1阶变换矩阵Hi-1的任意一行，所述b为所述第a行的第一个非负元素在所述第a行的位置，所述c为所述第a行的第二个非负元素在所述第a行的位置，所述a，所述b，所述c均为大于0的整数；
    根据
    Figure PCTCN2016096112-appb-100002
    生成补充矩阵Ai；其中，Ad,e表示补充矩阵Ai第d行第e列的元素，所述d为小于2im，且大于0的整数，所述e为小于2i-1m，且大于0的整数；
    拼接所述分裂矩阵Si和所述补充矩阵Ai以获得i阶变换矩阵Hi＝[Si,Ai]。
  9. 一种接收端，其特征在于，所述接收端预先配置有如权利要求1所述的基矩阵，所述接收端包括：
    接收单元，用于接收发送端采用预设的初传码率发送的初传低密度奇偶校验LDPC码；
    确定单元，用于确定所述接收单元接收到的所述初传LDPC码包含被打孔比特，并根据所述最低码率和所述初传码率确定所述基矩阵的校验位部分中需删除的列数x；
    变换单元，用于对所述基矩阵进行变换得到第一变换矩阵；其中，所述第一变换矩阵的码率与所述初传码率相等，所述第一变换矩阵是由所述基矩阵的校验位部分的最后一列开始，将所述检验位部分的x列删除，并每删除一列，合并与所述列对应的行之后得到的矩阵；
    译码单元，用于采用所述变换单元变换得到的所述第一变换矩阵对所述初传LDPC码进行译码。
  10. 根据权利要求9所述的接收端，其特征在于，所述接收端还包括：存储单元；
    针对所述基矩阵的校验位部分中的每列，所述存储单元中预先存储有该列和与该列对应的行的对应关系；
    其中，所述校验位部分的第2jm列与所述基矩阵的第2km行、第2km-1行、第2km-2行，…和第2km-2k-j+1+1行对应；
    所述校验位部分的第2jm-1列与所述基矩阵的第2km-2k-j+1行、第2km-2k-j+1-1行、第2km-2k-j+1-2行，…和第2km-2k-j+2行对应；
    以此类推；
    所述校验位部分的第2j-1m+1列与所述基矩阵的第2k-j+1行、…、第2行和第1行对应；j为小于k且大于0的整数。
  11. 根据权利要求9或10所述的接收端，其特征在于，所述接收端还包括：发送单元和合并单元；
    所述确定单元，还用于确定所述译码单元对所述初传LDPC码的 译码失败；
    所述发送单元，用于向所述发送端发送非确认NACK指令；
    所述接收单元，还用于接收所述发送端发送的重传比特；
    拼接单元，用于若重传码率大于所述最低码率，则将所述接收单元接收到的所述重传比特和所述初传LDPC码包括的所有比特进行拼接得到第一LDPC码；所述第一LDPC码的码率与所述重传码率相等；
    所述确定单元，还用于根据所述最低码率和所述重传码率确定所述基矩阵的校验位部分中需删除的列数y；
    所述变换单元，还用于对所述基矩阵进行变换得到第二变换矩阵；其中，所述第二变换矩阵是由所述基矩阵的校验位部分的最后一列开始，将所述校验位部分的y列删除，并每删除一列，合并与所述列对应的行之后得到的矩阵，所述第二变换矩阵的码率与所述重传码率相等；
    所述译码单元，还用于采用所述变换单元变换得到的所述第二变换矩阵对所述第一LDPC码进行译码。
  12. 一种发送端，其特征在于，所述发送端预先配置有如权利要求1所述的基矩阵，所述发送端包括：
    编码单元，用于采用所述基矩阵对待传输信息进行编码得到低密度奇偶校验LDPC码；
    确定单元，用于若预设的初传码率大于所述最低码率，则根据所述初传码率和所述最低码率确定需打孔的比特的位数；
    打孔单元，用于根据所述确定单元确定出的所述需打孔的比特的位数，从所述编码单元编码得到的所述LDPC码的最后一个比特开始对所述LDPC码进行打孔生成初传LDPC码；
    发送单元，用于采用所述初传码率将所述初传LDPC码发送至接收端。
  13. 根据权利要求12所述的发送端，其特征在于，还包括：接收单元和生成单元；
    接收单元，用于接收所述接收端发送的非确认NACK指令；
    生成单元，用于响应于所述接收单元接收到的所述NACK指令，根据预设的重传码率生成重传比特；其中，所述重传比特中包括部分或全部被打孔的比特，或所述重传比特中包括全部被打孔的比特，以及从所述LDPC码的第一个比特开始逐个重复的比特；
    所述发送单元，还用于将所述生成单元生成的所述重传比特发送至所述接收端。
  14. 根据权利要求13所述的发送端，其特征在于，
    所述生成单元，还用于若再次接收到所述接收端发送的所述NACK指令，则重新生成第一重传比特；
    所述发送单元，还用于发送所述生成单元生成的所述第一重传比特至所述接收端，直到接收到所述接收端发送的确认ACK指令或重传的次数达到预设的阈值。
  15. 一种低密度奇偶校验LDPC码的基矩阵生成设备，其特征在于，包括：至少一个处理器、存储器、系统总线和通信接口；
    所述存储器用于存储计算机执行指令，所述处理器与所述存储器通过所述系统总线连接，当所述LDPC码的基矩阵生成设备运行时，所述处理器执行所述存储器存储的所述计算机执行指令，以使所述LDPC码的基矩阵生成设备执行如权利要求1所述的LDPC码的基矩阵生成方法。
  16. 一种接收端，其特征在于，所述接收端预先配置有如权利要求1所述的基矩阵，所述接收端包括：至少一个处理器、存储器、系统总线和通信接口；
    所述存储器用于存储计算机执行指令，所述处理器与所述存储器通过所述系统总线连接，当所述接收端运行时，所述处理器执行所述存储器存储的所述计算机执行指令，以使所述接收端执行如权利要求2-4中任一项所述的译码方法。
  17. 一种发送端，其特征在于，所述发送端预先配置有如权利要求1所述的基矩阵，所述发送端包括：至少一个处理器、存储器、系统总线和通信接口；
    所述存储器用于存储计算机执行指令，所述处理器与所述存储器通过所述系统总线连接，当所述发送端运行时，所述处理器执行所述存储器存储的所述计算机执行指令，以使所述发送端执行如权利要求5-7中任一项所述的编码方法。
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