WO2017214851A1 - 一种信号传输的方法、发射端及接收端 - Google Patents

一种信号传输的方法、发射端及接收端 Download PDF

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Publication number
WO2017214851A1
WO2017214851A1 PCT/CN2016/085684 CN2016085684W WO2017214851A1 WO 2017214851 A1 WO2017214851 A1 WO 2017214851A1 CN 2016085684 W CN2016085684 W CN 2016085684W WO 2017214851 A1 WO2017214851 A1 WO 2017214851A1
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matrix
codeword
code rate
information sequence
row
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PCT/CN2016/085684
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English (en)
French (fr)
Inventor
马亮
魏岳军
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华为技术有限公司
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Priority to PCT/CN2016/085684 priority Critical patent/WO2017214851A1/zh
Priority to CN201680085716.3A priority patent/CN109155635A/zh
Publication of WO2017214851A1 publication Critical patent/WO2017214851A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

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  • the embodiments of the present invention relate to the field of mobile communications technologies, and in particular, to a signal transmission method, a transmitting end, and a receiving end.
  • the wireless network channel coding requires a flexible code rate to meet the requirements of Hybrid Automatic Repeat Request (HARQ) implementation.
  • Rate matching of Low density parity check code (LDPC) is usually implemented by puncture and extend methods. Both of them need to construct a mother matrix of codewords before implementation. Punching removes bits in some mother codewords to obtain a series of high code rate codes during transmission; expansion increases by adding more parity.
  • the equation constructs codewords of lower code rate from the high code rate mother code. In general, it is necessary to perform puncturing and expansion separately on the basis of the mother matrix to support a wide range of rate matching requirements. Has been widely used in microwave, optical network, WiFi and other fields.
  • the embodiment of the invention provides a signal transmission method, a transmitting end and a receiving end, and the transmitting end respectively performs corresponding deformation processing on the check matrix corresponding to the LDPC code according to the needs of the receiving end, including line combining operation and punching operation; Or do line splitting and expansion Calculations, etc. Then, according to the processed check matrix and the information sequence sent by the source, the coding process is performed, and the codeword is generated and sent to the receiving end for decoding.
  • the punching of the check matrix can improve the code rate of the transmitted codeword. When the punching results in a decrease in performance, the row combining operation can be performed to obtain a high code rate.
  • the code rate can be reduced.
  • the code rate of the low-density parity check code can be flexibly adjusted, and the flexible rate LDPC code can be constructed in a large range. At the same time, it is more convenient for the receiving end to decode the LDPC code.
  • the present invention provides a method for signal transmission, the method comprising: performing a low density parity check code LDPC encoding on a sequence of information according to a code rate of a second codeword and a second matrix; The second codeword is sent to the receiving end; wherein, the second matrix is obtained by performing at least one row combining operation on the mother matrix corresponding to the information sequence, and deleting at least one column of check bits.
  • the method further includes: receiving a negative acknowledgement that the receiving end decodes the second codeword; and if a code rate of the third codeword If the code rate of the matrix corresponding to the information sequence is greater than the code rate of the third codeword, the third codeword is obtained according to the code rate of the third codeword; and the third codeword is sent to the receiving end; wherein the code rate of the third codeword is less than Or equal to the code rate of the second codeword; the third matrix is obtained by performing at least one expansion and at least one row split operation on the second matrix.
  • the receiver receives a negative response to decoding the second codeword; if the code rate of the third codeword is less than or equal to the parent corresponding to the information sequence The code rate of the matrix is obtained according to the mother matrix corresponding to the information sequence, and the third codeword is sent to the receiving end.
  • the second matrix is specifically: a parent matrix corresponding to the information sequence All row elements perform at least one row merge operation to obtain the fourth moment a matrix, wherein the fourth matrix includes information bits and parity bits; and deleting at least one of the column parity bits of the fourth matrix, wherein the total number of columns of the parity bits of the fourth matrix is greater than or equal to two And all elements of at least one column of check digits deleted are less than zero.
  • an embodiment of the present invention provides another method for signal transmission, the method comprising: receiving a second codeword; performing low-density parity check code LDPC decoding on the second codeword according to the second matrix to obtain an information sequence
  • the second matrix is obtained by performing at least one row combining operation on the mother matrix corresponding to the information sequence, and deleting at least one column of check bits.
  • the LDPC decoding fails to perform the second codeword according to the second matrix, the negative response of the second codeword decoding failure is sent to the transmitting end.
  • Receiving a third codeword if the code rate of the third codeword is greater than a code rate of the corresponding mother matrix of the information sequence, determining a third matrix according to a code rate of the third codeword and the second matrix;
  • the third codeword performs LDPC decoding; wherein the code rate of the third codeword is less than or equal to the code rate of the second codeword; and the third matrix is obtained by performing at least one extension and at least one row splitting operation on the second matrix.
  • the negative response of the second codeword decoding failure is sent to the transmitting end.
  • the second matrix is specifically: a parent matrix corresponding to the information sequence Performing at least one row combining operation on all row elements to obtain a fourth matrix, wherein the fourth matrix includes information bits and parity bits; and deleting at least one column of all column parity bits in the fourth matrix, wherein The total number of columns of parity bits of the matrix is greater than or equal to two, and all elements of at least one column of the deleted check bits are less than zero.
  • an embodiment of the present invention provides a transmitting end, where the transmitting end includes: an encoding unit, configured to perform low-density parity check code LDPC encoding according to a code rate of a second codeword and a second matrix a second codeword; a processing unit, configured to perform at least one row combining operation on the mother matrix corresponding to the information sequence, and delete at least one column of check bits to obtain a second matrix; and a sending unit, configured to send the second codeword to Receiving end.
  • an encoding unit configured to perform low-density parity check code LDPC encoding according to a code rate of a second codeword and a second matrix a second codeword
  • a processing unit configured to perform at least one row combining operation on the mother matrix corresponding to the information sequence, and delete at least one column of check bits to obtain a second matrix
  • a sending unit configured to send the second codeword to Receiving end.
  • the transmitting end further includes: a receiving unit, configured to receive a negative response that the receiving end decodes the second codeword;
  • the coding unit is further configured to: when determining that a code rate of the third codeword is greater than a code rate of the mother matrix corresponding to the information sequence, obtain a third codeword according to a code rate of the third codeword and a third matrix; Also used to send the third codeword to the receiving end;
  • the code rate of the third codeword is less than or equal to the code rate of the second codeword; the third matrix is obtained by the processing unit performing the at least one extension and the at least one row split operation on the second matrix.
  • the transmitting end further includes: a receiving unit, configured to receive a negative response of the receiving end to the second codeword decoding; the encoding unit is further configured to determine When the code rate of the third codeword is less than or equal to the code rate of the mother matrix corresponding to the information sequence, the third codeword is obtained according to the mother matrix corresponding to the information sequence; the sending unit is further configured to send the third codeword to the receiving end.
  • the processing unit is specifically configured to: Performing at least one row combining operation on all row elements of the matrix to obtain a fourth matrix, wherein the fourth matrix includes information bits and parity bits; and deleting at least one column of all column parity bits in the fourth matrix, wherein The total number of columns of the parity bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one column of the check bits are less than zero.
  • an embodiment of the present invention provides a receiving end, where the receiving end includes: a receiving unit, configured to receive a second codeword; a processing unit, configured to perform at least one row combining operation on the mother matrix corresponding to the information sequence, and delete at least one column of check bits to obtain a second matrix; and the decoding unit is configured to The second matrix performs low-density parity check code LDPC decoding on the second codeword to obtain an information sequence.
  • the receiving end further includes:
  • a transmitting unit configured to: when the decoding unit fails to perform LDPC decoding on the second codeword according to the second matrix, send a negative acknowledgement that the second codeword decoding fails to the transmitting end; the receiving unit is further configured to receive the first a third codeword; the decoding unit is further configured to: when the code rate of the third codeword is greater than a code rate of the corresponding parent matrix of the information sequence, perform LDPC decoding on the third codeword according to the third matrix; wherein, the third The code rate of the codeword is less than or equal to the code rate of the second codeword; the third matrix is obtained by the processing unit performing at least one expansion and at least one row split operation on the second matrix.
  • the receiving end further includes: a sending unit, configured, when the decoding unit fails to perform LDPC decoding on the second codeword according to the second matrix, The transmitting end sends a negative acknowledgement that the second codeword decoding fails; the receiving unit is further configured to receive the third codeword; the decoding unit is further configured to: when the code rate of the third codeword is less than or equal to the parent matrix corresponding to the information sequence At the code rate, the third codeword is LDPC decoded according to the mother matrix corresponding to the information sequence.
  • the processing unit is specifically configured to: Performing at least one row combining operation on all row elements to obtain a fourth matrix, wherein the fourth matrix includes information bits and parity bits; and deleting at least one column of all column parity bits in the fourth matrix, wherein The total number of columns of parity bits of the matrix is greater than or equal to two, and all elements of at least one column of the deleted check bits are less than zero.
  • the method for signal transmission provided by the embodiment of the present invention can improve the code rate of the transmitted codeword by puncturing the check matrix corresponding to the LDPC code, and perform line merge when the performance of the puncturing result is decreased. Operation, delete a part of the check digit to get a high bit rate.
  • the codeword of the parity bit is increased by performing expansion and row splitting operations on the parity check matrix corresponding to the LDPC code, thereby achieving a reduced code rate.
  • FIG. 1 is a schematic flowchart 100 of a signal transmission method according to Embodiment 1 of the present invention.
  • FIG. 2 is a structural block diagram of expanding a mother matrix downward according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart 300 of another signal transmission method according to Embodiment 2 of the present invention.
  • FIG. 4 is a flow chart 400 of a method for encoding an LDPC code
  • Figure 5 is a flow chart 500 of the LDPC code decoding method
  • FIG. 6 is a schematic diagram of comparison of simulation results of rate matching methods of multiple parity codes provided by an embodiment
  • Figure 7 is a schematic structural diagram 700 of a signal transmission apparatus according to Embodiment 3 of the present invention.
  • FIG. 8 is a schematic structural diagram 800 of another signal transmission apparatus according to Embodiment 4 of the present invention.
  • FIG. 9 is a schematic structural diagram 900 of a signal transmission system according to Embodiment 5 of the present invention.
  • FIG. 10 is a schematic structural diagram 1000 of a transmitting end according to Embodiment 6 of the present invention.
  • FIG. 11 is a schematic structural diagram 1100 of a receiving end according to Embodiment 7 of the present invention.
  • the transmitting end and the receiving end respectively may be network devices such as a base station and a terminal that need to perform data transmission by using a wireless transmission manner.
  • the transmitting end is a base station
  • the corresponding receiving end is a terminal
  • the transmitting end is a terminal
  • the receiving end is a base station. It mainly distinguishes whether the transmitting end is a base station or a terminal, and whether it is an uplink transmission or a downlink transmission according to whether the data transmission is performed.
  • the transmitting end is the terminal, and the corresponding receiving end is the base station.
  • the transmitting end is the base station and the receiving end is the terminal.
  • the transmitting end refers to the base station, and the receiving end refers to the terminal. Since the techniques involved in the present invention are similar in the uplink and downlink implementations, they are not described again.
  • the parity of the codeword is divided into one iteration recoverable codeword according to the order of information recovery in the decoding iteration process, and the codeword can be recovered by 2 iterations until k times.
  • the iterative recoverable codewords are sequentially punched from the columns with smaller k values according to the number of punches actually needed.
  • the information of all the iterated recoverable codewords that are punctured can be recovered after one iteration.
  • k times of iterative recoverable codeword information requires k iterations. To recover.
  • the so-called puncturing means that in the process of wireless transmission, the codeword of the partial check bit in the codeword selected by the transmitting end is not transmitted, and the receiving end sets the channel confidence of the non-transmitted codeword to be determined during decoding. 0.
  • the mother matrix of an LDPC code is:
  • the expansion factor means that each element in the matrix represents a square matrix, when the expansion factor is At 12 o'clock, the square is a 12 ⁇ 12 square matrix.
  • the elements in the matrix H c may include -1, 0, and a positive integer greater than zero.
  • the representative square matrix is a 12 ⁇ 12 all-zero matrix.
  • the representative square is a 12 ⁇ 12 unit matrix.
  • the element is a positive integer greater than 1, it indicates that the square matrix is a square matrix obtained by cyclically shifting a 12 ⁇ 12 unit matrix.
  • each element in the matrix is 49, then each element in a 12 ⁇ 12 unit matrix needs to be cyclically shifted by 49 bits, and the square matrix finally obtained.
  • the expansion factor is 12, it means that an element matrix will return to the original position of the element after shifting 12 bits, then for the 49 bits of the loop, you can divide the remainder by 49 after dividing by 49.
  • the number of bits to calculate the actual shift of the element That is, when the matrix element is 49, it is only necessary to cyclically shift each element in the square matrix.
  • the matrix has a code rate of 1/2. That is, the information bits are 8 columns and the check digits are 8 columns. The ratio of the number of columns occupied by information bits to the total number of columns is the code rate.
  • the puncturing scheme is executed from the second column, and every other column is punctured, so that only one zero element in each row participates in the puncturing. (Because other elements in a row are -1, that is, all-zero matrix), in the decoding process, as long as iterating once, one punctured zero element of each row is restored, and the information of the parity bit is obtained. Decoding. Therefore, such a punctured point is divided into 1 iteration recoverable codeword.
  • the punctured points are divided into 2 iterative recoverable codewords, that is, in the decoding process, iteratively needs to be iterated twice to implement decoding. For K iterations, the codeword can be recovered, and iterative K times is needed to implement the decoding process.
  • this scheme has good performance in the range of recoverable codewords in one iteration, but when the number of punched holes is large, it is necessary to start 2 iterations to recover the codewords or higher-order punches.
  • the performance of this method will be greatly deteriorated.
  • the parity bit is punctured multiple times. These corrupted check bits will participate in each iterative calculation without providing any information, so the complexity is relatively high during the decoding process.
  • the present invention provides a method of signal transmission.
  • corresponding processing has been performed in the encoding process before the transmitting side transmits the codeword and in the process of decoding in the receiving end.
  • the check matrix corresponding to the LDPC code may be separately subjected to punching and row combining operations to obtain a high code rate; A row splitting operation and an expanding operation may be performed on the parity check matrix to obtain a low code rate, wherein the parity check matrix includes an initial mother matrix of the LDPC code and a correspondingly processed matrix.
  • the codeword with the highest code rate is first received.
  • the negative response of the decoding failure may be sent to the transmitting end, so that The transmitting end sends a codeword of a low code rate to the receiving end according to the negative acknowledgement of the decoding failure.
  • the high bit rate and low bit rate mentioned here are relative to the code rate of the code word transmitted by the transmitting end.
  • the embodiment of the present invention includes two signal transmission methods, and the specific method steps are as follows. .
  • FIG. 1 is a schematic flowchart 100 of a signal transmission method according to Embodiment 1 of the present invention. The method includes:
  • Step 110 Perform LDPC encoding on the information sequence according to the code rate of the second codeword and the second matrix to obtain a second codeword.
  • the acquiring of the code rate of the second codeword is actually that the receiving end (in this embodiment, referring to the terminal device) selects an appropriate code length and a code rate according to the channel estimation information, and the signal transmission control signaling is adopted. Parameters such as the corresponding code length and code rate are transmitted to the transmitting end (in this embodiment, the base station).
  • the code rate here is the second code rate.
  • the base station first obtains the code length and the code rate through the signal transmission control signaling, and performs at least one row combining operation on the mother matrix of the preset LDPC code according to the code length and the code rate, and deletes at least one column of the check bits. , get the second matrix. A second codeword is then obtained at a code rate according to the second matrix and the second codeword.
  • the mother matrix of the LDPC code is the check matrix with the lowest code rate corresponding to the information sequence.
  • the medium information sequence is a source bit transmitted by the source received by the transmitting end.
  • the mother matrix is pre-agreed between the base station and the terminal device, that is, in the base station and the terminal device, there is an m row and n column mother matrix.
  • a mother matrix may include m rows of n-m column information bits and m rows and m columns of parity bits.
  • the calculation of the code rate is the ratio of the number of columns of information bits of a mother matrix to the total number of columns of the mother matrix.
  • the LDPC code is a parent matrix H(m,n) of a quasi cycle low density parity check code (QC-LDPC) with a spreading factor of z, and the code rate can be given by formula 1- 1 means:
  • Ci denote the i-th column of the mother matrix.
  • d(Ci) represents the column weight of the i-th column (after the parity check matrix is expanded, the number of non-zero elements in each row is called row weight, and the number of non-zero elements in each column is called column weight).
  • the process of obtaining the second matrix specifically is as follows:
  • Step 110a Perform at least one row combining operation on all row elements of the parent matrix corresponding to the information sequence to obtain a fourth matrix.
  • the mother matrix contains elements of m rows and n columns.
  • the elements in the m row can be divided into groups, each group including at least two rows of elements.
  • modulo 2 addition operations are performed on the elements of at least two rows one by one.
  • a corresponding fourth matrix is obtained, wherein the fourth matrix is i rows and n columns, and i is a positive integer smaller than m.
  • the elements of the m rows can be directly subjected to a row combining operation, that is, all the row elements are subjected to the modulo-2 addition operation one by one to obtain the fourth matrix.
  • the fourth matrix is 1 row and n columns.
  • each row element in the m matrix and n column parent matrix only participates in one row merge operation, and cannot participate in multiple operations.
  • the modulo-2 addition operation is only a specific method in this embodiment, and other methods are not limited in the embodiment of the present invention.
  • the acquired fourth matrix includes information bits and check bits.
  • Step 110b Delete at least one of the check bits of all the columns in the fourth matrix to obtain the second matrix.
  • the fourth matrix is obtained, and the fourth matrix may include information bits of i rows and m columns and parity bits of i rows of n-m columns. There may be at least one column of elements in the check digit that are less than zero. As can be seen from the above, an element smaller than zero represents an all-zero submatrix. Therefore, a column of elements of this class can be deleted to obtain a second matrix.
  • step 110a the method may further include: step 110c:
  • At least one of the m-row m-column check bits of the mother matrix is punctured.
  • the check bits of at least one column of the punched holes are not adjacent to each other.
  • the selected columns of punched holes are separated by at least one column.
  • the two columns that need to be punched are separated by only one column.
  • the first column selecting punctured set Cset 0 described hereinabove according to the actual need to set a column Cset 0 in a plurality of rows or punctured.
  • Punching itself is a way to increase the bit rate.
  • the simple method of punching may not meet the actual needs, and may also lead to performance degradation. Therefore, if the required code rate is high, even if all the columns satisfying the conditions are punctured, if the required high code rate is not satisfied, the steps described below can be used. After the holes are merged by the matrix, a new matrix is obtained, and then the new matrix is punctured to obtain a higher code rate and reduce the decoding complexity.
  • the mother matrix of the low-density parity check code of the m rows and n columns described above may be a matrix of a double diagonal structure or a matrix of other forms. There are no restrictions here.
  • step 110c after the punctured column is punctured according to the principle described in step 110c, at least one row merging operation is performed on the mother matrix of the m rows and n columns, and the mother matrix corresponding to the information sequence of the i row and the n column is obtained.
  • it may include:
  • step 110c Because the check bits of at least one column that need to be punctured have been determined in step 110c, it can be determined that the rows of the two zero elements included in each of the check bits of at least one column of the punctured bits are located.
  • the rows in which the two zero elements included in each column of the check bits are respectively are subjected to row combining operations to obtain the fourth matrix of the i rows and n columns.
  • the second matrix is obtained according to the check bit of deleting at least one column element in the fourth matrix that is less than zero according to step 110b.
  • Punching is performed in the second matrix in accordance with the method described in step 110c so that the number of perforations is f columns. Until the number of columns i n to be punched is satisfied. Thus, the number of columns in the second matrix H' is ni n .
  • the code rate is As such, the code rate has been greatly improved.
  • the right side of the fourth matrix is a double-diagonal structure
  • the right side of the second matrix obtained by combining at least one column of check bits in step 110a and 110b is still a double-diagonal structure, and if the hole is punched, the number is still not satisfied.
  • the above steps may also be repeated for the second matrix, if required, as the case may be. Until the final acquisition of the check matrix code rate meets the required position.
  • Equation 1-2 the parent matrix H(8, 16) of the LDPC code is shown by Equation 1-2:
  • the matrix is a matrix of double diagonal structures with a spreading factor of 12 and a code rate of 1/2.
  • the actual required code rate is 4/5.
  • it is possible to calculate a column i n 6 that needs to be punctured.
  • the puncturing rule introduced in step 110c it can be determined that the columns of the punched holes are four columns of C 10 , C 12 , C 14 , C 16 , and the like.
  • the number of columns that need to be punched is 2 columns.
  • the rows in which the elements greater than or equal to zero existing in C 10 , C 12 , C 14 , and C 16 are respectively merged include, for the two behaviors in which the elements greater than or equal to zero exist in the column C 10 . One line and two lines. Therefore, the first row and the second row are merged. While the C 12, there are two elements of the behavior of greater than or equal to zero where the third and fourth rows. Therefore, the third row and the fourth row are merged. By analogy, the fifth and sixth rows are merged separately, and the seven rows and the eighth row are merged.
  • the matrix obtained after the row merge is:
  • puncturing rule redefine H 'in the column to punch, for example, the new matrix H' of C 10 and C 12.
  • the code rate becomes:
  • the code rate has changed from 1/2 to the required 4/5.
  • the check matrix H of the low density parity check code is a quasi-cyclic LDPC code check matrix of a double diagonal structure, and therefore, the process of obtaining a high code rate is as described above. Said.
  • the present invention is directed to a check matrix corresponding to a quasi-cyclic LDPC code of a double diagonal structure. Can be of any configuration of double diagonal structure The matrix is checked, and the code rate is not a code rate which is 1/2 code rate converted to 4/5 as exemplified in the present embodiment.
  • Step 120 Send the second codeword to the receiving end.
  • the LDPC code to be transmitted may be composed of a retransmission bit segment and an initial transmission bit segment.
  • the base station In the process of transmitting the LDPC code for the first time, the base station generally first transmits only the initial codeword, that is, the second codeword mentioned herein.
  • the base station when the base station sends the LDPC code to be transmitted to the terminal device, the information bit length and the total code length of the second matrix may be transmitted, and whether the mother matrix is subjected to operation processing, an implementation manner of the specific operation processing, and the like.
  • the base station After the terminal device receives the second codeword of the current transmission, if the decoding fails during the decoding process, a negative acknowledgement for decoding the second codeword is sent to the base station.
  • the base station transmits a retransmission bit segment when receiving a negative acknowledgement of the second codeword decoding sent by the terminal device, wherein the retransmission bit segment may be composed of at least one retransmission sub-bit segment.
  • the retransmission bit segment is the code word corresponding to the column deleted when the mother matrix is sequentially processed in step 110.
  • the last deleted codeword will be sent to the terminal device first.
  • the codeword code rate of the retransmission is greater than the code rate of the first codeword, and is less than or equal to the code rate of the second codeword.
  • the retransmitted codeword is a third codeword
  • the third codeword is derived from the code rate of the third codeword and the third matrix.
  • the third matrix mentioned here is actually obtained by performing at least one expansion and at least one line splitting operation according to the second matrix.
  • the mother matrix of the LDPC code described in step 110 is extended at least once and at least once.
  • the split operation is illustrated as an example:
  • the process that can be performed can include two ways.
  • the mother matrix of the low-density parity check code of m rows and n columns is first expanded at least once to obtain the fifth row of the h row and the j column.
  • the matrix is expanded.
  • a lower triangle or an approximate lower triangle structure may be adopted; an all-zero structure is adopted at the upper right of the extended parity check matrix, so that the check bit of the higher code rate is nested at the parity bit of the lower code rate.
  • the matrix in the lower left part can be calculated by density evolution theory to obtain the column redistribution.
  • the value of the elements in the matrix and the specific position of the element distribution are constructed by the PEG algorithm.
  • the lower right part can be filled with a unit matrix. The whole extended matrix thus obtained satisfies the structure of the lower triangle, and the column transformation is not required in the process of obtaining the generator matrix by Gaussian elimination, and the extended row does not affect the original matrix structure.
  • FIG. 2 is a structural block diagram of two extensions of the matrix.
  • the number of rows per extension is equal to the number of columns expanded.
  • the ⁇ 1 row is expanded, and the number of expanded columns is also ⁇ 1 column, that is, the expanded matrix is m + ⁇ 1 row, n + ⁇ 1 column.
  • the second expansion if the number of extended lines is ⁇ 2 lines, the number of expanded columns is also ⁇ 2 columns.
  • the resulting matrix is then m + ⁇ 1 + ⁇ 2 rows, n + ⁇ 1 + ⁇ 2 columns.
  • the line splitting algorithm is actually an inverse of the line merge algorithm in the first embodiment.
  • the specific algorithm is: split the elements of the same row in the mother matrix into two rows, and add the same check digits for the two rows.
  • one line can be split at a time, or multiple lines can be split. Whenever a row is split, the corresponding one adds a check digit with a -1 element.
  • the mother matrix of the low-density parity check code of m rows and n columns may be a matrix of a double diagonal structure.
  • the mother matrix of the low-density parity check code of m rows and n columns is a double-diagonal structure
  • the acquired third matrix will be h f Line j f column.
  • the two elements are respectively placed into the split two lines, and then the same new check bits are added to split the two.
  • the rows are connected so that the right side of the split matrix remains the same as the double diagonal structure.
  • each row participates in a split, for example, the matrix is represented by:
  • Equation 1-7 The check matrix after adding a new check digit is as shown in Equation 1-7:
  • the final step in the splitting process is to replace the two elements with a -1 element with the 0 element in the new parity bit to ensure that the right side of the split check matrix remains double.
  • the diagonal structure does not change.
  • the -1 element in the twelfth column of the four rows is replaced by the 0 element, so that the right side of the check matrix remains unchanged in the double diagonal structure, and the specific check equation is as shown in Equation 1-8:
  • the short loop in the check matrix deteriorates the performance of the decoding, and the line splitting process does not generate a new short loop, and thus does not cause deterioration in decoding performance.
  • the row splitting can be performed first, and then the extended operation is performed.
  • At least one row splitting operation is performed on the mother matrix of the low-density parity check code of m rows and n columns, and the sixth matrix of the m f row n f column is obtained, where f is the number of times of splitting the parent matrix.
  • f is a positive integer greater than or equal to 1;
  • extension method and the line splitting method in the method of the present invention it is found that if the extension method is used to achieve low rate rate matching, although the performance of the codeword waterfall area can be improved, This can lead to performance degradation in the wrong platform area; on the contrary, if the line splitting method is used alone to achieve low bit rate rate matching, the performance of the wrong platform area can be improved, but the performance of the waterfall area is deteriorated.
  • the extension method and the line splitting method are combined, and the ratio of the single column weight and the double column re-column number is flexibly adjusted according to the needs of the working point, and the number of single-column re-columns and the double-column re-column number are maintained at A suitable ratio can improve the performance of the codeword waterfall area (the area where the bit error rate drops rapidly) and improve the performance of the wrong platform area. The overall performance is optimized.
  • the single column weight here is the column with column weight 1.
  • the unit matrix is introduced.
  • the column weight of each column is 1;
  • the double column column is the column with column weight 2, and the double diagonal structure is The column weight is 2, and the row split is the inverse of the row merge.
  • Each split will add a column with a column weight of 2.
  • the third codeword should be a codeword equal to the first codeword, and the third codeword can be sent to the receiving end at this time.
  • the combination of the extended algorithm and the row splitting algorithm can effectively improve the performance of the waterfall area and the performance of the wrong platform area while ensuring that the number of single-column re-columns and double-column re-column columns is at an appropriate ratio. .
  • a method for transmitting a signal according to a first embodiment of the present invention provides a method, a device, and a system for transmitting a signal.
  • the transmitting end separately performs a check matrix corresponding to the LDPC code according to the needs of the receiving end.
  • Deformation processing including line merge operations and puncturing operations; or row splitting operations and extended operations.
  • the coding process is performed, and the codeword is generated and sent to the receiving end for decoding.
  • the punching of the check matrix can improve the code rate of the transmitted codeword.
  • the row combining operation can be performed to obtain a high code rate.
  • the code rate can be reduced.
  • the code rate of the low-density parity check code can be flexibly adjusted, and the flexible rate LDPC code can be constructed in a large range. At the same time, it is more convenient for the receiving end to decode the LDPC code.
  • FIG. 3 is a flowchart of another method for transmitting a signal according to an embodiment of the present invention. The method is mainly performed by the receiving end, and the specific method steps are as follows.
  • Step 310 Receive a second codeword.
  • the second codeword is sent by the transmitting end according to the code rate of the second codeword and the second codeword generated by the second matrix.
  • the receiving end After receiving the second codeword, the receiving end needs to decode the second codeword.
  • Step 320 Perform LDPC decoding on the second codeword according to the second matrix to obtain an information sequence.
  • the second matrix is obtained by performing at least one row combining operation on the mother matrix corresponding to the information sequence, and deleting at least one column of check bits.
  • the step of obtaining the second matrix is: performing at least one row combining operation on all row elements of the parent matrix corresponding to the information sequence to obtain a fourth matrix, wherein the fourth matrix includes information bits and check bits; and deleting all the fourth matrix At least one column of parity bits in the column check bits, wherein the total number of columns of the parity bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one column of the check bits are less than zero.
  • the method step of obtaining the second matrix in more detail has been introduced in the step 110 of the first embodiment.
  • the reader can refer to the step 110 in the first embodiment, and details are not described herein again.
  • the parent matrix corresponding to the information sequence is the mother matrix of the LDPC code, that is, the parity matrix having the lowest code rate.
  • the information sequence is first encoded at the transmitting end, wherein the information sequence is a source bit transmitted by the source received by the transmitting end.
  • the parent matrix is pre-agreed between the base station and the terminal device, that is, in the base station and the terminal device, there is a m row and n column mother matrix.
  • a mother matrix may include m rows of n-m column information bits and m rows and m columns of parity bits.
  • the calculation of the code rate is the ratio of the number of columns of information bits of a mother matrix to the total number of columns of the mother matrix.
  • the LDPC code is a parent matrix H(m,n) of a QC-LDPC code of a double diagonal structure, and the spreading factor is z, and the code rate can be expressed by Equation 3-1:
  • R i denote the i-th row of the mother matrix and C i denote the i-th column of the mother matrix.
  • d(C i ) represents the column weight of the i-th column (after the parity check matrix is expanded, the number of non-zero elements in each row is called row weight, and the number of non-zero elements in each column is called column weight).
  • the receiving end fails to decode the second codeword according to the second matrix.
  • the receiving end sends a negative acknowledgement that the second codeword decoding fails to the transmitting end.
  • the transmitting end receives a negative acknowledgement that the second codeword decoding failed
  • the third codeword is sent to the receiving end. The receiving end receives the third codeword.
  • the third matrix is determined according to the code rate of the third codeword and the second matrix. Moreover, the code rate of the third codeword is less than or equal to the code rate of the second codeword.
  • the specific third matrix acquisition manner is obtained by performing at least one expansion and at least one row splitting operation according to the second matrix. Specifically, how to perform at least one extension and at least one row splitting operation on the second matrix, the method step of obtaining the third matrix has been described in detail in the first embodiment, and is not described here for brevity.
  • the third matrix is equal to the mother matrix corresponding to the information sequence.
  • the receiving end may perform LDPC decoding on the third codeword according to the parent matrix corresponding to the information sequence.
  • the receiving end performs LDPC decoding on the third codeword according to the third matrix.
  • 4 is a flow chart 400 of a method for encoding an LDPC code. Specifically as shown in 4:
  • Step 410 performing LDPC encoding on the input information bits.
  • the transmitting end can encode according to the lowest code rate supported by the rate matching scheme (here said The lowest bit rate is the initial matrix
  • the encoding algorithm can adopt the general Gaussian erasing coding method, or the simplified coding method for the double diagonal structure or other corresponding simplified coding structure. This solution is incorrect.
  • the specific encoding algorithm at the sender side imposes any restrictions.
  • the corresponding part of the codeword is marked as a redundant codeword according to the order in which the mother matrix is extended to the low code rate.
  • m is the total number of times of matrix expansion or row splitting operation; the corresponding part of the codeword is marked as a redundant codeword according to the order of the mother matrix to the high code rate deformation
  • n is the total number of times the matrix puncturing or row merging operation is performed; the remaining coded codeword portion is marked as the base codeword. Since the LDPC code is the system code, the base codeword should contain all information bits to be encoded and redundancy. Codeword And redundant codewords Redundant bits other than . Redundant codeword And redundant codewords Composition rate matching redundancy bits
  • the transmitting end when the transmitting end sends a codeword with a high code rate to the receiving end, the codeword originally transmitted must be the highest code rate of the preset highest code rate.
  • the codeword with the highest code rate is the codeword processed by puncturing and row merging.
  • the transmitting end needs to reissue the codeword that has been deleted.
  • the order of replenishing the deleted codewords is the reverse of the order of deleting the codewords. That is, the last deleted codeword is first reissued to the receiving end. Therefore, redundant codewords The elements in the order are reversed. Similar principle, redundant codeword And redundant codewords Composition rate matching redundancy bits
  • the purpose is also to determine the order in which the transmitting end replenishes the deleted codewords to the receiving end. The specific working process is as described in step 420.
  • Step 420 Send an LDPC coded codeword.
  • the sending device can send the LDPC-encoded codeword.
  • the specific sending process is not described here.
  • FIG. 5 is a schematic flowchart 500 of an LDPC code decoding method, as shown in FIG. 5:
  • Step 510 Decode the initial transmission LDPC codeword according to an initial code rate.
  • the receiving end After receiving the codeword, the receiving end needs to calculate the LDPC code matrix corresponding to the code rate according to the predetermined initial code rate, according to the redundant codeword included therein. And redundant codewords The part of the part is modified accordingly.
  • the specific process is as follows:
  • the receiving end needs to perform k row combining operations on the mother matrix first, k ⁇ 0. After that, if the initial code contains redundant code words Only contains parts Redundant codeword Not included in The elements in the element are punctured elements. The receiving end needs to set the channel soft values of the punctured bits to 0, and then decode the matrix by using the merged mother matrix.
  • the receiving end first performs k-line splitting operation on the mother matrix, k ⁇ 0. If the initial code contains redundant code words It also includes elements that need to be expanded by m matrix, and then m matrix expansion is needed for the mother matrix. After m ⁇ 0, the matrix is split and expanded to decode the matrix.
  • the decoding algorithm may adopt an inverse belief propagation algorithm, a minimum sum algorithm, a layered minimum sum algorithm or other existing LDPC decoding algorithms. This scheme does not impose any restrictions on the specific decoding algorithm at the receiving end.
  • Step 520 if an error occurs in the initial codeword decoding, use a lower than the initial code rate.
  • the codeword is decoded, and the information to be transmitted is obtained from the decoding result.
  • a decoding error flag is returned to the transmitting end.
  • the sender will receive redundant bits according to the predetermined retransmission code rate. A certain number of remaining redundant bits are selected for transmission. After receiving the redundant bits and the initial codewords, the receiving end decodes the merged codewords according to the method described in step 510.
  • step 530 if an error occurs again after the retransmission, the redundant bits are continued to be re-issued until the correct decoding or the maximum number of retransmissions is reached.
  • the receiving end uses the codeword merged after retransmission for decoding again, an error decoding flag is returned to the transmitting end again.
  • the sender continues from the redundant bits Select a certain number of remaining redundant bits to send, if There are no redundant bits that have not been sent yet, then follow Start again The order is repeated to send the previously sent part.
  • the receiving end decodes the merged codewords according to the method described in step 510.
  • Step 530 will be repeated until a correct decoding is reached or a preset maximum number of retransmissions is reached.
  • the simulation curve represented by the K-SR method is from left to right, and the code rate is: 0.5, 0.6, 0.67, 0.8);
  • the simulation curve of the solid circle is the simulation curve realized by the LTE Turbo method, and the code rate of the Turbo code
  • the variation range is from 0.33 to 0.88 (the simulation curve represented by the LTE Turbo method is shown from left to right as shown in the figure, and the code rates are: 0.33, 0.4, 0.5, respectively. 0.6, 0.67, 0.8, 0.88); the curve in the figure is prismatic.
  • the simulation curve realized by the method in this paper (the simulation curve shown in the figure shows the implementation of the simulation curve from left to right, the code rate is: 0.33 , 0.4, 0.5, 0.6, 0.67, 0.8, 0.88).
  • the method is superior to the direct k-SR drilling performance in the range of 0.5 to 0.8; the range of 0.66 to 0.88 is better than the LTE Turbo, in the range of 0.4 to 0.6 and LTE. Turbo performance is close, and the vicinity of 0.33 is slightly worse than LTE Turbo.
  • FIG. 7 is a schematic diagram of an embodiment of the present invention.
  • a schematic diagram of a device structure at a transmitting end, the transmitting end includes: an encoding unit 701, a processing unit 702, and a transmitting unit 703.
  • the encoding unit 701 is configured to perform LDPC encoding on the information sequence according to the code rate of the second codeword and the second matrix to obtain the second codeword.
  • the processing unit 702 is configured to perform at least one row combining operation on the mother matrix corresponding to the information sequence, and delete at least one column of check bits to obtain the second matrix.
  • the processing unit 702 performs at least one row combining operation on all row elements of the parent matrix corresponding to the information sequence to obtain a fourth matrix, wherein the fourth matrix includes information bits and check bits, and deletes all column check bits in the fourth matrix. At least one column of parity bits, wherein the total number of columns of the parity bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one column of the parity bits are less than zero.
  • the sending unit 703 is configured to send the second codeword to the receiving end.
  • the transmitting end may further include: a receiving unit 704, configured to receive a negative response that the receiving end decodes the second codeword.
  • the coding unit 701 is further configured to: when the code rate of the third codeword is greater than the code rate of the mother matrix corresponding to the information sequence, according to the code rate of the third codeword and the third matrix And to a third codeword, wherein a code rate of the third codeword is less than or equal to a code rate of the second codeword.
  • the third matrix is obtained by the processing unit 702 performing at least one expansion and at least one row splitting operation on the second matrix.
  • the coding unit is further configured to: when the code rate of the third codeword is less than or equal to the code rate of the mother matrix corresponding to the information sequence, obtain the third codeword according to the mother matrix corresponding to the information sequence.
  • the sending unit 702 is further configured to send the third codeword to the receiving end.
  • FIG. 8 is a receiving manner according to an embodiment of the present invention.
  • a schematic diagram of a device structure of the terminal, the receiving end includes: a receiving unit 801, a processing unit 802, and a decoding unit 803.
  • the receiving unit 801 is configured to receive the second codeword.
  • the processing unit 802 performs at least one row combining operation on the mother matrix corresponding to the information sequence, and deletes at least one column of parity bits to obtain the second matrix.
  • the specific step includes: the processing unit 802 performs at least one row combining operation on all row elements of the parent matrix corresponding to the information sequence to obtain a fourth matrix, where the fourth matrix includes information bits and check bits, and deletes all columns in the fourth matrix. At least one column of parity bits in the parity bit, wherein the total number of columns of the parity bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one column of the parity bits are less than zero.
  • the decoding unit 803 is configured to perform LDPC decoding on the second codeword according to the second matrix to obtain an information sequence.
  • the receiving end further includes: a sending unit 804.
  • the sending unit 804 is configured to, when the decoding unit fails to perform LDPC decoding on the second codeword according to the second matrix, send a negative acknowledgement that the second codeword decoding fails to the transmitting end.
  • the transmitting end will send a third codeword to the receiving end after receiving a negative acknowledgement that the second codeword decoding fails.
  • the receiving unit 801 is further configured to receive the third codeword.
  • the decoding unit 803 is further configured to perform LDPC decoding on the third codeword according to the third matrix.
  • the code rate of the third codeword is less than or equal to the code rate of the second codeword, and the third matrix is obtained by the processing unit 802 performing at least one extension and at least one row split operation on the second matrix.
  • the decoding unit 803 is further configured to perform LDPC on the third codeword according to the parent matrix corresponding to the information sequence. Decoding.
  • the embodiment of the present invention further provides a signal transmission system.
  • the signal transmission system includes, for example, a transmitting end and a receiving end.
  • the transmitting end and the receiving end respectively can be network devices such as base stations and terminals that need to perform data transmission by wireless transmission.
  • the transmitting end is a base station
  • the corresponding receiving end is a terminal
  • the receiving end is a base station.
  • FIG. 10 is a schematic structural diagram 1000 of a transmitting end according to Embodiment 6 of the present invention. As shown in FIG. 10, the transmitting end includes a processor 1001 and a transmitter 1002.
  • the processor is configured to perform the information sequence according to the code rate of the second codeword and the second matrix
  • the LDPC code obtains the second codeword.
  • the second matrix is obtained by the processor 1001 performing at least one row combining operation on the mother matrix corresponding to the information sequence, and deleting at least one column of check bits.
  • the process of acquiring the second matrix is: performing at least one row combining operation on all row elements of the parent matrix corresponding to the information sequence to obtain a fourth matrix, wherein the fourth matrix includes information bits and check bits, and deleting the fourth matrix At least one of the column check bits, wherein the total number of columns of the check bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one column of check bits are less than zero.
  • the transmitting end may further include a receiver 1003, and receiving a negative response of the receiving end to the second codeword.
  • the transmitting end When the transmitting end receives the negative acknowledgement sent by the receiving end, it needs to resend the codeword of the low bit rate to the receiving end.
  • the processor 1001 is further configured to obtain the third according to the code rate of the third codeword and the third matrix. a codeword, wherein a code rate of the third codeword is less than or equal to a code rate of the second codeword.
  • the third matrix is obtained by the processor 1001 performing at least one expansion and at least one row splitting operation on the second matrix.
  • the processor 1001 is further configured to obtain the third codeword according to the parent matrix corresponding to the information sequence.
  • the transmitter 1002 is configured to send the third codeword to the receiving end.
  • the specific processor encoding process can refer to the method flow part of the LDPC code encoding.
  • FIG. 11 is a schematic structural diagram 1100 of a transmitting end according to Embodiment 7 of the present invention, As shown in FIG. 11, the receiving end includes: a receiver 1101, and a processor 1102.
  • the receiver 1101 is configured to receive a second codeword.
  • the processor 1102 is configured to perform LDPC decoding on the second codeword according to the second matrix to obtain a sequence of information.
  • the second matrix is obtained by the processor 1102 performing at least one row combining operation on the mother matrix corresponding to the information sequence, and deleting at least one column of check bits.
  • the process of acquiring the second matrix is: performing at least one row combining operation on all row elements of the parent matrix corresponding to the information sequence to obtain a fourth matrix, wherein the fourth matrix includes information bits and check bits, and deleting the fourth matrix At least one of the column check bits, wherein the total number of columns of the check bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one column of check bits are less than zero.
  • the receiving end further includes a transmitter 1103, configured to send a negative acknowledgement that the second codeword decoding fails to the transmitting end when the processor fails to perform LDPC decoding on the second codeword according to the second matrix.
  • the transmitting end receives a negative acknowledgement of the decoding failure, the codeword with a lower code rate than the second codeword is retransmitted to the receiving end.
  • the receiver 1101 is further configured to receive a third codeword.
  • the processor 1102 when the code rate of the third codeword is greater than the code rate of the corresponding mother matrix of the information sequence, the processor 1102 is further configured to perform LDPC decoding on the third codeword according to the third matrix.
  • the code rate of the third codeword is less than or equal to the code rate of the second codeword.
  • the third matrix is obtained by the processor 1102 performing at least one expansion and at least one row splitting operation on the second matrix.
  • the processor 1102 is further configured to perform LDPC translation on the third codeword according to the parent matrix corresponding to the information sequence. code.
  • the specific processor decoding process can refer to the method flow part of the LDPC code decoding.
  • the steps of a method or algorithm described in connection with the embodiments disclosed herein can be implemented in hardware, a software module executed by a processor, or a combination of both.
  • the software module can be placed in random access memory (RAM), memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or technical field. Any other form of storage medium known.

Abstract

本发明实施例涉及一种信号传输的方法、发射端及接收端，所述方法包括：根据第二码字的码率以及第二矩阵对信息序列进行低密度奇偶校验码LDPC编码得到第二码字；将第二码字发送至接收端；其中，第二矩阵为将信息序列对应的母矩阵进行至少一次行合并运算后，并删除至少一列校验位得到的。在本发明中，对LDPC码对应的校验矩阵进行打孔可以提高发送码字码率，当打孔导致性能下降较多时，进行行合并运算，删除一部分校验位以获得高码率。或者，通过对LDPC码对应的校验矩阵进行扩展和行分裂运算增加校验位的码字，从而实现降低码率。通过上述方法，可以灵活的调节低密度奇偶校验码的码率，在较大范围内构造速率灵活可变的LDPC码。

Description

一种信号传输的方法、发射端及接收端 技术领域
本发明实施例涉及移动通信技术领域，尤其涉及一种信号传输的方法、发射端及接收端。
背景技术
无线网络信道编码要求码率灵活可变，以满足混合自动重传请求(Hybrid Automatic Repeat request，简称HARQ)实现的需求。低密度奇偶校验码(Low density parity check code，简称LDPC)的速率匹配通常通过打孔(puncture)和扩展(extend)的方法来实现。两者在实施之前均需要构造一个码字的母矩阵，打孔通过在发送过程中去掉部分母码码字中的比特以获得一系列高码率码；扩展则通过增加更多的奇偶校验方程从高码率母码构建更低码率的码字。通常，需要在母矩阵的基础上，分别进行打孔和扩展以支持大范围的速率匹配需求。已被广泛应用于微波，光网络，WiFi等领域。但现有技术对速率兼容低密度奇偶校验码(Rate compatible Low density parity check code，简称RC-LDPC)的研究还不十分成熟，随机打孔和直接扩展等简单方法应用于LDPC码的性能较差，因此，如何在较大范围内构造速率灵活可变的LDPC码是亟待解决的技术问题。
发明内容
本发明实施例提供了一种信号传输的方法、发射端及接收端，发射端根据接收端的需要，分别对LDPC码对应的校验矩阵进行相应的变形处理，包括行合并运算和打孔运算；或者做行分裂运算以及扩展 运算等。然后根据处理后的校验矩阵和信源发送的信息序列做编码处理，生成码字后发送至接收端译码。其中，对校验矩阵进行打孔可以提高发送码字码率，当打孔导致性能下降较多时，进行行合并运算，可以获得高码率。或者，通过对校验矩阵进行扩展和行分裂运算增加校验位的码字，可以实现降低码率。通过上述方法，可以灵活的调节低密度奇偶校验码的码率，在较大范围内构造速率灵活可变的LDPC码。同时，也更加方便接收端对LDPC码进行译码。
第一方面，本发明提供了一种信号传输的方法，该方法包括：根据第二码字的码率以及第二矩阵对信息序列进行低密度奇偶校验码LDPC编码得到第二码字；将第二码字发送至接收端；其中，第二矩阵为将信息序列对应的母矩阵进行至少一次行合并运算后，并删除至少一列校验位得到的。
结合第一方面，在第一方面的第一种可能的实现方式中，所述方法还包括：接收到接收端对所述第二码字译码的否定应答；若第三码字的码率大于信息序列对应的母矩阵的码率，则根据第三码字的码率以及第三矩阵得到第三码字；将第三码字发送至接收端；其中，第三码字的码率小于或者等于第二码字的码率；第三矩阵为将第二矩阵进行至少一次扩展和至少一次行分裂运算得到的。
结合第一方面，在第一方面的第二种可能的实现方式中，接收到接收端对第二码字译码的否定应答；若第三码字的码率小于或者等于信息序列对应的母矩阵的码率，则根据信息序列对应的母矩阵得到第三码字；将第三码字发送至接收端。
结合第一方面至第一方面的第二种可能的实现方式中的任一种，在第一方面的第三种可能的实现方式中，第二矩阵具体为：将信息序列对应的母矩阵的所有行元素进行至少一次行合并运算，获取第四矩 阵，其中第四矩阵包括信息位和校验位；以及删除第四矩阵中所有列校验位中的至少一列校验位，其中，第四矩阵的校验位的总列数大于或者等于二，且删除的至少一列校验位的所有元素均小于零。
第二方面，本发明实施例提供了另一种信号传输的方法，该方法包括：接收第二码字；根据第二矩阵对第二码字进行低密度奇偶校验码LDPC译码得到信息序列；其中，第二矩阵为将信息序列对应的母矩阵进行至少一次行合并运算后，并删除至少一列校验位得到的。
结合第二方面，在第二方面的第一种可能的实现方式中，若根据第二矩阵对第二码字进行LDPC译码失败，则向发射端发送第二码字译码失败的否定应答；接收第三码字；若第三码字的码率大于信息序列的对应的母矩阵的码率，则根据第三码字的码率以及第二矩阵确定第三矩阵；根据第三矩阵对第三码字进行LDPC译码；其中，第三码字的码率小于或者等于第二码字的码率；第三矩阵为将第二矩阵进行至少一次扩展和至少一次行分裂运算得到的。
结合第二方面，在第二方面的第二种可能的实现方式中，若根据第二矩阵对第二码字进行LDPC译码失败，则向发射端发送第二码字译码失败的否定应答；接收第三码字；若第三码字的码率小于或者等于信息序列对应的母矩阵的码率，则根据信息序列对应的母矩阵对第三码字进行LDPC译码。
结合第二方面至第二方面的第二种可能的实现方式中的任一种，在第二方面的第三种可能的实现方式中，第二矩阵具体为：将信息序列对应的母矩阵的所有行元素进行至少一次行合并运算，获取第四矩阵，其中第四矩阵包括信息位和校验位；以及删除第四矩阵中所有列校验位中的至少一列校验位，其中，第四矩阵的校验位的总列数大于或者等于二，且删除的至少一列校验位的所有元素均小于零。
第三方面，本发明实施例提供了一种发射端，该发射端包括：编码单元，用于根据第二码字的码率以及第二矩阵对信息序列进行低密度奇偶校验码LDPC编码得到第二码字；处理单元，用于将信息序列对应的母矩阵进行至少一次行合并运算后，并删除至少一列校验位，获取第二矩阵；发送单元，用于将第二码字发送至接收端。
结合第三方面，在第三方面的第一种可能的实现方式中，发射端还包括：接收单元，用于接收接收端对所述第二码字译码的否定应答；
所述编码单元还用于，确定第三码字的码率大于所述信息序列对应的母矩阵的码率时，根据第三码字的码率以及第三矩阵得到第三码字；发送单元还用于，将第三码字发送至接收端；
其中，第三码字的码率小于或者等于第二码字的码率；第三矩阵为处理单元将第二矩阵进行至少一次扩展和至少一次行分裂运算得到的。
结合第三方面，在第三方面的第二种可能的实现方式中，发射端还包括：接收单元，用于接收接收端对第二码字译码的否定应答；编码单元还用于，确定第三码字的码率小于或者等于信息序列对应的母矩阵的码率时，根据信息序列对应的母矩阵得到第三码字；发送单元还用于，将第三码字发送至接收端。
结合第三方面至第三方面的第二种可能的实现方式中的任一种，在第三方面的第三种可能的实现方式中，所述处理单元具体用于：将信息序列对应的母矩阵的所有行元素进行至少一次行合并运算，获取第四矩阵，其中第四矩阵包括信息位和校验位；以及删除第四矩阵中所有列校验位中的至少一列校验位，其中，第四矩阵的校验位的总列数大于或者等于二，且删除的至少一列校验位的所有元素均小于零。
第四方面，本发明实施例提供了一种接收端，该接收端包括：接 收单元，用于接收第二码字；处理单元，用于对信息序列对应的母矩阵进行至少一次行合并运算，并删除至少一列校验位，获取第二矩阵；译码单元，用于根据第二矩阵对第二码字进行低密度奇偶校验码LDPC译码得到信息序列。
结合第四方面，在第四方面的第一种可能的实现方式中，接收端还包括：
发送单元：用于当译码单元根据第二矩阵对所述第二码字进行LDPC译码失败时，向发射端发送第二码字译码失败的否定应答；接收单元还用于，接收第三码字；译码单元还用于，当第三码字的码率大于信息序列的对应的母矩阵的码率时，根据第三矩阵对第三码字进行LDPC译码；其中，第三码字的码率小于或者等于第二码字的码率；第三矩阵为处理单元将第二矩阵进行至少一次扩展和至少一次行分裂运算得到的。
结合第四方面，在第四方面的第二种可能的实现方式中，接收端还包括：发送单元用于，当译码单元根据第二矩阵对第二码字进行LDPC译码失败时，向发射端发送第二码字译码失败的否定应答；接收单元还用于，接收第三码字；译码单元还用于，当第三码字的码率小于或者等于信息序列对应的母矩阵的码率时，根据信息序列对应的母矩阵对第三码字进行LDPC译码。
结合第四方面至第四方面的第二种可能的实现方式中的任一种，在第四方面的第三种可能的实现方式中，处理单元具体用于，将信息序列对应的母矩阵的所有行元素进行至少一次行合并运算，获取第四矩阵，其中第四矩阵包括信息位和校验位；以及删除第四矩阵中所有列校验位中的至少一列校验位，其中，第四矩阵的校验位的总列数大于或者等于二，且删除的至少一列校验位的所有元素均小于零。
基于上述技术方案，本发明实施例提供的一种信号传输的方法，通过对LDPC码对应的校验矩阵进行打孔可以提高发送码字码率，当打孔导致性能下降较多时，进行行合并运算，删除一部分校验位以获得高码率。或者，通过对LDPC码对应的校验矩阵进行扩展和行分裂运算增加校验位的码字，从而实现降低码率。通过上述方法，可以灵活的调节低密度奇偶校验码的码率，在较大范围内构造速率灵活可变的LDPC码。
附图说明
图1为本发明实施例一提供的一种信号传输方法的流程示意图100；
图2为本发明实施例提供的将母矩阵向下扩展的结构框图；
图3为本发明实施例二提供的另一种信号传输方法的流程示意图300；
图4为LDPC码编码的方法流程示意图400；
图5为LDPC码译码方法流程示意图500；
图6为实施例提供的多种奇偶校验码的速率匹配方法仿真结果对比示意图；
图7为本发明实施三提供的一种信号传输装置的结构示意图700；
图8为本发明实施例四提供的另一种信号传输装置的结构示意图800；
图9为本发明实施例五提供的一种信号传输系统的结构示意图900；
图10为本发明实施例六提供的一种发射端的结构示意图1000；
图11为本发明实施例七提供的一种接收端的结构示意图1100。
具体实施方式
下面通过附图和实施例，对本发明的技术方案做进一步的详细描述。
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。
本申请实施例中，首先要说明的是，发射端及接收端分别可以为需要以无线传输方式进行数据传输的基站、终端等网络设备。例如，当发射端是基站时，对应的接收端就是终端；相反，当发射端是终端时，那么接收端则是基站。主要区分发射端到底是基站还是终端，要根据数据传输是上行链路传输还是下行链路传输。当是上行链路传输时，那么，发射端就是终端，对应的接收端就是基站。相反，如果是下行链路，那么发射端是基站，接收端则是终端。而在下文的具体实施例中，仅以通过下行链路传输数据为例进行说明，即在具体的实施例中，发射端均指的是基站，而接收端则指的是终端。因为本发明所涉及的技术在上行链路和下行链路的实施方式类似，所以不再赘述。
在现有技术中，LDPC码在实现高速率匹配时，所采用的一种方案是在母矩阵上进行随机打孔。本实施例针对双对角线结构的LDPC码，按照解码迭代过程中信息的恢复顺序将码字的校验位划分为1次迭代可恢复码字，2次迭代可恢复码字，直至k次迭代可恢复码字，根据实际需要的打孔数目，从k值较小的列开始逐次打孔。而在译码的过程中，所有被打孔的1次迭代可恢复码字的信息可以在一次迭代以后得到恢复，同理，k次迭代可恢复码字的信息则需要k次迭代可 以恢复。
所谓打孔，是指在无线传输过程中，发送端选择编码后码字中的部分校验位的码字不发送，接收端在译码时将这些不发送的码字对应信道置信度设置为0。
例如：一个LDPC码的母阵为:
Figure PCTCN2016085684-appb-000001
首先简单介绍该矩阵的组成：该矩阵是一个16×8的矩阵，扩展因子为z0＝12，扩展因子指的是，矩阵中的每一个元素均代表的是一个方阵，当扩展因子为12时，则该方阵则是一个12×12的方阵。矩阵Hc中的元素可以包括-1、0和大于0的正整数。其中，当元素为-1时，代表方阵是一个12×12的全0矩阵。当元素为0时，代表方阵是一个12×12的单位矩阵。当元素为大于1的正整数时，则说明该方阵是一个12×12的单位矩阵经过循环移位后获取的方阵。例如，矩阵中的元素是49，则说明一个12×12的单位矩阵中的每一个元素需要循环移位49位，最终获取的方阵。而因为扩展因子是12，也就说明一个单位矩阵当移位12位后，将会回到该元素最初的位置，那么对于循环49位而言，就可以通过49除以12后，再取余数作为计算该元素实际移位的位数。即当矩阵元素为49时，其实只是将方阵中的每一个元素循环移位即可。当然，取余数获取最终的循环移位的个数仅仅是本实施例中的一种具体的实施方法，也可以通过其他方法获取最终的循环移位的位数，这里不做任何的限定。而该矩阵的码率为1/2。即信息位为8列，校验位为8列。信息位所占的列数与总列 数的比值即为码率。
而在打孔时，例如矩阵中对应校验位部分的8列中，从第二列开始执行打孔方案，每隔一列，打孔一列，那么每一行中仅有一个零元素参与了打孔(因为在一行中其他元素均为-1，也就是全零矩阵)，所以在译码过程中，只要迭代一次，恢复每一行的一个被打孔的零元素，获取校验位的信息，实现译码。因此，将此类被打孔的点划分为1次迭代可恢复码字。而当每一行有两个零元素被打孔时，则被打孔的点划分为2次迭代可恢复码字，也即是在译码过程中，需要迭代两次，实现译码。而对于K次迭代可恢复码字，则需要迭代K次，实现译码过程。
由此可以看出，这种方案在1次迭代可恢复码字范围内具有良好的性能，但是当打孔的数目较多时，必须开始2次迭代可恢复码字或者更高阶的打孔时候，该方法性能会有较大恶化。而且，当母矩阵当前码率较低，而为了实现高码率，即将校验位进行多次打孔。而这些被打掉的校验位将会参与每一次的迭代计算却不提供任何信息，因此在译码过程中复杂度相对较高。
而如果当一个母矩阵的码率很高，需要实现低码率时，在现有技术中主要是通过扩展母矩阵来实现，但是单独使用扩展算法虽然能够改善码字瀑布区(误比特率快速下降的区域)的性能(具体如图6所标注的曲线部分)，但是会导致错误平台区(瀑布区后误比特率缓慢下降的区域，如图6所标注的曲线部分，图6中仅在一条曲线上大概的标识了码字瀑布区和错误平台区的位置，其他曲线类似)性能恶化。
为了解决上述技术问题，本发明提供了信号传输的方法。在本发明中，为了避免上述问题，在发射端发送码字之前的编码过程中以及接收端在译码的过程中，就已经做了相应的处理。首先，根据信道条 件选择对LDPC码进行编码的码率，对待传输的LDPC码对应的校验矩阵进行处理时，可以分别对LDPC码对应的校验矩阵执行打孔和行合并运算，以获取高码率；也可以对校验矩阵执行行分裂运算和扩展运算，以获取低码率，其中校验矩阵包括LDPC码最初的母矩阵以及经过相应处理后的矩阵。而在译码过程中，首先接收的是最高码率的码字，如果接收端在根据最高码率的码字进行译码运算失败时，则可以向发射端发送译码失败的否定应答，以便发射端根据该译码失败的否定应答，向接收端发送低码率的码字。当然，这里所说的高码率和低码率均是相对发射端前一次发送的码字的码率而言。与此对应的，本发明实施例中包含了两种信号传输方法，具体方法步骤如下所述。。
下面首先介绍一种信号传输方法，该方法主要应用于发射端，具体如图1所示，图1为本发明实施例一提供的一种信号传输方法流程示意图100，该方法包括：
步骤110，根据第二码字的码率以及第二矩阵对信息序列进行LDPC编码得到第二码字。
具体的，第二码字的码率的获取其实是接收端(在本实施例中，指的是终端设备)会根据信道估计信息选择合适的码长和码率，通过信号传输控制信令将对应的码长和码率等参数发送至发射端(在本实施例中指的是基站)。当然，这里的码率即为第二码率。而基站则先通过信号传输控制信令获取码长和码率，根据码长、码率的不同，对预置的LDPC码的母矩阵进行至少一次行合并运算后，并删除至少一列校验位，获取第二矩阵。然后在根据第二矩阵和第二码字的码率得到第二码字。
其中，需要说明的是，LDPC码的母矩阵，也即是信息序列对应的具有最低码率的校验矩阵。在发射端首先对信息序列进行编码，其 中信息序列为发射端接收的由信源发送的信源比特。
母矩阵是基站和终端设备之间事先约定好的，即在基站和终端设备中，本身就存在一个m行n列母矩阵。一个母矩阵，可以包括m行n-m列信息位和m行m列的校验位。而码率的计算，则是一个母矩阵的信息位的列数和母矩阵总列数的比值。
例如，LDPC码为双对角结构的准循环LDPC码(Quasi cycle Low density parity check code，简称QC-LDPC)的母矩阵H(m,n)，扩展因子为z，码率可以用公式1-1表示：
Figure PCTCN2016085684-appb-000002
假设Ri表示母矩阵第i行，Ci表示母矩阵第i列。d(Ci)表示第i列的列重(校验矩阵展开后，每行中非零元素的个数称为行重，每列中非零元素的个数称为列重)。其中，矩阵H的校验位中的第一列Cn-m的列重d(Cn-m)＝3，其他校验位构成一个集合Cset0＝{Cn-m+1,Cn-m+2,┈┈Cn}，该集合中的任一列Ci的列重d(Ci)＝2，其中，n和m均为正整数，且n大于或者等于m，i为大于或者等于n-m，且小于或者等于n的正整数。
具体获取第二矩阵的过程如下：
步骤110a，对信息序列对应的母矩阵的所有行元素进行至少一次行合并运算，获取第四矩阵。
具体的，因为母矩阵中包含m行n列的元素。而在进行行合并时，可以将m行中的元素分为多组，每一组至少包括两行的元素。在进行行合并时，将至少两行的元素一一对应的做模2加运算。然后获取对应的第四矩阵，其中，第四矩阵为i行n列，i为小于m的正整数。
在特殊的情况下，可以直接将m行的元素直接进行一次行合并运算，即将所有的行元素一一对应的进行模2加运算，获取第四矩阵。 其中，第四矩阵为1行n列。
需要说明的是，m行n列的母矩阵中的每一行元素都仅参与一次行合并运算，而不能参与多次的运算。而进行模2加运算只是本实施例中的一种具体的方法，其他方法本发明实施例不做任何限定。同样的，获取的第四矩阵包括信息位和校验位。
步骤110b，删除第四矩阵中所有列的校验位中的的至少一列校验位，获取第二矩阵。
具体的，经过行合并运算后获取第四矩阵，第四矩阵中可以包括i行m列的信息位和i行n-m列的校验位。在校验位中可能存在至少一列的元素均小于零。由上文中可知，小于零的元素代表的是一个全零子矩阵。因此可以将此类的一列元素删除，获取第二矩阵。
可选的，在步骤110a之前，该方法还可以包括：步骤110c：
对母矩阵m行m列校验位中的至少一列进行打孔。
其中，所打孔的至少一列的校验位之间两两不相邻。换言之，就是在m列的校验位中，所选择的打孔的列之间相隔至少一列。当然，为了能够在母矩阵中，打孔的数目最多，一般而言，两个需要打孔的列之间仅相隔一列。
具体的，打孔的列首先选择在上文中所述的集合Cset0，按照实际需要将集合Cset0中的某一列或者多列进行打孔。在打孔的过程中，为了避免出现2次以上迭代才可恢复的码字，同时为了实现打孔的列数最大化。因此，在本实施例中，可以遵循一种原则，即所有打孔的列不相邻。即，对于任意打孔的列Ci和Cj均属于集合Cset0，且，j-i≠1。如此一来，矩阵H中满足打孔条件时，打孔的最大列数记作h，h＝m/2。这是因为一个矩阵包括n列，而信息位的列数为n-m列，所以校验位的列数为m列，而每隔一列进行一次打孔，那么最多打孔的 列数就是m/2列。
打孔本身，就是一种提高码率的方法。但是，在一定条件下，单纯的打孔方法可能并不满足实际需求，而且还有可能导致性能下降。所以，如果所需要的码率很高，即使在将所有满足条件的列都打孔的情况下，仍然不满足所需的高码率的要求时，则可以下文中所述的步骤，将打孔后的矩阵进行行合并之后，获取新的矩阵，然后在对新的矩阵进行打孔，以获取更高的码率并降低译码复杂度。
进一步的，上文中所述的m行n列的低密度奇偶校验码的母矩阵可以是一个双对角结构的矩阵，或者是其他形式的矩阵。这里不做任何限定。
当所构造m行n列的低密度奇偶校验码的母矩阵是一个双对角结构的矩阵时，
具体的，当所打孔的列是按照步骤110c中所述的原则进行打孔后，对m行n列的母矩阵进行至少一次行合并运算，获取i行n列的信息序列对应的母矩阵，具体可以包括：
假设需要打孔的数目为in列，而in大于步骤110c中所述的h，在步骤110c中已经确定打孔的数目为h列，就是说明还需要打孔的数目是f＝in-h列。
因为，已经在步骤110c中确定了需要打孔的至少一列的校验位，就可以确定打孔的至少一列的校验位中每一列校验位包含的两个零元素所在的行。分别将每一列校验位包含的两个零元素所在的行进行行合并运算，获取i行n列的第四矩阵。
然后，再按照步骤110b中所述的删除第四矩阵中的至少一列元素小于零的校验位，获取第二矩阵。在第二矩阵中按照步骤110c中所述的方法进行打孔，以便于打孔的数目为f列。直至满足所要打孔 的列数in。如此，第二矩阵H′中的列数为n-in。码率则为
Figure PCTCN2016085684-appb-000003
如此，码率已经大大的提高。
若第四矩阵右侧是双对角结构时，经步骤110a合并和110b删除至少一列校验位后得到的第二矩阵右侧依然是双对角结构，如果此次打孔但是数目仍然不满足要求时，在情况允许的情况下，还可以对第二矩阵重复执行上述步骤。直至最终获取校验矩阵的码率符合要求位置。
在一个具体的例子中，例如LDPC码的母矩阵H(8,16)用式1-2所示：
Figure PCTCN2016085684-appb-000004
该矩阵是一个双对角结构的矩阵，扩展因子为12，码率为1/2。而实际要求的码率为4/5。为了保证码率为4/5，所以，可以计算出需要打孔的列in＝6。
Figure PCTCN2016085684-appb-000005
而按照步骤110c中所介绍的打孔规则，可以确定打孔的列为C10、C12、C14、C16等4列。如此，还需要打孔的列数为2列。
所以，需要执行一下步骤：
具体的，分别对C10、C12、C14、C16中存在的大于或者等于零的元素所在的行进行行合并，包括，对于列C10中，存在大于或者等于零的元素所在的两行为第一行和第二行。所以，对第一行和第二行进行行合并。而C12中，存在大于或者等于零的元素所在的两行为第三行和第四行。所以，对第三行和第四行进行行合并。以此类推，分别 对第五行和第六行进行行合并，对七行和第八行做行合并。进行行合并后所获取的矩阵为：
Figure PCTCN2016085684-appb-000006
在进行行合并运算之后，可以看到，C10、C12、C14、C16中元素均变为了全零矩阵的-1元素，因此可以将这些列删除。获取新的矩阵如下：
Figure PCTCN2016085684-appb-000007
在获取的新的矩阵中，按照步骤140的打孔规则，重新确定H′中需要打孔的列，例如新矩阵H′中的C10和C12。打孔之后，码率则变为：
Figure PCTCN2016085684-appb-000008
由此，码率由1/2已经变为了所需要的4/5。
通过打孔和行合并算法相结合，获取高码率的低密度奇偶校验码，在保证提高码率的同时，还使校验矩阵变得更小，降低了编译码的复杂度，增加了迭代译码收敛速度。
需要说明的是，在本发明的实施例中，低密度奇偶校验码的校验矩阵H是一个双对角结构的准循环LDPC码校验矩阵，因此，在获取高码率的过程如上述所述。而本发明所针对的并非仅仅是双对角结构的准循环LDPC码对应的校验矩阵。可以为任意构造的双对角结构的 校验矩阵，而码率也并不是向本实施例中所举例的有1/2码率变换为4/5的码率。
步骤120，将第二码字发送至接收端。
具体的，待传输的LDPC码可以由重传比特段和初传比特段构成。在首次发送LDPC码过程中，基站一般会首先只发送初传码字，即本文中所说的第二码字。
另外，在基站向终端设备发送待传输的LDPC码时，还可以发送第二矩阵的信息位长度、总码长，以及是否对母矩阵进行了运算处理，以及具体运算处理的实施方式等。
当终端设备接收到此次传输的第二码字后，在进行译码过程中，如果译码失败，则会向基站发送一个对第二码字译码的否定应答。此时，基站在接收到终端设备发送的第二码字译码的否定应答时，将会传输重传比特段，其中，重传比特段可以由至少一个重传子比特段构成。这里的重传比特段即为步骤110中对母矩阵进行依次处理时所删除列对应的码字。并且最后删除的码字，将会最先发送至终端设备。其中，重传的码字码率大于第一码字的码率，且小于或者等于第二码字的码率。
例如，重传的码字为第三码字，而第三码字是根据第三码字的码率以及第三矩阵得到的。而这里所说的第三矩阵其实是根据第二矩阵进行至少一次扩展和至少一次行分裂运算得到的。
为了更简便的说明如何对一个矩阵进行至少一次扩展和至少一次行分裂运算，方便读者理解，本实施例中，以对步骤110中所述的LDPC码的母矩阵进行至少一次扩展和至少一次行分裂运算为例进行说明：
对m行n列的母矩阵进行至少一次扩展和至少一次行分裂运算， 获取第三矩阵。
具体的，在对m行n列的低密度奇偶校验码的母矩阵进行至少一次扩展和至少一次行分裂运算执行过程中，首先进行扩展运算还是首先进行行分裂运算，本申请中不做任何限定。
因此，可以执行的过程可以包括两种方式，在第一种执行的方式中，首先对m行n列的低密度奇偶校验码的母矩阵进行至少一次扩展，获取h行j列的第五矩阵，其中，h和j均为正整数，且h大于m，j大于n，h-m等于j-n，即扩展的行数与列数是相等的。
具体的，在母矩阵的基础上，扩展矩阵。为了便于快速编码，可以采用下三角或近似下三角结构；扩展校验矩阵右上方采用全“0"结构，目的是使较高码率的校验比特嵌套在较低码率的校验比特当中；左下部分的矩阵可以通过密度进化理论计算得到列重分布，通过PEG算法构造矩阵中元素的值以及元素分布具体位置。右下部分可以用单位阵填补。这样得到的整个扩展矩阵满足下三角的结构，在用高斯消去法得到生成矩阵的过程中不需要进行列变换，扩展行也不会对原有的矩阵结构产生影响。
具体的向下扩展的示意图如图2所示，图2为对矩阵进行两次扩展的结构框图。其中，每一次扩展的行数和扩展的列数相等。例如，在第一次扩展时，扩展Δ1行，那么扩展的列数同样为Δ1列，即扩展后的矩阵为m+Δ1行，n+Δ1列。同样的，在第二次扩展时，如果扩展的行数是Δ2行，那么扩展的列数同样得是Δ2列。最终获取的矩阵则是m+Δ1+Δ2行，n+Δ1+Δ2列。
扩展后的矩阵所展现的弊端在上文中已经说明，为了实现低码率的速率匹配，又要避免扩展矩阵的弊端。所以还需要执行行分裂的步骤，具体如下：
对h行j列的第二矩阵进行至少一次行分裂运算，获取hf行jf列的的信息序列对应的母矩阵，其中，f为对所述第五矩阵进行行分裂的次数，f为大于或者等于1的正整数。
行分裂算法其实是实施例一中行合并算法的一种逆运算。
具体算法为：将母矩阵中同一行的元素拆分到两行中，并为这两行添加相同的校验位。
具体而言，在进行行分裂时，一次可以只分裂一行，或者也可以分裂多行。每当分裂一行时，对应的会增加一列元素为-1的校验位。可选的，m行n列的低密度奇偶校验码的母矩阵可以为双对角结构的矩阵。
例如，如果m行n列的低密度奇偶校验码的母矩阵是双对角结构时，对h行j列的第五矩阵进行行一次分裂运算后，获取的第三矩阵将会是hf行jf列的。
具体的，将待拆分的行中校验位上的元素拆分成两个元素后，将两个元素分别放置到拆分后的两行，再添加相同的新校验位将分裂的两行连接起来，这样分裂后的矩阵右侧依然保持双对角结构不变。
在一个具体的实施例中，假设每一行都参与行分裂，例如矩阵用下式表示：
Figure PCTCN2016085684-appb-000009
在进行行分裂时，现将校验矩阵H1中的两行元素分别拆开，在拆分的过程中，信息位和校验位上的元素拆分成两个元素后，将两个元素分别放置到拆分后的两行，在拆分时按照均分的原则进行拆分。具体拆分后的矩阵如式1-6所示：
Figure PCTCN2016085684-appb-000010
然后，在校验位的对应列中每一列(校验矩阵H2的第9列和第10列)后面分别添加一列相同的新校验位，并且校验位元素均为-1。具体添加新校验位后的校验矩阵如式1-7所示：
Figure PCTCN2016085684-appb-000011
而进行行分裂的最后一步则是，在添加的新校验位中，将其中某两位为-1的元素替换为0元素，以此来保证分裂后的校验矩阵的右侧依然保持双对角结构不变。根据上式1-7所示的校验矩阵中，则需要将第第一行第十列和第二行第十列的-1元素替换为0元素，将第三行第十二列和第四行第十二列的-1元素替换为0元素，以满足校验矩阵的右侧依然保持双对角结构不变，具体校验式如式1-8所示：
Figure PCTCN2016085684-appb-000012
根据LDPC构造理论，校验矩阵中的短环会恶化译码的性能，而行分裂过程不会产生新的短环，因此不会导致译码性能的恶化。
在本实施例中，仅以行分裂一次，每次分裂时所有的行均参与分裂为例进行说明，而分裂一次，且仅有一行分裂的方式，以及分裂多次的方式与一次类似，这里不再赘述。
而在第二种具体的实现方式中，则可以首先进行行分裂，然后在执行扩展运算。
具体的，对m行n列的低密度奇偶校验码的母矩阵进行至少一次行分裂运算，获取mf行nf列的第六矩阵，其中，f为对母矩阵进行行分裂的次数，f为大于或者等于1的正整数；
对mf行nf列的第六矩阵进行至少一次扩展，获取i行l列的第三矩阵，其中i为大于mf的正整数，l为大于nf的正整数，i-mf等于l-nf。
具体的行分裂的过程与扩展的过程同第一种实施方式类似，这里不再赘述。
需要说明的是，通过不断利用本发明的方法中的扩展方法和行分裂方法进行测试，发现如果单独使用扩展方法实现低码率的速率匹配时，虽然可以改善码字瀑布区的性能，但是却会导致错误平台区的性能恶化；相反，如果单独使用行分裂方法实现低码率的速率匹配时，则可以改善错误平台区的性能，但是却会导致瀑布区性能恶化。因此，在本申请文件中，将扩展方法和行分裂方法相结合，根据工作点的需要，灵活的调整单列重和双列重列数的比例，保持单列重列数和双列重列数在一个合适的比例，即可以改善码字瀑布区(误比特率特快下降的区域)的性能，又能够改善错误平台区的性能。使得总体的性能达到最优。
这里的单列重就是列重为1的列，在向下扩展的过程中会引入单位矩阵，单位矩阵每列列重为1；双列重列就是列重为2的列，双对角结构每列列重均为2，行分裂是行合并的逆操作，每分裂一次都会增加一列列重为2的列。
在另一种可选的方式中，如果接收到接收端发送的对第二码字译码的否定应答时，若第三码字的码率小于或者等于第一码字的码率时，那么第三码字应该是与第一码字相等的码字，此时将第三码字发送至接收端即可。
需要说明的是，通过扩展算法和行分裂算法相结合，在保证单列重列和双列重列列数在一个合适的比例时，可以同时有效的改善瀑布区的性能，以及错误平台区的性能。另外，还可以灵活的获取较大范围内的低码率LDPC码。
本发明实施例一提供的一种信号传输的方法，本发明实施例提供了一种信号传输的方法、装置及系统，发射端根据接收端的需要，分别对LDPC码对应的校验矩阵进行相应的变形处理，包括行合并运算和打孔运算；或者做行分裂运算以及扩展运算等。然后根据处理后的校验矩阵和信源发送的信息序列做编码处理，生成码字后发送至接收端译码。其中，对校验矩阵进行打孔可以提高发送码字码率，当打孔导致性能下降较多时，进行行合并运算，可以获得高码率。或者，通过对校验矩阵进行扩展和行分裂运算增加校验位的码字，可以实现降低码率。通过上述方法，可以灵活的调节低密度奇偶校验码的码率，在较大范围内构造速率灵活可变的LDPC码。同时，也更加方便接收端对LDPC码进行译码。
本发明实施例二提供了另一种信号传输的方法，如图3所示，图3为本发明实施例提供的另一种信号传输方法流程图。该方法主要由接收端执行，具体方法步骤如下，
步骤310，接收第二码字。
具体的，由实施例一中，可知，第二码字为发射端发送的根据第二码字的码率和第二矩阵所生成的第二码字。
而接收端接收到第二码字后，需要对第二码字进行解码。
具体方法如步骤下文所述。
步骤320，根据第二矩阵对第二码字进行LDPC译码得到信息序列。
具体的，第二矩阵为信息序列对应的母矩阵进行至少一次行合并运算后，并删除至少一列校验位得到的。
获取第二矩阵的步骤为：将信息序列对应的母矩阵的所有行元素进行至少一次行合并运算，获取第四矩阵，其中第四矩阵包括信息位和校验位；以及删除第四矩阵中所有列校验位中的至少一列校验位，其中，第四矩阵的校验位的总列数大于或者等于二，且删除的至少一列校验位的所有元素均小于零。
而更详细的获取第二矩阵的方法步骤，已经在实施例一的步骤110中做了介绍，读者可以参考实施例一中的步骤110，这里不再赘述。
需要说明的是，信息序列对应的母矩阵即为LDPC码的母矩阵，也即是具有最低码率的校验矩阵。在发射端首先对信息序列进行编码，其中信息序列为发射端接收的由信源发送的信源比特。
其中，母矩阵是基站和终端设备之间事先约定好的，即在基站和终端设备中，本身就存在一个m行n列母矩阵。一个母矩阵，可以包括m行n-m列信息位和m行m列的校验位。而码率的计算，则是一个母矩阵的信息位的列数和母矩阵总列数的比值。
例如，LDPC码为双对角结构的QC-LDPC码的母矩阵H(m,n)，扩展因子为z，码率可以用公式3-1表示：
Figure PCTCN2016085684-appb-000013
假设Ri表示母矩阵第i行，Ci表示母矩阵第i列。d(Ci)表示第i列的列重(校验矩阵展开后，每行中非零元素的个数称为行重，每列中非零元素的个数称为列重)。其中，矩阵H的校验位中的第一列Cn-m的列重d(Cn-m)＝3，其他校验位构成一个集合Cset0＝{Cn-m+1,Cn-m+2,┈┈Cn}，该集合中的任一列Ci的列重d(Ci)＝2，其中，n和m 均为正整数，且n大于或者等于m，i为大于或者等于n-m，且小于或者等于n的正整数。
当然，在译码的过程中，有可能接收端在根据第二矩阵对第二码字进行译码时，译码失败。此时，接收端会向发射端发送第二码字译码失败的否定应答。当发射端接收到第二码字译码失败的否定应答时，则会向接收端发送第三码字。接收端接收第三码字。
在一种情况中，若第三码字的码率大于信息序列对应的母矩阵的码率，那么第三矩阵则是根据第三码字的码率以及第二矩阵确定的。而且，第三码字的码率是小于或者等于第二码字的码率。
而具体第三矩阵获取方式为根据第二矩阵进行至少一次扩展和至少一次行分裂运算得到的。具体如何对第二矩阵进行至少一次扩展和至少一次行分裂运算，获取第三矩阵的方法步骤已经在实施例一中做了详细介绍，为叙述简便，这里不再赘述。
在另一种情况中，若第三码字的码率小于或者等于信息序列对应的母矩阵的码率，则第三矩阵与信息序列对应的母矩阵相等。接收端可以根据信息序列对应的母矩阵对第三码字进行LDPC译码。
最后，接收端则根据第三矩阵对第三码字进行LDPC译码即可。
在本实施例中如何对LDPC编码和如何对LDPC码译码，已经做了详细的做了单独的介绍，详细内容请见下文中对LDPC码编码的方法流程和对LDPC码译码的方法流程。
图4为LDPC码编码的方法流程示意图400。具体如4所示：
步骤410，对输入信息比特进行LDPC编码。
在初始矩阵的结构，打孔及行合并的实施方法(例如实施例一中打孔及行合并的方法)确定以后，发射端可以根据该速率匹配方案支持的最低码率进行编码(这里所说的最低码率是指在对初始矩阵进行 扩展和行分裂等处理后，所获取的最低码率)，编码算法既可以采用通用的高斯消去编码方法，也可采用针对双对角结构或者其他相应简化编码结构的简化编码方法，本方案不对发送端的具体编码算法做任何限制。
之后，根据母矩阵向低码率扩展的先后顺序将码字中对应的部分标记为冗余码字
Figure PCTCN2016085684-appb-000014
m为矩阵扩展或行分裂操作进行的总的次数；根据母矩阵向高码率变形的先后顺序将码字中对应部分标记为冗余码字
Figure PCTCN2016085684-appb-000015
n为矩阵打孔或行合并操作进行的总的次数；将剩余编码码字部分标记为基础码字，由于LDPC码是系统码，基础码字中应该包含所有待编码的信息比特和除冗余码字
Figure PCTCN2016085684-appb-000016
和冗余码字
Figure PCTCN2016085684-appb-000017
以外的冗余比特。冗余码字
Figure PCTCN2016085684-appb-000018
和冗余码字
Figure PCTCN2016085684-appb-000019
组成速率匹配冗余比特
Figure PCTCN2016085684-appb-000020
这里需要说明的是，发射端在向接收端发送高码率的码字时，最初发送的一定是预设最高码率的码字。而最高码率的码字则是通过打孔和行合并处理后的码字。而接收端在译码过程中，如果根据最高码率的码字译码失败，那么发射端则需要补发已经删除的码字。而补发删除的码字的顺序则是和删除码字顺序相反。即最后删除的码字，最先补发到接收端。因此，冗余码字
Figure PCTCN2016085684-appb-000021
中的元素则是倒序的。类似的原理，将冗余码字
Figure PCTCN2016085684-appb-000022
和冗余码字
Figure PCTCN2016085684-appb-000023
组成速率匹配冗余比特
Figure PCTCN2016085684-appb-000024
的目的同样是为了确定发射端向接收端补发删除码字的顺序。具体工作过程如步骤420所述。
步骤420，发送LDPC编码后的码字。
编码完成后，根据预定的初传码率，按照向量
Figure PCTCN2016085684-appb-000025
的先后顺序，从中选择一定数目的冗余码字，将这些冗余码字和基础码字合并组成初传码字
Figure PCTCN2016085684-appb-000026
确保初传码字满足预定的初传码率。之后，发送设备可以 发送经LDPC编码后的码字，具体发送过程在此不再赘述。
图5为LDPC码译码方法流程示意图500，具体如图5所示：
步骤510，按照初始码率对初传LDPC码字进行译码。
在接收到所述码字后，接收端需要根据预定初传码率，先计算出该码率对应的LDPC码矩阵，依照其中包含的冗余码字
Figure PCTCN2016085684-appb-000027
和冗余码字
Figure PCTCN2016085684-appb-000028
的部分多少，对初始母矩阵进行相应变形。具体过程如下：
例如，假设经过第k次行合并后被删除的冗余比特构成集合Dk，经过k次行合并后未被删除的冗余比特构成集合
Figure PCTCN2016085684-appb-000029
当初传码字不包含冗余码字
Figure PCTCN2016085684-appb-000030
时(初传码字中不进行扩展处理)，假设初传其中包含的冗余码字
Figure PCTCN2016085684-appb-000031
中不包含Dk中的所有元素，而包含全部或者部分
Figure PCTCN2016085684-appb-000032
中的元素，则接收端需要先对母矩阵进行k次行合并操作，k≥0。之后，若初传其中包含的冗余码字
Figure PCTCN2016085684-appb-000033
中仅包含了部分
Figure PCTCN2016085684-appb-000034
中的元素，则冗余码字
Figure PCTCN2016085684-appb-000035
中不包含的
Figure PCTCN2016085684-appb-000036
中的元素为被打孔的元素，接收端需要将这些被打孔的比特的信道软值置为0之后，以行合并后的母矩阵为译码矩阵进行译码。
例如，当初传码字同时包含冗余码字
Figure PCTCN2016085684-appb-000037
和冗余码字
Figure PCTCN2016085684-appb-000038
时，若冗余码字
Figure PCTCN2016085684-appb-000039
中有需要进行k次行分裂操作才能得到的元素，则接收端先对母矩阵进行k次行分裂操作，k≥0。若初传其中包含的冗余码字
Figure PCTCN2016085684-appb-000040
中还包含需要m次矩阵扩展才能获得的元素，则还需要对母矩阵进行m次矩阵扩展，m≥0之后，以行分裂和扩展后的矩阵为译码矩阵进行译码。
译码算法可以采用反向置信传播算法，最小和算法，分层的最小和算法或者其他现有的LDPC译码算法，本方案不对接收端的具体译码算法做任何限制。
步骤520，若初传码字译码出现错误，则使用低于初始码率的合 并后码字进行译码，并从译码结果中获取待传输信息。
如果接收端使用初始码率译码发生错误，则向发送端返回译码错误标记。发送端会根据预定的重传码率，从冗余比特
Figure PCTCN2016085684-appb-000041
中选择一定数目的剩余冗余比特发送。接收端将补发的冗余比特和初传码字合并后，再依据步骤510所述方法对合并码字进行译码。
步骤530，若重传后译码再次出现错误，则继续补发冗余比特直到正确译码或者达到最大重传次数。
如果接收端使用一次重传后合并的码字进行译码再次发生错误，则再次向发送端返回错误译码标记。发送端继续从冗余比特
Figure PCTCN2016085684-appb-000042
中选择一定数目的剩余冗余比特发送，若
Figure PCTCN2016085684-appb-000043
中已没有尚未发送的冗余比特，则按照从
Figure PCTCN2016085684-appb-000044
开始再到
Figure PCTCN2016085684-appb-000045
的顺序重复发送之前发送过的部分。接收端将补发的冗余比特和初传码字合并后，再依据步骤510所述方法对合并码字进行译码。
步骤530将不断重复，直到达成正确译码或者达到预设的最大重传次数。
图6为本发明实施例提供的多种奇偶校验码的速率匹配方法仿真结果对比示意图。其对比了现有的三星公司单独使用K次迭代可恢复码字的方法，LTE Turbo方法和本发明提供的方法之间的性能，信息位长n＝1152，AWGN信道，BPSK调制；本方法和Turbo码的码率变化范围从0.33到0.88；图中曲线中点为空圈的为通过k-SR方法实现的仿真曲线，k-SR方法的码率变化范围从0.5到0.8(如图中所示代表K-SR方法实现的仿真曲线从左向右，码率依次为：0.5，0.6，0.67，0.8)；曲线中点为实心圈的为LTE Turbo方法实现的仿真曲线，Turbo码的码率变化范围从0.33到0.88(如图中所示代表LTE Turbo方法实现的仿真曲线从左向右，码率依次为：0.33，0.4，0.5， 0.6，0.67，0.8，0.88)；图中曲线中点为棱形的为本文方法实现的仿真曲线(如图中所示代表本申请方法实现的仿真曲线从左向右，码率依次为：0.33，0.4，0.5，0.6，0.67，0.8，0.88)。由图中对比可以看出，本方法在0.5到0.8的范围内均优于直接k-SR打孔的性能；在0.66到0.88码率的范围优于LTE Turbo，在0.4到0.6的范围和LTE Turbo性能接近，0.33附近略差于LTE Turbo。
另外，与本发明实施例一提供的一种信号传输的方法相对应的，在本发明实施例三提供了一种发射端，如图7所示，图7为本发明实施例提供的一种发射端的装置结构示意图，该发射端包括：编码单元701，处理单元702，发送单元703。
编码单元701，用于根据第二码字的码率以及第二矩阵对信息序列进行LDPC编码得到第二码字。
处理单元702，用于将信息序列对应的母矩阵进行至少一次行合并运算后，并删除至少一列校验位，获取第二矩阵。
具体步骤如下：
处理单元702将信息序列对应的母矩阵的所有行元素进行至少一次行合并运算，获取第四矩阵，其中第四矩阵包括信息位和校验位，以及删除第四矩阵中所有列校验位中的至少一列校验位，其中，第四矩阵的校验位的总列数大于或者等于二，且删除的至少一列校验位的所有元素均小于零。
发送单元703，用于将第二码字发送至接收端。
可选的，发射端还可以包括：接收单元704，用于接收到接收端对所第二码字译码的否定应答。
在一种情况中，编码单元701还用于，当第三码字的码率大于信息序列对应的母矩阵的码率时，根据第三码字的码率以及第三矩阵得 到第三码字，其中，第三码字的码率小于或者等于第二码字的码率。第三矩阵为处理单元702将第二矩阵进行至少一次扩展和至少一次行分裂运算得到的。
在另一种情况中，编码单元还用于，当第三码字的码率小于或者等于信息序列对应的母矩阵的码率时，根据信息序列对应的母矩阵得到第三码字。
最终，发送单元702还用于，将所述第三码字发送至接收端。
本申请实施例发射端的各部件的功能，均可以通过上述实施例一的方法步骤来实现，因此，本申请提供的发射端的具体工作过程，在此不复赘述。
与本发明实施例二提供的另一种信号传输的方法相对应的，在本发明实施例四提供了一种接收端，如图8所示，图8为本发明实施例提供的一种接收端的装置结构示意图，该接收端包括：接收单元801，处理单元802，译码单元803。
接收单元801，用于接收第二码字。
处理单元802，对信息序列对应的母矩阵进行至少一次行合并运算，并删除至少一列校验位，获取第二矩阵。
具体步骤包括：处理单元802将信息序列对应的母矩阵的所有行元素进行至少一次行合并运算，获取第四矩阵，其中第四矩阵包括信息位和校验位，以及删除第四矩阵中所有列校验位中的至少一列校验位，其中，第四矩阵的校验位的总列数大于或者等于二，且删除的至少一列校验位的所有元素均小于零。
译码单元803，用于根据第二矩阵对第二码字进行LDPC译码得到信息序列。
可选的，接收端还包括：发送单元804。
发送单元804用于，当译码单元根据第二矩阵对第二码字进行LDPC译码失败时，向发射端发送第二码字译码失败的否定应答。
此时，发射端将会在接收到第二码字译码失败的否定应答后，向接收端发送第三码字。
因此，接收单元801还用于，接收第三码字。
在一种情况中当第三码字的码率大于信息序列的对应的母矩阵的码率时，译码单元803还用于，根据第三矩阵对第三码字进行LDPC译码。其中，第三码字的码率小于或者等于第二码字的码率，而第三矩阵则为处理单元802将第二矩阵进行至少一次扩展和至少一次行分裂运算得到的。
在另一种情况中，当第三码字的码率小于或者等于信息序列对应的母矩阵的码率时，译码单元803还用于根据信息序列对应的母矩阵对第三码字进行LDPC译码。
本申请实施例接收端的各部件的功能，均可以通过上述实施例二所述的方法步骤来实现，因此，本申请提供的接收端的具体工作过程，在此不复赘述。
最后，本发明实施例还提供了一种信号传输系统，具体如图9所示，该信号传输系统包括如发射端和接收端。在本发明的说明书初始部分就已经说明，发射端及接收端分别可以为需要以无线传输方式进行数据传输的基站、终端等网络设备。例如，当发射端是基站时，对应的接收端就是终端；相反，当发射端是终端时，那么接收端则是基站。
图10为本发明实施例六提供的一种发射端的结构示意图1000，如图10所示，该发射端包括处理器1001和发送器1002。
处理器用于，根据第二码字的码率以及第二矩阵对信息序列进行 LDPC编码得到第二码字。
其中，第二矩阵为处理器1001将信息序列对应的母矩阵进行至少一次行合并运算后，并删除至少一列校验位得到的。
具体获取第二矩阵的过程为：将信息序列对应的母矩阵的所有行元素进行至少一次行合并运算，获取第四矩阵，其中第四矩阵包括信息位和校验位，以及删除第四矩阵中所有列校验位中的至少一列校验位，其中，第四矩阵的校验位的总列数大于或者等于二，且删除的至少一列校验位的所有元素均小于零。
可选的，该发射端还可以包括接收器1003，接收到接收端对第二码字的否定应答。
当发射端接收到接收端发送的否定应答时，需要重新发送低码率的码字至接收端。
因此，在一种情况中，当第三码字的码率大于信息序列对应的母矩阵的码率时，处理器1001还用于，根据第三码字的码率以及第三矩阵得到第三码字，其中，第三码字的码率小于或者等于第二码字的码率。第三矩阵为处理器1001将第二矩阵进行至少一次扩展和至少一次行分裂运算得到的。
在另一种情况中，当第三码字的码率小于或者等于所述信息序列对应的母矩阵的码率时，处理器1001还用于，根据信息序列对应的母矩阵得到第三码字。
最终，发送器1002则用于将第三码字发送至接收端。
发射端中各部件所执行的功能可参考实施例一所述的方法，这里不再赘述。具体的处理器编码过程则可以参考LDPC码编码的方法流程部分。
图11为本发明实施例七提供的一种发射端的结构示意图1100， 如图11所示，该接收端包括：接收器1101，处理器1102。
接收器1101，用于接收第二码字。
处理器1102，用于根据第二矩阵对第二码字进行LDPC译码得到信息序列。其中，第二矩阵为处理器1102将信息序列对应的母矩阵进行至少一次行合并运算后，并删除至少一列校验位得到的。
具体获取第二矩阵的过程为：将信息序列对应的母矩阵的所有行元素进行至少一次行合并运算，获取第四矩阵，其中第四矩阵包括信息位和校验位，以及删除第四矩阵中所有列校验位中的至少一列校验位，其中，第四矩阵的校验位的总列数大于或者等于二，且删除的至少一列校验位的所有元素均小于零。
此外，该接收端还包括发送器1103，用于当处理器根据第二矩阵对第二码字进行LDPC译码失败时，向发射端发送第二码字译码失败的否定应答。
此时，当发射端接收到译码失败的否定应答时，则会重新向接收端发送比第二码字码率更低的码字。
接收器1101还用于接收第三码字。
在一种情况中，当第三码字的码率大于信息序列的对应的母矩阵的码率时，处理器1102还用于根据第三矩阵对第三码字进行LDPC译码。其中，第三码字的码率小于或者等于第二码字的码率。第三矩阵为处理器1102将第二矩阵进行至少一次扩展和至少一次行分裂运算得到的。
在另一种情况中，当第三码字的码率小于或者等于信息序列对应的母矩阵的码率时，处理器1102还用于根据信息序列对应的母矩阵对第三码字进行LDPC译码。
接收端中各部件所执行的功能可参考实施例二所述的方法，这里 不再赘述。具体的处理器译码过程则可以参考LDPC码译码的方法流程部分。
专业人员应该还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
结合本文中所公开的实施例描述的方法或算法的步骤可以用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的存储介质中。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (16)

  1. 一种信号传输的方法，其特征在于，所述方法包括：
    根据第二码字的码率以及第二矩阵对信息序列进行低密度奇偶校验码LDPC编码得到第二码字；
    将所述第二码字发送至接收端；
    其中，所述第二矩阵为将所述信息序列对应的母矩阵进行至少一次行合并运算后，并删除至少一列校验位得到的。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    接收到接收端对所述第二码字译码的否定应答；
    若第三码字的码率大于所述信息序列对应的母矩阵的码率，则根据第三码字的码率以及第三矩阵得到第三码字；
    将所述第三码字发送至接收端；
    其中，所述第三码字的码率小于或者等于所述第二码字的码率；所述第三矩阵为将所述第二矩阵进行至少一次扩展和至少一次行分裂运算得到的。
  3. 根据权利要求1所述的方法，其特征在于，
    接收到接收端对所述第二码字译码的否定应答；
    若第三码字的码率小于或者等于所述信息序列对应的母矩阵的码率，则根据所述信息序列对应的母矩阵得到第三码字；
    将所述第三码字发送至接收端。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，所述第二矩阵具体为：
    将所述信息序列对应的母矩阵的所有行元素进行至少一次行合并运算，获取第四矩阵，其中所述第四矩阵包括信息位和校验位；
    以及删除所述第四矩阵中所有列校验位中的至少一列校验位，其 中，所述第四矩阵的校验位的总列数大于或者等于二，且删除的至少一列校验位的所有元素均小于零。
  5. 一种信号传输的方法，其特征在于，所述方法包括：
    接收第二码字；
    根据第二矩阵对所述第二码字进行低密度奇偶校验码LDPC译码得到信息序列；
    其中，所述第二矩阵为将所述信息序列对应的母矩阵进行至少一次行合并运算后，并删除至少一列校验位得到的。
  6. 根据权5所述的方法，其特征在于，
    若根据所述第二矩阵对所述第二码字进行LDPC译码失败，则向发射端发送所述第二码字译码失败的否定应答；
    接收第三码字；
    若第三码字的码率大于所述信息序列的对应的母矩阵的码率，则根据所述第三码字的码率以及所述第二矩阵确定第三矩阵；
    根据所述第三矩阵对所述第三码字进行LDPC译码；
    其中，所述第三码字的码率小于或者等于所述第二码字的码率；所述第三矩阵为将所述第二矩阵进行至少一次扩展和至少一次行分裂运算得到的。
  7. 根据权利要求5所述的方法，其特征在于，
    若根据所述第二矩阵对所述第二码字进行LDPC译码失败，则向发射端发送所述第二码字译码失败的否定应答；
    接收第三码字；
    若第三码字的码率小于或者等于所述信息序列对应的母矩阵的码率，则根据所述信息序列对应的母矩阵对所述第三码字进行LDPC译码。
  8. 根据权利要求5-7任一项所述的方法，其特征在于，所述第二矩阵具体为：
    将所述信息序列对应的母矩阵的所有行元素进行至少一次行合并运算，获取第四矩阵，其中所述第四矩阵包括信息位和校验位；
    以及删除所述第四矩阵中所有列校验位中的至少一列校验位，其中，所述第四矩阵的校验位的总列数大于或者等于二，且删除的至少一列校验位的所有元素均小于零。
  9. 一种发射端，其特征在于，所述发射端包括：
    编码单元，用于根据第二码字的码率以及第二矩阵对信息序列进行低密度奇偶校验码LDPC编码得到第二码字；
    处理单元，用于将所述信息序列对应的母矩阵进行至少一次行合并运算后，并删除至少一列校验位，获取第二矩阵；
    发送单元，用于将所述第二码字发送至接收端。
  10. 根据权利要求9所述的发射端，其特征在于，所述发射端还包括：
    接收单元，用于接收接收端对所述第二码字译码的否定应答；
    所述编码单元还用于，当第三码字的码率大于所述信息序列对应的母矩阵的码率时，根据第三码字的码率以及第三矩阵得到第三码字；
    所述发送单元还用于，将所述第三码字发送至接收端；
    其中，所述第三码字的码率小于或者等于所述第二码字的码率；所述第三矩阵为所述处理单元将所述第二矩阵进行至少一次扩展和至少一次行分裂运算得到的。
  11. 根据权利要求9所述的发射端，其特征在于，所述发射端还包括：
    接收单元，用于接收接收端对第二码字译码的否定应答；
    所述编码单元还用于，当第三码字的码率小于或者等于所述信息序列对应的母矩阵的码率时，根据所述信息序列对应的母矩阵得到第三码字；
    所述发送单元还用于，将所述第三码字发送至接收端。
  12. 根据权利要求9-11任一项所述的发射端，其特征在于，所述处理单元具体用于：
    将所述信息序列对应的母矩阵的所有行元素进行至少一次行合并运算，获取第四矩阵，其中所述第四矩阵包括信息位和校验位；
    以及删除所述第四矩阵中所有列校验位中的至少一列校验位，其中，所述第四矩阵的校验位的总列数大于或者等于二，且删除的至少一列校验位的所有元素均小于零。
  13. 一种接收端，其特征在于，所述接收端包括：
    接收单元，用于接收第二码字；
    处理单元，用于对信息序列对应的母矩阵进行至少一次行合并运算，并删除至少一列校验位，获取第二矩阵；
    译码单元，用于根据所述第二矩阵对所述第二码字进行低密度奇偶校验码LDPC译码得到信息序列。
  14. 根据权利要求13所述的接收端，其特征在于，所述接收端还包括：
    发送单元：用于当译码单元根据所述第二矩阵对所述第二码字进行LDPC译码失败时，向发射端发送所述第二码字译码失败的否定应答；
    所述接收单元还用于，接收第三码字；
    所述译码单元还用于，当所述第三码字的码率大于所述信息序列的对应的母矩阵的码率时，根据所述第三矩阵对所述第三码字进行 LDPC译码；
    其中，所述第三码字的码率小于或者等于所述第二码字的码率；所述第三矩阵为所述处理单元将所述第二矩阵进行至少一次扩展和至少一次行分裂运算得到的。
  15. 根据权利要求13所述的接收端，其特征在于，所述接收端还包括：
    发送单元用于，当所述译码单元根据所述第二矩阵对所述第二码字进行LDPC译码失败时，向发射端发送所述第二码字译码失败的否定应答；
    所述接收单元还用于，接收第三码字；
    所述译码单元还用于，当第三码字的码率小于或者等于所述信息序列对应的母矩阵的码率时，根据所述信息序列对应的母矩阵对所述第三码字进行LDPC译码。
  16. 根据权利要求13-15任一项所述的接收端，其特征在于，所述处理单元具体用于，
    将所述信息序列对应的母矩阵的所有行元素进行至少一次行合并运算，获取第四矩阵，其中所述第四矩阵包括信息位和校验位；
    以及删除所述第四矩阵中所有列校验位中的至少一列校验位，其中，所述第四矩阵的校验位的总列数大于或者等于二，且删除的至少一列校验位的所有元素均小于零。
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