WO2018032495A1 - Dispositif informatique analogique en mode temps - Google Patents

Dispositif informatique analogique en mode temps Download PDF

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Publication number
WO2018032495A1
WO2018032495A1 PCT/CN2016/095978 CN2016095978W WO2018032495A1 WO 2018032495 A1 WO2018032495 A1 WO 2018032495A1 CN 2016095978 W CN2016095978 W CN 2016095978W WO 2018032495 A1 WO2018032495 A1 WO 2018032495A1
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WO
WIPO (PCT)
Prior art keywords
signal
time
output
digital
edge
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PCT/CN2016/095978
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English (en)
Chinese (zh)
Inventor
汪波
黄继攀
王新安
陈红英
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北京大学深圳研究生院
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Priority to PCT/CN2016/095978 priority Critical patent/WO2018032495A1/fr
Publication of WO2018032495A1 publication Critical patent/WO2018032495A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop

Definitions

  • the present invention relates to a time mode analog computing device.
  • Integrated circuits are generally classified into analog integrated circuits and digital integrated circuits. Since the analog circuit cannot be proportionally reduced with the rhythm of Moore's Law, as the process size decreases, the analog circuit also has problems such as increased capacitance leakage, reduced power supply voltage, and the need for manual layout.
  • the digital integrated circuit itself has the advantages of high precision, good noise isolation, flexibility, programmability, and automated design tools. More importantly, the switching speed can be made faster as the process node progresses. Therefore, from the integrated circuit itself, digital integrated circuits are superior to analog integrated circuits. In reality, analog integrated circuits are being gradually replaced by digital integrated circuits.
  • analog values in an analog integrated circuit can be used to represent values
  • the disadvantage is the disadvantage of the analog integrated circuit itself as described above.
  • the voltage and current in the analog integrated circuit can be used to represent the magnitude of the value, and the relationship between the voltage and the current can be used to implement the corresponding calculation function.
  • the operational amplifier can be used as the basic arithmetic unit, and the voltage multiplied by the conductance is equal to the current.
  • an embodiment of the present invention provides a time mode analog computing device comprising at least one multiplication unit, the multiplication unit comprising:
  • a digital to time converter inputting a reference signal and a digital signal M1 for outputting a signal having a delay of
  • An edge detector for detecting edges of two signals output by the time amplifier to output a signal having a pulse width equal to a delay between the two signals.
  • an embodiment provides a time mode analog computing device, including a cascaded first multiplication unit and a second multiplication unit:
  • the first multiplication unit includes:
  • a first digital to time converter inputting a reference signal and a digital signal M1 for outputting a signal having a delay of
  • a first time amplifier that inputs the reference signal and an output signal of the first digital to time converter for amplifying a delay between the reference signal and an output signal of the first digital to time converter After M2
  • a first edge detector for detecting edges of two signals output by the first time amplifier to output a signal having a pulse width equal to a delay between the two signals
  • the second multiplication unit includes:
  • a second digital to time converter inputting an output signal of the first edge detector and a digital signal M3 for outputting a signal with a delay of
  • a second time amplifier inputting an output signal of the first edge detector and the second digital to time converter for outputting the output signal of the first edge detector and the output signal of the first digital to time converter
  • times are amplified by
  • a second edge detector for detecting edges of two signals output by the second time amplifier to output a signal having a pulse width equal to
  • the operation can be completed in one operation, which greatly improves the operation efficiency; since the value is represented by the time difference, the signal edge becomes steeper and steeper as the device speed increases.
  • the values indicated will be more and more accurate; since the digital-to-time converter DTC, the time amplifier TA, and the edge detector ED can all be implemented with digital integrated circuits, the existing EDA tools can be used to automatically place and route, greatly speeding up. Design process; applies to calculations with signed bits.
  • FIG. 1 is a schematic structural diagram of a time mode analog computing device in Embodiment 1 of the present application.
  • FIG. 2 is a timing diagram of a time mode analog computing device in Embodiment 1 of the present application.
  • FIG. 3 is a schematic structural diagram of a time mode analog computing device in Embodiment 2 of the present application.
  • FIG. 4 is a first schematic structural diagram of a time mode analog computing device in Embodiment 2 of the present application.
  • FIG. 5 is a second schematic structural diagram of a time mode analog computing device in Embodiment 2 of the present application.
  • FIG. 6 is a third schematic structural diagram of a time mode analog computing device in Embodiment 2 of the present application.
  • FIG. 7 is a schematic diagram showing the principle of storing a calculation result by a time mode analog computing device in Embodiment 3 of the present application.
  • FIG. 8 is a schematic structural diagram of a time mode analog computing device in Embodiment 3 of the present application.
  • the present application combines the advantages of analog circuits and digital circuits to propose an inventive concept calculated in a time mode.
  • the present application uses continuous time as a physical quantity to represent a numerical value, and thus can be obtained by one operation like an analog quantity. As a result, the speed of the operation is greatly accelerated.
  • the specific implementation circuit of the present application can be a digital integrated circuit, so that the design can be performed using a large-scale integrated circuit and the consistency of the circuit can be ensured.
  • the present embodiment provides a time mode analog computing device (hereinafter referred to as an analog computing device).
  • the present analog computing device includes at least one multiplying unit 10 including a digital to time converter (DTC, Digital). To Time Converter, Time Amplifier (TA) and Edge Detector (ED), in one embodiment, a symbol determiner 11 may also be included.
  • DTC digital to time converter
  • TA Time Amplifier
  • ED Edge Detector
  • a symbol determiner 11 may also be included. The following description will be made by taking an analog computing device including a multiplying unit 10 as an example.
  • the digital to time converter DTC converts the digital form (eg, M1) into a time form (eg, ⁇ t1). Specifically, the digital to time converter DTC requires a reference pulse signal (eg, Ref) as an input, and the output signal pulse The delay of the input reference pulse signal is controlled by an input digital signal (M1) so that the value of the input digital signal (M1) can be represented by the delay of the output signal pulse and the input reference pulse signal.
  • a reference pulse signal eg, Ref
  • the digital-to-time converter DTC has two inputs, respectively inputting a reference signal Ref and a digital signal M1, and outputting a signal with a delay of
  • the time amplifier TA has two inputs and two outputs for respectively converting from two inputs The delay between the signals input at the input is amplified, and then the two signals are respectively output through the two outputs.
  • the time amplifier TA inputs the reference signal Ref and the output signal of the digital to time converter DTC, and the delay between the reference signal Ref and the output signal of the digital to time converter is amplified
  • the amplification factor of the time amplifier TA can set different values according to different requirements.
  • the edge detector ED is used to detect the edges of the two signals output by the time amplifier TA to output a signal having a pulse width equal to the delay between the two signals.
  • the delay between the two signals output by the time amplifier TA is
  • the edge detector ED can detect the rising edge of the output signals of the two output terminals, and can also detect the falling edge of the output signals of the two output terminals, The delay of the two signals is extracted to output a signal having a pulse width equal to the delay between the two signals.
  • the edge detector ED can be implemented by a Phase Detector (PD) or a Phase Frequency Detector (PFD) for comparing two signal edges of the time amplifier TA output. Between the time difference and convert it to the pulse width of a square wave signal.
  • PD Phase Detector
  • PFD Phase Frequency Detector
  • the input of the phase frequency detector PFD can be set to be valid for the upper edge or the lower edge, which increases the flexibility of the setting, so as to process the calculation of the signed bit, when one of them
  • a valid signal edge appears on the input port, its corresponding output signal goes high.
  • the other input port then appears with a valid signal edge, its corresponding output signal also goes high, but this high power
  • the level is unstable and the moment will become low. Because the two output signals are sent to the input of a NAND gate, and the output signal is connected to the reset port of the phase frequency detector PFD.
  • the output square wave width is equal to the time difference between the first valid edge and the second effective edge. This achieves a square wave signal with adjustable time width, and the time width between the two edges corresponds to
  • the symbol determiner 11 is for determining the sign of the edge detector ED output signal based on the number of positive or negative signs of M1 and M2. Take the positive symbol as an example, when M1 and M2 When the number of positive symbols is an even number, the symbol determiner 11 determines that the edge detector ED output signal is positive, and conversely, the symbol determiner 11 determines that the edge detector ED output signal is negative. Need to explain, the even number here includes 0. As described above, the symbol determiner 11 is for determining the sign of the edge detector ED output signal, and if only the analog computing device of the present embodiment is used for the calculation of the positive number, it is not necessary to introduce the sign determiner 11.
  • the analog computing device of the embodiment may further include a plurality of time amplifiers TA, each time amplifier TA is cascaded, and the first time amplifier TA inputs the reference signal Ref and The output signal of the digital to time converter DTC, the tail stage time amplifier TA outputs the signal to the edge detector ED, the intermediate time amplifiers TA, the two outputs of the previous stage time amplifier TA and the time amplifier of the latter stage respectively The two inputs of the TA are connected.
  • Multiple time amplifiers TA can implement power operations.
  • the simulation computing device of the present embodiment includes two cascaded multiplying units: a first multiplying unit 21 and a second multiplying unit 22, which can be used to implement multiply and add operations, add operations, subtraction operations, and the like.
  • the first multiplying unit 21 includes a first digital to time converter DTC1, a first time amplifier TA1, and a first edge detector ED1.
  • the first digital to time converter DTC1 inputs a reference signal Ref and a digital signal M1 for outputting a signal having a delay of
  • the first time amplifier TA1 inputs the above reference signal Ref and the output signal of the first digital to time converter for amplifying the delay between the two signals of the reference signal Ref and the output signal of the first digital to time converter
  • These signals are output separately after M2
  • M2 is the amplification factor of the first time amplifier.
  • the delay between the two signals output by the first time amplifier TA1 is
  • the first edge detector ED1 is used to detect the edges of the two signals output by the first time amplifier TA1 to output a signal having a pulse width equal to the delay between the two signals. Thus, the first edge detector ED1 outputs a signal having a pulse width equal to
  • the second multiplying unit 22 includes a second digital to time converter DTC2, a second time amplifier TA2, and a second edge detector ED2.
  • the second digital-to-time converter DTC2 inputs the output signal of the first edge detector ED1 and the digital signal M3 for outputting a signal having a delay of
  • the output signal of the first edge detector ED1 is substantially used as a reference signal.
  • the second time amplifier TA2 inputs the output signals of the first edge detector ED1 and the second digital to time converter for outputting the output signal of the first edge detector ED1 with the first number
  • the delay between the two signals of the output signal of the time converter DTC1 is amplified by
  • M4 is the amplification factor of the second time amplifier.
  • the delay between the two signals output by the second time amplifier TA2 is
  • the second edge detector ED2 is used to detect the edges of the two signals output by the second time amplifier TA2 to output a signal having a pulse width equal to
  • the simulation computing device of this embodiment is for implementing M1*M2+M3*M4, which includes determining the size of M1*M2+M3*M4, that is, the value of
  • is assigned a positive or negative sign.
  • the absolute value and sign of M1*M2+M3*M4 differ depending on the M1, M2, M3, and M4 symbols. Please refer to Table 1 and Table 2 below, exhausting all the symbols of M1, M2, M3 and M4 and the corresponding calculation results.
  • M1*M2 is negative and M3*M4 is positive, so when
  • Figure 5 and Figure 6 show the timing of calculating M1*M2+M3*M4 in cases 9 to 16 in Table 2. It can be seen that
  • the falling edge of (TA2 out1) comes before the rising edge of the second signal (TA2 out2), as shown in Figure 5;
  • the falling edge of out1) does not come before the rising edge of the second signal (TA2 out2), as shown in Figure 6, wherein the first signal (ie, TA2 out1 in Figures 4, 5, and 6) is the first edge detector
  • the output signal (ie, ED1 out1 in Figures 4, 5, and 6) is output by the second time amplifier, and the second signal (ie, TA2 out2 in Figures 4, 5, and 6) is the second digital to time converter.
  • the output signal (ie, DTC2 out in Figures 4, 5, and 6) is output by the second time amplifier.
  • the analog computing device of the present embodiment further includes an edge determiner 23 and a symbol determiner 24.
  • the edge determiner 23 is for determining whether the second edge detector ED2 outputs a signal having a pulse width equal to
  • the signal in one embodiment, is used to cause the second edge detector ED2 to detect the output of the second time amplifier TA2 based on the number of positive or negative signs of M1, M2, M3, and M4.
  • the edge determiner 23 causes the second edge detector ED2 to detect when the number of positive or negative symbols of M1, M2, M3, and M4 is an even number (even in the present application includes 0).
  • the edge determiner 23 causes the second edge detector ED2 to detect the falling edge of the first signal output by the second time amplifier TA2 and the second when the number of positive or negative symbols of M1, M2, M3, and M4 is an odd number.
  • the rising edge of the signal thereby outputting a signal having a punch width equal to
  • the symbol determiner 24 is operative to determine the sign of the output signal of the second edge detector ED2 based on the positive or negative sign of M1, M2, M3 and M4.
  • the number of positive or negative symbols of M1, M2, M3, and M4 is an even number, if M1 and M2 are the same symbol, and M3 and M4 are also the same symbol, Then, the output signal of the second edge detector ED2 is marked as positive. If M1 and M2 are different symbols, and M3 and M4 are also different symbols, the output signal of the second edge detector ED2 is marked as negative.
  • the symbol determiner 24 when the number of positive or negative symbols of M1, M2, M3, and M4 is an odd number, if the falling edge of the first signal comes before the rising edge of the second signal, then when the M3 and M4 symbols are At the same time, the output signal of the second edge detector ED2 is positive, and when the M3 and M4 symbols are different, the output signal of the second edge detector ED2 is negative; if the falling edge of the first signal does not rise before the second signal Alongward, when the M1 and M2 symbols are the same, the output signal of the second edge detector ED2 is positive, and when the M1 and M2 symbols are not the same, the output signal of the second edge detector ED2 is negative.
  • the edge determiner 23 and the sign determiner 24 are for determining the absolute value and the sign of the output result of the second edge detector ED2, and if the analog computing device of the present embodiment is only used to calculate a positive number, then there is no It is necessary to introduce the edge determiner 23 and the sign determiner 24, and the second edge detector ED2 directly outputs a signal having a pulse width equal to
  • M2 and M4 are set to 1, the operation of M1+M3 can be realized, and if M2 is set to 1 and M4 is set to -1, the operation of M1-M3 can be realized.
  • the simulation computing device of the present embodiment further includes means for storing the calculation result.
  • the result of the calculation is expressed in the form of a pulse width of the square wave signal (see Figs. 2, 4, 5, and 6), so that a control circuit can be utilized, which controls the electricity.
  • the road uses this square wave signal to control the output of an oscillator circuit.
  • the waveform of the oscillator circuit is allowed to output during the pulse width time of the calculation result, otherwise the signal is not output, that is, a pulse signal of a certain number of oscillator circuits is output during the pulse width time of the calculation result.
  • the number of pulses output by the oscillator circuit is proportional to the pulse width of the calculation result, that is, proportional to the calculation result.
  • These pulse signals are sent to two non-volatile continuous resistive devices (RRAM/memorizer) to control and change their resistance.
  • One of the resistive devices is used to store the RRAM value of the calculation result, and the other resistive device is used to store the RRAM sign.
  • the amount of change in resistance is proportional to the number of pulses, and is a continuous approximately linear change, so that the calculation result is proportional to the amount of change in the resistance value.
  • the resistance of the resistor remains unchanged, thereby realizing the storage of the calculation result.
  • the absolute value of the calculation result (excluding the sign bit) can be stored in a high-precision resistive device capable of distinguishing a plurality of resistive states; and the sign bit of the calculation result need only be stored in an accuracy
  • the lower ones can be distinguished from the high-impedance and low-resistance resistance devices.
  • the simulation computing device of the embodiment may further include a value for storing the calculation result.
  • the non-volatile continuous resistive device RRAM1 and the non-volatile continuous resistive device RRAM2 storing the calculation result symbol.
  • the analog computing device of this embodiment may further include a controller 31 and an oscillator 32 for writing pulses output by the oscillator 32 into the resistive devices RRAM1 and RRAM2, respectively, during the pulse width of the output result.
  • the analog computing device disclosed in the present application is a pure time form analog calculation, which performs a multiplication operation with a time amplifier TA, requires only one operation, and does not need to be divided into multiple steps; and is sent to the next-stage multiplication unit with a time delay. Adding (accumulating) operations to select different signal edges to complete the operation of signed bits (addition or subtraction), three or more consecutive multiply-and-accumulate operations can repeatedly utilize the two-stage multiplication unit in Embodiment 2, There is no need to allocate a multiplication unit for each multiplication and addition calculation; when the calculation result is stored, the time difference is converted into a pulse number and a change in the resistance value, and then stored in the non-volatile resistance change device.
  • the analog computing device of the present application uses time as the analog value, and the operation can be completed in one operation, which greatly improves the operation efficiency; the value is represented by the time difference, and the signal edge becomes steeper and steeper as the device speed increases.
  • the value will be more and more accurate; the digital to time converter DTC, Time amplifier TA and edge detector ED can be realized by digital integrated circuit, which can be automatically laid out by existing EDA tools, which greatly speeds up the design process; applies to the calculation of signed bits; converts time difference into non-volatile resistance
  • the resistance of the device requires only two resistive devices to store any value, which is much better than the traditional digital memory requires a large number of components to represent multiple bits to store a value.

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Abstract

La présente invention concerne un dispositif informatique analogique en mode temps qui comprend au moins une unité de multiplication (10), l'unité de multiplication (10) comprenant : un convertisseur numérique de temps (DTC) qui applique un signal de référence (Ref) et un signal numérique (M1), de façon à émettre un signal, le retard temporel entre le signal et le signal de référence (Ref) étant |M1| ; un amplificateur de temps (TA) qui applique le signal de référence (Ref) et le signal de sortie du convertisseur numérique de temps (DTC), de façon à amplifier le retard temporel entre deux signaux, les deux signaux étant le signal de référence (Ref) et le signal de sortie du convertisseur numérique de temps (DTC), de |M2| fois et qui émet ensuite respectivement les deux signaux, M2 étant le facteur d'amplification de l'amplificateur de temps ; un détecteur de front (ED) qui détecte le front des deux signaux émis par l'amplificateur de temps (TA), de manière à émettre un signal dont la largeur d'impulsion est égale au retard temporel entre les deux signaux. Le dispositif informatique peut être obtenu sur la base d'un circuit intégré numérique et permet de représenter des valeurs numériques à l'aide du temps. Le calcul est effectué en une étape.
PCT/CN2016/095978 2016-08-19 2016-08-19 Dispositif informatique analogique en mode temps WO2018032495A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110908270A (zh) * 2019-11-19 2020-03-24 复旦大学 一种恒定斜率数字时间转换器及其控制方法
CN113917831A (zh) * 2021-10-19 2022-01-11 南京航空航天大学 一种低功耗高分辨率的时间数字转换器

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CN103444084A (zh) * 2011-12-21 2013-12-11 英特尔移动通信有限责任公司 具有高分辨率相位对准的dtc系统
CN104378112A (zh) * 2013-08-16 2015-02-25 英特尔Ip公司 用于生成相位调制信号的数字时间转换器和方法
US8994573B2 (en) * 2013-03-15 2015-03-31 Intel Mobile Communications GmbH Digital-to-time converter and calibration of digital-to-time converter

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Publication number Priority date Publication date Assignee Title
CN102111149A (zh) * 2009-12-24 2011-06-29 Nxp股份有限公司 数字锁相环
CN103444084A (zh) * 2011-12-21 2013-12-11 英特尔移动通信有限责任公司 具有高分辨率相位对准的dtc系统
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110908270A (zh) * 2019-11-19 2020-03-24 复旦大学 一种恒定斜率数字时间转换器及其控制方法
CN110908270B (zh) * 2019-11-19 2024-04-02 复旦大学 一种恒定斜率数字时间转换器及其控制方法
CN113917831A (zh) * 2021-10-19 2022-01-11 南京航空航天大学 一种低功耗高分辨率的时间数字转换器
CN113917831B (zh) * 2021-10-19 2022-06-10 南京航空航天大学 一种低功耗高分辨率的时间数字转换器

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