WO2018028476A1 - 一种数据发送的方法及装置、通信设备 - Google Patents
一种数据发送的方法及装置、通信设备 Download PDFInfo
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- WO2018028476A1 WO2018028476A1 PCT/CN2017/095485 CN2017095485W WO2018028476A1 WO 2018028476 A1 WO2018028476 A1 WO 2018028476A1 CN 2017095485 W CN2017095485 W CN 2017095485W WO 2018028476 A1 WO2018028476 A1 WO 2018028476A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
Definitions
- the present application relates to, but is not limited to, the field of communication technologies, and in particular, to a method and device for transmitting data, and a communication device.
- the transmitting end of the digital communication system usually includes a source, a channel coder and a modulator, and the receiving end usually includes a demodulator, a channel decoder and a sink, as shown in FIG.
- the channel coder is used to introduce information bits into the information bits according to certain rules so that the receiving channel decoder can correct the errors occurring when the information is transmitted on the channel to some extent.
- LDPC Low Density Parity Check Code
- LDPC Low Density Parity Check Code
- the graphical representation of the LDPC parity check matrix is a bipartite graph.
- An M*N parity check matrix H defines a constraint that each codeword having N bits satisfies M parity sets.
- a bipartite graph includes N variable nodes and M parity nodes.
- the bipartite graph there is no connection between any nodes of the same class, and the total number of edges in the bipartite graph is equal to the number of non-zero elements in the check matrix.
- the power of the unit matrix can be represented by 0, and the matrix is generally represented by -1.
- an M ⁇ N power matrix H b is obtained .
- H b is the basic matrix of H
- H is called the extension matrix of H b .
- z code length / number of columns N of the basic matrix, called the spreading factor.
- the encoder of such an LDPC code is uniquely generated by the basic matrix H b , the spreading factor z and the selected basic permutation matrix.
- the decoding of the LDPC code is usually performed by iterative decoding.
- a double frame decoding structure has been proposed.
- the existing code block (bit stream) segmentation algorithm does not support double frame decoding well.
- L coded bits can be selected as the output of the cyclic buffer rate match according to the desired output code rate; the cyclic buffer rate match starts from a specified one in the output buffer. Position reading L coded bits is called bit selection.
- the bits selected for transmission can be read from any location in the buffer. If the end of the buffer is reached, the data can continue to be read around the beginning of the buffer. Therefore, loop-based rate matching (deletion or duplication) can be achieved in a simple way.
- HARQ Hybrid Automatic Repeat Request
- the circular cache has the advantage of flexibility and granularity.
- Hybrid automatic repeat request is an extremely important link adaptation technique in digital communication systems.
- the receiving end decodes the HARQ data packet received by the receiving end, and if the decoding is correct, the ACK signal is fed back to the transmitting end to notify it to send a new HARQ data packet; if the decoding fails, the NACK signal is fed back to the transmitting end, and the requesting end is re-requested. Send a HARQ packet.
- the receiving end can increase the probability of successful decoding and achieve high reliability of link transmission by performing multiple encryption (Increasing Redundancy, IR for short) or Chase (repeating the same data) for multiple times. Claim.
- redundancy Version determines the multiple starting positions of the HARQ data packets read in the circular buffer.
- the redundancy version determines the starting position of the HARQ data packets read in the circular buffer. .
- the loop buffer is usually composed of sub-blocks or sub-bitstream interleavers, and the parameters of the interleaver affect the transmission performance of the rate-matched bitstream. Since the LDPC code is an error correction code based on a parity check matrix, it has a structural feature itself. Therefore, the parameters of the interleaver must be determined in a targeted manner.
- the broadband wireless transmission in order to transmit bursty services, such as low-latency services, it is necessary to occupy channel resources of the original service. If the original service is a low-density parity check code, then different mappings will have performance differences. At the same time, the wireless channel is not flat, and the quality of the channel is different on different resource units, and the importance of each bit of the code in the LDPC is also different.
- Embodiments of the present invention provide a data transmission method and apparatus, and a communication device, to implement flexible rate matching.
- An embodiment of the present invention provides a data sending method, including:
- N 1 is a positive integer, i is an integer, and 0 ⁇ i ⁇ N 1 -1;
- the first type of modulation symbol stream S i are mapped onto a physical channel resource.
- L 2 is the length of the second bit stream
- T is the preset maximum code block length
- operator Indicates an integer operation up.
- the low density parity check code is a quasi-cyclic low density parity check code
- the basic matrix of the low density parity check code is a matrix of mb rows and nb columns
- the extension The factor is z; where mb, nb, and z are all positive integers, and 0 ⁇ mb ⁇ nb.
- performing rate matching on the N 1 fifth bit streams D i and outputting N 1 sixth bit streams E i include:
- the number of rows r and the number of columns c of the interleaver are at least one of a function of a base matrix size of the low density parity check code and/or a function of the spreading factor.
- the number of rows r of the interleaver is a multiple or a factor of the spreading factor z.
- the number of columns c of the interleaver is a multiple or a factor of the number of columns nb of the basic matrix.
- the stream of the first modulation symbol S i are mapped onto a physical channel resources, comprising:
- Each modulation symbol of the first modulation symbol stream S i is sequentially mapped to the plurality of resource elements.
- the determining the ordering of the plurality of resource units is implemented in the following manner:
- the ordering of the plurality of resource units is determined according to whether the burst data is mapped, wherein the resource unit that does not map the burst data has a higher priority than the resource unit that maps the burst data.
- mapping each of the first modulation symbol streams S i to the plurality of resource units in sequence includes:
- a bit sequence including the largest column weight corresponding to the parity check matrix or the base matrix in the sixth bit stream E i is preferentially mapped to the top ranked resource unit.
- An embodiment of the present invention further provides an apparatus for data transmission, including:
- Adding a module adding a cyclic redundancy check code of a first length to the first bit stream to be transmitted, to obtain a second bit stream;
- a dividing module configured to divide the second type of bit stream into N 1 third bit streams P i according to a length of the second bit stream and a preset maximum code block length, and to the third Adding a second-length cyclic redundancy check code to the bit stream to obtain N 1 fourth bit streams C i ; wherein N 1 is a positive integer, i is an integer, and 0 ⁇ i ⁇ N 1 -1;
- the encoding module is configured to perform low-density parity check code encoding on the fourth bit stream C i to obtain N 1 fifth bit streams D i ;
- a matching module configured to perform rate matching on the N 1 fifth bit streams D i respectively, and output N 1 sixth bit streams E i ;
- a modulation module configured to perform digital baseband modulation on the N 1 sixth bit streams to obtain N1 first modulation symbol streams S i ;
- a mapping module to map the first set of modulation symbol streams based on S i to physical channel resources.
- the low density parity check code is a quasi-cyclic low density parity check code
- the basic matrix of the low density parity check code is a matrix of mb rows and nb columns
- the expansion factor is z.
- mb, nb, z are all positive integers, and 0 ⁇ mb ⁇ nb.
- the matching module includes:
- An input unit configured to input the N 1 fifth bit streams D i into an interleaver of r rows and c columns, respectively;
- a reading unit configured to read a data bit of a specific length from the interleaver to form a sixth bit stream E i ,
- the number of rows r and the number of columns c of the interleaver are at least one of a function of a base matrix size of the low density parity check code and a function of the spreading factor.
- the number of rows r of the interleaver is a multiple or a factor of the spreading factor z
- the number of columns c of the interleaver is a multiple or a factor of the number of columns nb of the basic matrix.
- mapping module includes:
- a dividing unit configured to divide the physical channel resource into a plurality of resource units, where the resource unit includes at least one subcarrier in a frequency domain and one orthogonal frequency division multiplexing symbol in a time domain;
- a determining unit configured to determine an order of the plurality of resource units
- a mapping unit arranged to each modulation symbol of the first modulation symbol stream S i is sequentially mapped to the plurality of resource elements.
- the determining unit is configured to determine an order of the multiple resource units according to a sequence of channel quality indication information of each resource unit from high to low; or determine whether to map the burst data according to whether The ordering of multiple resource units, wherein the resource unit that does not map the burst data has a higher priority than the resource unit that maps the burst data.
- the mapping unit is configured to preferentially map a modulation symbol of a system bit including the sixth bit stream E i to the resource unit that is ranked first; or The bit sequence of the bit stream E i corresponding to the parity check matrix or the base matrix having the largest column weight is preferentially mapped to the top ranked resource unit.
- the embodiment of the present invention further provides a communication device, including a processor and a memory storing the processor executable instructions.
- the instruction When the instruction is executed by the processor, the following operations are performed: adding a first bit stream to be transmitted a length of the cyclic redundancy check code to obtain a second bit stream; and dividing the second type of bit stream into N 1 third according to the length of the second bit stream and a preset maximum code block length a bit stream P i , and adding a second length cyclic redundancy check code to the third bit stream to obtain N 1 fourth bit streams C i ; wherein N 1 is a positive integer, i is an integer, and 0 ⁇ i ⁇ N 1 -1; respectively performing low-density parity check code encoding on the fourth bit stream C i to obtain N 1 fifth bit streams D i ; for the N 1 fifth bit streams D i Performing rate matching separately, outputting N 1 sixth bit streams E i ; performing digital baseband modulation on the N 1 sixth bit streams
- operator Represents an integer operation up.
- the low density parity check code is a quasi-cyclic low density parity check code
- the basic matrix of the low density parity check code is a matrix of mb rows and nb columns
- the expansion factor is z.
- mb, nb, z are all positive integers, and 0 ⁇ mb ⁇ nb.
- the N 1 fifth bit streams D i are respectively rate matched, and outputting N 1 sixth bit streams E i includes: using the N 1 fifth bit streams D i is input to the interleaver of the r row and c column, respectively, and reads data bits of a specific length from the interleaver to form a sixth bit stream E i , wherein the number of rows r and the number of columns c of the interleaver are At least one of a function of a base matrix size of the low density parity check code and a function of the spreading factor.
- the stream of the first modulation symbol S i are mapped onto a physical channel resources, comprising: said physical channel resources are divided into a plurality of resource units, the resource unit including at least the frequency domain a sub-carrier on an orthogonal frequency division multiplexing and time domain symbol; determining ordering of the plurality of resource units; each modulation symbol of the first modulation symbol stream S i is sequentially mapped to the plurality On the resource unit.
- the determining the ordering of the multiple resource units is implemented by: determining, according to a channel quality indicator information of each resource unit, a sequence of the plurality of resource units from high to low Sorting; or determining the ordering of the plurality of resource units according to whether the burst data is mapped, wherein the resource unit that does not map the burst data has a higher priority than the resource unit that maps the burst data.
- the mapping each of the first modulation symbol streams S i to the plurality of resource units in sequence comprises: a system that includes the sixth bit stream E i a modulation symbol of a bit, preferentially mapped to the resource unit on the top of the sort; or a bit sequence containing the largest column weight corresponding to the parity check matrix or the base matrix in the sixth bit stream E i , preferentially mapped to Sort the top resource unit.
- the embodiment of the invention further provides a computer readable storage medium storing computer executable instructions, the method for implementing the data transmission when the computer executable instructions are executed by the processor.
- an embodiment of the present invention provides a data transmission method and apparatus, and a communication device, which implements rate matching of a flexible low-density parity check code.
- the divided bit streams are even, so that the decoding of the receiving end facilitates the use of a dual frame decoding structure, which can improve the throughput of the decoder, reduce power consumption and complexity.
- Degree, low-density parity check code interleaving method wherein the parameters of the interleaver are functions of a parity check matrix or a basic matrix, and the interleaver design is convenient for matching different code lengths and code rates for facilitating inter-column rearrangement. Can reduce complexity.
- the scheme preferentially maps important system bits in the low-density parity check code to resource units with better channel conditions or no burst data, and can improve decoding performance.
- FIG. 1 is a schematic diagram of a related art digital communication system
- FIG. 3 is a schematic diagram of an apparatus for data transmission according to Embodiment 4 of the present invention.
- FIG. 4 is a schematic diagram of an apparatus for data transmission according to Embodiment 5 of the present invention.
- FIG. 5 is a schematic diagram of an apparatus for data transmission according to Embodiment 6 of the present invention.
- FIG. 6 is a schematic diagram of a communication device according to an embodiment of the present invention.
- An embodiment of the present invention provides a method for data transmission. As shown in FIG. 2, the method includes:
- Step 101 The first bit stream I to be transmitted by the transmitting end, adding a cyclic redundancy check code having a length of L crc1 bits, to obtain a second bit stream J;
- Step 102 Divide the second type bit stream J into N 1 third bit streams P i according to a length L 2 (bit) of the second bit stream J and a preset maximum code block length T (bit) And adding a cyclic redundancy check code having a length of L crc2 bits to the third bit stream P i to obtain N 1 fourth bit streams C i ; wherein N 1 is a positive integer, i is an integer, and 0 ⁇ i ⁇ N 1 -1;
- the second type bit stream J is divided into N 1 third class bit streams P i , where N 1 is determined by the following method:
- the bit stream segmentation method provided by the method of the embodiment has an even number of bitstreams, so that the structure of the double frame decoding is facilitated when decoding is performed at the receiving end, which can improve the throughput of the decoder and reduce the work. Consumption and complexity.
- Step 103 Perform low-density parity check code encoding on the fourth bit stream C i to obtain N 1 fifth bit streams D i ;
- the low density parity check code is a quasi-cyclic (or "structured") low density parity check code
- the base matrix of the low density parity check code is a matrix of mb rows and nb columns
- the size of the expansion factor is Where mb, nb, z are all positive integers, and 0 ⁇ mb ⁇ nb.
- Step 104 Perform rate matching on the N1 fifth bit streams D i respectively, and output N 1 sixth bit streams Ei; the step may include the following steps:
- Step 104.1 input the N 1 fifth bit streams into an interleaver of r rows and c columns;
- the number of rows r and the number of columns c of the interleaver are functions of a base matrix of the low density parity check code and/or the spreading factor;
- the number of rows r of the interleaver is a multiple of the expansion factor z or z;
- the number of columns c of the interleaver is a multiple of the number of columns nb or nb of the basic matrix
- the method further includes:
- Step 104.2 Read a specific length of data bits from the interleaver to form a sixth bit stream E i ;
- bit stream D i For each fifth bit stream D i starting from a given starting position, data bits of a particular length are read column by column in the order of the columns to form a sixth bit stream E i .
- This embodiment provides an interleaving method for low density parity check codes, wherein the parameters of the interleaver are functions of a parity check matrix or a base matrix.
- This interleaver design facilitates matching different code lengths and code rates for inter-column rearrangement, reducing complexity.
- Step 105 the bit stream of N1 sixth digital baseband modulation, the N 1 to give a first modulation symbol streams S i;
- Step 106 Map the first type of modulation symbol stream S i onto a physical channel resource.
- the modulation symbols of the system bits including the sixth bit stream E i are preferentially mapped to the resource elements of the top ranked;
- the resource unit includes at least One subcarrier in the frequency domain and one OFDM (Orthogonal Frequency Division Multiplexing) symbol in the time domain;
- Sorting the plurality of resource units is determined, the first modulation symbol in each modulation symbol stream S i are sequentially mapped to the plurality of resource elements;
- the ordering of the multiple resource units is determined by:
- a bit sequence including the largest column weight corresponding to the parity check matrix or the base matrix in the sixth bit stream E i is preferentially mapped to the top ranked resource unit.
- the column weight refers to the number of non-1 elements in the column elements of the basic matrix.
- This embodiment provides a new resource mapping method, which preferentially maps important system bits in a low-density parity check code to resource units with better channel conditions or no burst data, thereby improving decoding performance.
- the method of the embodiment of the invention can implement rate matching of flexible low density parity check codes.
- Embodiment 2 is a diagrammatic representation of Embodiment 1:
- the length of the ith fourth bit stream is or
- the length of the 0th fourth bit stream is Bits
- the first, second, and third fourth bitstreams are all Bit. Among them, 60 bits of padding bits are added to the top position of the 0th fourth bit stream.
- the low density parity check code is a quasi-cyclic (or "structured") low density parity check code
- Step 204 Perform rate matching on the N 1 fifth bit streams D i and output N 1 sixth bit streams Ei, which may include the following steps:
- Step 204.1 Input the N 1 fifth bit stream into an interleaver of r rows and c columns;
- each sixth bit stream has a length of 6000 bits; from the bit stream after each rearrangement, starting from a given starting position, column by column order Reading a data bit having a length of 6000 bits constitutes a sixth bit stream E i ; wherein the starting position can be indicated by a redundancy version.
- Step 205 the bit stream of N1 sixth digital baseband modulation, the N 1 to give a first modulation symbol streams S i;
- the digital baseband modulation may be QPSK (Quadrature Phase Shift Keying), 16QAM (Quadrature Amplitude Modulation), 64QAM or 256QAM modulation, wherein each modulation symbol includes 2 bits respectively. 4 bits, 6 bits or 8 bits of data; in this example, 16QAM modulation is assumed, and each 16QAM modulation symbol includes 4 bits of data.
- QPSK Quadrature Phase Shift Keying
- 16QAM Quadrature Amplitude Modulation
- 64QAM or 256QAM modulation wherein each modulation symbol includes 2 bits respectively. 4 bits, 6 bits or 8 bits of data; in this example, 16QAM modulation is assumed, and each 16QAM modulation symbol includes 4 bits of data.
- Step 206 the first modulation symbol stream S i are mapped onto a physical channel resource
- the physical resource is divided into two resource units, each of which includes at least one subcarrier in the frequency domain and one OFDM (Orthogonal Frequency Division Multiplexing) symbol in the time domain;
- the first resource unit has burst data
- the second resource unit has no burst data. Therefore, the second resource unit has a higher priority than the first resource unit.
- the modulation symbols corresponding to the systematic bits of the sixth bitstream in the first modulation symbol stream are preferentially mapped onto the high priority resource elements. It is assumed that in the present embodiment, the first 1264 16QAM symbols ⁇ s 0 , s 1 , . . . , s 1263 ⁇ in the first modulation symbol stream S 1 correspond to systematic bits of the sixth bit stream E 1 , in S 1 The last 236 16QAM symbols ⁇ s 1264 , s 1265 , . . . , s 1499 ⁇ correspond to the parity bits of the sixth bit stream E 1 , and then the first 1264 16QAMs are preferentially mapped onto the second resource unit.
- Embodiment 3 is a diagrammatic representation of Embodiment 3
- the length of the ith fourth bit stream is or
- the lengths of the 0th and 1st fourth bit streams are Bits
- the first, second, third, fourth, fifth, and sixth fourth bitstreams are all of length Bit.
- 56 bits of padding bits are added at the most forward position of the 0th fourth bit stream.
- Step 304 Perform rate matching on the N 1 fifth bit streams D i and output N 1 sixth bit streams Ei, which may include the following steps:
- Step 304.1 input the N 1 fifth bit stream into an interleaver of r rows and c columns;
- a 1/2 is assumed, the interleaver of the bit streams D 0 and D 1 is an interleaver of 208 rows and 24 columns, and the interleaver used for the bit streams D 1 , D 2 and D 3 is 212 lines. 24 columns of interleaver;
- Step 304.2 Perform an inter-column rearrangement according to a given rearrangement vector for each bit stream input to the interleaver;
- the column index is from 1 onwards.
- Step 305 the bit stream of N1 sixth digital baseband modulation, the N 1 to give a first modulation symbol streams S i;
- the digital baseband modulation may be QPSK, 16QAM, 64QAM or 256QAM modulation, wherein each modulation symbol includes 2 bits, 4 bits, 6 bits or 8 bits of data, respectively; in this embodiment, QPSK modulation is assumed, each QPSK The modulation symbol includes 2-bit data.
- Step 306 Map the first modulation symbol stream S i to a physical channel resource.
- the physical resource is divided into four resource units, each resource element includes at least one subcarrier in the frequency domain and one OFDM symbol in the time domain; wherein the channel indication information CQI on each resource unit is high to a low order of CQI 2 ⁇ CQI 3 ⁇ CQI 1 ⁇ CQI 4 ; the priority order of each resource element is a resource unit priority of the highest priority, followed by the resource unit 3 2, the resource unit priority 1 Third, resource unit 4 has the lowest priority.
- a modulation symbol corresponding to a systematic bit of the sixth bitstream in the first modulation symbol stream is preferentially mapped to a high priority resource unit. It is assumed that in this example, the first 1664 QPSK symbols ⁇ s 0 , s 1 , . . . , s 1663 ⁇ in the first modulation symbol stream S 1 correspond to the systematic bits of the sixth bit stream E 1 , and in the S 1 832 QPSK symbols ⁇ s 1664 , s 1665 , . . .
- the first 1664 16QAMs are preferentially mapped onto the second resource unit, and then mapped Go to the third resource unit, then the first resource unit, and finally the fourth resource unit.
- the method of this embodiment can implement rate matching of flexible low density parity check codes.
- the method of this embodiment further provides a new bit stream segmentation method, and the divided bit streams are even, so that the decoding of the decoder is convenient when the decoding is performed at the receiving end, and the throughput of the decoder can be improved. Quantity, reducing power consumption and complexity;
- the method of this embodiment further provides an interleaving method suitable for low density parity check codes, wherein the parameters of the interleaver are functions of a parity check matrix or a basic matrix, and the interleaver is designed to match different code lengths and codes.
- the rate is convenient for column-to-column rearrangement, which reduces complexity;
- the method of this embodiment further provides a new resource mapping method, which will be used in a low density parity check code. Important system bits are preferentially mapped to resource elements with good channel conditions or without burst data, which can improve decoding performance.
- FIG. 3 is a schematic diagram of an apparatus for data transmission according to an embodiment of the present invention. As shown in FIG. 3, the apparatus of this embodiment includes:
- the adding module 21 is configured to add a first-length cyclic redundancy check code to the first bit stream to be transmitted, to obtain a second bit stream;
- the dividing module 22 is configured to divide the second type bit stream into N 1 third bit streams P i according to the length of the second bit stream and a preset maximum code block length, and to The three-bit stream is respectively added with a second-length cyclic redundancy check code to obtain N 1 fourth bit streams C i ; wherein N 1 is a positive integer, i is an integer, and 0 ⁇ i ⁇ N 1 -1;
- L 2 is the length of the second bit stream
- T is the preset maximum code block length
- operator Indicates an integer operation up.
- the encoding module 23 is configured to perform low-density parity check code encoding on the fourth bit stream C i to obtain N 1 fifth bit streams D i ;
- the matching module 24 is configured to perform rate matching on the N 1 fifth bit streams D i respectively, and output N 1 sixth bit streams E i ;
- the modulation module 25 is configured to perform digital baseband modulation on the N 1 sixth bit streams to obtain N1 first modulation symbol streams S i ;
- Mapping module 26 arranged to map the first modulation symbol stream S i based on the physical channel resource.
- the low density parity check code is a quasi-cyclic low density parity check code, and the basic matrix of the low density parity check code is a matrix of mb rows and nb columns, and the expansion factor is z; wherein, mb , nb, z are all positive integers, and 0 ⁇ mb ⁇ nb.
- the matching module 24 includes:
- the input unit 241 is configured to input the N 1 fifth bit streams D i into the interleaver of the r rows and c columns, respectively;
- the reading unit 242 is configured to read a data bit of a specific length from the interleaver to form a sixth bit stream E i ,
- the number of rows r and the number of columns c of the interleaver are functions of a base matrix of the low density parity check code and/or the spreading factor.
- the number of rows r of the interleaver is a multiple or a factor of the spreading factor z
- the number of columns c of the interleaver is a multiple or a factor of the number of columns nb of the basic matrix.
- the mapping module 26 includes:
- the dividing unit 261 is configured to divide the physical channel resource into multiple resource units, where the resource unit includes at least one subcarrier in the frequency domain and one orthogonal frequency division multiplexing symbol in the time domain;
- a determining unit 262 configured to determine an order of the plurality of resource units
- Mapping unit 263, arranged for each modulation symbol of the first modulation symbol stream S i is sequentially mapped to the plurality of resource elements.
- the determining unit 262 may be configured to determine an order of the multiple resource units according to a sequence of channel quality indication information of each resource unit from high to low, or determine the multiple according to whether to map burst data.
- the mapping unit 263 may be configured to preferentially map the modulation symbols of the system bits including the sixth bit stream E i to the resource elements that are ranked first; or include the sixth bit stream E i
- the bit sequence corresponding to the parity check matrix or the base matrix having the largest column weight is preferentially mapped to the top ranked resource unit.
- the embodiment of the present invention further provides a communication device, as shown in FIG. 6, comprising a processor 31 and a memory 32 storing the processor executable instructions.
- the instructions When the instructions are executed by the processor, the following operations are performed: Adding a first-length cyclic redundancy check code to the first bit stream to be transmitted, to obtain a second bit stream; and according to the length of the second bit stream and a preset maximum code block length, the second class bit stream is divided into a third bit stream the N 1 P i, and the third bit stream are cyclic redundancy check code added to the second length, to obtain the N 1 fourth bit stream C i; wherein, N 1 Is a positive integer, i is an integer, and 0 ⁇ i ⁇ N 1 -1; performing low-density parity check code encoding on the fourth bit stream C i to obtain N 1 fifth bit streams D i ; N 1 fifth bit streams D i are respectively rate matched, and N 1 sixth bit streams E i are output; digital base
- operator Indicates an integer operation up.
- the low density parity check code is a quasi-cyclic low density parity check code
- the basic matrix of the low density parity check code is a matrix of mb rows and nb columns
- the expansion factor is z.
- mb, nb, z are all positive integers, and 0 ⁇ mb ⁇ nb.
- the N 1 fifth bit streams D i are respectively rate matched, and outputting N 1 sixth bit streams E i includes: using the N 1 fifth bit streams D i is input to the interleaver of the r row and c column, respectively, and reads data bits of a specific length from the interleaver to form a sixth bit stream E i , wherein the number of rows r and the number of columns c of the interleaver are A basic matrix of low density parity check codes and/or a function of the spreading factor.
- the stream of the first modulation symbol S i are mapped onto a physical channel resources, comprising: said physical channel resources are divided into a plurality of resource units, the resource unit including at least the frequency domain a sub-carrier on an orthogonal frequency division multiplexing and time domain symbol; determining ordering of the plurality of resource units; each modulation symbol of the first modulation symbol stream S i is sequentially mapped to the plurality On the resource unit.
- the determining the ordering of the multiple resource units is implemented by: determining, according to a channel quality indicator information of each resource unit, a sequence of the plurality of resource units from high to low Sorting; or determining the ordering of the plurality of resource units according to whether the burst data is mapped, wherein the resource unit that does not map the burst data has a higher priority than the resource unit that maps the burst data.
- the mapping each of the first modulation symbol streams S i to the plurality of resource units in sequence comprises: a system that includes the sixth bit stream E i a modulation symbol of a bit, preferentially mapped to the resource unit on the top of the ranking; or preferentially mapping a bit sequence containing the largest column weight corresponding to the parity check matrix or the base matrix in the sixth bit stream E i to Sort the top resource unit.
- the embodiment of the invention further provides a computer readable storage medium storing computer executable instructions, the computer executable instructions being executed to perform the following operations:
- Embodiments of the present invention provide a data transmission method and apparatus, and a communication device, which implement rate matching of a flexible low-density parity check code.
- the divided bit streams are even, so that the decoding of the receiving end facilitates the use of a dual frame decoding structure, which can improve the throughput of the decoder, reduce power consumption and complexity.
- Degree, low-density parity check code interleaving method wherein the parameters of the interleaver are functions of a parity check matrix or a basic matrix, and the interleaver design is convenient for matching different code lengths and code rates for facilitating inter-column rearrangement. Can reduce complexity.
- the scheme preferentially maps important system bits in the low-density parity check code to resource units with better channel conditions or no burst data, and can improve decoding performance.
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- Error Detection And Correction (AREA)
Abstract
一种数据发送的方法及装置、通信设备,其中所述方法包括:对待传输的第一比特流添加第一长度的循环冗余校验码得到第二比特流;根据第二比特流的长度以及预先设定的最大码块长度,将第二类比特流分割为N1个第三比特流Pi,并对第三比特流分别添加第二长度的循环冗余校验码,得到N1个第四比特流Ci;对第四比特流Ci分别进行低密度奇偶校验码编码,得到N1个第五比特流Di;对所述N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei;对N1个第六比特流进行数字基带调制,得到N1个第一调制符号流Si;将第一类调制符号流Si映射到物理信道资源上。
Description
本申请涉及但不限于通信技术领域,尤指一种数据发送的方法及装置、通信设备。
数字通信系统的发射端通常包括信源、信道编码器和调制器等部分,接收端通常包括解调器、信道译码器和信宿,如图1所示。信道编码器用于给信息比特按照一定的规则引入冗余信息以便接收端信道译码器能够在一定程度上纠正信息在信道上传输时发生的误码。
LDPC(Low Density Parity Check Code,低密度奇偶校验码)是一种基于稀疏校验矩阵的线性分组码,正是利用它的校验矩阵的稀疏性,才能实现低复杂度的编译码,从而使得LDPC走向实用化。
LDPC奇偶校验矩阵的图形表示形式是二分图。二分图和校验矩阵之间具有一一对应的关系,一个M*N的奇偶校验矩阵H定义了每个具有N比特的码字满足M个奇偶校验集的约束。一个二分图包括N个变量节点和M个奇偶校验节点。当第m个校验涉及到第n个比特位,即H中第m行第n列的元素Hm,n=1时,将有一根连线连接校验节点m和变量节点n。二分图中,任何同一类的节点之间都不会有连接,并且二分图中的总边数和校验矩阵中非零元素的个数相等。
一类特殊LDPC由于具有准循环(或称“结构化”)的特征,逐渐成为主流应用。设这种LDPC的奇偶校验矩阵H为(M×z)×(N×z)矩阵,它是由M×N个分块矩阵构成,每个分块矩阵都是z×z的基本置换矩阵的不同幂次,基本置换矩阵为单位阵时,它们都是单位阵的循环移位矩阵(文中默认为右移)。具有如下的形式:
通过这样的幂次就可以唯一标识每一个分块矩阵,单位矩阵的幂次可用0表示,矩阵一般用-1来表示。这样,如果将H的每个分块矩阵都用它的幂次代替,就得到一个M×N的幂次矩阵Hb。这里,定义Hb是H的基础矩阵,H称为Hb的扩展矩阵。在实际编码时,z=码长/基础矩阵的列数N,称为扩展因子。
例如,矩阵
可以用下面的参数z和一个2×4的基础矩阵Hb扩展得到:
因此,也可以说这类LDPC码的编码器是由基础矩阵Hb,扩展因子z及所选择的基本置换矩阵唯一生成的。
LDPC码的译码通常采用迭代译码的方式进行。为了减少相邻两次迭代之间的等待时间,提高译码器的吞吐量,人们提出了一种双帧译码的结构。
但是已有码块(比特流)分割算法并不能很好地支持双帧译码。
在循环缓存速率匹配(Circular Buffer Rate Matching)算法中,根据期望的输出码率,可以选择L个编码比特,作为循环缓存速率匹配的输出;循环缓存速率匹配从输出缓存器中某个指定的开始位置读出L个编码比特,被称为比特选择。总地来说,被选择用于传输的比特可以从缓存器中的任何位置开始读出来。如果达到缓存器的末尾,可以绕到缓存器的开始位置继续读取数据。所以,通过简单的方法便可实现基于循环缓存的速率匹配(删除或重复)。对于混合自动重传请求(Hybrid Automatic Repeat Request,简称HARQ)操作,循环缓存又具有灵活性和颗粒度的优势。
混合自动重传请求是一种数字通信系统中极其重要的链路自适应技术。接收端对其接收的HARQ数据包进行译码,若译码正确则反馈ACK信号给发送端,通知其发送新的HARQ数据包;若译码失败则反馈NACK信号给发送端,请求发送端重新发送HARQ数据包。接收端通过对多次重传的数据包进行递增冗余(Increasing Redundancy,简称IR)或Chase(重复发送相同数据)合并译码,可以提高其译码成功概率,实现链路传输的高可靠性要求。
在混合自动重传请求方式下,在循环缓存中可以指定不同的位置作为每次传输HARQ数据包读取的起点位置。冗余版本(Redundancy Version)的定义即确定了HARQ数据包在循环缓存中读取的多个起点位置,冗余版本取值便确定了本次传输HARQ数据包在循环缓存中读取的起点位置。
循环缓存通常是由子块或者子比特流交织器构成,而交织器的参数对速率匹配后的比特流的传输性能会产生影响。由于LDPC码是一种基于奇偶校验矩阵的纠错编码,其本身具有结构化的特点。因此必须有针对性地确定交织器的参数。
另外,在宽带无线传输中,有时为了传输突发的业务,比如低延时的业务时,需要占用原有业务的信道资源。如果原有业务是低密度奇偶校验码,那么不同的映射会产生性能上的差异。同时无线信道也不是平坦的,在不同的资源单元上信道的好坏也不尽相同,而LDPC中码的每个比特的重要性也不尽相同。
发明概述
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本发明实施例提供一种数据发送的方法及装置、通信设备,以实现灵活的速率匹配。
本发明实施例提供了一种数据发送的方法,包括:
对待传输的第一比特流添加第一长度的循环冗余校验码,得到第二比特流;
根据所述第二比特流的长度以及预先设定的最大码块长度,将所述第二类比特流分割为N1个第三比特流Pi,并对所述第三比特流分别添加第二长度的循环冗余校验码,得到N1个第四比特流Ci;其中,N1是正整数,i是整数,并且0≤i≤N1-1;
对所述第四比特流Ci分别进行低密度奇偶校验码编码,得到N1个第五比特流Di;
对所述N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei;
对所述N1个第六比特流进行数字基带调制,得到N1个第一调制符号流Si;
将所述第一类调制符号流Si映射到物理信道资源上。
在一实施方式中,所述低密度奇偶校验码为准循环的低密度奇偶校验码,且所述低密度奇偶校验码的基础矩阵是一个mb行nb列的矩阵,扩展
因子为z;其中,mb、nb、z均为正整数,并且,0<mb<nb。
在一实施方式中,所述对所述N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei,包括:
将所述N1个所述第五比特流Di分别输入到r行c列的交织器中,
从所述交织器中读取特定长度的数据比特组成第六比特流Ei,
其中,所述交织器的行数r和列数c是所述低密度奇偶校验码的基础矩阵大小的函数和/或所述扩展因子的函数中的至少之一。在一实施方式中,所述交织器的行数r是所述扩展因子z的倍数或者因子。
在一实施方式中,所述交织器的列数c是所述基础矩阵的列数nb的倍数或者因子。
在一实施方式中,所述将所述第一调制符号流Si映射到物理信道资源上,包括:
将所述物理信道资源划分为多个资源单元,所述资源单元至少包括频域上的一个子载波和时域上的一个正交频分复用符号;
确定所述多个资源单元的排序;
将所述第一调制符号流Si中的每个调制符号依次映射到所述多个资源单元上。
在一实施方式中,所述确定所述多个资源单元的排序是通过下面的方式实现的:
按照每个资源单元的信道质量指示信息从高到低的顺序,确定所述多个资源单元的排序;或者
按照是否映射突发数据确定所述多个资源单元的排序,其中,未映射突发数据的资源单元的优先级高于映射了突发数据的资源单元的优先级。
在一实施方式中,所述将所述第一调制符号流Si中的每个调制符号,依次映射到所述多个资源单元上,包括:
将包含所述第六比特流Ei的系统比特的调制符号,优先映射到排序靠前的所述资源单元上;或者
将包含所述第六比特流Ei中对应于奇偶校验矩阵或者基础矩阵的列重量最大的比特序列,优先映射到排序最靠前的资源单元上。
本发明实施例还提供一种数据发送的装置,包括:
添加模块,设置为对待传输的第一比特流添加第一长度的循环冗余校验码,得到第二比特流;
分割模块,设置为根据所述第二比特流的长度以及预先设定的最大码块长度,将所述第二类比特流分割为N1个第三比特流Pi,并对所述第三比特流分别添加第二长度的循环冗余校验码,得到N1个第四比特流Ci;其中,N1是正整数,i是整数,并且0≤i≤N1-1;
编码模块,设置为对所述第四比特流Ci分别进行低密度奇偶校验码编码,得到N1个第五比特流Di;
匹配模块,设置为对所述N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei;
调制模块,设置为对所述N1个第六比特流进行数字基带调制,得到N1个第一调制符号流Si;
映射模块,设置为将所述第一类调制符号流Si映射到物理信道资源上。
在一实施方式中,所述低密度奇偶校验码为准循环的低密度奇偶校验码,且所述低密度奇偶校验码的基础矩阵是一个mb行nb列的矩阵,扩展因子为z;其中,mb、nb、z均为正整数,并且,0<mb<nb。
在一实施方式中,所述匹配模块包括:
输入单元,设置为将所述N1个所述第五比特流Di分别输入到r行c列的交织器中;
读取单元,设置为从所述交织器中读取特定长度的数据比特组成第六比特流Ei,
其中,所述交织器的行数r和列数c是所述低密度奇偶校验码的基础矩阵大小的函数和所述扩展因子的函数中的至少之一。
在一实施方式中,所述交织器的行数r是所述扩展因子z的倍数或者因子,
所述交织器的列数c是所述基础矩阵的列数nb的倍数或者因子。
在一实施方式中,所述映射模块包括:
划分单元,设置为将所述物理信道资源划分为多个资源单元,所述资源单元至少包括频域上的一个子载波和时域上的一个正交频分复用符号;
确定单元,设置为确定所述多个资源单元的排序;
映射单元,设置为将所述第一调制符号流Si中的每个调制符号依次映射到所述多个资源单元上。
在一实施方式中,所述确定单元,设置为按照每个资源单元的信道质量指示信息从高到低的顺序,确定所述多个资源单元的排序;或者按照是否映射突发数据确定所述多个资源单元的排序,其中,未映射突发数据的资源单元的优先级高于映射了突发数据的资源单元的优先级。
在一实施方式中,所述映射单元,设置为将包含所述第六比特流Ei的系统比特的调制符号,优先映射到排序靠前的所述资源单元上;或者将包含所述第六比特流Ei中对应于奇偶校验矩阵或者基础矩阵的列重量最大的比特序列,优先映射到排序最靠前的资源单元上。
本发明实施例还提供一种通信设备,包括处理器以及存储有所述处理器可执行指令的存储器,当所述指令被处理器执行时,执行如下操作:对待传输的第一比特流添加第一长度的循环冗余校验码,得到第二比特流;根据所述第二比特流的长度以及预先设定的最大码块长度,将所述第二类比特流分割为N1个第三比特流Pi,并对所述第三比特流分别添加第二长度的循环冗余校验码,得到N1个第四比特流Ci;其中,N1是正整数,i是整数,并且0≤i≤N1-1;对所述第四比特流Ci分别进行低密度奇偶校验码编码,得到N1
个第五比特流Di;对所述N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei;对所述N1个第六比特流进行数字基带调制,得到N1个第一调制符号流Si;将所述第一类调制符号流Si映射到物理信道资源上。
在一实施方式中,所述低密度奇偶校验码为准循环的低密度奇偶校验码,且所述低密度奇偶校验码的基础矩阵是一个mb行nb列的矩阵,扩展因子为z;其中,mb、nb、z均为正整数,并且,0<mb<nb。
在一实施方式中,所述对所述N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei包括:将所述N1个所述第五比特流Di分别输入到r行c列的交织器中,从所述交织器中读取特定长度的数据比特组成第六比特流Ei,其中,所述交织器的行数r和列数c是所述低密度奇偶校验码的基础矩阵大小的函数和所述扩展因子的函数中的至少之一。
在一实施方式中,所述将所述第一调制符号流Si映射到物理信道资源上,包括:将所述物理信道资源划分为多个资源单元,所述资源单元至少包括频域上的一个子载波和时域上的一个正交频分复用符号;确定所述多个资源单元的排序;将所述第一调制符号流Si中的每个调制符号依次映射到所述多个资源单元上。
在一实施方式中,所述确定所述多个资源单元的排序是通过下面的方式实现的:按照每个资源单元的信道质量指示信息从高到低的顺序,确定所述多个资源单元的排序;或者按照是否映射突发数据确定所述多个资源单元的排序,其中,未映射突发数据的资源单元的优先级高于映射了突发数据的资源单元的优先级。
在一实施方式中,所述将所述第一调制符号流Si中的每个调制符号,依次映射到所述多个资源单元上,包括:将包含所述第六比特流Ei的系统比特的调制符号,优先映射到排序靠前的所述资源单元上;或者将包含所述第六比特流Ei中对应于奇偶校验矩阵或者基础矩阵的列重量最大的比特序列,
优先映射到排序最靠前的资源单元上。
本发明实施例还提供一种计算机可读存储介质,存储有计算机可执行指令,所述计算机可执行指令被处理器执行时实现上述数据发送的方法。
综上,本发明实施例提供一种数据发送的方法及装置、通信设备,实现灵活的低密度奇偶校验码的速率匹配。本方案中的比特流分割方法,分割后的比特流是偶数个,这样在接收端进行译码的时候便于采用双帧译码的结构,可以提高译码器的吞吐量,降低功耗和复杂度,低密度奇偶校验码的交织方法,其中交织器的参数是奇偶校验矩阵或者基础矩阵的函数,这种交织器设计便于匹配不同的码长和码率便于进行进行列间重排,可降低复杂度。本方案将低密度奇偶校验码中重要的系统比特优先映射到信道条件较好或者没有突发数据的资源单元上,可以提高译码的性能。
在阅读并理解了附图和详细描述后,可以明白其他方面。
附图概述
图1是相关技术的数字通信系统的示意图;
图2是本发明实施例一的数据发送的方法的流程图;
图3是本发明实施例四的数据发送的装置的示意图;
图4是本发明实施例五的数据发送的装置的示意图;
图5是本发明实施例六的数据发送的装置的示意图;
图6为本发明实施例的通讯设备的示意图。
详述
下文中将结合附图对本发明的实施例进行详细说明。
实施例一
本发明实施例,提供了一种数据发送的方法,如图2所示,该方法包括:
步骤101:发送端对待传输的第一比特流I,添加长度为Lcrc1比特的循环冗余校验码,得到第二比特流J;
步骤102:根据第二比特流J的长度L2(比特)以及预先设定的最大码块长度T(比特),将所述第二类比特流J分割为N1个第三比特流Pi,并对所述第三比特流Pi分别添加长度为Lcrc2比特的循环冗余校验码,得到N1个第四比特流Ci;其中N1是正整数,i是整数,并且0≤i≤N1-1;
其中,根据第二比特流J的长度L2(比特)以及预先设定的最大码块长度T(比特),将所述第二类比特流J分割为N1个第三类比特流Pi,其中N1通过如下方法确定:
根据上述确定的第三类比特流的个数N1,对第二比特流进行均匀或者近似均匀分割,并对所述第三比特流Pi分别添加长度为Lcrc2比特的循环冗余校验码,得到N1个第四比特流Ci;
本实施例的方法提供的比特流分割方法,分割后的比特流是偶数个,这样在接收端进行译码的时候便于采用双帧译码的结构,可以提高译码器的吞吐量,降低功耗和复杂度。
步骤103:对所述第四比特流Ci分别进行低密度奇偶校验码编码,得到N1个第五比特流Di;
其中,所述低密度奇偶校验码为准循环(或“结构化”)的低密度奇偶校
验码,并且所述低密度奇偶校验码的基础矩阵是一个mb行nb列的矩阵;所述扩展因子的大小为其中,mb,nb,z都是正整数,并且,0<mb<nb。
步骤104:对所述的N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei;该步骤可以包括以下步骤:
步骤104.1、将所述的N1个第五比特流输入到r行c列的交织器中;
其中,所述交织器的行数r和列数c是所述低密度奇偶校验码的基础矩阵和/或所述扩展因子的函数;
进一步地,所述交织器的行数r是所述扩展因子z或者z的倍数;
进一步地,所述交织器的列数c是所述基础矩阵的列数nb或者nb的倍数;
进一步地,所述方法还包括:
根据给定的重排向量,分别对输入到每个所述交织器中的比特流进行列间重排;
步骤104.2、从所述交织器中读取特定长度的数据比特组成第六比特流Ei;
对于每个第五比特流Di从给定的起始位置开始,沿着列的顺序逐列读取特定长度的数据比特组成第六比特流Ei。
本实施例提供了低密度奇偶校验码的交织方法,其中交织器的参数是奇偶校验矩阵或者基础矩阵的函数。这种交织器设计便于匹配不同的码长和码率便于进行进行列间重排,可降低复杂度。
步骤105:对所述N1个第六比特流进行数字基带调制,得到N1个第一调制符号流Si;
步骤106:将所述第一类调制符号流Si映射到物理信道资源上。
在一实施方式中,将包含所述第六比特流Ei的系统比特的调制符号,优先映射到排序靠前的资源单元上;或者,
将所述物理信道资源划分为多个资源单元;其中所述资源单元至少包括
频域上的一个子载波和时域上的一个OFDM(Orthogonal Frequency Division Multiplexing,正交频分复用)符号;
确定所述多个资源单元的排序,将所述第一调制符号流Si中的每个调制符号,依次映射到所述多个资源单元上;
其中,通过如下方式确定所述多个资源单元的排序:
按照每个资源单元的信道质量指示信息CQI(Channel Quality Indicator,信道质量指示)从高到低的顺序,确定所述多个资源单元的排序;
或者,按照是否映射突发数据确定所述多个资源单元排序,其中,未映射突发数据的资源单元的优先级高于映射了突发数据的资源单元的优先级;
将包含所述第六比特流Ei中对应于奇偶校验矩阵或者基础矩阵的列重量最大的比特序列,优先映射到排序最靠前的资源单元上。其中,所述列重量是指所述基础矩阵的列元素中非-1元素的个数。
本实施例提供了一种新的资源映射方法,将低密度奇偶校验码中重要的系统比特优先映射到信道条件较好或者没有突发数据的资源单元上,可以提高译码的性能。
本发明实施例的方法可以实现灵活的低密度奇偶校验码的速率匹配。
实施例二:
步骤201:发送端对长度为L1=20000比特的待传输的第一比特流I,添加长度为Lcrc1=24比特的循环冗余校验码,得到长度为L2=20024比特的第二比特流J;
步骤202:预先设定的最大码块长度为T=6120比特。
对第二比特流I进行分割,因为是奇数,则分割后的第三比特流的数目对所述第三比特流Pi分别添加长度为Lcrc2=24比特的循环冗余校验码,得到N1个第四比特流Ci,其长度是所述预先设定的取值集合Π中的一个元素,并且,所述第i个第四比特流的长度是所述预先设定的取值集合Π中小于或者等于比特的最
大的元素,或者大于等于5040比特的最小的元素。
在本实施例中,假设所述预先设定的集合Π为{……,4800,4864,4928,4992,5056,5120,5184,……},则所述第i个第四比特流的长度或者在本例中,第0个第四比特流的长度为比特,第1,第2和第3个第四比特流长度都为比特。其中,在第0个第四比特流的最靠前的位置上添加了60比特的填充比特。
步骤203:对所述第四比特流Ci分别采用进行低密度奇偶校验码编码,得到N1=4个第五比特流Di;
其中,所述低密度奇偶校验码为准循环(或“结构化”)的低密度奇偶校验码,并且所述低密度奇偶校验码的基础矩阵是一个mb=4行nb=12列的矩阵;所述扩展因子的大小为其中,第0比特流的扩展因子为z=624;第1,第2和第3个第四比特流的扩展因子为632。
步骤204:对所述的N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei,可以包括以下步骤:
步骤204.1、将所述的N1个第五比特流输入到r行c列的交织器中;
在本实施例中,假设所述交织器的行数r是等于扩展因子r=z,交织器的列数等于基础矩阵的列数c=nb;其中,比特流D0的交织器是624行12列的交织器,比特流D1,D2和D3所用的交织器是632行12列的交织器;
步骤204.2、对所述输入到交织器中的每个比特流根据给定的重排向量进行列间重排列;在本例中假设重排向量为PV=[1,2,3,4,5,6,7,8,12,10,9,11];所述PV向量表示重排后的列索引。其中列索引是从1开始。
步骤204.3、在本实施例中,假设每个第六比特流的长度都为6000比特;从对于每个重排后的比特流,从给定的起始位置开始,沿着列的顺序逐列读取长度为6000比特的数据比特组成第六比特流Ei;其中,所述的起始位置可以通过冗余版本来指示。
步骤205:对所述N1个第六比特流进行数字基带调制,得到N1个第一调制符号流Si;
所述数字基带调制可以是QPSK(Quadrature Phase Shift Keying,正交相移键控),16QAM(Quadrature Amplitude Modulation,相正交振幅调制),64QAM或者256QAM调制,其中每个调制符号中分别包括2比特,4比特,6比特或者8比特数据;在本例中假设为16QAM调制,每个16QAM调制符号中包括4比特数据。
步骤206:将所述第一调制符号流Si映射到物理信道资源上;
其中,所述物理资源划分为两个资源单元,每个资源单元都至少包括频域上的一个子载波和时域上的一个OFDM(Orthogonal Frequency Division Multiplexing,正交频分复用)符号;其中,第一资源单元上有突发数据,第二资源单元上没有突发数据,因此,第二资源单元的优先级高于第一资源单元。
将所述第一调制符号流中对应于第六比特流的系统比特的调制符号优先映射到高优先级的资源单元上。假设在本实施例中,第一调制符号流S1中的前1264个16QAM符号{s0,s1,….,s1263}对应于第六比特流E1的系统比特,S1中的后236个16QAM符号{s1264,s1265,….,s1499}对应于第六比特流E1的校验比特,则将所述的前1264个16QAM优先映射到第二资源单元上。
其他的第一调制符号流也做类似处理。
实施例三:
步骤301:发送端对长度为L1=20000比特的待传输的第一比特流I,添加长度为Lcrc1=24比特的循环冗余校验码,得到长度为L2=20024比特的第二比特流J;
步骤302:预先设定的最大码块长度为T=6120比特。
对第二比特流I进行分割,因为是奇数,则分割后的第三比特流的数目对所述第三比特流Pi分别添加长度为Lcrc2=24比特的循环冗余校验码,得到N1个第四比特流Ci,其长度是所述预先设定的取值集合Π中的一个元素,并且,所述第i个第四比特流的长度是所述预先
设定的取值集合Π中小于或者等于比特的最大的元素,或者大于等于3361比特的最小的元素。
在本实施例中,假设所述预先设定的集合Π为{……,3200,3264,3328,3392,3456,3520……},则所述第i个第四比特流的长度或者在本实施例中,第0和第1个第四比特流的长度为比特,第1、第2、第3、第4、第5、第6个第四比特流长度都为比特。其中,在第0个第四比特流的最靠前的位置上添加了56比特的填充比特。
步骤303:对所述第四比特流Ci分别采用进行低密度奇偶校验码编码,得到N1=6个第五比特流Di;
其中,所述低密度奇偶校验码为准循环(或“结构化”)的低密度奇偶校验码,并且所述低密度奇偶校验码的基础矩阵是一个mb=4行nb=12列的矩阵;所述扩展因子的大小为其中,第0和第1比特流的扩展因子为z=416;第1,第2和第3个第四比特流的扩展因子为424。
步骤304:对所述的N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei,可以包括以下步骤:
步骤304.1、将所述的N1个第五比特流输入到r行c列的交织器中;
在本实施例中,假设所述交织器的行数r是扩展因子的倍数或者因子r=a*z,交织器的列数等于基础矩阵的列数的倍数或者因子c=nb/a,其中a为正数。
在本实施例中,假设a=1/2,则比特流D0和D1的交织器是208行24列的交织器,比特流D1,D2和D3所用的交织器是212行24列的交织器;
步骤304.2、对所述输入到交织器中的每个比特流根据给定的重排向量进行列间重排列;
在本实施例中假设重排向量为PV=[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,23,24,19,20,17,18,21,22];其中,PV向量中的每个元素代表交织器中的1列;所述PV向量表示重排后的列索引。
其中列索引是从1开始。
步骤305:对所述N1个第六比特流进行数字基带调制,得到N1个第一调制符号流Si;
所述数字基带调制可以是QPSK,16QAM,64QAM或者256QAM调制,其中每个调制符号中分别包括2比特,4比特,6比特或者8比特数据;在本实施例中假设为QPSK调制,每个QPSK调制符号中包括2比特数据。
步骤306:将所述第一调制符号流Si映射到物理信道资源上;
其中,所述物理资源划分为4个资源单元,每个资源单元都至少包括频域上的一个子载波和时域上的一个OFDM符号;其中,每个资源单元上的信道指示信息CQI从高到低的顺序为CQI2≥CQI3≥CQI1≥CQI4;则每个资源单元的优先级顺序为资源单元2的优先级最高,资源单元3的优先级次之,资源单元1的优先级第三,资源单元4的优先级最低。
将所述第一调制符号流中对应于第六比特流的系统比特的调制符号优先映射到高优先级的资源单元。假设在本例中,第一调制符号流S1中的前1664个QPSK符号{s0,s1,….,s1663}对应于第六比特流E1的系统比特,S1中的后832个QPSK符号{s1664,s1665,….,s2495}对应于第六比特流E1的校验比特,则将所述的前1664个16QAM优先映射到第二资源单元上,接着映射到第三资源单元上,然后是第一资源单元,最后是第四资源单元。
其他的第一调制符号流也做类似处理。
本发明实施例的方法具有以下优点:
本实施例的方法可以实现灵活的低密度奇偶校验码的速率匹配。
本实施例的方法还提供一种新的比特流分割方法,分割后的比特流是偶数个,这样在接收端进行译码的时候便于采用双帧译码的结构,可以提高译码器的吞吐量,降低功耗和复杂度;
本实施例的方法还提供一种适用于低密度奇偶校验码的交织方法,其中交织器的参数是奇偶校验矩阵或者基础矩阵的函数,这种交织器设计便于匹配不同的码长和码率便于进行进行列间重排,可降低复杂度;
本实施例的方法还提供一种新的资源映射方法,将低密度奇偶校验码中
重要的系统比特优先映射到信道条件较好,或者没有突发数据的资源单元上,可以提高译码的性能。
实施例四
图3为本发明实施例的一种数据发送的装置的示意图,如图3所示,本实施例的装置包括:
添加模块21,设置为对待传输的第一比特流添加第一长度的循环冗余校验码,得到第二比特流;
分割模块22,设置为根据所述第二比特流的长度以及预先设定的最大码块长度,将所述第二类比特流分割为N1个第三比特流Pi,并对所述第三比特流分别添加第二长度的循环冗余校验码,得到N1个第四比特流Ci;其中,N1是正整数,i是整数,并且0≤i≤N1-1;其中,
编码模块23,设置为对所述第四比特流Ci分别进行低密度奇偶校验码编码,得到N1个第五比特流Di;
匹配模块24,设置为对所述N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei;
调制模块25,设置为对所述N1个第六比特流进行数字基带调制,得到N1个第一调制符号流Si;
映射模块26,设置为将所述第一类调制符号流Si映射到物理信道资源上。
其中,所述低密度奇偶校验码为准循环的低密度奇偶校验码,且所述低密度奇偶校验码的基础矩阵是一个mb行nb列的矩阵,扩展因子为z;其中,mb、nb、z均为正整数,并且,0<mb<nb。
实施例五
本实施例中,如图4所示,所述匹配模块24包括:
输入单元241,设置为将所述N1个所述第五比特流Di分别输入到r行c列的交织器中;
读取单元242,设置为从所述交织器中读取特定长度的数据比特组成第六比特流Ei,
其中,所述交织器的行数r和列数c是所述低密度奇偶校验码的基础矩阵和/或所述扩展因子的函数。
其中,所述交织器的行数r是所述扩展因子z的倍数或者因子,
所述交织器的列数c是所述基础矩阵的列数nb的倍数或者因子。
下面结合附图和实施例对本申请作进一步地描述。
实施例六
本实施例中,如图5所示,所述映射模块26包括:
划分单元261,设置为将所述物理信道资源划分为多个资源单元,所述资源单元至少包括频域上的一个子载波和时域上的一个正交频分复用符号;
确定单元262,设置为确定所述多个资源单元的排序;
映射单元263,设置为将所述第一调制符号流Si中的每个调制符号依次映射到所述多个资源单元上。
其中,所述确定单元262,可以设置为按照每个资源单元的信道质量指示信息从高到低的顺序,确定所述多个资源单元的排序;或者按照是否映射突发数据确定所述多个资源单元的排序,其中,未映射突发数据的资源单元的优先级高于映射了突发数据的资源单元的优先级。
所述映射单元263,可以设置为将包含所述第六比特流Ei的系统比特的调制符号,优先映射到排序靠前的所述资源单元上;或者将包含所述第六比特流Ei中对应于奇偶校验矩阵或者基础矩阵的列重量最大的比特序列,优
先映射到排序最靠前的资源单元上。
本发明实施例还提供了一种通信设备,如图6所示,包括处理器31以及存储有所述处理器可执行指令的存储器32,当所述指令被处理器执行时,执行如下操作:对待传输的第一比特流添加第一长度的循环冗余校验码,得到第二比特流;根据所述第二比特流的长度以及预先设定的最大码块长度,将所述第二类比特流分割为N1个第三比特流Pi,并对所述第三比特流分别添加第二长度的循环冗余校验码,得到N1个第四比特流Ci;其中,N1是正整数,i是整数,并且0≤i≤N1-1;对所述第四比特流Ci分别进行低密度奇偶校验码编码,得到N1个第五比特流Di;对所述N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei;对所述N1个第六比特流进行数字基带调制,得到N1个第一调制符号流Si;将所述第一类调制符号流Si映射到物理信道资源上。
在一实施方式中,所述低密度奇偶校验码为准循环的低密度奇偶校验码,且所述低密度奇偶校验码的基础矩阵是一个mb行nb列的矩阵,扩展因子为z;其中,mb、nb、z均为正整数,并且,0<mb<nb。
在一实施方式中,所述对所述N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei包括:将所述N1个所述第五比特流Di分别输入到r行c列的交织器中,从所述交织器中读取特定长度的数据比特组成第六比特流Ei,其中,所述交织器的行数r和列数c是所述低密度奇偶校验码的基础矩阵和/或所述扩展因子的函数。
在一实施方式中,所述将所述第一调制符号流Si映射到物理信道资源上,包括:将所述物理信道资源划分为多个资源单元,所述资源单元至少包括频域上的一个子载波和时域上的一个正交频分复用符号;确定所述多个资源单元的排序;将所述第一调制符号流Si中的每个调制符号依次映射到所述多个资源单元上。
在一实施方式中,所述确定所述多个资源单元的排序是通过下面的方式实现的:按照每个资源单元的信道质量指示信息从高到低的顺序,确定所述多个资源单元的排序;或者按照是否映射突发数据来确定所述多个资源单元的排序,其中,未映射突发数据的资源单元的优先级高于映射了突发数据的资源单元的优先级。
在一实施方式中,所述将所述第一调制符号流Si中的每个调制符号,依次映射到所述多个资源单元上,包括:将包含所述第六比特流Ei的系统比特的调制符号,优先映射到排序靠前的所述资源单元上;或者将包含所述第六比特流Ei中对应于奇偶校验矩阵或者基础矩阵的列重量最大的比特序列,优先映射到排序最靠前的资源单元上。
本发明实施例还提供了一种计算机可读存储介质,其存储有计算机可执行指令,所述计算机可执行指令被执行时实现执行如下操作:
对待传输的第一比特流添加第一长度的循环冗余校验码,得到第二比特流;根据所述第二比特流的长度以及预先设定的最大码块长度,将所述第二类比特流分割为N1个第三比特流Pi,并对所述第三比特流分别添加第二长度的循环冗余校验码,得到N1个第四比特流Ci;其中,N1是正整数,i是整数,并且0≤i≤N1-1;对所述第四比特流Ci分别进行低密度奇偶校验码编码,得到N1个第五比特流Di;对所述N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei;对所述N1个第六比特流进行数字基带调制,得到N1个第一调制符号流Si;将所述第一类调制符号流Si映射到物理信道资源上。
本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序来指令相关硬件完成,所述程序可以存储于计算机可读存储介质中,如只读存储器、磁盘或光盘等。上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现。相应地,上述实施例中的各模块/单元可以采用硬件的形式实现,也可以采用软件功能模块的形式实现。本发明实施例不限制于任何特定形式的硬件和软件的结合。
以上仅为本发明的实施例,当然,本申请还可有其他多种实施例,在不背离本申请精神及其实质的情况下,熟悉本领域的技术人员当可根据本申请作出各种相应的改变和变形,但这些相应的改变和变形都应属于本申请所附的权利要求的保护范围。
本发明实施例提供一种数据发送的方法及装置、通信设备,实现灵活的低密度奇偶校验码的速率匹配。本方案中的比特流分割方法,分割后的比特流是偶数个,这样在接收端进行译码的时候便于采用双帧译码的结构,可以提高译码器的吞吐量,降低功耗和复杂度,低密度奇偶校验码的交织方法,其中交织器的参数是奇偶校验矩阵或者基础矩阵的函数,这种交织器设计便于匹配不同的码长和码率便于进行进行列间重排,可降低复杂度。本方案将低密度奇偶校验码中重要的系统比特优先映射到信道条件较好或者没有突发数据的资源单元上,可以提高译码的性能。
Claims (25)
- 一种数据发送的方法,包括:对待传输的第一比特流添加第一长度的循环冗余校验码,得到第二比特流;根据所述第二比特流的长度以及预先设定的最大码块长度,将所述第二类比特流分割为N1个第三比特流Pi,并对所述第三比特流分别添加第二长度的循环冗余校验码,得到N1个第四比特流Ci;其中,N1是正整数,i是整数,并且0≤i≤N1-1;对所述第四比特流Ci分别进行低密度奇偶校验码编码,得到N1个第五比特流Di;对所述N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei;对所述N1个第六比特流进行数字基带调制,得到N1个第一调制符号流Si;将所述第一类调制符号流Si映射到物理信道资源上。
- 如权利要求1所述的方法,其中,所述低密度奇偶校验码为准循环的低密度奇偶校验码,且所述低密度奇偶校验码的基础矩阵是一个mb行nb列的矩阵,扩展因子为z;其中,mb、nb、z均为正整数,并且,0<mb<nb。
- 如权利要求1-3任一项所述的方法,其中,所述对所述N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei,包括:将所述N1个所述第五比特流Di分别输入到r行c列的交织器中,从所述交织器中读取特定长度的数据比特组成第六比特流Ei,其中,所述交织器的行数r和列数c是所述低密度奇偶校验码的基础矩阵大小的函数和所述扩展因子的函数中的至少之一。
- 如权利要求4所述的方法,其中,所述交织器的行数r是所述扩展因子z的倍数或者因子。
- 如权利要求4所述的方法,其中,所述交织器的列数c是所述基础矩阵的列数nb的倍数或者因子。
- 如权利要求1所述的方法,其中,所述将所述第一调制符号流Si映射到物理信道资源上,包括:将所述物理信道资源划分为多个资源单元,所述资源单元至少包括频域上的一个子载波和时域上的一个正交频分复用符号;确定所述多个资源单元的排序;将所述第一调制符号流Si中的每个调制符号依次映射到所述多个资源单元上。
- 如权利要求7所述的方法,其中,所述确定所述多个资源单元的排序是通过下面的方式实现的:按照每个资源单元的信道质量指示信息从高到低的顺序,确定所述多个资源单元的排序;或者按照是否映射突发数据确定所述多个资源单元的排序,其中,未映射突发数据的资源单元的优先级高于映射了突发数据的资源单元的优先级。
- 如权利要求7所述的方法,其中,所述将所述第一调制符号流Si中的每个调制符号,依次映射到所述多个资源单元上,包括:将包含所述第六比特流Ei的系统比特的调制符号,优先映射到排序靠前的所述资源单元上;或者将包含所述第六比特流Ei中对应于奇偶校验矩阵或者基础矩阵的列重量最大的比特序列,优先映射到排序最靠前的资源单元上。
- 一种数据发送的装置,包括:添加模块,设置为对待传输的第一比特流添加第一长度的循环冗余校验码,得到第二比特流;分割模块,设置为根据所述第二比特流的长度以及预先设定的最大码块长度,将所述第二类比特流分割为N1个第三比特流Pi,并对所述第三比特流分别添加第二长度的循环冗余校验码,得到N1个第四比特流Ci;其中,N1是正整数,i是整数,并且0≤i≤N1-1;编码模块,设置为对所述第四比特流Ci分别进行低密度奇偶校验码编码,得到N1个第五比特流Di;匹配模块,设置为对所述N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei;调制模块,设置为对所述N1个第六比特流进行数字基带调制,得到N1个第一调制符号流Si;映射模块,设置为将所述第一类调制符号流Si映射到物理信道资源上。
- 如权利要求10所述的装置,其中,所述低密度奇偶校验码为准循环的低密度奇偶校验码,且所述低密度奇偶校验码的基础矩阵是一个mb行nb列的矩阵,扩展因子为z;其中,mb、nb、z均为正整数,并且,0<mb<nb。
- 如权利要求10或12所述的装置,其中,所述匹配模块包括:输入单元,设置为将所述N1个所述第五比特流Di分别输入到r行c列的交织器中;读取单元,设置为从所述交织器中读取特定长度的数据比特组成第六比特流Ei,其中,所述交织器的行数r和列数c是所述低密度奇偶校验码的基础矩阵大小的函数和所述扩展因子的函数中的至少之一。
- 如权利要求13所述的装置,其中,所述交织器的行数r是所述扩展因子z的倍数或者因子,所述交织器的列数c是所述基础矩阵的列数nb的倍数或者因子。
- 如权利要求10所述的装置,其中,所述映射模块包括:划分单元,设置为将所述物理信道资源划分为多个资源单元,所述资源单元至少包括频域上的一个子载波和时域上的一个正交频分复用符号;确定单元,设置为确定所述多个资源单元的排序;映射单元,设置为将所述第一调制符号流Si中的每个调制符号依次映射到所述多个资源单元上。
- 如权利要求15所述的装置,其中,所述确定单元,设置为按照每个资源单元的信道质量指示信息从高到低的顺序,确定所述多个资源单元的排序;或者按照是否映射突发数据确定所述多个资源单元的排序,其中,未映射突发数据的资源单元的优先级高于映射了突发数据的资源单元的优先级。
- 如权利要求15所述的装置,其中,所述映射单元,设置为将包含所述第六比特流Ei的系统比特的调制符号,优先映射到排序靠前的所述资源单元上;或者将包含所述第六比特流Ei中对应于奇偶校验矩阵或者基础矩阵的列重量最大的比特序列,优先映射到排序最靠前的资源单元上。
- 一种通信设备,包括处理器以及存储有所述处理器可执行指令的存储器,当所述指令被处理器执行时,执行如下操作:对待传输的第一比特流添加第一长度的循环冗余校验码,得到第二比特流;根据所述第二比特流的长度以及预先设定的最大码块长度,将所述第二类比特流分割为N1个第三 比特流Pi,并对所述第三比特流分别添加第二长度的循环冗余校验码,得到N1个第四比特流Ci;其中,N1是正整数,i是整数,并且0≤i≤N1-1;对所述第四比特流Ci分别进行低密度奇偶校验码编码,得到N1个第五比特流Di;对所述N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei;对所述N1个第六比特流进行数字基带调制,得到N1个第一调制符号流Si;将所述第一类调制符号流Si映射到物理信道资源上。
- 如权利要求18所述的通信设备,其中所述低密度奇偶校验码为准循环的低密度奇偶校验码,且所述低密度奇偶校验码的基础矩阵是一个mb行nb列的矩阵,扩展因子为z;其中,mb、nb、z均为正整数,并且,0<mb<nb。
- 如权利要求18-20任一项所述的通信设备,其中,所述对所述N1个第五比特流Di分别进行速率匹配,输出N1个第六比特流Ei包括:将所述N1个所述第五比特流Di分别输入到r行c列的交织器中,从所述交织器中读取特定长度的数据比特组成第六比特流Ei,其中,所述交织器的行数r和列数c是所述低密度奇偶校验码的基础矩阵大小的函数和所述扩展因子的函数中的至少之一。
- 如权利要求18所述的通信设备,其中,所述将所述第一调制符号流Si映射到物理信道资源上,包括:将所述物理信道资源划分为多个资源单元,所述资源单元至少包括频域上的一个子载波和时域上的一个正交频分复用符号;确定所述多个资源单元的排序;将所述第一调制符号流Si中的每个调制符号依次映射到所述多个资源单元上。
- 如权利要求22所述的通信设备,其中,所述确定所述多个资源单元的排序是通过下面的方式实现的:按照每个 资源单元的信道质量指示信息从高到低的顺序,确定所述多个资源单元的排序;或者将所述多个资源单元按照是否映射突发数据确定排序,其中,未映射突发数据的资源单元的优先级高于映射了突发数据的资源单元的优先级。
- 如权利要求22所述的通信设备,其中,所述将所述第一调制符号流Si中的每个调制符号,依次映射到所述多个资源单元上,包括:将包含所述第六比特流Ei的系统比特的调制符号,优先映射到排序靠前的所述资源单元上;或者将包含所述第六比特流Ei中对应于奇偶校验矩阵或者基础矩阵的列重量最大的比特序列,优先映射到排序最靠前的资源单元上。
- 一种计算机可读存储介质,存储有计算机可执行指令,所述计算机可执行指令用于执行权利要求1-9任一项的数据发送的方法。
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