WO2018018887A1 - 电平转换器及其操作方法、栅极驱动电路和显示装置 - Google Patents

电平转换器及其操作方法、栅极驱动电路和显示装置 Download PDF

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WO2018018887A1
WO2018018887A1 PCT/CN2017/074529 CN2017074529W WO2018018887A1 WO 2018018887 A1 WO2018018887 A1 WO 2018018887A1 CN 2017074529 W CN2017074529 W CN 2017074529W WO 2018018887 A1 WO2018018887 A1 WO 2018018887A1
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nth
output
signal
input
control signal
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PCT/CN2017/074529
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English (en)
French (fr)
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耿伟彪
赖意强
张春兵
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/553,044 priority Critical patent/US10402013B2/en
Priority to EP17751590.5A priority patent/EP3493196A4/en
Publication of WO2018018887A1 publication Critical patent/WO2018018887A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0833—Several active elements per pixel in active matrix panels forming a linear amplifier or follower
    • G09G2300/0838—Several active elements per pixel in active matrix panels forming a linear amplifier or follower with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness

Definitions

  • the present disclosure relates to a level shifter and method of operating the same, a gate drive circuit, and a display device.
  • the existing display device with touch function can be generally divided into an on-cell touch panel and an in-cell touch panel.
  • the in-cell touch panel has a thinner thickness and a higher light transmittance than a surface touch panel.
  • the present disclosure proposes a level shifter and its operating method, a gate driving circuit and a display device, which can solve the problem that the partial line display of the picture is dark due to the long horizontal blanking time.
  • a level shifter comprising:
  • the level conversion unit is connected to the N input terminals, the N control signal terminals, and the N output terminals, and is configured to determine, according to the nth control signal of the control signal end, that the nth input signal is directly used as the nth output signal. Output, or convert the nth input signal and then output as the nth output signal;
  • the conversion is to convert the nth input signal having a faster rise time into the nth output signal having a slower rise time, and N is a positive integer, 1 ⁇ n ⁇ N.
  • the nth input signal is directly output as the nth output signal; otherwise, the conversion is performed.
  • the level conversion unit includes first to Nth resistors and first to Nth switches, wherein the nth resistor and the nth switch are connected in parallel, and one end of the nth resistor and the nth switch are connected to the nth input signal, The nth resistor and the other end of the nth switch are connected to the nth output signal.
  • the nth switch when the nth control signal is equal to n, the nth switch is turned on; otherwise, the nth switch remains off.
  • the switch is a thin film transistor.
  • N 6
  • a gate driving circuit including a plurality of cascaded GOA units each of a group of N GOA units, the GOA units in each group receiving first to Nth clock signals, respectively, is disclosed.
  • the N output signals of the above-described level shifters are supplied as the first to Nth clock signals.
  • the N control signal terminals receive N-way control signals from the timing controller.
  • the output controller of the next GOA unit is detected by the timing controller, and the output behavior of the next GOA unit is detected as the Nth LHB +1 line or the Nth LHB +2 line or the Nth LHB +3 line, and the next GOA
  • the timing controller outputs an nth way control signal equal to n, wherein the long horizontal blanking time is turned on after the end of the Nth LHB line charging.
  • a display device including the above-described gate driving circuit is disclosed.
  • a method of operating the above-described level shifter including:
  • the level conversion unit determines whether to output the nth input signal directly as the nth output signal according to the nth control signal of the control signal end, or convert the nth input signal to be the nth output. Signal output;
  • the conversion is to convert the nth input signal having a faster rise time into the nth output signal having a slower rise time, and N is a positive integer, 1 ⁇ n ⁇ N.
  • the level shifter, the gate driving circuit, and the display device of the embodiments of the present disclosure it is possible to solve the problem that the partial display of the screen is dark due to the long horizontal blanking time, thereby improving the picture quality.
  • Figure 1 is a circuit diagram of a GOA unit
  • FIG. 2 is a timing chart showing the operation of the GOA unit of Figure 1;
  • FIG. 3 is a timing diagram of signals in a gate driving circuit formed by cascading GOA units in FIG. 1;
  • FIG. 4 is a schematic structural diagram of a level shifter according to an embodiment of the present disclosure.
  • FIG. 5 is a circuit diagram of a level shifting unit in a level shifter in accordance with an embodiment of the present disclosure
  • FIG. 6 is a flow chart showing a method of controlling the above-described level conversion unit by using a timing controller in the above-described gate driving circuit;
  • FIG. 7 is an effect diagram of a corresponding output signal of the GOA unit in the case where the voltage is dropped at the pull-up node, the switch is turned off in the level shifting unit, and the switch is closed in the level shifting unit.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • the connection modes of the drain and the source of each transistor are interchangeable. Therefore, the drain and source of each transistor in the embodiment of the present disclosure are practically indistinguishable.
  • the drain and source of each transistor in the embodiment of the present disclosure are practically indistinguishable.
  • the gate one of which is called the drain and the other is called the source.
  • the applicant has noticed that in the in-cell touch technology based on the GOA unit, since there is a long horizontal blanking (Long-H Blank, LHB) time to wait for the touch action to be completed, during this LHB, the subsequent GOA The unit shortens the charging time of the pixels of the corresponding row, causing the partial line of the picture to be displayed dark.
  • LHB horizontal blanking
  • the present disclosure proposes a level shifter, a gate driving circuit, and a display device, which can solve the above problem that the partial line display of the screen is dark due to the long horizontal blanking time.
  • Figure 1 is a circuit diagram of a GOA unit.
  • 2 is an operational timing diagram of the GOA unit of FIG. 1.
  • the GOA unit includes first to twelfth transistors M1-M12 and a first capacitor C1.
  • the operation method of the GOA unit in Fig. 1 will be described below with reference to Figs. 1 and 2.
  • transistors in FIG. 1 are N-type transistors.
  • the input terminal INPUT is at a high level
  • the input transistor M1 is turned on, and the high level of the input terminal INPUT is transmitted to the pull-up node PU, and the pull-up node PU is at the first high voltage.
  • the output transistor M3 is turned on, and the output terminal OUTPUT outputs a low level because the first clock signal of the first clock signal terminal CLK is at a low level.
  • the pull-up node PU is at a high level
  • the first pull-down control transistor M6 and the second pull-down control transistor M7 are turned on, so that the pull-down node PD is at a low level, correspondingly the node pull-down transistor M9 and The output pull-down transistor M10 is turned off.
  • the reset signal of the reset signal terminal RESET is at a low level, and the node reset transistor M2 is turned off.
  • the input terminal INPUT is at a low level
  • the input transistor M1 is turned off
  • the reset signal terminal RESET is at a low level
  • the node reset transistor M2 is kept off
  • the pull-up node PU continues to turn on the output transistor M3.
  • the first clock signal of the first clock signal terminal CLK is at a high level
  • the output terminal OUTPUT outputs a high level. Due to the voltage coupling of the first capacitor C1, the pull-up node PU is raised from the first high voltage to the first Two high voltages.
  • the input terminal INPUT is at a low level
  • the input transistor M1 remains off
  • the reset signal of the reset signal terminal RESET is at a high level
  • the node reset transistor M2 and the output reset transistor M4 are turned on, respectively
  • the pull-up signal at the pull-up node PU and the output signal of the output terminal OUTPUT are pulled down to the power supply voltage of the first power supply voltage terminal VSS.
  • the pull-up node PU is at a low level
  • the first pull-down control transistor M6 and the second pull-down control transistor M7 are both turned off, because the second clock signal of the second clock signal terminal CLKB is at a high level.
  • the third pull-down control transistor M5 and the fourth pull-down control transistor M8 are both turned on, so that the pull-down node PD transitions from a low level to a high level, and accordingly the node pull-down transistor M9 and the output pull-down transistor M10 are both turned on and pulled up.
  • the pull-up signal at the node PU and the output signal of the output terminal OUTPUT are pulled down to the power supply voltage of the first power supply voltage terminal VSS.
  • the second clock signal of the second clock signal terminal CLKB is at a low level, and the third pull-down control transistor M5 and the fourth pull-down control transistor M8 are both turned off, because the pull-up node PU is in a low state.
  • the first pull-down control transistor M6 and the second pull-down control transistor M7 are both kept off.
  • the voltage of the pull-down node PD is at a high level, correspondingly the node pulls down the crystal
  • the tube M9 and the output pull-down transistor M10 are both turned on, and the pull-up node PU and the output terminal OUTPUT are kept pulled down to the power supply voltage of the first power supply voltage terminal VSS.
  • the first power supply voltage terminal VSS is a low power supply voltage terminal.
  • the pull-up node PU is always at a low level
  • the pull-down node PD is always at a high level
  • the output terminal OUTPUT always outputs a low-voltage signal.
  • the GOA unit re-executes the first stage after receiving the high level signal of the input terminal INPUT.
  • the first clock signal of the first clock signal terminal CLK is inverted with the second clock signal of the second clock signal terminal CLKB.
  • FIG. 3 is a timing chart of signals in a gate driving circuit formed by cascading GOA cells in FIG. 1.
  • every 6 GOA units are a group
  • FIG. 3 shows the respective clock signals CLK1-CLK6 of the 6 GOA units, and the initial input signal of the first input of the 6 GOA units.
  • the gate driving circuit may actually be cascaded in any group of N GOA units, and includes a plurality of such group.
  • the input of the first one of the plurality of GOA units receives the first frame start signal STV.
  • the input ends of the second to third GOA units respectively receive second to third frame start signals (not shown).
  • the input terminals of the fourth to sixth GOA units respectively receive the output signals of the first to third GOA units.
  • the first clock signal terminals of the first to sixth GOA units respectively receive the first to sixth clock signals CLK1-CLK6. According to the foregoing description, it can be known that the output signals of the first to sixth GOA units correspond to the first to sixth clock signals CLK1-CLK6, respectively.
  • the SW signal controls whether or not touch is performed.
  • the present disclosure provides a level shifter, a gate driving circuit, and a display device, which can improve the charging time of the GOA unit at the LHB time after the voltage drop at the pull-up node PU with respect to the GOA unit at the non-LHB time. Due to the voltage drop at the pull-up node PU, the partial line of the picture is displayed dark, thereby improving the picture quality.
  • the level shifter 100 includes: N input terminals for receiving N input signals input(1)-input(N); N control signal terminals for receiving N control signals LHB (1)-LHB(N); N outputs for outputting N output signals output(1)-output(N); and level shifting unit 10, connecting N input terminals, N control signal terminals, and N output terminals for determining whether to output the nth input signal input(n) directly as the nth output signal output(n) according to the nth control signal LHB(n) of the control signal end, or The nth input signal input(n) is converted and then output as the nth output signal output(n).
  • the conversion is to convert the nth input signal input(n) having a faster rise time into the nth output signal output(n) having a slow rise time, and N is a positive integer, 1 ⁇ n ⁇ N .
  • the nth input signal input(n) is directly output as the nth output signal output(n); Said conversion.
  • the N-way control signals LHB(1)-LHB(N) described above may be from the timing controller 20.
  • FIG. 5 is a circuit diagram of level shifting unit 10 in level shifter 100, in accordance with an embodiment of the present disclosure.
  • the level conversion unit includes first to Nth resistors and first to Nth switches.
  • the nth resistor Rn and the nth switch Sn are connected in parallel, and one end of the nth resistor Rn and the nth switch Sn is connected to the nth input signal input(n), the nth resistor Rn and the nth switch Sn The other end is connected to the nth output signal output(n).
  • the nth switch Sn when the nth way control signal LHB(n) is equal to n, the nth switch Sn is turned on; otherwise, the nth switch Sn remains off.
  • LHB(2) 2, the second switch S2 is turned on; when LHB(2) ⁇ 2, the second switch S2 is kept off.
  • the switch is a thin film transistor.
  • N 6.
  • a level shifter employing the level shifting unit described above can be used to provide a clock signal to the gate drive circuit discussed in connection with FIGS. 1 and 3.
  • a method of operating the level shifter 100 described above including:
  • the level conversion unit 10 determines to output the nth input signal input(n) directly as the nth output signal output(n) according to the nth control signal LHB(n) of the control signal terminal, or The n input signal input(n) is converted and then output as the nth output signal output(n);
  • the conversion is to convert the nth input signal input(n) having a faster rise time into the nth output signal output(n) having a slow rise time, and N is a positive integer, 1 ⁇ n ⁇ N .
  • a gate driving circuit including a plurality of cascaded GOA units, each N GOA units being a group, and the GOA units in each group respectively receive the first to Nth clock signals
  • the N output signals of the level shifter 100 described above are supplied as the first to Nth clock signals, and N is a positive integer.
  • N control signal terminals receive N-way control signals from timing controller 20.
  • the output line of the next GOA unit is detected by the timing controller 20, and the output behavior of the next GOA unit is detected as the Nth LHB +1 line or the Nth LHB +2 line or the Nth LHB +
  • the timing controller outputs an nth path control signal LHB(n) equal to n, wherein the long horizontal blanking time is turned on after the end of the Nth LHB line charging.
  • N LHB can be set by the user.
  • N 6
  • FIG. 6 is a flow chart showing a method of controlling the level shifting unit by a timing controller in the above-described gate driving circuit.
  • N 6 as an example.
  • the level shifter of the conversion unit can be used to provide a clock signal to the gate drive circuit discussed in connection with Figures 1 and 3.
  • method 200 begins in step S201 and ends in step S205.
  • the output signal of the output terminal OUTPUT of the current row (denoted as the nth row) of the GOA unit is the input signal of the GOA unit of the n+3th row.
  • the output line of the next GOA unit is detected by the timing controller 20. If it is detected in step S202 that the output line of the next GOA unit is not any of the Nth LHB +1, the Nth LHB +2 line, or the Nth LHB +3 line, the method returns to step S201.
  • the rise time of the control signal such as a square wave signal
  • the rise time of the row output signal output(n) is relatively short, that is, for the corresponding GOA unit, the rise time of the received first clock signal is relatively short, thereby making the GOA unit
  • the rise time of the output signal is shortened. Since the voltage at the pull-up node PU of the GOA unit drops due to the presence of leakage current, the output transistor M3 is insufficiently turned on, so that the rise time of the output signal of the GOA unit becomes long.
  • FIG. 7 is an effect diagram of the corresponding output signal G_out of the GOA unit in the case where the voltage is dropped at the pull-up node PU, the switch is turned off in the level shifting unit, and the switch is closed in the level shifting unit.
  • the voltage at the pull-up node PU decreases, and the rise time of the corresponding output signal G_out of the GOA unit is longer; in the second case, the switch in the level shift unit is turned off.
  • the rise time of the corresponding output signal G_out of the GOA unit is centered; in the third case, the switch in the level shift unit is closed, and the rise time of the corresponding output signal G_out of the GOA unit is short.
  • the rise time of the corresponding output signal G_out of the GOA in the case where the first case and the third case are combined should be substantially the same as the rise time of the corresponding output signal G_out of the GOA in the second case, thereby solving the above-mentioned long level
  • the blank line caused by the blanking time shows a problem of darkness.
  • a display device including the above-described gate driving circuit is disclosed.
  • the display device here can be: electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator and the like with any display product or component.
  • the level shifter, the gate driving circuit, and the display device of the embodiments of the present disclosure it is possible to solve the problem that the partial display of the screen is dark due to the long horizontal blanking time, thereby improving the picture quality.

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  • General Engineering & Computer Science (AREA)
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  • Crystallography & Structural Chemistry (AREA)
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Abstract

一种电平转换器及其操作方法、栅极驱动电路和显示装置。该电平转换器（100）包含：N个输入端，用于接收N路输入信号（input(1)-input(N)）；N个控制信号端，用于接收N路控制信号（LHB(1)-LHB(N)）；N个输出端，用于输出N路输出信号（output(1)-output(N)）；电平转换单元（10），连接N个输入端、N个控制信号端和N个输出端，用于根据控制信号端的第n路控制信号（LHB(n)），来确定将第n路输入信号（input(n)）直接作为第n路输出信号（output(n)）进行输出，或是将第n路输入信号（input(n)）进行转换后再作为第n路输出信号（output(n)）进行输出；其中转换是将具有较快上升时间的第n路输入信号转换为具有较慢上升时间的第n路输出信号，并且N为正整数，1≤n≤N。该电平转换器解决了由于长水平消隐时间导致的画面部分行显示偏暗的问题。

Description

电平转换器及其操作方法、栅极驱动电路和显示装置 技术领域
本公开涉及一种电平转换器及其操作方法、栅极驱动电路和显示装置。
背景技术
随着显示技术的急速进步，具有触控功能的显示装置由于其所具有的可视化操作等优点而逐渐受到越来越多人们的欢迎。根据触控面板与显示面板相对位置的不同，一般可以将现有的具有触控功能的显示装置分为表面式(on cell)触控面板与内嵌式(in cell)触控面板两种。与表面式触控面板相比，内嵌式触控面板具有更薄的厚度与更高的光透过率。
发明内容
本公开提出一种电平转换器及其操作方法、栅极驱动电路和显示装置，可以解决由于长水平消隐时间导致的画面部分行显示偏暗的问题。
根据本公开的一方面，公开了一种电平转换器，包含：
N个输入端，用于接收N路输入信号；
N个控制信号端，用于接收N路控制信号；
N个输出端，用于输出N路输出信号；以及
电平转换单元，连接N个输入端、N个控制信号端和N个输出端，用于根据控制信号端的第n路控制信号，来确定将第n路输入信号直接作为第n路输出信号进行输出，或是将第n路输入信号进行转换后再作为第n路输出信号进行输出；
其中所述转换是将具有较快上升时间的第n路输入信号转换为具有较慢上升时间的第n路输出信号，并且N为正整数，1≤n≤N。
例如，在第n路控制信号等于n时，将第n路输入信号直接作为第n路输出信号进行输出；否则，进行所述转换。
例如，电平转换单元包括第一至第N电阻和第一至第N开关，其中，第n电阻和第n开关并联，第n电阻和第n开关的一端连接第n路输入信号， 第n电阻和第n开关的另一端连接第n路输出信号。
例如，在第n路控制信号等于n时，第n开关导通；否则，第n开关保持断开。
例如，所述开关是薄膜晶体管。
例如，N＝6。
根据本公开的另一方面，公开了一种栅极驱动电路，包括多个级联的GOA单元，每N个GOA单元为一组，每组中的GOA单元分别接收第一至第N时钟信号，其中上述电平转换器的N路输出信号被提供作为该第一至第N时钟信号。
例如，N个控制信号端接收来自时序控制器的N路控制信号。
例如，用时序控制器检测下一GOA单元的输出行，在检测到下一GOA单元的输出行为第NLHB+1行或第NLHB+2行或第NLHB+3行，并且下一GOA单元接收第n时钟信号时，则时序控制器输出等于n的第n路控制信号，其中在第NLHB行充电结束后开启长水平消隐时间。
根据本公开的又一方面，公开了一种包含上述栅极驱动电路的显示装置。
根据本公开的再一方面，公开了一种上述电平转换器的操作方法，包含：
由N个输入端分别接收N路输入信号；
由N个控制信号端分别接收N路控制信号；
由电平转换单元根据控制信号端的第n路控制信号，来确定将第n路输入信号直接作为第n路输出信号进行输出，或是将第n路输入信号进行转换后再作为第n路输出信号进行输出；以及
由N个输出端分别输出N路输出信号；
其中所述转换是将具有较快上升时间的第n路输入信号转换为具有较慢上升时间的第n路输出信号，并且N为正整数，1≤n≤N。
根据本公开实施例的电平转换器、栅极驱动电路和显示装置，可以解决由于长水平消隐时间导致的画面部分行显示偏暗的问题，从而提升画面品质。
附图说明
图1是一种GOA单元的电路图；
图2是图1的GOA单元的操作时序图；
图3是由图1中的GOA单元级联形成的栅极驱动电路中各信号的时序图；
图4是根据本公开一个实施例的电平转换器的示意结构图；
图5是根据本公开一个实施例的电平转换器中的电平转换单元的电路图；
图6是在上述栅极驱动电路中利用时序控制器来控制上述电平转换单元的方法的流程图；
图7是在上拉节点处电压下降、电平转换单元中开关断开、电平转换单元中开关闭合三种情况下GOA单元的对应输出信号的效果图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本实施例中，每个晶体管的漏极和源极的连接方式可以互换，因此，本公开实施例中各晶体管的漏极、源极实际是没有区别的。这里，仅仅是为了区分晶体管除栅极之外的两极，而将其中一极称为漏极，另一极称为源极。
申请人注意到，在基于GOA单元的内嵌式触控技术中，由于存在长水平消隐(Long-H Blank，简称LHB)时间以等待触控动作完成，因此，在此LHB期间，后续GOA单元对相应行的像素充电时间缩短，导致画面部分行显示偏暗。
本公开提出一种电平转换器、栅极驱动电路和显示装置，可以解决上述由于长水平消隐时间导致的画面部分行显示偏暗的问题。
图1是一种GOA单元的电路图。图2是图1的GOA单元的操作时序图。如图1所示，该GOA单元包含第一至第十二晶体管M1-M12以及第一电容C1。下面结合图1和图2对图1中的GOA单元的操作方法进行说明。
下面以图1中的晶体管均为N型晶体管为例进行说明。
在第一阶段(输入阶段)1，输入端INPUT处于高电平，输入晶体管M1导通，将输入端INPUT的高电平传递到上拉节点PU，此时上拉节点PU处于第一高电压，使得输出晶体管M3导通，由于第一时钟信号端CLK的第一时钟信号处于低电平，输出端OUTPUT输出低电平。此外，在该阶段中，由于上拉节点PU处于高电平，第一下拉控制晶体管M6和第二下拉控制晶体管M7导通，使得下拉节点PD处于低电平，相应地节点下拉晶体管M9和输出下拉晶体管M10均截止。此外，在该阶段中，复位信号端RESET的复位信号处于低电平，节点复位晶体管M2截止。
在第二阶段(输出阶段)2，输入端INPUT处于低电平，输入晶体管M1截止，复位信号端RESET处于低电平，节点复位晶体管M2保持截止，上拉节点PU继续使得输出晶体管M3导通，第一时钟信号端CLK的第一时钟信号处于高电平，输出端OUTPUT输出高电平，由于第一电容C1的电压耦合作用，此时上拉节点PU被从第一高电压抬升到第二高电压。此外，在该阶段中，由于上拉节点PU仍处于高电平，第一下拉控制晶体管M6和第二下拉控制晶体管M7保持导通，下拉节点PD仍处于低电平，相应地节点下拉晶体管M9和输出下拉晶体管M10均保持截止。
在第三阶段(复位阶段)3，输入端INPUT处于低电平，输入晶体管M1保持截止，复位信号端RESET的复位信号处于高电平，节点复位晶体管M2和输出复位晶体管M4导通，分别将上拉节点PU处的上拉信号和输出端OUTPUT的输出信号下拉至第一电源电压端VSS的电源电压。此外，在该阶段中，由于上拉节点PU处于低电平，第一下拉控制晶体管M6和第二下拉控制晶体管M7均截止，由于第二时钟信号端CLKB的第二时钟信号处于高电平，第三下拉控制晶体管M5和第四下拉控制晶体管M8均导通，使得下拉节点PD从低电平跳变至高电平，相应地节点下拉晶体管M9和输出下拉晶体管M10均导通，将上拉节点PU处的上拉信号和输出端OUTPUT的输出信号下拉至第一电源电压端VSS的电源电压。
在第四阶段(保持阶段)4，第二时钟信号端CLKB的第二时钟信号处于低电平，第三下拉控制晶体管M5和第四下拉控制晶体管M8均截止，由于上拉节点PU处于低电平，第一下拉控制晶体管M6和第二下拉控制晶体管M7均保持截止。下拉节点PD的电压处于高电平，相应地节点下拉晶体 管M9和输出下拉晶体管M10均导通，将上拉节点PU和输出端OUTPUT保持下拉至第一电源电压端VSS的电源电压。
第一电源电压端VSS是低电源电压端。
此后，在下一帧到来之前，上拉节点PU一直处于低电平，下拉节点PD一直处于高电平，输出端OUTPUT一直输出低压信号。直至下一帧到来，所述GOA单元收到输入端INPUT的高电平信号后，重新执行上述第一阶段。
由图2可以看出，第一时钟信号端CLK的第一时钟信号与第二时钟信号端CLKB的第二时钟信号反相。
图3是由图1中的GOA单元级联形成的栅极驱动电路中各信号的时序图。在图3的示例中，每6个GOA单元为一组，图3示出了该6个GOA单元的各自的时钟信号CLK1-CLK6、6个GOA单元中的第一个输入的起始输入信号STV以及控制是否进行触控的信号SW的时序。应注意，虽然本公开以栅极驱动电路中6个GOA单元为一组作为示例，然而，栅极驱动电路中实际上可以以任意N个GOA单元级联为一组，并且包含多个这样的组。
在图3的示例中，该多个GOA单元中的第一个GOA单元的输入端接收第一帧起始信号STV。第二至第三GOA单元的输入端分别接收第二至第三帧起始信号(未示出)。第四至第六GOA单元的输入端分别接收第一至第三GOA单元的输出信号。第一至第六GOA单元的第一时钟信号端分别接收第一至第六时钟信号CLK1-CLK6。根据先前的描述，可以知道，第一至第六GOA单元的输出信号分别与第一至第六时钟信号CLK1-CLK6相对应。SW信号控制是否进行触控。
下面结合图1和图3进行说明。在上述栅极驱动电路中，存在长水平消隐时间，等待触控动作完成，在此期间，GOA单元关闭以等待触控动作完成。假设第NLHB行充电结束后开启长水平消隐时间，则第NLHB+1、NLHB+2、NLHB+3行对应的GOA单元的输入信号已经有效，这些GOA单元的上拉节点PU处的电压拉高，但是在长水平消隐时间内，因为漏电流的存在，上拉节点PU处的电压会下降，导致输出晶体管M3开启程度不足，在第一时钟信号端CLK的第一时钟信号处于高电平时，会由于输出晶体管M3充电能力不足，导致NLHB+1、NLHB+2、NLHB+3行对应的GOA单元的输出端OUTPUT的输出信号上升时间增长，从而导致对NLHB+1、NLHB+2、NLHB+3行的像素 的充电时间缩短，对应此三行的画面显示效果就会偏暗。
本公开提出一种电平转换器、栅极驱动电路和显示装置，可以相对于非LHB时间下的GOA单元，提升LHB时间下的GOA单元在上拉节点PU处电压下降后的充电时间，改善由于上拉节点PU处电压下降导致的画面部分行显示偏暗，从而提升画面品质。
图4是根据本公开一个实施例的电平转换器的示意图。如图4所示，该电平转换器100包含：N个输入端，用于接收N路输入信号input(1)-input(N)；N个控制信号端，用于接收N路控制信号LHB(1)-LHB(N)；N个输出端，用于输出N路输出信号output(1)-output(N)；以及电平转换单元10，连接N个输入端、N个控制信号端和N个输出端，用于根据控制信号端的第n路控制信号LHB(n)，来确定将第n路输入信号input(n)直接作为第n路输出信号output(n)进行输出，或是将第n路输入信号input(n)进行转换后再作为第n路输出信号output(n)进行输出。
其中所述转换是将具有较快上升时间的第n路输入信号input(n)转换为具有较慢上升时间的第n路输出信号output(n)，并且N为正整数，1≤n≤N。
在一个实施例中，例如，在第n路控制信号LHB(n)等于n时，将第n路输入信号input(n)直接作为第n路输出信号output(n)进行输出；否则，进行所述转换。例如，在LHB(2)＝2时，将第2路输入信号input(2)直接作为第2路输出信号output(2)进行输出。
在一个实施例中，例如，上述N路控制信号LHB(1)-LHB(N)可以来自时序控制器20。
图5是根据本公开一个实施例的电平转换器100中的电平转换单元10的电路图。如图5所示，该电平转换单元包括第一至第N电阻和第一至第N开关。对于1≤n≤N，第n电阻Rn和第n开关Sn并联，第n电阻Rn和第n开关Sn的一端连接第n路输入信号input(n)，第n电阻Rn和第n开关Sn的另一端连接第n路输出信号output(n)。
在一个实施例中，例如，在第n路控制信号LHB(n)等于n时，第n开关Sn导通；否则，第n开关Sn保持断开。例如，在LHB(2)＝2时，第2开关S2导通；在LHB(2)≠2时，第2开关S2保持断开。
在一个实施例中，例如，上述开关是薄膜晶体管。
在一个实施例中，例如，N＝6。在这种情况下，采用上述电平转换单元的电平转换器可以用于提供时钟信号给结合图1和图3讨论的栅极驱动电路。
能够理解，图5中所示出的电平转换单元10的具体电路结构仅仅是一种示例，其也可以采用其他适当的电路结构，只要能实现其功能即可，本发明对此不做限制。
根据本公开的另一方面，公开了一种上述电平转换器100的操作方法，包含：
由N个输入端分别接收N路输入信号input(1)-input(N)；
由N个控制信号端分别接收N路控制信号LHB(1)-LHB(N)；
由电平转换单元10根据控制信号端的第n路控制信号LHB(n)，来确定将第n路输入信号input(n)直接作为第n路输出信号output(n)进行输出，或是将第n路输入信号input(n)进行转换后再作为第n路输出信号output(n)进行输出；以及
由N个输出端分别输出N路输出信号output(1)-output(N)；
其中所述转换是将具有较快上升时间的第n路输入信号input(n)转换为具有较慢上升时间的第n路输出信号output(n)，并且N为正整数，1≤n≤N。
根据本公开的又一方面，公开了一种栅极驱动电路，包括多个级联的GOA单元，每N个GOA单元为一组，每组中的GOA单元分别接收第一至第N时钟信号，上述电平转换器100的N路输出信号被提供作为该第一至第N时钟信号，N为正整数。
在一个实施例中，例如，N个控制信号端接收来自时序控制器20的N路控制信号。
在一个实施例中，例如，用时序控制器20检测下一GOA单元的输出行，在检测到下一GOA单元的输出行为第NLHB+1行或第NLHB+2行或第NLHB+3行、并且下一GOA单元接收第n时钟信号时，则时序控制器输出等于n的第n路控制信号LHB(n)，其中在第NLHB行充电结束后开启长水平消隐时间。NLHB可以由用户进行设定。
例如，N＝6。
图6是在上述栅极驱动电路中利用时序控制器来控制上述电平转换单元的方法的流程图。下面以N＝6为例进行说明。在这种情况下，采用上述电平 转换单元的电平转换器可以用于提供时钟信号给结合图1和图3讨论的栅极驱动电路。
一般地，方法200开始于步骤S201并在步骤S205结束。
GOA单元的当前行(记为第n行)的输出端OUTPUT的输出信号为第n+3行的GOA单元的输入信号。在步骤S202，用时序控制器20检测下一GOA单元的输出行。如果在步骤S202检测到下一GOA单元的输出行不是第NLHB+1、第NLHB+2行或第NLHB+3行中的任一个，则方法返回到步骤S201。如果在步骤S202检测到下一GOA单元的输出行为第NLHB+1行、第NLHB+2行或第NLHB+3行中的任一个、并且下一GOA单元接收第n时钟信号，则在步骤S203，则时序控制器20输出等于n的第n路控制信号LHB(n)，即LHB(n)＝n(1≤n≤6)的控制信号给电平转换单元10。在步骤S204，电平转换单元接收LHB(n)＝n的控制信号之后，第n输入端input(n)对应的开关Sn闭合，电阻Rn短路。如本领域技术人员所理解的，控制信号，例如方波信号，经过开关之后的输出信号的上升时间相较于经过电阻之后的输出信号的上升时间缩短。因此，在上述示例中，该行输出信号output(n)的上升时间相对较短，即，对于对应的GOA单元，其接收的第一时钟信号的上升时间相对较短，从而使得该GOA单元的输出信号的上升时间缩短。而由于该GOA单元的上拉节点PU处电压因为漏电流的存在而下降，导致输出晶体管M3开启程度不足，因此使得该GOA单元的输出信号的上升时间变长。这两种效果相互抵消，从而使得该GOA单元的输出信号的上升时间和其它行对应的GOA单元的输出信号的上升时间一致，从而使NLHB+1、NLHB+2、NLHB+3行对应的GOA单元的输出信号也与其它行对应的GOA单元的输出信号保持一致，从而改善NLHB+1、NLHB+2、NLHB+3行三行画面显示偏暗的问题，提升画面品质。
图7是在上拉节点PU处电压下降、电平转换单元中开关断开、电平转换单元中开关闭合三种情况下GOA单元的对应输出信号G_out的效果图。如图7所示，在第一种情况下，上拉节点PU处电压下降，GOA单元的对应输出信号G_out的上升时间较长；在第二种情况下，电平转换单元中开关断开，GOA单元的对应输出信号G_out的上升时间居中；在第三种情况下，电平转换单元中开关闭合，GOA单元的对应输出信号G_out的上升时间较短。 上述第一种情况和第三种情况结合的情形下的GOA的对应输出信号G_out的上升时间应与第二种情况下的GOA的对应输出信号G_out的上升时间大致一致，从而解决上述由于长水平消隐时间导致的画面部分行显示偏暗的问题。
根据本公开的再一方面，公开了一种包含上述栅极驱动电路的显示装置。
这里的显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
根据本公开实施例的电平转换器、栅极驱动电路和显示装置，可以解决由于长水平消隐时间导致的画面部分行显示偏暗的问题，从而提升画面品质。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年7月29日递交的中国专利申请第201610615583.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (11)

  1. 一种电平转换器，包含：
    N个输入端，用于接收N路输入信号；
    N个控制信号端，用于接收N路控制信号；
    N个输出端，用于输出N路输出信号；以及
    电平转换单元，连接N个输入端、N个控制信号端和N个输出端，用于根据控制信号端的第n路控制信号，来确定将第n路输入信号直接作为第n路输出信号进行输出，或是将第n路输入信号进行转换后再作为第n路输出信号进行输出；
    其中所述转换是将具有较快上升时间的第n路输入信号转换为具有较慢上升时间的第n路输出信号，并且N为正整数，1≤n≤N。
  2. 根据权利要求1所述的电平转换器，其中，在第n路控制信号等于n时，将第n路输入信号直接作为第n路输出信号进行输出；否则，进行所述转换。
  3. 根据权利要求1或2所述的电平转换器，电平转换单元包括第一至第N电阻和第一至第N开关，
    其中，第n电阻和第n开关并联，第n电阻和第n开关的一端连接第n路输入信号，第n电阻和第n开关的另一端连接第n路输出信号。
  4. 根据权利要求3所述的电平转换器，在第n路控制信号等于n时，第n开关导通；否则，第n开关保持断开。
  5. 根据权利要求3所述的电平转换器，其中，所述开关是薄膜晶体管。
  6. 根据权利要求1-5中任一项所述的电平转换器，其中，N＝6。
  7. 一种栅极驱动电路，包括多个级联的GOA单元，每N个GOA单元为一组，每组中的GOA单元分别用于接收第一至第N时钟信号，其中根据权利要求1-6任一项所述的电平转换器的N路输出信号被提供作为该第一至第N时钟信号。
  8. 根据权利要求7所述的栅极驱动电路，其中，N个控制信号端接收来自时序控制器的N路控制信号。
  9. 根据权利要求8所述的栅极驱动电路，其中，时序控制器被配置为检 测下一GOA单元的输出行，在检测到下一GOA单元的输出行为第NLHB+1行或第NLHB+2行或第NLHB+3行，并且下一GOA单元接收第n时钟信号时，则时序控制器输出等于n的第n路控制信号，其中在第NLHB行充电结束后开启长水平消隐时间。
  10. 一种显示装置，包含根据权利要求7-9任一项所述的栅极驱动电路。
  11. 一种根据权利要求1所述的电平转换器的操作方法，包含：
    由N个输入端分别接收N路输入信号；
    由N个控制信号端分别接收N路控制信号；
    由电平转换单元根据控制信号端的第n路控制信号，来确定将第n路输入信号直接作为第n路输出信号进行输出，或是将第n路输入信号进行转换后再作为第n路输出信号进行输出；以及
    由N个输出端分别输出N路输出信号；
    其中所述转换是将具有较快上升时间的第n路输入信号转换为具有较慢上升时间的第n路输出信号，并且N为正整数，1≤n≤N。
PCT/CN2017/074529 2016-07-29 2017-02-23 电平转换器及其操作方法、栅极驱动电路和显示装置 WO2018018887A1 (zh)

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