WO2018018855A1 - 一种液晶显示面板及制作方法 - Google Patents

一种液晶显示面板及制作方法 Download PDF

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WO2018018855A1
WO2018018855A1 PCT/CN2017/070896 CN2017070896W WO2018018855A1 WO 2018018855 A1 WO2018018855 A1 WO 2018018855A1 CN 2017070896 W CN2017070896 W CN 2017070896W WO 2018018855 A1 WO2018018855 A1 WO 2018018855A1
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layer
film
film formation
forming
active layer
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French (fr)
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吕晓文
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/329,323 priority Critical patent/US10211346B2/en
Publication of WO2018018855A1 publication Critical patent/WO2018018855A1/zh
Priority to US16/238,496 priority patent/US20190140107A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6706—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing leakage current 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/57—Physical imperfections the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices

Definitions

  • the present invention belongs to the field of liquid crystal display technology, and in particular, to a liquid crystal display panel and a manufacturing method thereof.
  • the BCE (B represents the base, C represents the collector, and E represents the emitter) transistor structure.
  • the active layer generally adopts the AL/AH structure.
  • AL is the main conductive channel, which is formed by low-speed film formation to ensure good film quality and less interface defects.
  • AH uses high-speed film formation and interface defects.
  • Vg is a small negative voltage, that is, when the transistor is in the negative sub-threshold region of conduction, a small conductive path is formed at the back channel, causing back channel leakage.
  • the turn-off voltage of the TFT-LCD device is also generally set near the negative subthreshold region.
  • the poor uniformity of AH deposition and many defects it is easily affected by subsequent processes, which causes high leakage current at the back channel and is relatively discrete, resulting in uneven brightness display and signal tolerance.
  • the device subthreshold region I-V represents the region shown in Figure 1, which is primarily affected by the interface characteristics of the device back channel and the back channel and passivation layer PV.
  • the present invention provides a liquid crystal display panel and a method of fabricating the same.
  • a liquid crystal display panel including a thin film transistor, wherein
  • the active layer for connecting the drain of the thin film transistor source is composed of more than two film forming layers, and the contact of the active layer with the passivation layer of the panel is a non-high speed film forming layer in the active layer.
  • the active layer comprises three film forming layers.
  • the second film forming layer is disposed between the first film forming layer and the third film forming layer, wherein
  • the first film formation layer is a low speed film formation layer
  • the third film formation layer is a high speed film formation layer
  • the film formation speed of the second film formation layer is between the film formation speed of the first film formation layer and the formation of the third film formation layer. Between film speeds.
  • the contact of the active layer with the passivation layer is a second film formation layer of the active layer.
  • a sum of thicknesses of the first film forming layer and the second film forming layer is 1/3 of an overall thickness of the active layer.
  • a method for fabricating a liquid crystal display panel including:
  • a passivation layer is formed on the source and the drain of the thin film transistor, and the contact of the active layer and the passivation layer is a non-high speed film formation layer in the active layer.
  • the active layer comprises three film forming layers.
  • the method when the active layer is formed, the method includes:
  • the first film forming layer is a low speed film forming layer
  • the third film forming layer is a high speed film forming layer
  • the film forming speed of the second film forming layer is between the film forming speed of the first film forming layer Between the film formation speed of the third film formation layer.
  • the contact between the active layer and the passivation layer is the first of the active layer Two film layers.
  • a sum of thicknesses of the first film forming layer and the second film forming layer is 1/3 of an overall thickness of the active layer.
  • the present invention converts the currently used active layer AS from the two-layer structure of the high-speed film-forming layer AH and the low-speed film-forming layer AL to the current AL1/AL2/AH three-layer structure, and ensures that the total thickness of AL1/AL2 is greater than
  • the thickness of the source layer AS conductive layer is such that the active layer at the PV interface of the back channel and the passivation layer is AL2.
  • the AL2 film formation rate is higher than AL1 and lower than AH, and the film quality and interface state density are better than AH, so that the liquid crystal display panel of the present invention has better back channel characteristics and leakage is lower.
  • FIG. 1 is a schematic view showing a sub-threshold area I-V display of a liquid crystal display device in the prior art
  • FIG. 2 is a schematic cross-sectional view showing a back channel of a liquid crystal display panel in the prior art
  • FIG. 3 is a cross-sectional view showing a back channel of a liquid crystal display panel according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram showing leakage current display at different points in the back channel of the same liquid crystal display panel in the prior art
  • Fig. 5 is a schematic view showing leakage current display at different points in the back channel of the liquid crystal display panel of the present invention.
  • the active layer AS on the liquid crystal display panel that communicates with the source and drain of the thin film transistor is generally composed of a two-layer structure of a high-speed film-forming AH layer and a low-speed film-forming AL layer.
  • a gate electrode M1 is formed on a substrate; a gate insulating layer GI is formed on the gate electrode M1; and an active layer AS is formed on the gate insulating layer GI, where the active layer includes a gate electrode formed thereon.
  • the source S and the drain D; a passivation layer PV is formed on the source S and the drain D of the thin film transistor.
  • the passivation layer PV is in contact with the high-speed film-forming layer AH layer of the active layer AS, and the AH layer film quality and the interface state density are lower than those of the AL layer due to the high deposition rate of the AH layer.
  • This will result in poor uniformity of the AH layer and more defects, resulting in a large leakage current in the back channel.
  • the film formation rate in the high-speed film-forming AH layer and the low-speed film-forming layer AL is relatively high, that is, the film formation rate of the high-speed film-forming AH layer is higher than that of the low-speed film-forming layer AL.
  • the film forming speed of the high-speed film-forming AH layer is a high-speed film forming speed which is common in the prior art
  • the film forming speed of the low-speed film forming AL layer is a general low-speed film forming speed in the prior art.
  • the present invention provides a liquid crystal display panel including a thin film transistor, wherein an active layer for connecting a source and a drain of a thin film transistor is composed of more than two film forming layers, and The contact of the source layer with the passivation layer on the panel is a non-high speed film forming layer of the active layer.
  • the film quality and interface state density at the contact of the passivation layer with the active layer can be made better than that of the AH layer, so that the back channel has better characteristics and the back channel leakage is reduced.
  • the liquid crystal display panel has a gate electrode M1 formed on the substrate; a gate insulating layer GI formed on the gate electrode M1; and an active layer AS formed on the gate insulating layer GI, where the active layer is formed.
  • the first low-speed film formation layer AL1 formed on the gate insulating layer GI1, the second film formation layer formed on the first low-speed film formation layer AL1 (corresponding to the first film formation layer), and the second film formation layer AL2 are formed.
  • a high-speed film formation layer AH (corresponding to a third film formation layer) on the second film formation layer; an ohmic contact layer N+ formed on the high speed film formation layer AH; and a source of a thin film transistor formed on the ohmic contact layer N+ a terminal S and a drain D; a passivation layer PV is formed on the source S and the drain D of the thin film transistor.
  • FIG. 3 of the present invention includes three film forming layers, including the high speed film forming AH layer and the low speed film forming AL layer (corresponding to the first low speed in the prior art).
  • a second film formation layer AL2 is disposed between the high speed film formation AH layer and the first low speed film formation AL1 layer.
  • the film formation rate of the second film formation layer AL2 is higher than AL1 and lower than AH, and its film quality and interface state density are better than AH, which has better back channel characteristics, lower leakage current, and more CVD film formation. To be even.
  • the contact of the active layer with the passivation layer is the second film formation layer of the active layer.
  • the PV channel of the back channel and the passivation layer is set as the second film formation layer AL2, and the film quality and interface state density of the second film formation layer are better than AH, and the back groove is better. Channel characteristics, thus reducing back-channel leakage current.
  • the thickness of the first low-speed film-forming layer AL1 (first film-forming layer) and the second film-forming layer AL2 And set to 1/3 of the overall thickness of the active layer.
  • the present invention converts the currently used active layer AS from the two-layer structure of the high-speed film-forming layer AH and the low-speed film-forming layer AL to the current AL1/AL2/AH three-layer structure, and ensures that the total thickness of AL1/AL2 is greater than
  • the thickness of the conductive layer of the source layer AS is such that the active layer at the PV interface of the back channel and the passivation layer is AL2, because the film formation rate of AL2 is higher than that of AL1 and lower than AH, and the film quality and interface state density are better than AH.
  • the present invention has better back channel characteristics and lower leakage current.
  • FIG. 4 is a schematic diagram of leakage currents of three different positions of an active layer using a two-layer structure film formation layer of the prior art. As can be seen from the figure, some dot leakage current Ioff of the back channel is relatively high and discrete, uniform. Bad sex.
  • FIG. 5 is a schematic diagram of leakage currents at three different positions of the active layer of the present invention. As can be seen from the figure, the electrical uniformity at the back channel is good, and the leakage current Ioff has no significant high point. . As can be seen from FIG. 5, the present invention improves the uniformity of the device while reducing the back channel leakage current Ioff.
  • a method of fabricating a liquid crystal display panel includes: forming a gate M1 on a substrate; forming a gate insulating layer GI on the gate M1; and forming a gate insulating layer GI
  • the active layer AS where the active layer includes a first low-speed film-forming layer AL1 formed on the gate insulating layer GI1, and a second layer formed on the first low-speed film-forming layer AL1 (corresponding to the first film-forming layer) a film layer and a high speed film forming layer AH formed on the second film forming layer AL2 (corresponding to the second film forming layer) (corresponding to the third film forming layer); an ohmic contact layer N+ is formed on the high speed film forming layer AH; A source S and a drain D of the thin film transistor are formed on the ohmic contact layer N+; a passivation layer PV is formed on the source S and the drain D of the thin film transistor, and the contact between the active layer and the passivation layer is
  • the active layer comprises three film forming layers.
  • the method further includes the steps of: forming a first film forming layer on the gate insulating layer; forming a second film forming layer on the first film forming layer; A third film forming layer is formed on the second film forming layer, wherein the first film forming layer is a low speed film forming layer, the third film forming layer is a high speed film forming layer, and the film forming speed of the second film forming layer is between the first film forming layer Between the speed of the film layer and the third film forming layer.
  • the contact of the active layer with the passivation layer is the second film formation layer of the active layer.
  • the sum of the thicknesses of the first film forming layer and the second film forming layer is set to be 1/3 of the entire thickness of the active layer.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

一种液晶显示面板及制作方法，该液晶显示面板包括薄膜晶体管，其中，用于连接薄膜晶体管源漏极（S，D）的有源层（AS）由多于2个的成膜层构成，并且有源层（AS）与面板上的钝化层（PV）的接触处为有源层（AS）中的非高速成膜层（AL1，AL2）。

Description

一种液晶显示面板及制作方法
相关申请的交叉引用
本申请要求享有2016年07月29日提交的名称为“一种液晶显示面板及制作方法”的中国专利申请CN201610613722.3的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明属于液晶显示技术领域，具体地说，尤其涉及一种液晶显示面板及制作方法。
背景技术
近年来，大尺寸、高解析度的电视受到越来越多商家和消费者的青睐。随着显示器尺寸越来越大，在保证开启电流Ion和阈值电压Vth的基础上，显示器的电容保持效果也越来越重要。由于液晶显示器件大部分时间都工作在关态，所以漏电流对器件显示性能的影响很大。
一般BCE(B表示基极，C表示集电极，E表示发射极)晶体管结构，沟道做完以后，后续还有沉积金属等很多制程，这些后续制程会对背沟道特性产生影响。有源层一般都采用AL/AH结构，其中，AL是主要导电通道，采用低速成膜，用以以保证良好的薄膜品质，较少的界面缺陷；AH使用的是高速成膜，界面缺陷较多，在背沟道有很多的界面态。当栅极电压Vg为一小的负电压时，也就是晶体管处于导电的负亚阈值区时，在背沟道处会形成一小的导电通道，造成背沟道漏电。同时，TFT-LCD器件的关断电压一般也设定在负亚阈值区附近。并且，由于AH沉积均一性较差且缺陷较多，很容易受后续制程影响，会造成背沟道处漏电流较高且较为离散，导致亮度显示不均、信耐性等问题。
因此，提高背沟道均一性，改善背沟道处有源层的界面特性，对显示器性能提升的意义重大。器件亚阈值区I-V表现如图1标注所示的区域，其主要受器件背沟道及背沟道和钝化层PV的界面特性影响。
发明内容
为解决以上问题，本发明提供了一种液晶显示面板及制作方法。
根据本发明的一个方面，提供了一种液晶显示面板，包括薄膜晶体管，其中，
用于连通薄膜晶体管源漏极的有源层由多于2个的成膜层构成，并且有源层与所述面板的钝化层的接触处为有源层中的非高速成膜层。
根据本发明的一个实施例，所述有源层包括3个成膜层。
根据本发明的一个实施例，第二成膜层设置于第一成膜层和第三成膜层之间，其中，
第一成膜层为低速成膜层，第三成膜层为高速成膜层，第二成膜层的成膜速度介于第一成膜层的成膜速度和第三成膜层的成膜速度之间。
根据本发明的一个实施例，所述有源层与钝化层的接触处为有源层的第二成膜层。
根据本发明的一个实施例，所述第一成膜层和所述第二成膜层的厚度之和为所述有源层整体厚度的1/3。
根据本发明的另一个方面，还提供了一种液晶显示面板制作方法，包括：
在基底上形成栅极；
在栅极上形成栅绝缘层；
在栅绝缘层上形成有源层，其中，所述有源层由多于2个的成膜层构成；
在有源层上形成欧姆接触层；
在欧姆接触层上形成薄膜晶体管的源极和漏极；
在薄膜晶体管的源极和漏极上形成有钝化层，所述有源层与所述钝化层的接触处为有源层中的非高速成膜层。
根据本发明的一个实施例，所述有源层包括3个成膜层。
根据本发明的一个实施例，在形成所述有源层时包括：
在栅绝缘层上形成第一成膜层；
在第一成膜层上形成第二成膜层；
在第二成膜层上形成第三成膜层，
其中，所述第一成膜层为低速成膜层，所述第三成膜层为高速成膜层，所述第二成膜层的成膜速度介于第一成膜层的成膜速度和第三成膜层的成膜速度之间。
根据本发明的一个实施例，所述有源层与所述钝化层的接触处为有源层的第 二成膜层。
根据本发明的一个实施例，所述第一成膜层和所述第二成膜层的厚度之和为所述有源层整体厚度的1/3。
本发明的有益效果：
本发明将目前常用的有源层AS由高速成膜层AH和低速成膜层AL的两层结构，改为目前的AL1/AL2/AH三层结构，并且保证AL1/AL2的总厚度大于有源层AS导电层厚度，以保证背沟道和钝化层PV界面处的有源层为AL2。AL2成膜速度高于AL1低于AH，膜质及界面态密度均优于AH，从而使得本发明的液晶显示面板具有更好的背沟道特性，漏电会更低。
本发明的其他优点、目标，和特征在某种程度上将在随后的说明书中进行阐述，并且在某种程度上，基于对下文的考察研究对本领域技术人员而言将是显而易见的，或者可以从本发明的实践中得到教导。本发明的目标和其他优点可以通过下面的说明书，权利要求书，以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请的技术方案或现有技术的进一步理解，并且构成说明书的一部分。其中，表达本申请实施例的附图与本申请的实施例一起用于解释本申请的技术方案，但并不构成对本申请技术方案的限制。
图1是现有技术中液晶显示器件亚阈值区I-V显示示意图；
图2是现有技术中一种液晶显示面板背沟道处的剖面示意图；
图3是根据本发明的一个实施例的液晶显示面板背沟道处的剖面示意图；
图4是现有技术中同一液晶显示面板背沟道不同点位的漏电流显示示意图；
图5是采用本发明的液晶显示面板背沟道不同点位的漏电流显示示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成相应技术效果的实现过程能充分理解并据以实施。本申请实施例以及实施例中的各个特征，在不相冲突前提下可以相互结合，所形成的技术方案均在本发明的保护范围之内。
目前，液晶显示面板上连通薄膜晶体管源漏极的有源层AS通常由高速成膜AH层和低速成膜AL层两层结构构成。如图2所示，在基底上形成有栅极M1；在栅极M1上形成有栅绝缘层GI；在栅绝缘层GI上形成有有源层AS，此处的有源层包括形成于栅绝缘层GI上的低速成膜层AL和形成于低速成膜层AL上的高速成膜层AH；在高速成膜层AH上形成有欧姆接触层N+；在欧姆接触层N+上形成有薄膜晶体管的源极S和漏极D；在薄膜晶体管的源极S和漏极D上形成有钝化层PV。
由图2可知，钝化层PV与有源层AS的高速成膜层AH层接触，由于AH层成膜速度高，形成的AH层膜质及界面态密度较AL层差。这就会造成AH层均一性较差，缺陷较多，造成背沟道漏电流较大。此处的高速成膜AH层和低速成膜AL层中的成膜速度是相对而言的，即高速成膜AH层的成膜速度大于低速成膜AL层的成膜速度。在本发明中，高速成膜AH层的成膜速度采用现有技术中通用的高速成膜速度，低速成膜AL层的成膜速度采用现有技术中的通用的低速成膜速度。
为解决以上问题，本发明提供了一种液晶显示面板，该液晶显示面板包括薄膜晶体管，其中，用于连通薄膜晶体管源漏极的有源层由多于2个的成膜层构成，并且有源层与面板上的钝化层的接触处为有源层的非高速成膜层。这样，可以使得钝化层与有源层接触处的膜质及界面态密度优于AH层，从而使得背沟道具有更好的特性，背沟道漏电会降低。
如图3所示为根据本发明的一个实施例的液晶显示面板背沟道处的剖面结构示意图，该图中的有源层包括3个成膜层，以下参考图3来对本发明进行详细说明。如图3所示，该液晶显示面板在基底上形成有栅极M1；在栅极M1上形成有栅绝缘层GI；在栅绝缘层GI上形成有有源层AS，此处的有源层包括形成于栅绝缘层GI上的第一低速成膜层AL1、形成于第一低速成膜层AL1(对应第一成膜层)上的第二成膜层和形成于第二成膜层AL2(对应第二成膜层)上的高速成膜层AH(对应第三成膜层)；在高速成膜层AH上形成有欧姆接触层N+；在欧姆接触层N+上形成有薄膜晶体管的源极S和漏极D；在薄膜晶体管的源极S和漏极D上形成有钝化层PV。
对比图2和图3可知，两种结构中有源层的结构不同。图2中的现有技术中采用高速成膜AH层和低速成膜AL层两层结构。而本发明的图3中包括3个成膜层，除包括现有技术中采用高速成膜AH层和低速成膜AL层(对应第一低速 成膜层AL1)两层结构外，还在高速成膜AH层和第一低速成膜AL1层之间设置了一第二成膜层AL2。
其中，第二成膜层AL2的成膜速度高于AL1而低于AH，其膜质及界面态密度均优于AH，具有更好的背沟道特性，漏电会更低，CVD成膜更为均匀。
在本发明的一个实施例中，有源层与钝化层的接触处为有源层的第二成膜层。如图3所示，将背沟道和钝化层PV接触处设置为第二成膜层AL2，由于第二成膜层AL2膜质及界面态密度均优于AH，具有更好的背沟道特性，因此可以降低背沟道漏电流。
为保证背沟道的导电层厚度及控制该制程所花费时间，在本发明的一个实施例中，第一低速成膜层AL1(第一成膜层)和第二成膜层AL2的厚度之和设置为有源层整体厚度的1/3。
本发明将目前常用的有源层AS由高速成膜层AH和低速成膜层AL的两层结构，改为目前的AL1/AL2/AH三层结构，且保证AL1/AL2的总厚度大于有源层AS导电层厚度，以保证背沟道和钝化层PV界面处的有源层为AL2，因为AL2成膜速度高于AL1低于AH，膜质及界面态密度均优于AH。本发明有更好的背沟道特性，漏电会更低。
如图4所示为采用现有技术的两层结构成膜层的有源层三个不同位置的漏电示意图，由该图可知，背沟道有些点位漏电流Ioff较高且较为离散，均一性不好。
如图5所示为采用本发明的有源层的三个不同位置的漏电示意图，由该图可知，背沟道处的电性均一性较好，且漏电流Ioff无明显很高的点位。由图5可知，本发明在降低背沟道漏电流Ioff的同时提高了器件的均一性。
根据本发明的另一个方面，还提供了一种液晶显示面板制作方法，包括：在基底上形成有栅极M1；在栅极M1上形成有栅绝缘层GI；在栅绝缘层GI上形成有有源层AS，此处的有源层包括形成于栅绝缘层GI上的第一低速成膜层AL1、形成于第一低速成膜层AL1(对应第一成膜层)上的第二成膜层和形成于第二成膜层AL2(对应第二成膜层)上的高速成膜层AH(对应第三成膜层)；在高速成膜层AH上形成有欧姆接触层N+；在欧姆接触层N+上形成有薄膜晶体管的源极S和漏极D；在薄膜晶体管的源极S和漏极D上形成有钝化层PV，有源层与钝化层的接触处为有源层中的非高速成膜层，形成的液晶显示面板沟道处的剖面如图3所示。
在本发明的一个实施例中，该有源层包括3个成膜层。在形成该具有3个成膜层的有源层时，具体包括以下几个步骤：在栅绝缘层上形成第一成膜层；在第一成膜层上形成第二成膜层；在第二成膜层上形成第三成膜层，其中，第一成膜层为低速成膜层，第三成膜层为高速成膜层，第二成膜层的成膜速度介于第一成膜层和第三成膜层的速度之间。具体实现时，只需在CVD沉积的时候，将有源层AS两步沉积变成三步沉积，刻蚀的时候重新确认刻蚀条件和时间即可，制程较容易实现。
在本发明的一个实施例中，有源层与钝化层的接触处为有源层的第二成膜层。
在本发明的一个实施例中，第一成膜层和第二成膜层的厚度之和设置为有源层整体厚度的1/3。
虽然本发明所揭露的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (12)

  1. 一种液晶显示面板，包括薄膜晶体管，其中，
    用于连通薄膜晶体管源漏极的有源层由多于2个的成膜层构成，并且有源层与所述面板的钝化层的接触处为有源层中的非高速成膜层。
  2. 根据权利要求1所述的面板，其中，所述有源层包括3个成膜层。
  3. 根据权利要求2所述的面板，其中，第二成膜层设置于第一成膜层和第三成膜层之间，其中，
    第一成膜层为低速成膜层，第三成膜层为高速成膜层，第二成膜层的成膜速度介于第一成膜层的成膜速度和第三成膜层的成膜速度之间。
  4. 根据权利要求3所述的面板，其中，所述有源层与钝化层的接触处为有源层的第二成膜层。
  5. 根据权利要求3所述的面板，其中，所述第一成膜层和所述第二成膜层的厚度之和为所述有源层整体厚度的1/3。
  6. 根据权利要求4所述的面板，其中，所述第一成膜层和所述第二成膜层的厚度之和为所述有源层整体厚度的1/3。
  7. 一种液晶显示面板制作方法，包括：
    在基底上形成栅极；
    在栅极上形成栅绝缘层；
    在栅绝缘层上形成有源层，其中，所述有源层由多于2个的成膜层构成；
    在有源层上形成欧姆接触层；
    在欧姆接触层上形成薄膜晶体管的源极和漏极；
    在薄膜晶体管的源极和漏极上形成有钝化层，所述有源层与所述钝化层的接触处为有源层中的非高速成膜层。
  8. 根据权利要求7所述的方法，其中，所述有源层包括3个成膜层。
  9. 根据权利要求8所述的方法，其中，在形成所述有源层时包括：
    在栅绝缘层上形成第一成膜层；
    在第一成膜层上形成第二成膜层；
    在第二成膜层上形成第三成膜层，
    其中，所述第一成膜层为低速成膜层，所述第三成膜层为高速成膜层，所述第二成膜层的成膜速度介于第一成膜层的成膜速度和第三成膜层的成膜速度之间。
  10. 根据权利要求9所述的方法，其中，所述有源层与所述钝化层的接触处为有源层的第二成膜层。
  11. 根据权利要求9所述的方法，其中，所述第一成膜层和所述第二成膜层的厚度之和为所述有源层整体厚度的1/3。
  12. 根据权利要求10所述的方法，其中，所述第一成膜层和所述第二成膜层的厚度之和为所述有源层整体厚度的1/3。
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