WO2018014441A1 - 薄膜晶体管及其制作方法 - Google Patents

薄膜晶体管及其制作方法 Download PDF

Info

Publication number
WO2018014441A1
WO2018014441A1 PCT/CN2016/098572 CN2016098572W WO2018014441A1 WO 2018014441 A1 WO2018014441 A1 WO 2018014441A1 CN 2016098572 W CN2016098572 W CN 2016098572W WO 2018014441 A1 WO2018014441 A1 WO 2018014441A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
thin film
substrate
film transistor
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/098572
Other languages
English (en)
French (fr)
Inventor
刘洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/310,430 priority Critical patent/US20180182869A1/en
Publication of WO2018014441A1 publication Critical patent/WO2018014441A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6314—Formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6324—Formation by anodic treatments, e.g. anodic oxidation

Definitions

  • the invention belongs to the technical field of electronic component manufacturing, and in particular to a thin film transistor and a manufacturing method thereof.
  • the flexible display has the characteristics of being light, thin, bendable, foldable, etc., and has a broad application prospect compared to a flat display of a conventional rigid substrate such as a glass substrate.
  • the fabrication process temperature especially the PECVD process temperature
  • the temperature of the substrate is required to be high.
  • the flexible substrate is then generally made of an organic polymer material, which is difficult to withstand higher temperatures, and the direct application of conventional fabrication processes (such as PECVD processes) will hinder the development of flexible display technologies.
  • the present invention provides a thin film transistor using an anodizing process and a method of fabricating the same.
  • a method of fabricating a thin film transistor includes: forming an active layer on a substrate; simultaneously forming a source and a drain respectively contacting the both ends of the active layer and covering on the substrate An insulating layer of the active layer, the source and the drain; a gate electrode and a passivation layer covering the gate are simultaneously formed on the insulating layer.
  • an active layer is formed on the substrate using a metal oxide semiconductor material.
  • a specific method of simultaneously forming a source and a drain respectively contacting both ends of the active layer and an insulating layer covering the active layer, the source and the drain on the substrate includes: forming an overlying active layer on the substrate a metal layer; a photoresist layer formed on the metal layer opposite to a region where the source and the drain are to be formed; an anodization treatment on the metal layer, wherein the metal layer not covered by the photoresist layer is oxidized, Lithography
  • the metal layer covered by the adhesive layer is not oxidized; the photoresist layer is peeled off, and the metal layer is anodized to further oxidize the surface of the unoxidized metal layer to be oxidized without being covered by the photoresist layer.
  • the metal layer forms an insulating layer, and the metal layer which is not oxidized after continuing anodizing treatment forms a source and a drain.
  • a specific method of simultaneously forming a gate electrode and a passivation layer covering the gate electrode on the insulating layer includes: forming a metal layer on the insulating layer; forming a photoresist layer on the metal layer opposite to a region where the gate electrode is to be formed Anodizing the metal layer, wherein the metal layer not covered by the photoresist layer is oxidized, the metal layer covered by the photoresist layer is not oxidized; the photoresist layer is stripped, and the metal layer is anodized continuously
  • the treatment causes the surface of the unoxidized metal layer to be oxidized, thereby forming a passivation layer with the metal layer not covered by the photoresist layer and being oxidized, and the metal layer not oxidized after the anodizing treatment continues to form the gate electrode.
  • a thin film transistor comprising: an active layer on a substrate; a source and a drain on the substrate and respectively contacting both ends of the active layer; on the substrate An insulating layer covering the active layer, the source and the drain; a gate on the insulating layer; and a passivation layer over the insulating layer and covering the gate.
  • the active layer is formed of a metal oxide semiconductor material.
  • the substrate is a flexible substrate or a rigid substrate.
  • the source, the drain, and the insulating layer are simultaneously formed by anodization.
  • the gate electrode and the passivation layer are simultaneously formed by an anodization process.
  • the invention has the beneficial effects that the invention combines the preparation process of the metal oxide semiconductor thin film transistor (TFT) with the anodizing technology, and the whole preparation process is carried out at normal temperature, thereby realizing the preparation of the thin film transistor on the flexible substrate which is not resistant to high temperature, and even No need for expensive equipment such as PECVD, which can greatly reduce the process cost of flexible display manufacturing.
  • TFT metal oxide semiconductor thin film transistor
  • FIG. 1 shows a schematic structural view of a thin film transistor according to an embodiment of the present invention
  • FIGS. 2A through 2H are flow charts showing a method of fabricating a thin film transistor in accordance with an embodiment of the present invention.
  • FIG. 1 shows a schematic structural view of a thin film transistor according to an embodiment of the present invention.
  • a thin film transistor has a top gate structure including: an active layer 20 on a substrate 10; and a source 30 on the substrate 10 and in contact with both ends of the active layer 20, respectively And a drain 40; an insulating layer 50 covering the active layer 20, the source 30 and the drain 40 on the substrate 10; a gate 60 on the insulating layer 50; and a passivation on the insulating layer 50 and covering the gate 60 Layer 70.
  • the substrate 10 may be a flexible substrate made of a flexible material, but the invention is not limited thereto.
  • the substrate 10 may also be a glass substrate or other rigid substrate.
  • the active layer 20 is made of a metal oxide semiconductor material such as zinc oxide (ZnO), indium trioxide (In 2 O 3 ), tin dioxide (SnO 2 ), or the like.
  • ZnO zinc oxide
  • In 2 O 3 indium trioxide
  • SnO 2 tin dioxide
  • the source 30, the drain 40, and the gate 60 may be made of a metal material or an alloy material, such as a metal such as aluminum, magnesium, or titanium, and an alloy material thereof.
  • the source 30, the drain 40, and the insulating layer 50 may be simultaneously formed using an anodizing process.
  • the insulating layer 50 may be formed of an oxide of a metal material or an alloy material forming the source electrode 30 and the drain electrode 40.
  • the gate electrode 60 and the passivation layer 70 may be simultaneously formed using an anodization process. among them, The passivation layer 70 may be formed of an oxide of a metal material or an alloy material forming the gate electrode 60.
  • FIGS. 2A through 2H are flow charts showing a method of fabricating a thin film transistor in accordance with an embodiment of the present invention.
  • an active layer 20 is formed on the substrate 10. Specifically, first, a metal oxide semiconductor material layer is deposited on the substrate 10; then, the metal oxide semiconductor material layer is exposed and etched to form the active layer 20.
  • a metal layer M1 covering the active layer 20 is formed on the substrate 10.
  • the metal layer M1 covering the active layer 20 may be deposited on the substrate 10 using a suitable deposition method.
  • a photoresist layer PR1 is formed on the metal layer M1 opposite to a region where the source and drain electrodes are to be formed, that is, both end regions of the active layer 20.
  • two photoresist layers PR are formed on the metal layer M1, one of which is opposite to the region where the source is to be formed, and the other of which is opposite to the region where the drain is to be formed.
  • the metal layer M1 is anodized, wherein a metal layer not covered by the photoresist layer is oxidized to form an oxidized metal layer MO, and the metal layer M1 covered by the photoresist layer is not oxidized.
  • the photoresist layer PR1 is peeled off, and the unoxidized metal layer M1 is anodized to further oxidize the surface of the unoxidized metal layer M1, thereby being oxidized without being covered by the photoresist layer.
  • the metal layer i.e., MO in Fig. 2D
  • a metal layer M2 is formed on the insulating layer 50.
  • the metal layer M2 may be deposited on the insulating layer 50 by a suitable deposition method.
  • a photoresist layer PR2 is formed on the metal layer M2 opposite to a region where a gate electrode is to be formed.
  • the metal layer M2 not covered by the photoresist layer PR2 is removed.
  • the photoresist layer PR2 is stripped and the remaining metal layer M2 is anodized.
  • the treatment causes the surface of the remaining metal layer M2 to be oxidized to form a passivation layer 70, and the unoxidized metal layer forms the gate electrode 60.
  • a thin film transistor and a method of fabricating the same combine a metal oxide semiconductor (TOS) thin film transistor (TFT) fabrication process with an anodization technique, and the entire preparation process is performed at a normal temperature. Therefore, thin film transistors can be fabricated on a flexible substrate that is not resistant to high temperatures, and even expensive equipment such as PECVD is not required, which can greatly reduce the process cost of flexible display manufacturing.
  • TOS metal oxide semiconductor
  • TFT thin film transistor

Landscapes

  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

一种薄膜晶体管的制作方法，其包括：在基板（10）上形成有源层（20）；在基板（10）上同时形成与有源层（20）的两端分别接触的源极（30）和漏极（40）以及覆盖有源层（20）、源极（30）和漏极（40）的绝缘层（50）；在绝缘层（50）上同时形成栅极（60）以及覆盖栅极（60）的钝化层（70）。一种利用该制作方法制作的薄膜晶体管。薄膜晶体管可以在常温下进行，从而实现不耐高温的柔性基板上制备薄膜晶体管的目的，甚至不需要PECVD等昂贵的设备，能够大大降低柔性显示制造的工艺成本。

Description

薄膜晶体管及其制作方法 技术领域
本发明属于电子元器件制作技术领域，具体地讲，涉及一种薄膜晶体管及其制作方法。
背景技术
柔性显示具有轻、薄、可弯曲、可折叠等特点，其相比传统的硬质基板(诸如玻璃基板)的平板显示，具有广阔的应用前景。
在传统的平板显示中，尤其在薄膜晶体管的制作过程中，由于制作工艺温度特别是PECVD工艺温度较高，对基板的温度要求较高。然后柔性基板一般采用有机高分子材料，其很难承受较高的温度，如果直接应用传统的制作工艺(诸如PECVD工艺)将阻碍柔性显示技术的发展。
发明内容
为了解决上述问题，本发明提供了一种采用阳极氧化处理工艺的薄膜晶体管及其制作方法。
根据本发明的一方面，提供了一种薄膜晶体管的制作方法，其包括：在基板上形成有源层；在基板上同时形成与有源层的两端分别接触的源极和漏极以及覆盖有源层、源极和漏极的绝缘层；在绝缘层上同时形成栅极以及覆盖栅极的钝化层。
进一步地，利用金属氧化物半导体材料在基板上形成有源层。
进一步地，在基板上同时形成与有源层的两端分别接触的源极和漏极以及覆盖有源层、源极和漏极的绝缘层的具体方法包括：在基板上形成覆盖有源层的金属层；在金属层上形成与将要形成源极和漏极的区域相对的光刻胶层；对金属层进行阳极氧化处理，其中，未被光刻胶层覆盖的金属层被氧化，被光刻 胶层覆盖的金属层未被氧化；剥离光刻胶层，继续对金属层进行阳极氧化处理，使未被氧化的金属层的表面被氧化，从而与未被光刻胶层覆盖而被氧化的金属层形成绝缘层，经继续阳极氧化处理后未被氧化的金属层形成源极和漏极。
进一步地，在绝缘层上同时形成栅极以及覆盖栅极的钝化层的具体方法包括：在绝缘层上形成金属层；在金属层上形成与将要形成栅极的区域相对的光刻胶层；对金属层进行阳极氧化处理，其中，未被光刻胶层覆盖的金属层被氧化，被光刻胶层覆盖的金属层未被氧化；剥离光刻胶层，继续对金属层进行阳极氧化处理，使未被氧化的金属层的表面被氧化，从而与未被光刻胶层覆盖而被氧化的金属层形成钝化层，经继续阳极氧化处理后未被氧化的金属层形成栅极。
根据本发明的另一方面，还提供了一种薄膜晶体管，其包括：在基板上的有源层；在基板上且与有源层的两端分别接触的源极和漏极；在基板上覆盖有源层、源极和漏极的绝缘层；在绝缘层上的栅极；在绝缘层上且覆盖栅极的钝化层。
进一步地，所述有源层由金属氧化物半导体材料形成。
进一步地，所述基板为柔性基板或硬质基板。
进一步地，利用阳极氧化处理的方法同时形成所述源极、所述漏极及所述绝缘层。
进一步地，利用阳极氧化处理的方法同时形成所述栅极和所述钝化层。
本发明的有益效果：本发明将金属氧化物半导体薄膜晶体管(TFT)的制备工艺与阳极氧化技术相结合，整个制备过程在常温下进行，从而实现不耐高温的柔性基板上制备薄膜晶体管，甚至不需要PECVD等昂贵的设备，能够大大降低柔性显示制造的工艺成本。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1示出了根据本发明的实施例的薄膜晶体管的结构示意图；
图2A至图2H示出了根据本发明的实施例的薄膜晶体管的制作方法的流程图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚器件，夸大了层和区域的厚度。相同的标号在附图中始终表示相同的元件。
图1示出了根据本发明的实施例的薄膜晶体管的结构示意图。
参照图1，根据本发明的实施例的薄膜晶体管具有顶栅结构，其包括：在基板10上的有源层20；在基板10上且与有源层20的两端分别接触的源极30和漏极40；在基板10上覆盖有源层20、源极30和漏极40的绝缘层50；在绝缘层50上的栅极60；在绝缘层50上且覆盖栅极60的钝化层70。
优选地，基板10可以为柔性基板，其采用柔性材料制成，但本发明并不限制于此，例如基板10也可以是玻璃基板或者其他的硬质基板。
可选地，有源层20由金属氧化物半导体材料制成，诸如二氧化锌(ZnO)、三氧化二铟(In2O3)、二氧化锡(SnO2)等。
可选地，源极30、漏极40和栅极60可以由金属材料或者合金材料制成，例如铝、镁、钛等金属及其合金材料。
可选地，可以利用阳极氧化处理工艺同时形成源极30、漏极40和绝缘层50。其中，绝缘层50可以由形成源极30和漏极40的金属材料或合金材料的氧化物形成。
可选地，可以利用阳极氧化处理工艺同时形成栅极60和钝化层70。其中， 钝化层70可以由形成栅极60的金属材料或合金材料的氧化物形成。
图2A至图2H示出了根据本发明的实施例的薄膜晶体管的制作方法的流程图。
参照图2A，在基板10上形成有源层20。具体地，首先，在基板10上沉积金属氧化物半导体材料层；接着，对金属氧化物半导体材料层进行曝光、刻蚀，以形成有源层20。
参照图2B，在基板10上形成覆盖有源层20的金属层M1。具体地，可利用合适的沉积方法在基板10上沉积覆盖有源层20的金属层M1。
参照图2C，在金属层M1上形成与将要形成源极和漏极的区域(即有源层20的两端区域)相对的光刻胶层PR1。这里，在金属层M1上形成两个光刻胶层PR，其中一个相对于将要形成源极的区域，其中另一个相对于将要形成漏极的区域。
参照图2D，对金属层M1进行阳极氧化处理，其中，未被光刻胶层覆盖的金属层被氧化，以形成氧化金属层MO，被光刻胶层覆盖的金属层M1未被氧化。
参照图2E，剥离光刻胶层PR1，继续对未被氧化的金属层M1进行阳极氧化处理，使未被氧化的金属层M1的表面被氧化，从而与未被光刻胶层覆盖而被氧化的金属层(即图2D中的MO)形成绝缘层50，经继续阳极氧化处理后未被氧化的金属层形成源极30和漏极40。
参照图2F，在绝缘层50上形成金属层M2。具体地，可利用合适的沉积方法在绝缘层50上沉积金属层M2。
参照图2G，在金属层M2上形成与将要形成栅极的区域相对的光刻胶层PR2。
参照图2H，经曝光、刻蚀处理后，将未被光刻胶层PR2覆盖的金属层M2去除。
返回参照图1，剥离光刻胶层PR2，并对剩余的金属层M2进行阳极氧化 处理，使剩余的金属层M2的表面被氧化，以形成钝化层70，未被氧化的金属层形成栅极60。
综上所述，根据本发明的实施例的薄膜晶体管及其制作方法，其将金属氧化物半导体(TOS)薄膜晶体管(TFT)的制备工艺与阳极氧化技术相结合，整个制备过程在常温下进行，从而实现不耐高温的柔性基板上制备薄膜晶体管，甚至不需要PECVD等昂贵的设备，能够大大降低柔性显示制造的工艺成本。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (12)

  1. 一种薄膜晶体管的制作方法，其中，包括：
    在基板上形成有源层；
    在基板上同时形成与有源层的两端分别接触的源极和漏极以及覆盖有源层、源极和漏极的绝缘层；
    在绝缘层上同时形成栅极以及覆盖栅极的钝化层。
  2. 根据权利要求1所述的薄膜晶体管的制作方法，其中，利用金属氧化物半导体材料在基板上形成有源层。
  3. 根据权利要求1所述的薄膜晶体管的制作方法，其中，在基板上同时形成与有源层的两端分别接触的源极和漏极以及覆盖有源层、源极和漏极的绝缘层的具体方法包括：
    在基板上形成覆盖有源层的金属层；
    在金属层上形成与将要形成源极和漏极的区域相对的光刻胶层；
    对金属层进行阳极氧化处理，其中，未被光刻胶层覆盖的金属层被氧化，被光刻胶层覆盖的金属层未被氧化；
    剥离光刻胶层，继续对金属层进行阳极氧化处理，使未被氧化的金属层的表面被氧化，从而与未被光刻胶层覆盖而被氧化的金属层形成绝缘层，经继续阳极氧化处理后未被氧化的金属层形成源极和漏极。
  4. 根据权利要求1所述的薄膜晶体管的制作方法，其中，在绝缘层上同时形成栅极以及覆盖栅极的钝化层的具体方法包括：
    在绝缘层上形成金属层；
    在金属层上形成与将要形成栅极的区域相对的光刻胶层；
    将未被光刻胶层覆盖的金属层去除；
    剥离光刻胶层，并对剩余的金属层进行阳极氧化处理，使剩余的金属层的表面被氧化以形成钝化层，未被氧化的金属层形成栅极。
  5. 根据权利要求3所述的薄膜晶体管的制作方法，其中，在绝缘层上同时形成栅极以及覆盖栅极的钝化层的具体方法包括：
    在绝缘层上形成金属层；
    在金属层上形成与将要形成栅极的区域相对的光刻胶层；
    将未被光刻胶层覆盖的金属层去除；
    剥离光刻胶层，并对剩余的金属层进行阳极氧化处理，使剩余的金属层的表面被氧化以形成钝化层，未被氧化的金属层形成栅极。
  6. 根据权利要求1所述的薄膜晶体管的制作方法，其中，所述基板为柔性基板或硬质基板。
  7. 一种薄膜晶体管，其中，包括：
    在基板上的有源层；
    在基板上且与有源层的两端分别接触的源极和漏极；
    在基板上覆盖有源层、源极和漏极的绝缘层；
    在绝缘层上的栅极；
    在绝缘层上且覆盖栅极的钝化层。
  8. 根据权利要求7所述的薄膜晶体管，其中，所述有源层由金属氧化物半导体材料形成。
  9. 根据权利要求7所述的薄膜晶体管，其中，所述基板为柔性基板或硬质基板。
  10. 根据权利要求7所述的薄膜晶体管，其中，利用阳极氧化处理的方法 同时形成所述源极、所述漏极及所述绝缘层。
  11. 根据权利要求7所述的薄膜晶体管，其中，利用阳极氧化处理的方法同时形成所述栅极和所述钝化层。
  12. 根据权利要求10所述的薄膜晶体管，其中，利用阳极氧化处理的方法同时形成所述栅极和所述钝化层。
PCT/CN2016/098572 2016-07-20 2016-09-09 薄膜晶体管及其制作方法 Ceased WO2018014441A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/310,430 US20180182869A1 (en) 2016-07-20 2016-09-09 Thin film transistor and method of fabricating the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610576516.XA CN106024638A (zh) 2016-07-20 2016-07-20 薄膜晶体管及其制作方法
CN201610576516.X 2016-07-20

Publications (1)

Publication Number Publication Date
WO2018014441A1 true WO2018014441A1 (zh) 2018-01-25

Family

ID=57116921

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/098572 Ceased WO2018014441A1 (zh) 2016-07-20 2016-09-09 薄膜晶体管及其制作方法

Country Status (3)

Country Link
US (1) US20180182869A1 (zh)
CN (1) CN106024638A (zh)
WO (1) WO2018014441A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107256878A (zh) 2017-06-09 2017-10-17 京东方科技集团股份有限公司 一种有机电致发光显示面板及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0513590A2 (en) * 1991-05-08 1992-11-19 Seiko Epson Corporation Thin-film transistor and method for manufacturing it
CN1832194A (zh) * 2006-02-28 2006-09-13 友达光电股份有限公司 有机电致发光显示单元
CN102332404A (zh) * 2011-09-21 2012-01-25 华南理工大学 基于阳极氧化绝缘层的薄膜晶体管的制备方法
CN105374748A (zh) * 2015-10-13 2016-03-02 深圳市华星光电技术有限公司 薄膜晶体管基板的制作方法及制得的薄膜晶体管基板

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4115446C1 (zh) * 1991-05-11 1992-02-20 Continental Aktiengesellschaft, 3000 Hannover, De
KR101623958B1 (ko) * 2008-10-01 2016-05-25 삼성전자주식회사 인버터 및 그의 동작방법과 인버터를 포함하는 논리회로
JP5676326B2 (ja) * 2011-03-18 2015-02-25 富士フイルム株式会社 電界効果型トランジスタ
CN103076703B (zh) * 2012-12-28 2015-11-25 南京中电熊猫液晶显示科技有限公司 一种液晶显示面板及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0513590A2 (en) * 1991-05-08 1992-11-19 Seiko Epson Corporation Thin-film transistor and method for manufacturing it
CN1832194A (zh) * 2006-02-28 2006-09-13 友达光电股份有限公司 有机电致发光显示单元
CN102332404A (zh) * 2011-09-21 2012-01-25 华南理工大学 基于阳极氧化绝缘层的薄膜晶体管的制备方法
CN105374748A (zh) * 2015-10-13 2016-03-02 深圳市华星光电技术有限公司 薄膜晶体管基板的制作方法及制得的薄膜晶体管基板

Also Published As

Publication number Publication date
CN106024638A (zh) 2016-10-12
US20180182869A1 (en) 2018-06-28

Similar Documents

Publication Publication Date Title
US20170110323A1 (en) Method of forming patterned metal film layer and preparation method of transistor and array substrate
CN109166865B (zh) 阵列基板及其制造方法、显示面板
WO2017063292A1 (zh) 薄膜晶体管基板的制作方法及制得的薄膜晶体管基板
WO2016173027A1 (zh) 薄膜晶体管阵列基板及其制作方法
CN106920753B (zh) 薄膜晶体管及其制作方法、阵列基板和显示器
WO2015143745A1 (zh) 一种阵列基板的制造方法
WO2013127229A1 (zh) 薄膜晶体管及其制造方法、阵列基板、显示装置
JP6899487B2 (ja) Ｔｆｔ基板及びその製造方法
WO2017016152A1 (zh) 阵列基板及其制造方法、显示装置
WO2017024612A1 (zh) 氧化物半导体tft基板的制作方法及其结构
WO2015043008A1 (zh) 薄膜晶体管阵列基板的制造方法
CN104576760A (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
TW201334082A (zh) 薄膜電晶體及其製作方法及顯示器
CN107579006A (zh) 一种薄膜晶体管、阵列基板及其制备方法
CN105990332B (zh) 薄膜晶体管基板及其显示面板
TWI546850B (zh) 顯示面板之製備方法
WO2017133114A1 (zh) 薄膜晶体管及其制造方法
CN111129083A (zh) 显示面板的制造方法及显示面板
CN107490911B (zh) 阵列基板及其制作方法和显示面板
WO2019210776A1 (zh) 阵列基板、显示装置、薄膜晶体管及阵列基板的制作方法
WO2019223076A1 (zh) 金属氧化物薄膜晶体管及其制作方法、显示器
WO2016058312A1 (zh) 一种薄膜晶体管及其制作方法、显示基板和显示装置
WO2020047916A1 (zh) 有机发光二极管驱动背板制造方法
WO2018014441A1 (zh) 薄膜晶体管及其制作方法
CN104681626A (zh) 氧化物薄膜晶体管及其制作方法、阵列基板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15310430

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16909368

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16909368

Country of ref document: EP

Kind code of ref document: A1