WO2017063292A1 - 薄膜晶体管基板的制作方法及制得的薄膜晶体管基板 - Google Patents

薄膜晶体管基板的制作方法及制得的薄膜晶体管基板 Download PDF

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WO2017063292A1
WO2017063292A1 PCT/CN2015/099273 CN2015099273W WO2017063292A1 WO 2017063292 A1 WO2017063292 A1 WO 2017063292A1 CN 2015099273 W CN2015099273 W CN 2015099273W WO 2017063292 A1 WO2017063292 A1 WO 2017063292A1
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layer
metal
photoresist pattern
film transistor
metal layer
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PCT/CN2015/099273
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English (en)
French (fr)
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刘洋
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深圳市华星光电技术有限公司
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Priority to US14/917,567 priority Critical patent/US9881811B2/en
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a thin film transistor substrate and a fabricated thin film transistor substrate.
  • the flexible display technology makes the design of the display device no longer limited to planarization, but provides a variety of shapes and designs, while the thin and shock-resistant features are suitable for portable products such as mobile phones, PDAs or notebook computers.
  • These display devices are soft, deformable and non-destructive, and can be mounted on curved surfaces to create the e-newsletter, wall TV, and wearable display that people have always dreamed of, showing the charm of organic semiconductors.
  • TFT-LCD Liquid Crystal Display
  • AMOLED Active Matrix Oranic Light Emitting Diode
  • TFT Thin Film Transistor
  • TFT-LCD The difference from the TFT structure of the TFT-LCD is that the LCD is driven by voltage, and the AMOLED is driven by current, and its brightness is proportional to the current, so in addition to the address TFT that performs the ON/OFF switching action, it needs to be sufficient.
  • SRAM Static Random Access Memory
  • a process temperature particularly a plasma enhanced chemical vapor deposition (PECVD) process
  • PECVD plasma enhanced chemical vapor deposition
  • the substrate is generally made of organic polymer material, which is difficult to withstand higher temperatures and hinders flexibility.
  • the object of the present invention is to provide a method for fabricating a thin film transistor substrate.
  • the whole manufacturing process is performed at a normal temperature, and is suitable for a flexible display technology, does not require a flexible substrate with high temperature resistance, and does not require high-temperature process equipment such as expensive chemical vapor deposition. , can greatly reduce the process cost of flexible display manufacturing.
  • the present invention provides a method of fabricating a thin film transistor substrate, comprising the steps of:
  • Step 1 providing a substrate, on which a first metal layer is deposited
  • Step 2 coating a photoresist layer on the first metal layer, performing patterning on the photoresist layer, leaving only the first photoresist pattern, and using the first photoresist pattern as a mask,
  • the first metal layer is anodized such that a portion of the first metal layer not covered by the first photoresist pattern is oxidized, converted into a first metal oxide, covered by the first photoresist pattern Partially unoxidized, still metal;
  • Step 3 peeling off the first photoresist pattern from the first metal layer, continuing anodizing the first metal layer, and oxidizing the surface of the metal previously covered by the first photoresist pattern to form a first metal oxide a material such that the under-oxidized metal forms a gate, and the first metal oxide located above the gate and the substrate constitutes a gate insulating layer;
  • Step 4 depositing a metal oxide semiconductor material on the gate insulating layer, forming an active layer through a photolithography process;
  • Step 5 depositing a second metal layer on the active layer and the gate insulating layer;
  • Step 6 coating a photoresist layer on the second metal layer, performing patterning on the photoresist layer, leaving only the second photoresist pattern, and using the second photoresist pattern as a mask,
  • the second metal layer is anodized so that a portion of the second metal layer not covered by the second photoresist pattern is oxidized, converted into a second metal oxide, covered by the second photoresist pattern Partially unoxidized, still metal;
  • Step 7 Stripping the second photoresist pattern from the second metal layer, and continuing anodizing the second metal layer to oxidize the surface of the metal previously covered by the second photoresist pattern to form a second metal oxide.
  • Step 8 forming a via hole above the corresponding drain on the passivation layer by a photolithography process. Then, a transparent conductive film is deposited on the passivation layer, and the transparent conductive film is patterned by a photolithography process to form a pixel electrode, and the pixel electrode is in contact with the drain through the through hole.
  • the material of the first metal layer and the second metal layer is at least one of aluminum, magnesium, titanium, an aluminum alloy, a magnesium alloy, and a titanium alloy.
  • the metal oxide semiconductor material is a combination of one or more of ZnO, In 2 O 3 , and SnO 2 .
  • the material of the pixel electrode is indium tin oxide or indium zinc oxide.
  • the step 1 deposits the first metal layer by physical vapor deposition; the step 4 deposits the metal oxide semiconductor material by physical vapor deposition; and the step 5 deposits the second metal by physical vapor deposition a layer; the step 8 deposits the transparent conductive film by physical vapor deposition.
  • the corrosion-resistant conductive material is used as the cathode in the anodizing treatment; the weak acid or weak alkali solution is used as the electrolyte solution.
  • Graphite or platinum is used as the cathode in the anodizing treatment; a citric acid solution or an ammonium tartrate solution is used as the electrolyte solution.
  • the present invention also provides a thin film transistor substrate, comprising: a substrate substrate, a gate electrode disposed on the substrate substrate, a gate insulating layer disposed on the gate electrode and the substrate substrate, and the gate insulating layer disposed on the gate An active layer on the insulating layer, a source and a drain provided on the active layer and the gate insulating layer, and the source, the drain, the active layer, and the gate insulating layer a passivation layer, and a pixel electrode disposed on the passivation layer; wherein the material of the gate insulating layer is an oxide of a gate material, and the material of the passivation layer is a source and a drain material Oxide.
  • a through hole is formed on the passivation layer corresponding to the drain, and the pixel electrode is in contact with the drain through the through hole.
  • the material of the gate, the source, and the drain is at least one of aluminum, magnesium, titanium, aluminum alloy, magnesium alloy, and titanium alloy; the material of the active layer is a metal oxide semiconductor material; The material of the pixel electrode is indium tin oxide or indium zinc oxide.
  • the invention also provides a method for fabricating a thin film transistor substrate, comprising the following steps:
  • Step 1 providing a substrate, on which a first metal layer is deposited
  • Step 2 coating a photoresist layer on the first metal layer, performing patterning on the photoresist layer, leaving only the first photoresist pattern, and using the first photoresist pattern as a mask,
  • the first metal layer is anodized such that a portion of the first metal layer not covered by the first photoresist pattern is oxidized, converted into a first metal oxide, covered by the first photoresist pattern Partially unoxidized, still metal;
  • Step 3 peeling off the first photoresist pattern from the first metal layer, continuing anodizing the first metal layer, and oxidizing the surface of the metal previously covered by the first photoresist pattern to form a first metal oxide a material such that the under-oxidized metal forms a gate, and the first metal oxide located above the gate and the substrate constitutes a gate insulating layer;
  • Step 4 depositing a metal oxide semiconductor material on the gate insulating layer, forming an active layer through a photolithography process;
  • Step 5 depositing a second metal layer on the active layer and the gate insulating layer;
  • Step 6 coating a photoresist layer on the second metal layer, performing patterning on the photoresist layer, leaving only the second photoresist pattern, and using the second photoresist pattern as a mask,
  • the second metal layer is anodized so that a portion of the second metal layer not covered by the second photoresist pattern is oxidized, converted into a second metal oxide, covered by the second photoresist pattern Partially unoxidized, still metal;
  • Step 7 Stripping the second photoresist pattern from the second metal layer, and continuing anodizing the second metal layer to oxidize the surface of the metal previously covered by the second photoresist pattern to form a second metal oxide.
  • Step 8 forming a via hole over the corresponding drain on the passivation layer by a photolithography process, then depositing a transparent conductive film on the passivation layer, and patterning the transparent conductive film by a photolithography process Processing, forming a pixel electrode, the pixel electrode being in contact with the drain through the through hole;
  • the material of the first metal layer and the second metal layer is at least one of aluminum, magnesium, titanium, aluminum alloy, magnesium alloy, and titanium alloy;
  • the metal oxide semiconductor material is a combination of one or more of ZnO, In 2 O 3 , and SnO 2 ;
  • the material of the pixel electrode is indium tin oxide or indium zinc oxide.
  • a method of fabricating a thin film transistor substrate and a obtained thin film transistor substrate are provided.
  • the photoresist layer is used as a mask, and the metal layer is directly oxidized by anodization as a gate insulating layer or a passivation layer, and a gate electrode or a source/drain electrode pattern is formed at the same time.
  • the process is carried out at room temperature and can be fabricated on flexible substrates that are not resistant to high temperatures. It is suitable for flexible display technology, does not require flexible substrates with high temperature resistance, and does not require expensive high-temperature process equipment such as chemical vapor deposition, which can greatly reduce flexible displays. Process cost of manufacturing.
  • the thin film transistor substrate prepared by the invention has excellent electrical properties and is suitable for a flexible display.
  • Figure 1 is a schematic diagram of the principle of anodizing technology
  • FIG. 2 is a schematic view showing the first step of the method for fabricating a thin film transistor substrate of the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating a thin film transistor substrate of the present invention
  • step 3 is a schematic diagram of step 3 of a method for fabricating a thin film transistor substrate of the present invention.
  • step 4 is a schematic diagram of step 4 of a method for fabricating a thin film transistor substrate of the present invention
  • step 5 is a schematic diagram of step 5 of a method for fabricating a thin film transistor substrate of the present invention.
  • step 6 is a schematic diagram of step 6 of a method for fabricating a thin film transistor substrate of the present invention.
  • step 7 of a method for fabricating a thin film transistor substrate of the present invention is a schematic diagram of step 7 of a method for fabricating a thin film transistor substrate of the present invention.
  • FIG. 9 is a schematic view showing the step 8 of the method for fabricating a thin film transistor substrate of the present invention and a schematic structural view of the thin film transistor substrate of the present invention.
  • the inventive concept of the present invention is based on a metal oxide semiconductor (TOS) thin film transistor (TFT) fabrication process, combined with anodization technology, to propose a fabrication method of a thin film transistor substrate suitable for flexible display.
  • Anodic oxidation technology is an electrochemical oxidation technique of a metal or alloy. Metal and its alloys under the corresponding electrolyte and specific process conditions, due to the application of current, the anode metal loses electrons, the electrolyte solution is ionized, an oxidation reaction occurs, and an oxide film is formed on the surface of the anode metal, according to the anode. A film of several nanometers to several micrometers thick can be formed depending on the oxidation time.
  • FIG. 1 is a schematic diagram of the principle of anodizing technology.
  • an anode 100 made of metal aluminum and a cathode 200 made of graphite or metal platinum are provided, and a constant connection between the anode 100 and the cathode 200 is provided.
  • the electrolyte solution 400 is a weak acid or weak alkali solution such as a citric acid solution or an ammonium tartrate solution, and the anode 100 and the cathode 200 are energized.
  • the electrochemical reaction occurring at the anode 100 is: 2Al + 3H 2 O ⁇ Al 2 O 3 + 6e + 6H +
  • the electrochemical reaction of the cathode 200 occurs: 6H 2 O + 6e ⁇ 3H 2 + 6OH - , thereby It can be seen that the reaction occurring at the anode 100 is a metal oxidation reaction.
  • the present invention designs a photoresist pattern as a mask, directly oxidizes the metal layer by anodization as a gate insulating layer or a passivation layer, and simultaneously forms a gate electrode or a source/drain electrode pattern, and the entire fabrication process It can be fabricated at room temperature and can be fabricated on flexible substrates that are not resistant to high temperatures, even without expensive high-temperature process equipment such as chemical vapor deposition, which can greatly reduce the process cost of flexible display manufacturing.
  • the present invention firstly provides a method for fabricating a thin film transistor substrate, comprising the following steps:
  • Step 1 As shown in FIG. 2, a substrate 1 is provided on which a first metal layer 10 is deposited.
  • the base substrate 1 may be a flexible substrate or a rigid substrate.
  • the flexible substrate may be a substrate made of an organic polymer material; and the hard substrate may be a glass substrate.
  • the material of the first metal layer 10 is at least one of aluminum (Al), magnesium (Mg), titanium (Ti), aluminum alloy, magnesium alloy, and titanium alloy.
  • the first metal layer 10 is deposited by a method such as Physical Vapor Deposition (PVD).
  • PVD Physical Vapor Deposition
  • Step 2 As shown in FIG. 3, a photoresist layer is coated on the first metal layer 10, and the photoresist layer is patterned to retain only the first photoresist pattern 12, and the first The photoresist pattern 12 is a mask, and the first metal layer 10 is anodized so that a portion of the first metal layer 10 not covered by the first photoresist pattern 12 is oxidized and converted into a first metal oxide. The portion covered by the first photoresist pattern 12 is not oxidized and is still a metal.
  • Step 3 as shown in FIG. 4, the first photoresist pattern 12 is peeled off from the first metal layer 10, and the first metal layer 10 is anodized to control the oxidation time.
  • the metal surface covered by the resist pattern 12 is oxidized to form a first metal oxide such that the under-oxidized metal forms the gate electrode 2, and the first metal oxide located above the gate electrode 2 and the substrate substrate 1 constitutes a gate insulating layer.
  • Layer 3
  • Step 4 As shown in FIG. 5, a metal oxide semiconductor material is deposited on the gate insulating layer 3, and an active layer 4 is formed by a photolithography process.
  • the metal oxide semiconductor material is a combination of one or more of ZnO, In 2 O 3 , and SnO 2 .
  • the metal oxide semiconductor material is deposited by a method such as physical vapor deposition.
  • the photolithography process includes a photoresist, exposure, development, and etching process.
  • Step 5 As shown in FIG. 6, a second metal layer 50 is deposited on the active layer 4 and the gate insulating layer 3.
  • the material of the second metal layer 50 is at least one of aluminum (Al), magnesium (Mg), titanium (Ti), aluminum alloy, magnesium alloy, and titanium alloy.
  • the second metal layer 50 is deposited by a method such as physical vapor deposition.
  • Step 6 as shown in FIG. 7, a photoresist layer is coated on the second metal layer 50, and the photoresist layer is patterned to retain only the second photoresist pattern 52, and the second The photoresist pattern 52 is a mask, and the second metal layer 50 is anodized so that a portion of the second metal layer 50 not covered by the second photoresist pattern 52 is oxidized to be converted into a second metal oxide. The portion covered by the second photoresist pattern 52 is not oxidized and is still a metal.
  • Step 7 as shown in FIG. 8, the second photoresist pattern 52 is peeled off from the second metal layer 50, and the second metal layer 50 is anodized to control the oxidation time.
  • the metal surface covered by the resist pattern 52 is oxidized to form a second metal oxide such that the under-oxidized metal forms the source 51 and the drain 53 at the source 51, the drain 53, the active layer 4, and the gate.
  • the second metal oxide over the insulating layer 3 constitutes a passivation layer 6.
  • the corrosion-resistant conductive material such as graphite or platinum is used as the cathode 100 in the anodizing treatment; the weak acid or weak is used in the citric acid solution or the ammonium tartrate solution.
  • the alkali solution serves as the electrolyte solution 400.
  • Step 8 As shown in FIG. 9, a through hole 61 is formed on the passivation layer 6 over the corresponding drain electrode 53 by a photolithography process, and then a transparent conductive film is deposited on the passivation layer 6 through a light.
  • the transparent conductive film is patterned by an engraving process to form a pixel electrode 7, and the pixel electrode 7 is in contact with the drain electrode 53 through the through hole 61.
  • the material of the pixel electrode 7 is a transparent conductive material such as ITO (indium tin oxide) or IZO (indium zinc oxide).
  • the transparent conductive film is deposited by a method such as physical vapor deposition.
  • the photoresist layer is used as a mask, and the metal layer is directly oxidized by anodization as a gate insulating layer or a passivation layer, and a gate electrode or a source/drain electrode pattern is formed at the same time. It can be fabricated at room temperature and can be fabricated on flexible substrates that are not resistant to high temperatures. It does not even require expensive high-temperature process equipment such as chemical vapor deposition, which can greatly reduce the process cost of flexible display manufacturing.
  • the present invention further provides a thin film transistor substrate, including: a substrate 1 , a gate 2 disposed on the substrate 1 , and a substrate 2 disposed on the gate 2 and the substrate 1 a gate insulating layer 3, an active layer 4 disposed on the gate insulating layer 3, a source 51 and a drain 53 provided on the active layer 4 and the gate insulating layer 3, and a source 51, a drain 53, an active layer 4, and a passivation layer 6 on the gate insulating layer 3, and a pixel electrode 7 disposed on the passivation layer 6; wherein the material of the gate insulating layer 3 is an oxide of the gate 2 material, the blunt The material of the layer 6 is an oxide of the material of the source 51 and the drain 53.
  • a through hole 61 is formed on the passivation layer 6 corresponding to the drain electrode 53.
  • the pixel electrode 7 is in contact with the drain electrode 53 through the through hole 61.
  • the base substrate 1 may be a flexible substrate or a rigid substrate.
  • the flexible substrate may be a substrate made of an organic polymer material; and the hard substrate may be a glass substrate.
  • the material of the gate electrode 2 is at least one of aluminum (Al), magnesium (Mg), titanium (Ti), aluminum alloy, magnesium alloy, and titanium alloy.
  • the material of the active layer 4 is a metal oxide semiconductor material.
  • the metal oxide semiconductor material is a combination of one or more of ZnO, In 2 O 3 , or SnO 2 .
  • the material of the source 51 and the drain 53 is at least one of aluminum (Al), magnesium (Mg), titanium (Ti), an aluminum alloy, a magnesium alloy, and a titanium alloy.
  • the material of the pixel electrode 7 is a transparent conductive material such as ITO (indium tin oxide) or IZO (indium zinc oxide).
  • the present invention provides a method of fabricating a thin film transistor substrate and a fabricated thin film transistor substrate.
  • the photoresist layer is used as a mask, and the metal layer is directly oxidized by anodization as a gate insulating layer or a passivation layer, and a gate electrode or a source/drain electrode pattern is formed at the same time.
  • the process is carried out at room temperature, can be fabricated on flexible substrates that are not resistant to high temperatures, and does not even require expensive high-temperature process equipment such as chemical vapor deposition, which can greatly reduce the process cost of flexible display manufacturing.
  • the thin film transistor substrate prepared by the invention has excellent electrical properties and is suitable for a flexible display.

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Abstract

提供一种薄膜晶体管基板的制作方法及制得的薄膜晶体管基板。薄膜晶体管基板的制作方法，利用光阻图案作为掩膜，将金属层通过阳极氧化技术直接氧化作为栅极绝缘层（3）或钝化层（6），同时形成栅电极（2）或源/漏电极（51，53）图形，整个制作工艺在常温下进行，可在不耐高温的柔性基底上制作，适用于柔性显示技术，不需要耐高温的柔性基板，也不需要使用昂贵的化学气相沉积等高温制程设备，能够大大降低柔性显示器制造的工艺成本。制得的薄膜晶体管基板电学性能优良，适用于柔性显示器。

Description

薄膜晶体管基板的制作方法及制得的薄膜晶体管基板 技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管基板的制作方法及制得的薄膜晶体管基板。
背景技术
可弯曲显示技术使显示器件的设计不再局限于平面化，而是提供多元的外形与设计，而轻薄、耐冲击的特性则适用于移动电话、PDA或笔记本电脑等便携式产品。这类显示器件柔软可变形且不易损坏，可以安装在弯曲的表面，可以制成人们梦寐以求的电子报刊、墙壁电视、可穿戴的显示器，淋漓尽致的展现有机半导体的魅力。
除此之外，开发柔性显示器件的另一个重要因素在于其工艺可以由sheet-fed Batch Processing(分批装片式制程)转换成Roll-to-Roll Manufacturing(滚动条式制程)，意味着显示器件的制造成本可大幅降低。凭借与纸张相似的厚度及柔性、数字电子媒体的信息可更新性、机械性能上的优点、制造成本的优势，柔性显示器件极有可能替换目前的平面显示器件，在新兴市场取得商机。
TFT-LCD(液晶显示器)是指液晶显示器上的每一液晶像素点都是由集成在其后的薄膜晶体管来驱动，利用扫描的方法任意控制一个显示点的ON/OFF，从而可以做到高速度、高亮度、高对比度地显示信息。AMOLED(Active Matrix Oranic Light Emitting Diode，有源有机电致发光显示器件)同样可以用TFT(Thin Film Transistor，薄膜晶体管)驱动，每个像素配备具有开关功能的薄膜晶体管，而且每个像素配备一个电荷存储电容，外围驱动电路和显示阵列整个系统集成在同一基板上。与TFT-LCD的TFT结构不同之处在于，LCD采用电压驱动，而AMOLED采用电流驱动，其亮度与电流成正比，因此除了进行ON/OFF切换动作的选址TFT之外，还需要能让足够电流通过的ON阻抗较低的小型驱动TFT。SRAM(静态随机存储器)同样可以用TFT进行驱动。
传统的柔性显示器的薄膜晶体管制作过程中，由于工艺温度特别是等离子体增强化学气相沉积(PECVD，Plasma Enhanced Chemical Vapor Deposition)工艺温度较高，对基底温度要求较高，柔性显示器中的薄膜晶体管的基底一般采用有机高分子材料，很难承受较高的温度，阻碍了柔性 显示技术的发展。
发明内容
本发明的目的在于提供一种薄膜晶体管基板的制作方法，整个制作工艺在常温下进行，适用于柔性显示技术，不需要耐高温的柔性基板，也不需要使用昂贵的化学气相沉积等高温制程设备，能够大大降低柔性显示器制造的工艺成本。
本发明的目的还在于提供一种薄膜晶体管基板，电学性能优良，适用于柔性显示器。
为实现上述目的，本发明提供一种薄膜晶体管基板的制作方法，包括以下步骤：
步骤1、提供一衬底基板，在所述衬底基板上沉积第一金属层；
步骤2、在所述第一金属层上涂布一光阻层，对所述光阻层进行图案化处理，仅保留第一光阻图案，以所述第一光阻图案为掩膜，对所述第一金属层进行阳极氧化处理，使得第一金属层上未被所述第一光阻图案覆盖的部分被氧化，转变为第一金属氧化物，被所述第一光阻图案覆盖的部分未被氧化，依旧为金属；
步骤3、从第一金属层上剥离所述第一光阻图案，继续对所述第一金属层进行阳极氧化处理，将之前被第一光阻图案覆盖的金属表面氧化，形成第一金属氧化物，使得下方未被氧化的金属形成栅极，位于所述栅极与衬底基板上方的第一金属氧化物构成栅极绝缘层；
步骤4、在所述栅极绝缘层上沉积金属氧化物半导体材料，通过一道光刻制程形成有源层；
步骤5、在所述有源层与栅极绝缘层上沉积第二金属层；
步骤6、在所述第二金属层上涂布一光阻层，对所述光阻层进行图案化处理，仅保留第二光阻图案，以所述第二光阻图案为掩膜，对所述第二金属层进行阳极氧化处理，使得第二金属层上未被所述第二光阻图案覆盖的部分被氧化，转变为第二金属氧化物，被所述第二光阻图案覆盖的部分未被氧化，依旧为金属；
步骤7、从第二金属层上剥离所述第二光阻图案，继续对所述第二金属层进行阳极氧化处理，将之前被第二光阻图案覆盖的金属表面氧化，形成第二金属氧化物，使得下方未被氧化的金属形成源极与漏极，位于所述源极、漏极、有源层、以及栅极绝缘层上方的第二金属氧化物构成钝化层；
步骤8、通过一道光刻制程在所述钝化层上对应漏极上方形成一通孔， 然后在所述钝化层上沉积一透明导电薄膜，通过一道光刻制程对所述透明导电薄膜进行图案化处理，形成像素电极，所述像素电极通过所述通孔与漏极相接触。
所述第一金属层与第二金属层的材料为铝、镁、钛、铝合金、镁合金、钛合金中的至少一种。
所述金属氧化物半导体材料为ZnO、In2O3、SnO2中的一种或多种的组合。
所述像素电极的材料为氧化铟锡或氧化铟锌。
所述步骤1通过物理气相沉积法沉积所述第一金属层；所述步骤4通过物理气相沉积法沉积所述金属氧化物半导体材料；所述步骤5通过物理气相沉积法沉积所述第二金属层；所述步骤8通过物理气相沉积法沉积所述透明导电薄膜。
所述步骤2、步骤3、步骤6、步骤7中，所述阳极氧化处理过程中采用耐腐蚀导电材料作为阴极；采用弱酸或弱碱溶液作为电解质溶液。
所述阳极氧化处理过程中采用石墨或铂作为阴极；采用柠檬酸溶液或酒石酸铵溶液作为电解质溶液。
本发明还提供一种薄膜晶体管基板，包括：衬底基板、设于所述衬底基板上的栅极、设于所述栅极及衬底基板上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层及栅极绝缘层上的源极与漏极、设于所述源极、漏极、有源层、及栅极绝缘层上的钝化层、以及设于所述钝化层上的像素电极；其中，所述栅极绝缘层的材料为栅极材料的氧化物，所述钝化层的材料为源极与漏极材料的氧化物。
所述钝化层上对应漏极上方形成有一通孔，所述像素电极通过该通孔与漏极相接触。
所述栅极、源极、及漏极的材料为铝、镁、钛、铝合金、镁合金、钛合金中的至少一种；所述有源层的材料为金属氧化物半导体材料；所述像素电极的材料为氧化铟锡或氧化铟锌。
本发明还提供一种薄膜晶体管基板的制作方法，包括以下步骤：
步骤1、提供一衬底基板，在所述衬底基板上沉积第一金属层；
步骤2、在所述第一金属层上涂布一光阻层，对所述光阻层进行图案化处理，仅保留第一光阻图案，以所述第一光阻图案为掩膜，对所述第一金属层进行阳极氧化处理，使得第一金属层上未被所述第一光阻图案覆盖的部分被氧化，转变为第一金属氧化物，被所述第一光阻图案覆盖的部分未被氧化，依旧为金属；
步骤3、从第一金属层上剥离所述第一光阻图案，继续对所述第一金属层进行阳极氧化处理，将之前被第一光阻图案覆盖的金属表面氧化，形成第一金属氧化物，使得下方未被氧化的金属形成栅极，位于所述栅极与衬底基板上方的第一金属氧化物构成栅极绝缘层；
步骤4、在所述栅极绝缘层上沉积金属氧化物半导体材料，通过一道光刻制程形成有源层；
步骤5、在所述有源层与栅极绝缘层上沉积第二金属层；
步骤6、在所述第二金属层上涂布一光阻层，对所述光阻层进行图案化处理，仅保留第二光阻图案，以所述第二光阻图案为掩膜，对所述第二金属层进行阳极氧化处理，使得第二金属层上未被所述第二光阻图案覆盖的部分被氧化，转变为第二金属氧化物，被所述第二光阻图案覆盖的部分未被氧化，依旧为金属；
步骤7、从第二金属层上剥离所述第二光阻图案，继续对所述第二金属层进行阳极氧化处理，将之前被第二光阻图案覆盖的金属表面氧化，形成第二金属氧化物，使得下方未被氧化的金属形成源极与漏极，位于所述源极、漏极、有源层、以及栅极绝缘层上方的第二金属氧化物构成钝化层；
步骤8、通过一道光刻制程在所述钝化层上对应漏极上方形成一通孔，然后在所述钝化层上沉积一透明导电薄膜，通过一道光刻制程对所述透明导电薄膜进行图案化处理，形成像素电极，所述像素电极通过所述通孔与漏极相接触；
其中，所述第一金属层与第二金属层的材料为铝、镁、钛、铝合金、镁合金、钛合金中的至少一种；
其中，所述金属氧化物半导体材料为ZnO、In2O3、SnO2中的一种或多种的组合；
其中，所述像素电极的材料为氧化铟锡或氧化铟锌。
本发明的有益效果：本发明提供一种薄膜晶体管基板的制作方法及制得的薄膜晶体管基板。本发明的薄膜晶体管基板的制作方法，利用光阻图案作为掩膜，将金属层通过阳极氧化技术直接氧化作为栅极绝缘层或钝化层，同时形成栅电极或源/漏电极图形，整个制作工艺在常温下进行，可在不耐高温的柔性基底上制作，适用于柔性显示技术，不需要耐高温的柔性基板，也不需要使用昂贵的化学气相沉积等高温制程设备，能够大大降低柔性显示器制造的工艺成本。本发明制得的薄膜晶体管基板电学性能优良，适用于柔性显示器。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本 发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为阳极氧化技术的原理示意图；
图2为本发明的薄膜晶体管基板的制作方法步骤1的示意图；
图3为本发明的薄膜晶体管基板的制作方法步骤2的示意图；
图4为本发明的薄膜晶体管基板的制作方法步骤3的示意图；
图5为本发明的薄膜晶体管基板的制作方法步骤4的示意图；
图6为本发明的薄膜晶体管基板的制作方法步骤5的示意图；
图7为本发明的薄膜晶体管基板的制作方法步骤6的示意图；
图8为本发明的薄膜晶体管基板的制作方法步骤7的示意图；
图9为本发明的薄膜晶体管基板的制作方法步骤8的示意图暨本发明的薄膜晶体管基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明的发明构思为：基于金属氧化物半导体(TOS)薄膜晶体管(TFT)的制作工艺，结合阳极氧化技术，提出一种适用于柔性显示的薄膜晶体管基板的制作方法。阳极氧化(anodic oxidation)技术，是一种金属或合金的电化学氧化技术。金属及其合金在相应的电解液和特定的工艺条件下，由于外加电流的作用下，阳极金属失去电子，使电解质溶液发生电离，发生氧化反应，在阳极金属表面形成一层氧化膜，根据阳极氧化时间的不同，可以形成数纳米至数微米厚的薄膜。
请参阅图1，为阳极氧化技术的原理示意图，如图1所示，提供一金属铝制作的阳极100、以及一石墨或金属铂制作的阴极200，在阳极100与阴极200之间连接一恒压或恒流电源300后，将阳极100与阴极200均浸泡于电解质溶液400中，所述电解质溶液400为柠檬酸溶液、酒石酸铵溶液等弱酸或弱碱溶液，对阳极100与阴极200进行通电后，阳极100发生的电化学反应为：2Al+3H2O→Al2O3+6e+6H+，阴极200发生的电化学反 应为：6H2O+6e→3H2+6OH-，由此可见，阳极100发生的反应为金属氧化反应。
基于上述阳极氧化技术，本发明设计利用光阻图案作为掩膜，将金属层通过阳极氧化技术直接氧化作为栅极绝缘层或钝化层，同时形成栅电极或源/漏电极图形，整个制作工艺在常温下进行，可在不耐高温的柔性基底上制作，甚至不需要化学气相沉积等昂贵的高温制程设备，能够大大降低柔性显示器制造的工艺成本。
请参阅图2-9，本发明首先提供一种薄膜晶体管基板的制作方法，包括以下步骤：
步骤1、如图2所示，提供一衬底基板1，在所述衬底基板1上沉积第一金属层10。
具体的，所述衬底基板1可以为柔性基板或者硬质基板。进一步的，所述柔性基板可以为有机高分子材料制作的基板；所述硬质基板可以为玻璃基板。
具体的，所述第一金属层10的材料为铝(Al)、镁(Mg)、钛(Ti)、铝合金、镁合金、钛合金中的至少一种。
具体的，通过物理气相沉积(Physical Vapor Deposition，PVD)等方法沉积所述第一金属层10。
步骤2、如图3所示，在所述第一金属层10上涂布一光阻层，对所述光阻层进行图案化处理，仅保留第一光阻图案12，以所述第一光阻图案12为掩膜，对所述第一金属层10进行阳极氧化处理，使得第一金属层10上未被所述第一光阻图案12覆盖的部分被氧化，转变为第一金属氧化物，被所述第一光阻图案12覆盖的部分未被氧化，依旧为金属。
步骤3、如图4所示，从第一金属层10上剥离所述第一光阻图案12，继续对所述第一金属层10进行阳极氧化处理，控制氧化时间，将之前被第一光阻图案12覆盖的金属表面氧化，形成第一金属氧化物，使得下方未被氧化的金属形成栅极2，位于所述栅极2与衬底基板1上方的第一金属氧化物构成栅极绝缘层3。
步骤4、如图5所示，在所述栅极绝缘层3上沉积金属氧化物半导体材料，通过一道光刻制程形成有源层(Active Layer)4。
优选的，所述金属氧化物半导体材料为ZnO、In2O3、SnO2中的一种或多种的组合。
具体的，通过物理气相沉积等方法沉积所述金属氧化物半导体材料。
具体的，所述光刻制程包括涂光阻、曝光、显影、及蚀刻过程。
步骤5、如图6所示，在所述有源层4与栅极绝缘层3上沉积第二金属层50。
具体的，所述第二金属层50的材料为铝(Al)、镁(Mg)、钛(Ti)、铝合金、镁合金、钛合金中的至少一种。
具体的，通过物理气相沉积等方法沉积所述第二金属层50。
步骤6、如图7所示，在所述第二金属层50上涂布一光阻层，对所述光阻层进行图案化处理，仅保留第二光阻图案52，以所述第二光阻图案52为掩膜，对所述第二金属层50进行阳极氧化处理，使得第二金属层50上未被所述第二光阻图案52覆盖的部分被氧化，转变为第二金属氧化物，被所述第二光阻图案52覆盖的部分未被氧化，依旧为金属。
步骤7、如图8所示，从第二金属层50上剥离所述第二光阻图案52，继续对所述第二金属层50进行阳极氧化处理，控制氧化时间，将之前被第二光阻图案52覆盖的金属表面氧化，形成第二金属氧化物，使得下方未被氧化的金属形成源极51与漏极53，位于所述源极51、漏极53、有源层4、以及栅极绝缘层3上方的第二金属氧化物构成钝化层6。
具体的，所述步骤2、步骤3、步骤6、步骤7中，所述阳极氧化处理过程中采用石墨或铂等耐腐蚀导电材料作为阴极100；采用柠檬酸溶液或酒石酸铵溶液等弱酸或弱碱溶液作为电解质溶液400。
步骤8、如图9所示，通过一道光刻制程在所述钝化层6上对应漏极53上方形成一通孔61，然后在所述钝化层6上沉积一透明导电薄膜，通过一道光刻制程对所述透明导电薄膜进行图案化处理，形成像素电极7，所述像素电极7通过所述通孔61与漏极53相接触。
具体的，所述像素电极7的材料为ITO(氧化铟锡)、或IZO(氧化铟锌)等透明导电材料。
具体的，通过物理气相沉积等方法沉积所述透明导电薄膜。
上述薄膜晶体管基板的制作方法，利用光阻图案作为掩膜，将金属层通过阳极氧化技术直接氧化作为栅极绝缘层或钝化层，同时形成栅电极或源/漏电极图形，整个制作工艺在常温下进行，可在不耐高温的柔性基底上制作，甚至不需要化学气相沉积等昂贵的高温制程设备，能够大大降低柔性显示器制造的工艺成本。
请参阅图9，本发明还提供一种薄膜晶体管基板，包括：衬底基板1、设于所述衬底基板1上的栅极2、设于所述栅极2及衬底基板1上的栅极绝缘层3、设于所述栅极绝缘层3上的有源层4、设于所述有源层4及栅极绝缘层3上的源极51与漏极53、设于所述源极51、漏极53、有源层4、及 栅极绝缘层3上的钝化层6、以及设于所述钝化层6上的像素电极7；其中，所述栅极绝缘层3的材料为栅极2材料的氧化物，所述钝化层6的材料为源极51与漏极53材料的氧化物。
具体的，所述钝化层6上对应漏极53上方形成有一通孔61，所述像素电极7通过该通孔61与漏极53相接触。
具体的，所述衬底基板1可以为柔性基板或者硬质基板。进一步的，所述柔性基板可以为有机高分子材料制作的基板；所述硬质基板可以为玻璃基板。
具体的，所述栅极2的材料为铝(Al)、镁(Mg)、钛(Ti)、铝合金、镁合金、钛合金中的至少一种。
所述有源层4的材料为金属氧化物半导体材料，优选的，所述金属氧化物半导体材料为ZnO、In2O3、或SnO2中的一种或多种的组合。
所述源极51与漏极53的材料为铝(Al)、镁(Mg)、钛(Ti)、铝合金、镁合金、钛合金中的至少一种。
具体的，所述像素电极7的材料为ITO(氧化铟锡)、或IZO(氧化铟锌)等透明导电材料。
综上所述，本发明提供一种薄膜晶体管基板的制作方法及制得的薄膜晶体管基板。本发明的薄膜晶体管基板的制作方法，利用光阻图案作为掩膜，将金属层通过阳极氧化技术直接氧化作为栅极绝缘层或钝化层，同时形成栅电极或源/漏电极图形，整个制作工艺在常温下进行，可在不耐高温的柔性基底上制作，甚至不需要化学气相沉积等昂贵的高温制程设备，能够大大降低柔性显示器制造的工艺成本。本发明制得的薄膜晶体管基板电学性能优良，适用于柔性显示器。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (14)

  1. 一种薄膜晶体管基板的制作方法，包括以下步骤：
    步骤1、提供一衬底基板，在所述衬底基板上沉积第一金属层；
    步骤2、在所述第一金属层上涂布一光阻层，对所述光阻层进行图案化处理，仅保留第一光阻图案，以所述第一光阻图案为掩膜，对所述第一金属层进行阳极氧化处理，使得第一金属层上未被所述第一光阻图案覆盖的部分被氧化，转变为第一金属氧化物，被所述第一光阻图案覆盖的部分未被氧化，依旧为金属；
    步骤3、从第一金属层上剥离所述第一光阻图案，继续对所述第一金属层进行阳极氧化处理，将之前被第一光阻图案覆盖的金属表面氧化，形成第一金属氧化物，使得下方未被氧化的金属形成栅极，位于所述栅极与衬底基板上方的第一金属氧化物构成栅极绝缘层；
    步骤4、在所述栅极绝缘层上沉积金属氧化物半导体材料，通过一道光刻制程形成有源层；
    步骤5、在所述有源层与栅极绝缘层上沉积第二金属层；
    步骤6、在所述第二金属层上涂布一光阻层，对所述光阻层进行图案化处理，仅保留第二光阻图案，以所述第二光阻图案为掩膜，对所述第二金属层进行阳极氧化处理，使得第二金属层上未被所述第二光阻图案覆盖的部分被氧化，转变为第二金属氧化物，被所述第二光阻图案覆盖的部分未被氧化，依旧为金属；
    步骤7、从第二金属层上剥离所述第二光阻图案，继续对所述第二金属层进行阳极氧化处理，将之前被第二光阻图案覆盖的金属表面氧化，形成第二金属氧化物，使得下方未被氧化的金属形成源极与漏极，位于所述源极、漏极、有源层、以及栅极绝缘层上方的第二金属氧化物构成钝化层；
    步骤8、通过一道光刻制程在所述钝化层上对应漏极上方形成一通孔，然后在所述钝化层上沉积一透明导电薄膜，通过一道光刻制程对所述透明导电薄膜进行图案化处理，形成像素电极，所述像素电极通过所述通孔与漏极相接触。
  2. 如权利要求1所述的薄膜晶体管基板的制作方法，其中，所述第一金属层与第二金属层的材料为铝、镁、钛、铝合金、镁合金、钛合金中的至少一种。
  3. 如权利要求1所述的薄膜晶体管基板的制作方法，其中，所述金属 氧化物半导体材料为ZnO、In2O3、SnO2中的一种或多种的组合。
  4. 如权利要求1所述的薄膜晶体管基板的制作方法，其中，所述像素电极的材料为氧化铟锡或氧化铟锌。
  5. 如权利要求1所述的薄膜晶体管基板的制作方法，其中，所述步骤1通过物理气相沉积法沉积所述第一金属层；所述步骤4通过物理气相沉积法沉积所述金属氧化物半导体材料；所述步骤5通过物理气相沉积法沉积所述第二金属层；所述步骤8通过物理气相沉积法沉积所述透明导电薄膜。
  6. 如权利要求1所述的薄膜晶体管基板的制作方法，其中，所述步骤2、步骤3、步骤6、步骤7中，所述阳极氧化处理过程中采用耐腐蚀导电材料作为阴极；采用弱酸或弱碱溶液作为电解质溶液。
  7. 如权利要求6所述的薄膜晶体管基板的制作方法，其中，所述阳极氧化处理过程中采用石墨或铂作为阴极；采用柠檬酸溶液或酒石酸铵溶液作为电解质溶液。
  8. 一种薄膜晶体管基板，包括：衬底基板、设于所述衬底基板上的栅极、设于所述栅极及衬底基板上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层及栅极绝缘层上的源极与漏极、设于所述源极、漏极、有源层、及栅极绝缘层上的钝化层、以及设于所述钝化层上的像素电极；其中，所述栅极绝缘层的材料为栅极材料的氧化物，所述钝化层的材料为源极与漏极材料的氧化物。
  9. 如权利要求8所述的薄膜晶体管基板，其中，所述钝化层上对应漏极上方形成有一通孔，所述像素电极通过该通孔与漏极相接触。
  10. 如权利要求8所述的薄膜晶体管基板，其中，所述栅极、源极、及漏极的材料为铝、镁、钛、铝合金、镁合金、钛合金中的至少一种；所述有源层的材料为金属氧化物半导体材料；所述像素电极的材料为氧化铟锡或氧化铟锌。
  11. 一种薄膜晶体管基板的制作方法，包括以下步骤：
    步骤1、提供一衬底基板，在所述衬底基板上沉积第一金属层；
    步骤2、在所述第一金属层上涂布一光阻层，对所述光阻层进行图案化处理，仅保留第一光阻图案，以所述第一光阻图案为掩膜，对所述第一金属层进行阳极氧化处理，使得第一金属层上未被所述第一光阻图案覆盖的部分被氧化，转变为第一金属氧化物，被所述第一光阻图案覆盖的部分未被氧化，依旧为金属；
    步骤3、从第一金属层上剥离所述第一光阻图案，继续对所述第一金属层进行阳极氧化处理，将之前被第一光阻图案覆盖的金属表面氧化，形成 第一金属氧化物，使得下方未被氧化的金属形成栅极，位于所述栅极与衬底基板上方的第一金属氧化物构成栅极绝缘层；
    步骤4、在所述栅极绝缘层上沉积金属氧化物半导体材料，通过一道光刻制程形成有源层；
    步骤5、在所述有源层与栅极绝缘层上沉积第二金属层；
    步骤6、在所述第二金属层上涂布一光阻层，对所述光阻层进行图案化处理，仅保留第二光阻图案，以所述第二光阻图案为掩膜，对所述第二金属层进行阳极氧化处理，使得第二金属层上未被所述第二光阻图案覆盖的部分被氧化，转变为第二金属氧化物，被所述第二光阻图案覆盖的部分未被氧化，依旧为金属；
    步骤7、从第二金属层上剥离所述第二光阻图案，继续对所述第二金属层进行阳极氧化处理，将之前被第二光阻图案覆盖的金属表面氧化，形成第二金属氧化物，使得下方未被氧化的金属形成源极与漏极，位于所述源极、漏极、有源层、以及栅极绝缘层上方的第二金属氧化物构成钝化层；
    步骤8、通过一道光刻制程在所述钝化层上对应漏极上方形成一通孔，然后在所述钝化层上沉积一透明导电薄膜，通过一道光刻制程对所述透明导电薄膜进行图案化处理，形成像素电极，所述像素电极通过所述通孔与漏极相接触；
    其中，所述第一金属层与第二金属层的材料为铝、镁、钛、铝合金、镁合金、钛合金中的至少一种；
    其中，所述金属氧化物半导体材料为ZnO、In2O3、SnO2中的一种或多种的组合；
    其中，所述像素电极的材料为氧化铟锡或氧化铟锌。
  12. 如权利要求11所述的薄膜晶体管基板的制作方法，其中，所述步骤1通过物理气相沉积法沉积所述第一金属层；所述步骤4通过物理气相沉积法沉积所述金属氧化物半导体材料；所述步骤5通过物理气相沉积法沉积所述第二金属层；所述步骤8通过物理气相沉积法沉积所述透明导电薄膜。
  13. 如权利要求11所述的薄膜晶体管基板的制作方法，其中，所述步骤2、步骤3、步骤6、步骤7中，所述阳极氧化处理过程中采用耐腐蚀导电材料作为阴极；采用弱酸或弱碱溶液作为电解质溶液。
  14. 如权利要求13所述的薄膜晶体管基板的制作方法，其中，所述阳极氧化处理过程中采用石墨或铂作为阴极；采用柠檬酸溶液或酒石酸铵溶液作为电解质溶液。
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CN104979406B (zh) * 2015-07-31 2018-05-25 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制备方法和显示装置
CN105529275A (zh) * 2016-02-03 2016-04-27 京东方科技集团股份有限公司 薄膜晶体管及其制造方法
CN106024638A (zh) * 2016-07-20 2016-10-12 深圳市华星光电技术有限公司 薄膜晶体管及其制作方法
CN108172612B (zh) * 2016-12-07 2020-07-10 清华大学 一种薄膜晶体管及其制备方法
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CN107086181B (zh) * 2017-04-18 2021-08-13 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板和显示器
CN107331708B (zh) * 2017-06-30 2020-06-16 京东方科技集团股份有限公司 薄膜晶体管的制作方法、阵列基板的制作方法及阵列基板、显示装置
CN107910375A (zh) * 2017-11-02 2018-04-13 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置
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CN109887930A (zh) * 2019-02-20 2019-06-14 深圳市华星光电技术有限公司 显示面板及其制作方法
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CN111146277A (zh) * 2020-01-02 2020-05-12 歌尔股份有限公司 场效应晶体管及其制备方法
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CN112114460B (zh) 2020-09-23 2022-12-23 北海惠科光电技术有限公司 基于阵列基板的绝缘单元及其制备方法、阵列基板及其制备方法、显示机构
CN112466931A (zh) * 2020-11-27 2021-03-09 Tcl华星光电技术有限公司 电极结构及其制备方法、薄膜晶体管

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6569719B2 (en) * 1993-07-07 2003-05-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for producing the same
CN101894846A (zh) * 2009-05-21 2010-11-24 友达光电股份有限公司 电泳式显示器、主动元件阵列背板及其制造方法
CN102332404A (zh) * 2011-09-21 2012-01-25 华南理工大学 基于阳极氧化绝缘层的薄膜晶体管的制备方法
CN102522429A (zh) * 2011-12-28 2012-06-27 华南理工大学 一种基于金属氧化物的薄膜晶体管及其制备方法和应用

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10242469A (ja) * 1997-02-27 1998-09-11 Sharp Corp 薄膜トランジスタの製造方法
JP4550944B2 (ja) * 2008-11-18 2010-09-22 パナソニック株式会社 フレキシブル半導体装置およびその製造方法
DE112010003143T5 (de) * 2009-07-31 2012-06-14 National University Corporation Tohoku University Halbleitervorrichtung, Verfahren zum Herstellen einer Halbleitervorrichtung, und Anzeigevorrichtung
KR101351219B1 (ko) * 2010-04-06 2014-01-13 가부시키가이샤 히타치세이사쿠쇼 박막 트랜지스터 및 그 제조 방법
CN102629628B (zh) * 2011-09-29 2016-06-01 京东方科技集团股份有限公司 一种tft阵列基板及其制造方法和液晶显示器
KR20140125181A (ko) * 2013-04-18 2014-10-28 삼성디스플레이 주식회사 평판표시장치용 백플레인 및 그의 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6569719B2 (en) * 1993-07-07 2003-05-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for producing the same
CN101894846A (zh) * 2009-05-21 2010-11-24 友达光电股份有限公司 电泳式显示器、主动元件阵列背板及其制造方法
CN102332404A (zh) * 2011-09-21 2012-01-25 华南理工大学 基于阳极氧化绝缘层的薄膜晶体管的制备方法
CN102522429A (zh) * 2011-12-28 2012-06-27 华南理工大学 一种基于金属氧化物的薄膜晶体管及其制备方法和应用

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