CN108172612B - 一种薄膜晶体管及其制备方法 - Google Patents

一种薄膜晶体管及其制备方法 Download PDF

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CN108172612B
CN108172612B CN201611114618.6A CN201611114618A CN108172612B CN 108172612 B CN108172612 B CN 108172612B CN 201611114618 A CN201611114618 A CN 201611114618A CN 108172612 B CN108172612 B CN 108172612B
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thin film
film transistor
layer
dielectric layer
substrate
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CN108172612A (zh
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赵宇丹
霍雨佳
肖小阳
王营城
张天夫
金元浩
李群庆
范守善
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Tsinghua University
Hongfujin Precision Industry Shenzhen Co Ltd
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Tsinghua University
Hongfujin Precision Industry Shenzhen Co Ltd
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Priority to CN201611114618.6A priority Critical patent/CN108172612B/zh
Priority to TW105141975A priority patent/TWI633048B/zh
Priority to US15/817,499 priority patent/US20180158904A1/en
Priority to JP2017235415A priority patent/JP6648098B2/ja
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Abstract

本发明涉及一种薄膜晶体管及其制备方法。该薄膜晶体管包括；一基底；一栅极，所述栅极设置于所述基底的一表面；一电介质层，所述电介质层设置于所述基底上且将所述栅极覆盖；一半导体层，所述半导体层设置于所述电介质层远离所述基底的表面，且所述半导体层包括多个纳米半导体材料；一源极和一漏极，所述源极和漏极间隔设置于所述电介质层远离所述基底的一侧，且分别与所述半导体层电连接；其中，所述电介质层为采用磁控溅射法制备的氧化物层，且与所述栅极直接接触。本发明的薄膜晶体管具有反常迟滞曲线。

Description

一种薄膜晶体管及其制备方法
技术领域
本发明涉及一种薄膜晶体管，尤其涉及一种采用纳米材料作为半导体层的薄膜晶体管。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)是现代微电子技术中的一种关键性电子元件，目前已经被广泛的应用于平板显示器等领域。薄膜晶体管主要包括基底、栅极、电介质层、半导体层、源极和漏极。
对于半导体型单壁碳纳米管(SWCNT)或二维半导体材料(如MoS2)作为半导体层的薄膜晶体管，由于沟道层与电介质层间的界面态，或电介质层中的缺陷，会束缚电荷，从而在器件的转移特性曲线上会表现出迟滞曲线的特性。具体表现为栅极电压VG从负向扫至正向，和正向扫至负向的沟道层的漏电流ID曲线不重合，即在开关电流相同的情况下，阈值电压的不同。传统电介质层通常为ALD生长、电子束蒸发、热氧化、PECVD等方法制备的Al2O3层、SiO2层、HfO2层以及Si3N4层等。
发明人研究发现，采用磁控溅射法制备的氧化物材料作为电介质层得到的迟滞曲线与采用传统电介质层得到的迟滞曲线方向相反。本发明定义传统电介质材料为正常迟滞材料，采用磁控溅射法制备的氧化物材料为反常迟滞材料。进一步，发明人研究发现，采用正常迟滞材料和反常迟滞材料的双层电介质层结构可以减小甚至消除迟滞曲线。而采用减小或消除迟滞曲线的薄膜晶体管具有一些优异的电学性能。
发明内容
有鉴于此，确有必要提供一种具有反常迟滞曲线的薄膜晶体管及其制备方法。
一种薄膜晶体管，其包括；一基底；一栅极，所述栅极设置于所述基底的一表面；一电介质层，所述电介质层设置于所述基底上且将所述栅极覆盖；一半导体层，所述半导体层设置于所述电介质层远离所述基底的表面，且所述半导体层包括多个纳米半导体材料；一源极和一漏极，所述源极和漏极间隔设置于所述电介质层远离所述基底的一侧，且分别与所述半导体层电连接；其中，所述电介质层为采用磁控溅射法制备的氧化物层，且与所述栅极直接接触。
一种薄膜晶体管的制备方法，该方法包括：提供一基底；在所述基底表面沉积一栅极；在所述基底表面采用磁控溅射法制备一氧化物层作为电介质层，且所述氧化物层将所述栅极覆盖且与所述栅极直接接触；在所述电介质层表面制备一半导体层，所述半导体层包括多个纳米材料；在所述电介质层表面制备源极和漏极，且所述源极和漏极与所述半导体层电连接。
相较于现有技术，本发明的薄膜晶体管采用电介质层为采用磁控溅射法制备的氧化物层，且与所述栅极直接接触，因此，该薄膜晶体管具有反常迟滞曲线。
附图说明
图1为本发明实施例1提供的薄膜晶体管的结构示意图。
图2为本发明实施例1的比较例1的薄膜晶体管的迟滞曲线测试结果。
图3为本发明实施例1的比较例2的薄膜晶体管的迟滞曲线测试结果。
图4为本发明实施例1的比较例3的薄膜晶体管的迟滞曲线测试结果。
图5为本发明实施例1的比较例4的薄膜晶体管的迟滞曲线测试结果。
图6为本发明实施例1提供的薄膜晶体管的迟滞曲线测试结果。
图7为本发明实施例2提供的薄膜晶体管的结构示意图。
图8为本发明实施例2的比较例5的薄膜晶体管的迟滞曲线测试结果。
图9为本发明实施例2的比较例6的薄膜晶体管的迟滞曲线测试结果。
图10为本发明实施例2提供的薄膜晶体管的迟滞曲线测试结果。
图11为本发明实施例3提供的薄膜晶体管的结构示意图。
图12为本发明实施例3的比较例7的薄膜晶体管的迟滞曲线测试结果。
图13为本发明实施例3提供的薄膜晶体管的迟滞曲线测试结果。
图14为本发明实施例3提供的薄膜晶体管的迟滞曲线消除的稳定性进行测试结果。
图15为本发明实施例4的比较例8的薄膜晶体管的迟滞曲线测试结果。
图16为本发明实施例4提供的薄膜晶体管的迟滞曲线测试结果。
图17为本发明实施例5提供的薄膜晶体管的结构示意图。
图18为本发明实施例5的比较例9的薄膜晶体管的迟滞曲线测试结果。
图19为本发明实施例5提供的薄膜晶体管的迟滞曲线测试结果。
图20为本发明实施例5的比较例9的薄膜晶体管的输出特性测试结果。
图21为本发明实施例5提供的薄膜晶体管的输出特性测试结果。
图22为本发明实施例6的比较例10的薄膜晶体管的迟滞曲线测试结果。
图23为本发明实施例6的比较例11的薄膜晶体管的迟滞曲线测试结果。
图24为本发明实施例6提供的薄膜晶体管的迟滞曲线测试结果。
图25为本发明实施例7的比较例12的薄膜晶体管的迟滞曲线测试结果。
图26为本发明实施例7提供的薄膜晶体管的迟滞曲线测试结果。
图27为本发明实施例8的比较例14的薄膜晶体管的迟滞曲线测试结果。
图28为本发明实施例8提供的薄膜晶体管的迟滞曲线测试结果。
图29为本发明实施例9的比较例15的薄膜晶体管的迟滞曲线测试结果。
图30为本发明实施例9的比较例16的薄膜晶体管的迟滞曲线测试结果。
图31为本发明实施例9提供的薄膜晶体管的迟滞曲线测试结果。
图32为本发明实施例10的比较例17的薄膜晶体管的迟滞曲线测试结果。
图33为本发明实施例10提供的薄膜晶体管的迟滞曲线测试结果。
图34为本发明实施例11提供的薄膜晶体管的迟滞曲线测试结果。
图35为本发明实施例12提供的逻辑电路的结构示意图。
图36为本发明实施例12的比较例18的逻辑电路的输入输出特性曲线。
图37为本发明实施例12提供的逻辑电路的输入输出特性曲线。
图38为本发明实施例12和比较例18的逻辑电路的在输入频率为0.1kHz的频率输出响应结果。
图39为本发明实施例12和比较例18的逻辑电路的在输入频率为1kHz的频率输出响应结果。
图40为图39的单一周期的频率输出波形的放大图。
图41为本发明实施例13提供的逻辑电路的结构示意图。
图42为本发明实施例14提供的逻辑电路的结构示意图。
主要元件符号说明
逻辑电路 10,10A,10B
薄膜晶体管 100,100A,100B,100C
基底 101
栅极 102
电介质层 103,103a,103b
第一子电介质层 1031,1031a,1031b
第二子电介质层 1032,1032a,1032b
半导体层 104,104a,104b
源极 105,105a,105b
漏极 106,106a,106b
具体实施方式
下面将结合附图及具体实施例对本发明作进一步的详细说明。
实施例1
请参阅图1，本发明实施例1提供一种薄膜晶体管100，所述薄膜晶体管100为底栅型，其包括一基底101、一栅极102、一电介质层103、一半导体层104、一源极105和一漏极106。所述栅极102设置于所述基底101的一表面。所述电介质层103设置于所述基底101上且将所述栅极102覆盖。所述半导体层104设置于所述电介质层103远离所述基底101的表面。所述源极105和漏极106间隔设置于所述电介质层103远离所述基底101的一侧，且分别与所述半导体层104电连接。所述半导体层104位于所述源极105和漏极106之间的部分形成一沟道层。
所述基底101用于支撑所述栅极102、电介质层103、半导体层104、源极105和漏极106。所述基底101的尺寸和形状不限，可以根据需要选择。所述基底101的材料可以为绝缘材料，例如玻璃、聚合物、陶瓷或石英等。所述基底101也可以为设置有绝缘层的半导体基底或导电基底。本实施例中，所述基底101为一具有二氧化硅绝缘层的硅片。
所述电介质层103为采用磁控溅射法制备的氧化物层，且与所述栅极102直接接触。所述电介质层103的厚度为10纳米～1000纳米。所述氧化物可以为金属氧化物，例如，Al2O3，也可以为硅氧化物，例如，SiO2。本实施例中，所述电介质层103为采用磁控溅射法制备的厚度40纳米的SiO2层。
所述半导体层104包括多个纳米半导体材料。所述纳米半导体材料可以为石墨烯、碳纳米管、MoS2、WS2、MnO2、ZnO、MoSe2、MoTe2、TaSe2、NiTe2、Bi2Te3等。所述纳米半导体材料通过生长、转移、沉积或旋涂等方法形成于所述电介质层103表面。所述半导体层104为单层或少层纳米半导体材料，例如1～5层。本实施例中，所述半导体层104为通过沉积单壁碳纳米管形成单壁碳纳米管网络制备而成。
所述栅极102、源极105和漏极106由导电材料制备，其制备方法可以为化学蒸镀、电子束蒸发、热沉积或磁控溅射等。优选地，所述栅极102、源极105和漏极106为一层导电薄膜。该导电薄膜的厚度为0.5纳米～100微米。该导电薄膜的材料为金属，如铝、铜、钨、钼、金、钛、钕、钯、铯等。可以理解，所述栅极102、源极105和漏极106的材料也可为导电浆料、ITO、碳纳米管或石墨烯等。本实施例中，所述栅极102、源极105和漏极106的材料为钛金复合金属层，厚度为40纳米。
所述薄膜晶体管100的制备方法包括以下步骤：
步骤S11，提供一基底101；
步骤S12，在所述基底101表面沉积一栅极102；
步骤S13，在所述基底101表面采用磁控溅射法制备一氧化物层作为电介质层103，且所述氧化物层将所述栅极102覆盖且与所述栅极102直接接触；
步骤S14，在所述电介质层103表面制备一半导体层104，所述半导体层104包括多个纳米材料；
步骤S15，在所述电介质层103表面制备源极105和漏极106，且所述源极105和漏极106与所述半导体层104电连接。
本实施例中，所述步骤S13中，在所述基底101表面采用磁控溅射法制备SiO2层。所述磁控溅射的溅射靶与样品距离可以为50毫米～120毫米，溅射前的真空度为小于10-5Pa，溅射的功率可以为150瓦～200瓦，载气为氩气，溅射时的压强可以为0.2帕～1帕。本实施例分别采用不同的工艺参数制备厚度为10纳米、20纳米、100纳米、500纳米、1000纳米的SiO2层作为电介质层103，结果均表明采用磁控溅射法制备SiO2层为反常迟滞材料。
为了研究采用磁控溅射法制备的SiO2层作为电介质层103对所述薄膜晶体管100的迟滞曲线的反常影响，本实施例还分别制备了采用正常迟滞材料的比较例1-4。比较例与本实施例的区别仅为所述电介质层103的材料和制备方法。其中，比较例1采用电子束蒸发20纳米SiO2层作为电介质层103，比较例2采用电子束蒸发20纳米Al2O3层作为电介质层103，比较例3采用ALD法沉积20纳米Al2O3层作为电介质层103，比较例3采用ALD法沉积20纳米HfO2层作为电介质层103。比较结果参见表1。
表1实施例1与比较例的工艺参数以及测试结果对比
Figure GDA0002405428030000061
本实施例的薄膜晶体管100进行测量时，所述半导体层104暴露在空气中。比较例1-4以及本实施例的薄膜晶体管100均为P型。参见图2-6，分别为比较例1-4以及本实施例的薄膜晶体管100的迟滞曲线测试结果。其中，图2-5分别给出了多个比较样品的测试结果。进一步参见表1可见，比较例1-4的薄膜晶体管100的迟滞曲线均表现为逆时针，而本实施例的薄膜晶体管100的迟滞曲线表现为顺时针。由比较例1和本实施例可知，在底栅型薄膜晶体管100中，采用磁控溅射法制备的SiO2层作为电介质层103可以得到反常迟滞曲线。
实施例2
请参阅图7，本发明实施例2提供一种薄膜晶体管100A，其包括一基底101、一栅极102、一电介质层103、一半导体层104、一源极105和一漏极106。所述半导体层104设置于所述基底101的一表面。所述源极105和漏极106间隔设置于所述基底101上，且分别与所述半导体层104电连接。所述半导体层104位于所述源极105和漏极106之间的部分形成一沟道层。所述电介质层103设置于所述半导体层104远离所述基底101的表面，且将所述半导体层104、源极105和漏极106覆盖。所述栅极102设置于所述电介质层103远离所述基底101的表面。
本发明实施例2的薄膜晶体管100A与本发明实施例1的薄膜晶体管100结构基本相同，其区别为，所述薄膜晶体管100A为顶栅型。所述薄膜晶体管100A的制备方法包括以下步骤：
步骤S21，提供一基底101；
步骤S22，在所述基底101表面制备一半导体层104，所述半导体层104包括多个纳米材料；
步骤S23，在所述基底101上制备源极105和漏极106，且所述源极105和漏极106与所述半导体层104电连接；
步骤S24，在所述半导体层104远离所述基底101的表面采用磁控溅射法制备一氧化物层作为电介质层103，且所述氧化物层将所述半导体层104、源极105和漏极106覆盖；
步骤S25，在所述电介质层103远离所述基底101的表面制备一栅极102，且所述栅极102与所述电介质层103直接接触。
为了研究采用磁控溅射法制备的SiO2层作为电介质层103对所述薄膜晶体管100A的迟滞曲线的影响，本实施例还分别制备了采用正常迟滞材料的比较例5-6。比较例与本实施例的区别仅为所述电介质层103的材料和制备方法。其中，比较例5采用电子束蒸发20纳米SiO2层作为电介质层103，比较例6采用热氧化法制备20纳米Y2O3层作为电介质层103。比较结果参见表2。
表2实施例2与比较例的工艺参数以及测试结果对比
Figure GDA0002405428030000081
本实施例的薄膜晶体管100A进行测量。比较例5-6以及本实施例的薄膜晶体管100A为P型。参见图8-9，比较例5-6的薄膜晶体管100A的迟滞曲线表现为逆时针。参见图10，本实施例的薄膜晶体管100A的迟滞曲线表现为顺时针，即迟滞反常。由比较例5-6和本实施例可知，在顶栅型薄膜晶体管100A中，采用磁控溅射法制备的SiO2层作为电介质层103可以得到反常迟滞曲线，而且保持薄膜晶体管100A的极性不变。
实施例3
请参阅图11，本发明实施例3提供一种薄膜晶体管100B，其包括一基底101、一栅极102、一电介质层103、一半导体层104、一源极105和一漏极106。所述栅极102设置于所述基底101的一表面。所述电介质层103设置于所述基底101上且将所述栅极102覆盖。所述半导体层104设置于所述电介质层103远离所述基底101的表面。所述源极105和漏极106间隔设置于所述电介质层103远离所述基底101的一侧，且分别与所述半导体层104电连接。所述半导体层104位于所述源极105和漏极106之间的部分形成一沟道层。所述薄膜晶体管100B也为底栅型。
本发明实施例3的薄膜晶体管100B与本发明实施例1的薄膜晶体管100结构基本相同，其区别为，所述电介质层103为双层结构，其包括层叠设置的第一子电介质层1031和第二子电介质层1032。所述第一子电介质层1031为反常迟滞材料层，即采用磁控溅射法制备的SiO2层。所述第二子电介质层1032为正常迟滞材料层。所述薄膜晶体管100B的制备方法包括以下步骤：
步骤S31，提供一基底101；
步骤S32，在所述基底101表面沉积一栅极102；
步骤S33，在所述基底101表面采用磁控溅射法制备一SiO2层作为第一子电介质层1031，且所述SiO2层将所述栅极102覆盖且与所述栅极102直接接触；
步骤S34，在所述第一子电介质层1031表面制备一正常迟滞材料层作为第二子电介质层1032，从而得到一双层结构的电介质层103；
步骤S35，在所述电介质层103表面制备一半导体层104，所述半导体层104包括多个纳米材料；
步骤S36，在所述电介质层103表面制备源极105和漏极106，且所述源极105和漏极106与所述半导体层104电连接。
本实施例中，所述第二子电介质层1032的正常迟滞材料层为采用ALD法沉积的20纳米厚的Al2O3层。为了研究采用磁控溅射法制备的SiO2反常迟滞材料层对正常迟滞材料层的迟滞曲线的影响，本实施例还还制备比较例7。比较例7与本实施例的区别仅为：所述第一子电介质层1031为采用ALD法沉积的20纳米厚的Al2O3正常迟滞材料，而第二子电介质层1032为反常迟滞材料层。比较结果参见表3。
表3实施例3与比较例的工艺参数以及测试结果对比
Figure GDA0002405428030000091
本实施例的薄膜晶体管100B进行测量。比较例7以及本实施例的薄膜晶体管100B均为P型。参见图12和图4可见，比较例7的薄膜晶体管的迟滞曲线与比较例3的薄膜晶体管的迟滞曲线基本相同。由此可见，比较例7中，采用磁控溅射法制备的SiO2对薄膜晶体管的迟滞曲线几乎没有影响。参见图13，实施例3的薄膜晶体管100B的迟滞曲线被明显减小甚至消除。对比比较例7和实施例3可见，只有当反常迟滞材料层直接与栅极102接触，起到调制沟道层作用时，所述反常迟滞材料层才会产生反常迟滞曲线。实施例3中，所述反常迟滞材料层的顺时针迟滞曲线与正常迟滞材料层的逆时针迟滞曲线相互抵消，从而起到消除薄膜晶体管的迟滞曲线的作用。
进一步，本发明对实施例3的薄膜晶体管100B的迟滞曲线消除的稳定性进行测试。参见图14，60天之后，实施例3的薄膜晶体管100B的迟滞曲线与之前基本吻合。由此可见，该结构可以稳定消除TFT迟滞曲线。
实施例4
本发明实施例4的薄膜晶体管100B与本发明实施例3的薄膜晶体管100B结构基本相同，其区别为，所述第一子电介质层1031为反常迟滞材料层，采用磁控溅射法制备的SiO2层；所述第二子电介质层1032为正常迟滞材料层，采用电子束蒸发法制备的SiO2层。
本实施例还还制备比较例8。比较例8与本实施例的区别仅为：所述第一子电介质层1031为正常迟滞材料，而第二子电介质层1032为反常迟滞材料层。比较结果参见表4。
表4实施例4与比较例的工艺参数以及测试结果对比
Figure GDA0002405428030000101
本实施例的薄膜晶体管100B进行测量。比较例8以及本实施例的薄膜晶体管100B均为P型。参见图15，比较例8的薄膜晶体管具有明显的迟滞曲线。参见图16，实施例4的薄膜晶体管100B的迟滞曲线被明显减小甚至消除。由本实施例、比较例1和比较例8可以看出，电子束蒸镀制备SiO2为正常迟滞材料，而采用磁控溅射法制备的SiO2层为反常迟滞材料。而且，只有当反常迟滞材料层直接与栅极102接触，起到调制沟道层作用时，所述反常迟滞材料层才会产生反常迟滞曲线。
实施例5
请参阅图17，本发明实施例5提供一种薄膜晶体管100C，其包括一基底101、一栅极102、一电介质层103、一半导体层104、一源极105和一漏极106。所述半导体层104设置于所述基底101的一表面。所述源极105和漏极106间隔设置于所述基底101上，且分别与所述半导体层104电连接。所述半导体层104位于所述源极105和漏极106之间的部分形成一沟道层。所述电介质层103设置于所述半导体层104远离所述基底101的表面，且将所述半导体层104、源极105和漏极106覆盖。所述栅极102设置于所述电介质层103远离所述基底101的表面。所述薄膜晶体管100C为顶栅型。
本发明实施例5的薄膜晶体管100C与本发明实施例2的薄膜晶体管100A结构基本相同，其区别为，所述电介质层103为双层结构，其包括层叠设置的第一子电介质层1031和第二子电介质层1032。所述第一子电介质层1031为反常迟滞材料层，即采用磁控溅射法制备的SiO2层。所述第二子电介质层1032为正常迟滞材料层。所述薄膜晶体管100C的制备方法包括以下步骤：
步骤S51，提供一基底101；
步骤S52，在所述基底101表面制备一半导体层104，所述半导体层104包括多个纳米材料；
步骤S53，在所述基底101上制备源极105和漏极106，且所述源极105和漏极106与所述半导体层104电连接；
步骤S54，在所述半导体层104远离所述基底101的表面制备一正常迟滞材料层作为第二子电介质层1032，所述第二子电介质层1032将所述半导体层104、源极105和漏极106覆盖；
步骤S55，在所述第二子电介质层1032远离所述基底101的表面采用磁控溅射法制备一SiO2层作为第一子电介质层1031，所述第一子电介质层1031将所述第二子电介质层1032覆盖，从而形成电介质层103；
步骤S56，在所述电介质层103远离所述基底101的表面制备一栅极102，且所述栅极102与所述第一子电介质层1031直接接触。
本实施例中，所述第二子电介质层1032的正常迟滞材料层为采用热氧化法制备5纳米Y2O3层。为了研究采用磁控溅射法制备的SiO2反常迟滞材料层对正常迟滞材料层的迟滞曲线的影响，本实施例还还制备比较例9。比较例9与本实施例的区别仅为：所述第一子电介质层1031为采用热氧化法制备的20纳厚度的Y2O3正常迟滞材料，而第二子电介质层1032为反常迟滞材料层。比较结果参见表5。
表5实施例5与比较例的工艺参数以及测试结果对比
Figure GDA0002405428030000121
本实施例的薄膜晶体管100C进行测量。比较例9以及本实施例的薄膜晶体管100C为P型。参见图18，比较例9的薄膜晶体管具有明显的迟滞曲线。参见图19，当采用磁控溅射法制备的SiO2反常迟滞材料层与所述栅极102直接接触设置时，薄膜晶体管100C的迟滞曲线被明显减小甚至消除。
进一步，对比较例9以及本实施例的薄膜晶体管100C的输出特性进行测试。输出特性曲线为一组随着栅极电压VG不同，导致漏电流ID随漏电压VD变化的曲线。参见图20，对比较例9的薄膜晶体管100C，由于具有迟滞，VG从0V扫描至-3V，与从-3V扫描至0V，在相同的VG下(相同线条)曲线不重合。参见图21，对本实施例的薄膜晶体管100C，有于没有迟滞，即使VG的扫描方向不同，其对应的ID-VD曲线是基本重合的。这对于TFT在逻辑电路、传感器等方面的应用是很重要的。
实施例6
本发明实施例6的薄膜晶体管100C与本发明实施例5的薄膜晶体管100C结构基本相同，其区别为，所述第一子电介质层1031为反常迟滞材料层，采用磁控溅射法制备的SiO2层；所述第二子电介质层1032为正常迟滞材料层，采用ALD法制备的Al2O3层。由于隔绝空气和固定电荷掺杂，实施例6的薄膜晶体管100C成为双极型。
本实施例还还制备比较例10-11。比较例10与本实施例的区别仅为：所述电介质层103为如图7所示的单层结构，且所述电介质层103也为采用ALD法制备的Al2O3层。比较例11与本实施例的区别仅为：所述第一子电介质层1031为正常迟滞材料，而第二子电介质层1032为反常迟滞材料层。比较结果参见表6。
表6实施例6与比较例的工艺参数以及测试结果对比
Figure GDA0002405428030000131
本实施例的薄膜晶体管100C进行测量。比较例10-11以及本实施例的薄膜晶体管100C为双极型。参见图22和图23，当采用磁控溅射法制备的SiO2反常迟滞材料层与所述栅极102间隔设置时，对薄膜晶体管的迟滞曲线几乎没有影响。参见图24，当采用磁控溅射法制备的SiO2反常迟滞材料层与所述栅极102直接接触设置时，薄膜晶体管100C的迟滞曲线被明显减小甚至消除。
实施例7
本发明实施例7的薄膜晶体管100C与本发明实施例5的薄膜晶体管100C结构基本相同，其区别为，所述第一子电介质层1031为反常迟滞材料层，采用磁控溅射法制备的SiO2层；所述第二子电介质层1032为正常迟滞材料层，采用PECVD法制备的Si3N4层。
本实施例还还制备比较例12-13。比较例12与本实施例的区别仅为：所述电介质层103为如图7所示的单层结构，且所述电介质层103也为采用PECVD法制备的Si3N4层。比较例13与本实施例的区别仅为：所述第一子电介质层1031为正常迟滞材料，而第二子电介质层1032为反常迟滞材料层。
比较结果参见表7。
表7实施例7与比较例的工艺参数以及测试结果对比
Figure GDA0002405428030000141
本实施例的薄膜晶体管100C进行测量。比较例12和本实施例的薄膜晶体管100C为N型。比较例13的薄膜晶体管为双极型。由于比较例13的结构无法得到N型薄膜晶体管，因此，本实施例与比较例13的迟滞曲线没有比较意义。由于P型和N型的区别，导致P型的正常迟滞为逆时针，而N型的正常迟滞为顺时针，但迟滞曲线本质是一样的。参见图25和图26，相较于比较例12的采用PECVD法制备的单层Si3N4正常迟滞材料层的薄膜晶体管，采用磁控溅射法制备的SiO2反常迟滞材料层，且反常迟滞材料层与所述栅极102直接接触设置，薄膜晶体管100C的迟滞曲线被明显减小甚至消除。
实施例8
本发明实施例8的薄膜晶体管100C与本发明实施例5的薄膜晶体管100C结构基本相同，其区别为，所述第一子电介质层1031为反常迟滞材料层，采用磁控溅射法制备的SiO2层；所述第二子电介质层1032为正常迟滞材料层，采用电子束蒸发法制备的SiO2层。
本实施例还制备比较例14。比较例14与本实施例的区别仅为：所述第一子电介质层1031为正常迟滞材料，而第二子电介质层1032为反常迟滞材料层。比较结果参见表8。
表8实施例8与比较例的工艺参数以及测试结果对比
Figure GDA0002405428030000151
本实施例的薄膜晶体管100C进行测量。比较例14和本实施例的薄膜晶体管100C为P型。参见图27，比较例14的薄膜晶体管具有明显的迟滞曲线。参见图28，实施例8的薄膜晶体管100C的迟滞曲线被明显减小甚至消除。
实施例9
本发明实施例9的薄膜晶体管100A与本发明实施例2的薄膜晶体管100A结构基本相同，其区别为，所述半导体层104采用二硫化钼二维纳米材料制备。
本实施例还制备比较例15-16。比较例15与本实施例的区别仅为：薄膜晶体管结构为100，所述电介质层103为采用热氧化法制备的SiO2层。比较例16与本实施例的区别仅为：所述电介质层103为采用ALD法制备的Al2O3层。比较结果参见表9。
表9实施例9与比较例的工艺参数以及测试结果对比
Figure GDA0002405428030000152
本实施例的薄膜晶体管100A进行测量。比较例15-16和本实施例的薄膜晶体管100A为N型。参见图29-30，比较例15-16的薄膜晶体管100A的正常迟滞曲线为顺时针。参见图31，本实施例的薄膜晶体管100A的迟滞曲线为逆时针，即反常迟滞曲线。由此可见，即使采用其他低维纳米半导体材料薄膜，采用磁控溅射法制备的氧化物层仍然具有反常迟滞曲线为作用。
实施例10
本发明实施例10的薄膜晶体管100C与本发明实施例5的薄膜晶体管100C结构基本相同，其区别为，所述第一子电介质层1031为反常迟滞材料层，采用磁控溅射法制备的SiO2层；所述第二子电介质层1032为正常迟滞材料层，采用ALD法制备的Al2O3层。
本实施例还制备比较例17。比较例17与本实施例的区别仅为：所述第一子电介质层1031为正常迟滞材料，而第二子电介质层1032为反常迟滞材料层。比较结果参见表10。
表10实施例10与比较例的工艺参数以及测试结果对比
Figure GDA0002405428030000161
本实施例的薄膜晶体管100C进行测量。比较例17和本实施例的薄膜晶体管100C为N型。参见图32，比较例17的薄膜晶体管具有明显的迟滞曲线，且与比较例16迟滞曲线基本相同。参见图33，实施例10的薄膜晶体管100C的迟滞曲线被明显减小甚至消除。
实施例11
本发明实施例11的薄膜晶体管100与本发明实施例1的薄膜晶体管100结构基本相同，其区别为，所述电介质层103为采用磁控溅射法制备的Al2O3层。本实施例分别采用不同的磁控溅射工艺参数制备厚度为10纳米、20纳米、100纳米、500纳米、1000纳米的Al2O3层作为电介质层103，结果均表明采用磁控溅射法制备的Al2O3层为反常迟滞材料。本实施例中，将实施例11的薄膜晶体管100与上述比较例2-3进行比较，结果参见表11。
表11实施例11与比较例的工艺参数以及测试结果对比
Figure GDA0002405428030000171
本实施例的薄膜晶体管100进行测量。本实施例的薄膜晶体管100为P型。参见图34和图3-4可见，本实施例的薄膜晶体管100的迟滞曲线为顺时针，即反常迟滞曲线。可以理解，采用磁控溅射法制备的Al2O3层为反常迟滞材料与其他正常迟滞材料形成双层电介质层103，且使所述栅极102与所述反常迟滞材料层直接接触，同样可以起到减小或消除迟滞曲线的作用。
实施例12
请参阅图35，本发明实施例12提供一种采用上述减小或消除迟滞曲线的薄膜晶体管100C的逻辑电路10。所述逻辑电路10包括两个双极性的顶栅型薄膜晶体管100C，且每个薄膜晶体管100C包括一基底101、一栅极102、一电介质层103、一半导体层104、一源极105和一漏极106。所述电介质层103为双层结构，其包括层叠设置的第一子电介质层1031和第二子电介质层1032。所述两个双极性的薄膜晶体管100C的栅极102电连接，且所述两个双极性的薄膜晶体管100C的源极105或漏极106电连接。可以理解，本实施例中，所述逻辑电路10为一反向器。
具体地，所述两个双极性的薄膜晶体管100C共用一个基底101、共用一个漏极106、且共用一个栅极102。所述两个双极性的薄膜晶体管100C的半导体层104可以通过图案化一连续的碳纳米管层制备。所述两个双极性的薄膜晶体管100C的第一子电介质层1031或第二子电介质层1032均为一次沉积制备的连续整体结构。所述第一子电介质层1031为采用磁控溅射法制备的SiO2反常迟滞材料层。所述第二子电介质层1032为采用ALD法制备的Al2O3正常迟滞材料层。
本实施例还制备比较例18。比较例18与本实施例的区别仅为：所述第一子电介质层1031为正常迟滞材料，而第二子电介质层1032为反常迟滞材料层。比较结果参见表12。
表12实施例12与比较例的工艺参数以及测试结果对比
Figure GDA0002405428030000181
本实施例对所述逻辑电路10的输入输出特性进行测试。参见图36，比较例18的逻辑电路10的转换阈值的差别达到1V以上。参见图37，本实施例的逻辑电路10的转换阈值的差别在0.1V左右。
本实施例还对所述逻辑电路10的频率响应特性进行测试。实验中，比较例18和本实施例的逻辑电路10的开态电流相同，以保证单个器件的迁移率相同，从而比较迟滞对于频率响应的影响。参见图38和39，为输入频率为0.1kHz和1kHz时，比较例18和本实施例的逻辑电路10的输出响应。由图38可见，输入频率为0.1kHz时，比较例18的逻辑电路10在低电平不稳定，而本实施例的逻辑电路10输出反相方波性能良好。由图39可见，输入频率为1kHz时，本实施例的逻辑电路10仍然能正常工作，而比较例18的逻辑电路10则已经完全没有了低电平，上升沿下降沿延迟时间都明显大于本实施例的逻辑电路10。
参见图40，通过放大图38的单一周期的频率输出波形，可以看到，本实施例的逻辑电路10上升沿与下降沿的延迟时间均小于比较例18的逻辑电路10。通过截止工作频率计算公式f＝1/(2*max(tr,tf))，可以得出在单个器件延迟时间类似的情况下，本实施例的逻辑电路10的截止工作频率比比较例18的逻辑电路10高将近5倍。以上实验结果说明了TFT迟滞对于逻辑电路稳定性以及频率响应特性都存在很大的影响。因此消除迟滞是非常必要的。而且，本发明通过消除迟滞，极大改善了逻辑电路10的电学性能。
实施例13
请参阅图41，本发明实施例13提供一种采用上述减小或消除迟滞曲线的薄膜晶体管100C的逻辑电路10A。所述逻辑电路10A包括一个N型的顶栅型薄膜晶体管100C和一个P型的顶栅型薄膜晶体管100C。所述N型薄膜晶体管100C包括一基底101、一栅极102、一电介质层103a、一半导体层104a、一源极105a和一漏极106。所述电介质层103a为双层结构，其包括层叠设置的第一子电介质层1031和第二子电介质层1032a。所述P型薄膜晶体管100C包括一基底101、一栅极102、一电介质层103b、一半导体层104b、一源极105b和一漏极106。所述电介质层103b为双层结构，其包括层叠设置的第一子电介质层1031和第二子电介质层1032b。所述N型薄膜晶体管100C和P型薄膜晶体管100C的栅极102电连接，且源极105或漏极106电连接。可以理解，本实施例中，所述逻辑电路10A也为一反向器。
具体地，所述N型薄膜晶体管100C和P型薄膜晶体管100C共面设置，共用一个基底101、共用一个漏极106、且共用一个栅极102。所述N型薄膜晶体管100C和P型薄膜晶体管100C的半导体层104可以通过图案化一连续的碳纳米管层制备。所述N型薄膜晶体管100C和P型薄膜晶体管100C的第一子电介质层1031为一次沉积制备的连续整体结构。所述N型薄膜晶体管100C的第二子电介质层1032a和P型薄膜晶体管100C的第二子电介质层1032b采用不同的正常迟滞材料层。所述第一子电介质层1031为采用磁控溅射法制备的SiO2反常迟滞材料层。所述第二子电介质层1032a为采用PECVD法制备的Si3N4正常迟滞材料层。所述第二子电介质层1032b为采用热氧化法制备的Y2O3正常迟滞材料层。
实施例14
请参阅图42，本发明实施例14提供一种采用上述减小或消除迟滞曲线的薄膜晶体管100B和薄膜晶体管100C的逻辑电路10B。所述逻辑电路10B包括一个N型的顶栅型薄膜晶体管100C和一个P型的底栅极型薄膜晶体管100B。所述N型薄膜晶体管100C包括一基底101、一栅极102、一电介质层103a、一半导体层104a、一源极105a和一漏极106a。所述电介质层103a为双层结构，其包括层叠设置的第一子电介质层1031a和第二子电介质层1032a。所述P型薄膜晶体管100B包括一栅极102、一电介质层103b、一半导体层104b、一源极105b和一漏极106b。所述电介质层103b为双层结构，其包括层叠设置的第一子电介质层1031b和第二子电介质层1032b。所述N型薄膜晶体管100C和P型薄膜晶体管100B的栅极102电连接，且源极105a、105b或漏极106a、106b电连接。可以理解，本实施例中，所述逻辑电路10B也为一反向器。
具体地，所述N型薄膜晶体管100C和P型薄膜晶体管100B层叠设置，共用一个基底101、且共用一个栅极102。所述N型薄膜晶体管100C直接设置于所述基底101表面。所述电介质层103a和电介质层103b具有一通孔，所述漏极106b延伸通过该通孔与所述漏极106a电连接。所述P型薄膜晶体管100B设置于所述第一子电介质层1031a表面。所述第一子电介质层1031a和第一子电介质层1031b均为采用磁控溅射法制备的SiO2反常迟滞材料层。所述第二子电介质层1032a为采用PECVD法制备的Si3N4正常迟滞材料层。所述第二子电介质层1032b为采用ALD制备的Al2O3正常迟滞材料层。
本发明具有以下优点：第一，采用磁控溅射法制备的氧化物材料作为电介质层可以得到具有反常迟滞曲线的薄膜晶体管；第二，采用正常迟滞材料和反常迟滞材料的双层电介质层结构可以减小甚至消除迟滞曲线；第三，采用减小或消除迟滞曲线的薄膜晶体管制备的逻辑器件具有优异的电学性能。
另外，本领域技术人员还可以在本发明精神内做其它变化，这些依据本发明精神所做的变化，都应包含在本发明所要求保护的范围内。

Claims (10)

1.一种薄膜晶体管，其包括；
一基底；
一栅极，所述栅极设置于所述基底的一表面；
一电介质层，所述电介质层设置于所述基底上且将所述栅极覆盖；
一半导体层，所述半导体层设置于所述电介质层远离所述基底的表面，且所述半导体层包括多个纳米半导体材料；
一源极和一漏极，所述源极和漏极间隔设置于所述电介质层远离所述基底的一侧，且分别与所述半导体层电连接；
其特征在于，所述电介质层为采用磁控溅射法制备的氧化物层，且与所述栅极直接接触；所述薄膜晶体管为P性时迟滞曲线表现为顺时针，所述薄膜晶体管为N性时迟滞曲线表现为逆时针。
2.如权利要求1所述的薄膜晶体管，其特征在于，所述氧化物为金属氧化物。
3.如权利要求2所述的薄膜晶体管，其特征在于，所述金属氧化物为Al2O3。
4.如权利要求1所述的薄膜晶体管，其特征在于，所述氧化物为SiO2。
5.如权利要求1所述的薄膜晶体管，其特征在于，所述电介质层的厚度为10纳米～1000纳米。
6.如权利要求1所述的薄膜晶体管，其特征在于，所述纳米半导体材料为石墨烯、碳纳米管、MoS2、WS2、MnO2、ZnO、MoSe2、MoTe2、TaSe2、NiTe2或Bi2Te3。
7.如权利要求1所述的薄膜晶体管，其特征在于，所述半导体层为1～5层纳米半导体材料。
8.如权利要求1所述的薄膜晶体管，其特征在于，所述基底的材料为二氧化硅、玻璃、聚合物、陶瓷或石英。
9.一种薄膜晶体管的制备方法，该方法包括：
提供一基底；
在所述基底表面沉积一栅极；
在所述基底表面采用磁控溅射法制备一氧化物层作为电介质层，且所述氧化物层将所述栅极覆盖且与所述栅极直接接触；
在所述电介质层表面制备一半导体层，所述半导体层包括多个纳米材料；
在所述电介质层表面制备源极和漏极，且所述源极和漏极与所述半导体层电连接；所述薄膜晶体管为P性时迟滞曲线表现为顺时针，所述薄膜晶体管为N性时迟滞曲线表现为逆时针。
10.如权利要求9所述的薄膜晶体管的制备方法，其特征在于，所述磁控溅射前的真空度为小于10-5Pa，溅射的功率为150瓦～200瓦，溅射时的压强为0.2帕～1帕。
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