TW201821352A - 一種薄膜電晶體及其製備方法 - Google Patents

一種薄膜電晶體及其製備方法 Download PDF

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TW201821352A
TW201821352A TW105141975A TW105141975A TW201821352A TW 201821352 A TW201821352 A TW 201821352A TW 105141975 A TW105141975 A TW 105141975A TW 105141975 A TW105141975 A TW 105141975A TW 201821352 A TW201821352 A TW 201821352A
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film transistor
thin film
dielectric layer
layer
substrate
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TW105141975A
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TWI633048B (zh
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趙宇丹
霍雨佳
肖小陽
王营城
張天夫
金元浩
李群慶
范守善
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鴻海精密工業股份有限公司
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Abstract

一種薄膜電晶體及其製備方法。該薄膜電晶體包括；一基底；一柵極，所述柵極設置於所述基底的一表面；一電介質層，所述電介質層設置於所述基底上且將所述柵極覆蓋；一半導體層，所述半導體層設置於所述電介質層遠離所述基底的表面，且所述半導體層包括複數個奈米半導體材料；一源極和一漏極，所述源極和漏極間隔設置於所述電介質層遠離所述基底的一側，且分別與所述半導體層電連接；其中，所述電介質層為採用磁控濺射法製備的氧化物層，且與所述柵極直接接觸。本發明的薄膜電晶體具有反常遲滯曲線。

Description

一種薄膜電晶體及其製備方法
本發明涉及一種薄膜電晶體，尤其涉及一種採用奈米材料作為半導體層的薄膜電晶體。
薄膜電晶體（Thin Film Transistor，TFT）是現代微電子技術中的一種關鍵性電子元件，目前已經被廣泛的應用於平板顯示器等領域。薄膜電晶體主要包括基底、柵極、電介質層、半導體層、源極和漏極。
對於半導體型單壁奈米碳管（SWCNT）或二維半導體材料(如MoS2)作為半導體層的薄膜電晶體，由於溝道層與電介質層間的介面態，或電介質層中的缺陷，會束縛電荷，從而在器件的轉移特性曲線上會表現出遲滯曲線的特性。具體表現為柵極電壓VG從負向掃至正向，和正向掃至負向的溝道層的漏電流ID曲線不重合，即在開關電流相同的情況下，閾值電壓的不同。傳統電介質層通常為ALD生長、電子束蒸發、熱氧化、PECVD等方法製備的Al2 O3 層、SiO2 層、HfO2 層以及Si3 N4 層等。
發明人研究發現，採用磁控濺射法製備的氧化物材料作為電介質層得到的遲滯曲線與採用傳統電介質層得到的遲滯曲線方向相反。本發明定義傳統電介質材料為正常遲滯材料，採用磁控濺射法製備的氧化物材料為反常遲滯材料。進一步，發明人研究發現，採用正常遲滯材料和反常遲滯材料的雙層電介質層結構可以減小甚至消除遲滯曲線。而採用減小或消除遲滯曲線的薄膜電晶體具有一些優異的電學性能。
有鑑於此，確有必要提供一種具有反常遲滯曲線的薄膜電晶體及其製備方法。
一種薄膜電晶體，其包括；一基底；一柵極，所述柵極設置於所述基底的一表面；一電介質層，所述電介質層設置於所述基底上且將所述柵極覆蓋；一半導體層，所述半導體層設置於所述電介質層遠離所述基底的表面，且所述半導體層包括複數個奈米半導體材料；一源極和一漏極，所述源極和漏極間隔設置於所述電介質層遠離所述基底的一側，且分別與所述半導體層電連接；其中，所述電介質層為採用磁控濺射法製備的氧化物層，且與所述柵極直接接觸。
一種薄膜電晶體的製備方法，該方法包括：提供一基底；在所述基底表面沈積一柵極；在所述基底表面採用磁控濺射法製備一氧化物層作為電介質層，且所述氧化物層將所述柵極覆蓋且與所述柵極直接接觸；在所述電介質層表面製備一半導體層，所述半導體層包括複數個奈米材料；在所述電介質層表面製備源極和漏極，且所述源極和漏極與所述半導體層電連接。
相較於先前技術，本發明的薄膜電晶體採用電介質層為採用磁控濺射法製備的氧化物層，且與所述柵極直接接觸，故，該薄膜電晶體具有反常遲滯曲線。
下面將結合附圖及具體實施例對本發明作進一步的詳細說明。
實施例1
請參閱圖1，本發明實施例1提供一種薄膜電晶體100，所述薄膜電晶體100為底柵型，其包括一基底101、一柵極102、一電介質層103、一半導體層104、一源極105和一漏極106。所述柵極102設置於所述基底101的一表面。所述電介質層103設置於所述基底101上且將所述柵極102覆蓋。所述半導體層104設置於所述電介質層103遠離所述基底101的表面。所述源極105和漏極106間隔設置於所述電介質層103遠離所述基底101的一側，且分別與所述半導體層104電連接。所述半導體層104位於所述源極105和漏極106之間的部分形成一溝道層。
所述基底101用於支撐所述柵極102、電介質層103、半導體層104、源極105和漏極106。所述基底101的尺寸和形狀不限，可以根據需要選擇。所述基底101的材料可以為絕緣材料，例如玻璃、聚合物、陶瓷或石英等。所述基底101也可以為設置有絕緣層的半導體基底或導電基底。本實施例中，所述基底101為一具有二氧化矽絕緣層的矽片。
所述電介質層103為採用磁控濺射法製備的氧化物層，且與所述柵極102直接接觸。所述電介質層103的厚度為10奈米~1000奈米。所述氧化物可以為金屬氧化物，例如，Al2 O3 ，也可以為矽氧化物，例如，SiO2 。本實施例中，所述電介質層103為採用磁控濺射法製備的厚度40奈米的SiO2 層。
所述半導體層104包括複數個奈米半導體材料。所述奈米半導體材料可以為石墨烯、奈米碳管、MoS2 、WS2 、MnO2 、ZnO、MoSe2 、MoTe2 、TaSe2 、NiTe2 、Bi2Te3 等。所述奈米半導體材料通過生長、轉移、沈積或旋塗等方法形成於所述電介質層103表面。所述半導體層104為單層或少層奈米半導體材料，例如1~5層。本實施例中，所述半導體層104為通過沈積單壁奈米碳管形成單壁奈米碳管網路製備而成。
所述柵極102、源極105和漏極106由導電材料製備，其製備方法可以為化學蒸鍍、電子束蒸發、熱沈積或磁控濺射等。優選地，所述柵極102、源極105和漏極106為一層導電薄膜。該導電薄膜的厚度為0.5奈米~100微米。該導電薄膜的材料為金屬，如鋁、銅、鎢、鉬、金、鈦、釹、鈀、銫等。可以理解，所述柵極102、源極105和漏極106的材料也可為導電漿料、ITO、奈米碳管或石墨烯等。本實施例中，所述柵極102、源極105和漏極106的材料為鈦金複合金屬層，厚度為40奈米。
所述薄膜電晶體100的製備方法包括以下步驟：
步驟S11，提供一基底101；
步驟S12，在所述基底101表面沈積一柵極102；
步驟S13，在所述基底101表面採用磁控濺射法製備一氧化物層作為電介質層103，且所述氧化物層將所述柵極102覆蓋且與所述柵極102直接接觸；
步驟S14，在所述電介質層103表面製備一半導體層104，所述半導體層104包括複數個奈米材料；
步驟S15，在所述電介質層103表面製備源極105和漏極106，且所述源極105和漏極106與所述半導體層104電連接。
本實施例中，所述步驟S13中，在所述基底101表面採用磁控濺射法製備SiO2 層。所述磁控濺射的濺射靶與樣品距離可以為50毫米~120毫米，濺射前的真空度為小於10− 5 Pa，濺射的功率可以為150瓦~200瓦，載氣為氬氣，濺射時的壓強可以為0.2帕~1帕。本實施例分別採用不同的工藝參數製備厚度為10奈米、20奈米、100奈米、500奈米、1000奈米的SiO2 層作為電介質層103，結果均表明採用磁控濺射法製備SiO2層為反常遲滯材料。
為了研究採用磁控濺射法製備的SiO2 層作為電介質層103對所述薄膜電晶體100的遲滯曲線的反常影響，本實施例還分別製備了採用正常遲滯材料的比較例1-4。比較例與本實施例的區別僅為所述電介質層103的材料和製備方法。其中，比較例1採用電子束蒸發20奈米SiO2 層作為電介質層103，比較例2採用電子束蒸發20奈米Al2O3層作為電介質層103，比較例3採用ALD 法沈積20奈米Al2 O3 層作為電介質層103，比較例3採用ALD 法沈積20奈米HfO2層作為電介質層103。比較結果參見表1。
本實施例的薄膜電晶體100進行測量時，所述半導體層104暴露在空氣中。比較例1-4以及本實施例的薄膜電晶體100均為P型。參見圖2-6，分別為比較例1-4以及本實施例的薄膜電晶體100的遲滯曲線測試結果。其中，圖2-5分別給出了複數個比較樣品的測試結果。進一步參見表1可見，比較例1-4的薄膜電晶體100的遲滯曲線均表現為逆時針，而本實施例的薄膜電晶體100的遲滯曲線表現為順時針。由比較例1和本實施例可知，在底柵型薄膜電晶體100中，採用磁控濺射法製備的SiO2 層作為電介質層103可以得到反常遲滯曲線。
實施例2
請參閱圖7，本發明實施例2提供一種薄膜電晶體100A，其包括一基底101、一柵極102、一電介質層103、一半導體層104、一源極105和一漏極106。所述半導體層104設置於所述基底101的一表面。所述源極105和漏極106間隔設置於所述基底101上，且分別與所述半導體層104電連接。所述半導體層104位於所述源極105和漏極106之間的部分形成一溝道層。所述電介質層103設置於所述半導體層104遠離所述基底101的表面，且將所述半導體層104、源極105和漏極106覆蓋。所述柵極102設置於所述電介質層103遠離所述基底101的表面。
本發明實施例2的薄膜電晶體100A與本發明實施例1的薄膜電晶體100結構基本相同，其區別為，所述薄膜電晶體100A為頂柵型。所述薄膜電晶體100A的製備方法包括以下步驟：
步驟S21，提供一基底101；
步驟S22，在所述基底101表面製備一半導體層104，所述半導體層104包括複數個奈米材料；
步驟S23，在所述基底101上製備源極105和漏極106，且所述源極105和漏極106與所述半導體層104電連接；
步驟S24，在所述半導體層104遠離所述基底101的表面採用磁控濺射法製備一氧化物層作為電介質層103，且所述氧化物層將所述半導體層104、源極105和漏極106覆蓋；
步驟S25，在所述電介質層103遠離所述基底101的表面製備一柵極102，且所述柵極102與所述電介質層103直接接觸。
為了研究採用磁控濺射法製備的SiO2 層作為電介質層103對所述薄膜電晶體100A的遲滯曲線的影響，本實施例還分別製備了採用正常遲滯材料的比較例5-6。比較例與本實施例的區別僅為所述電介質層103的材料和製備方法。其中，比較例5採用電子束蒸發20奈米SiO2 層作為電介質層103，比較例6採用熱氧化法製備20奈米Y2 O3 層作為電介質層103。比較結果參見表2。
本實施例的薄膜電晶體100A進行測量。比較例5-6以及本實施例的薄膜電晶體100A為P型。參見圖8-9，比較例5-6的薄膜電晶體100A的遲滯曲線表現為逆時針。參見圖10，本實施例的薄膜電晶體100A的遲滯曲線表現為順時針，即遲滯反常。由比較例5-6和本實施例可知，在頂柵型薄膜電晶體100A中，採用磁控濺射法製備的SiO2 層作為電介質層103可以得到反常遲滯曲線，而且保持薄膜電晶體100A 的極性不變。
實施例3
請參閱圖11，本發明實施例3提供一種薄膜電晶體100B，其包括一基底101、一柵極102、一電介質層103、一半導體層104、一源極105和一漏極106。所述柵極102設置於所述基底101的一表面。所述電介質層103設置於所述基底101上且將所述柵極102覆蓋。所述半導體層104設置於所述電介質層103遠離所述基底101的表面。所述源極105和漏極106間隔設置於所述電介質層103遠離所述基底101的一側，且分別與所述半導體層104電連接。所述半導體層104位於所述源極105和漏極106之間的部分形成一溝道層。所述薄膜電晶體100B也為底柵型。
本發明實施例3的薄膜電晶體100 B與本發明實施例1的薄膜電晶體100結構基本相同，其區別為，所述電介質層103為雙層結構，其包括層疊設置的第一子電介質層1031和第二子電介質層1032。所述第一子電介質層1031為反常遲滯材料層，即採用磁控濺射法製備的SiO2 層。所述第二子電介質層1032為正常遲滯材料層。
所述薄膜電晶體100B的製備方法包括以下步驟：
步驟S31，提供一基底101；
步驟S32，在所述基底101表面沈積一柵極102；
步驟S33，在所述基底101表面採用磁控濺射法製備一SiO2層作為第一子電介質層1031，且所述SiO2 層將所述柵極102覆蓋且與所述柵極102直接接觸；
步驟S34，在所述第一子電介質層1031表面製備一正常遲滯材料層作為第二子電介質層1032，從而得到一雙層結構的電介質層103；
步驟S35，在所述電介質層103表面製備一半導體層104，所述半導體層104包括複數個奈米材料；
步驟S36，在所述電介質層103表面製備源極105和漏極106，且所述源極105和漏極106與所述半導體層104電連接。
本實施例中，所述第二子電介質層1032的正常遲滯材料層為採用ALD 法沈積的20奈米厚的Al2 O3 層。為了研究採用磁控濺射法製備的SiO2 反常遲滯材料層對正常遲滯材料層的遲滯曲線的影響，本實施例還還製備比較例7。比較例7與本實施例的區別僅為：所述第一子電介質層1031為採用ALD 法沈積的20奈米厚的Al2 O3 正常遲滯材料，而第二子電介質層1032為反常遲滯材料層。比較結果參見表3。
本實施例的薄膜電晶體100B進行測量。比較例7以及本實施例的薄膜電晶體100B均為P型。參見圖12和圖4可見，比較例7的薄膜電晶體的遲滯曲線與比較例3的薄膜電晶體的遲滯曲線基本相同。由此可見，比較例7中，採用磁控濺射法製備的SiO2 對薄膜電晶體的遲滯曲線幾乎沒有影響。參見圖13，實施例3的薄膜電晶體100B的遲滯曲線被明顯減小甚至消除。對比比較例7和實施例3可見，只有當反常遲滯材料層直接與柵極102接觸，起到調製溝道層作用時，所述反常遲滯材料層才會產生反常遲滯曲線。實施例3中，所述反常遲滯材料層的順時針遲滯曲線與正常遲滯材料層的逆時針遲滯曲線相互抵消，從而起到消除薄膜電晶體的遲滯曲線的作用。
進一步，本發明對實施例3的薄膜電晶體100B的遲滯曲線消除的穩定性進行測試。參見圖14，60天之後，實施例3的薄膜電晶體100B的遲滯曲線與之前基本吻合。由此可見，該結構可以穩定消除TFT遲滯曲線。
實施例4
本發明實施例4的薄膜電晶體100 B與本發明實施例3的薄膜電晶體100 B結構基本相同，其區別為，所述第一子電介質層1031為反常遲滯材料層，採用磁控濺射法製備的SiO2 層；所述第二子電介質層1032為正常遲滯材料層，採用電子束蒸發法製備的SiO2 層。
本實施例還還製備比較例8。比較例8與本實施例的區別僅為：所述第一子電介質層1031為正常遲滯材料，而第二子電介質層1032為反常遲滯材料層。比較結果參見表4。
本實施例的薄膜電晶體100B進行測量。比較例8以及本實施例的薄膜電晶體100B均為P型。參見圖15，比較例8的薄膜電晶體具有明顯的遲滯曲線。參見圖16，實施例4的薄膜電晶體100B的遲滯曲線被明顯減小甚至消除。由本實施例、比較例1和比較例8可以看出，電子束蒸鍍製備SiO2 為正常遲滯材料，而採用磁控濺射法製備的SiO2 層為反常遲滯材料。而且，只有當反常遲滯材料層直接與柵極102接觸，起到調製溝道層作用時，所述反常遲滯材料層才會產生反常遲滯曲線。
實施例5
請參閱圖17，本發明實施例5提供一種薄膜電晶體100C，其包括一基底101、一柵極102、一電介質層103、一半導體層104、一源極105和一漏極106。所述半導體層104設置於所述基底101的一表面。所述源極105和漏極106間隔設置於所述基底101上，且分別與所述半導體層104電連接。所述半導體層104位於所述源極105和漏極106之間的部分形成一溝道層。所述電介質層103設置於所述半導體層104遠離所述基底101的表面，且將所述半導體層104、源極105和漏極106覆蓋。所述柵極102設置於所述電介質層103遠離所述基底101的表面。所述薄膜電晶體100C為頂柵型。
本發明實施例5的薄膜電晶體100C與本發明實施例2的薄膜電晶體100A結構基本相同，其區別為，所述電介質層103為雙層結構，其包括層疊設置的第一子電介質層1031和第二子電介質層1032。所述第一子電介質層1031為反常遲滯材料層，即採用磁控濺射法製備的SiO2 層。所述第二子電介質層1032為正常遲滯材料層。
所述薄膜電晶體100C的製備方法包括以下步驟：
步驟S51，提供一基底101；
步驟S52，在所述基底101表面製備一半導體層104，所述半導體層104包括複數個奈米材料；
步驟S53，在所述基底101上製備源極105和漏極106，且所述源極105和漏極106與所述半導體層104電連接；
步驟S54，在所述半導體層104遠離所述基底101的表面製備一正常遲滯材料層作為第二子電介質層1032，所述第二子電介質層1032將所述半導體層104、源極105和漏極106覆蓋；
步驟S55，在所述第二子電介質層1032遠離所述基底101的表面採用磁控濺射法製備一SiO2 層作為第一子電介質層1031，所述第一子電介質層1031將所述第二子電介質層1032覆蓋，從而形成電介質層103；
步驟S56，在所述電介質層103遠離所述基底101的表面製備一柵極102，且所述柵極102與所述第一子電介質層1031直接接觸。
本實施例中，所述第二子電介質層1032的正常遲滯材料層為採用熱氧化法製備5奈米Y2 O3 層。為了研究採用磁控濺射法製備的SiO2 反常遲滯材料層對正常遲滯材料層的遲滯曲線的影響，本實施例還還製備比較例9。比較例9與本實施例的區別僅為：所述第一子電介質層1031為採用熱氧化法製備的20納厚度的Y2 O3 正常遲滯材料，而第二子電介質層1032為反常遲滯材料層。比較結果參見表5。
本實施例的薄膜電晶體100C進行測量。比較例9以及本實施例的薄膜電晶體100C為P型。參見圖18，比較例9的薄膜電晶體具有明顯的遲滯曲線。參見圖19，當採用磁控濺射法製備的SiO2 反常遲滯材料層與所述柵極102直接接觸設置時，薄膜電晶體100C的遲滯曲線被明顯減小甚至消除。
進一步，對比較例9以及本實施例的薄膜電晶體100C的輸出特性進行測試。輸出特性曲線為一組隨著柵極電壓VG不同，導致漏電流ID隨漏電壓VD變化的曲線。參見圖20，對比較例9的薄膜電晶體100C，由於具有遲滯，VG從0V掃描至-3V，與從-3V掃描至0V，在相同的VG下（相同線條）曲線不重合。參見圖21，對本實施例的薄膜電晶體100C，有於沒有遲滯，即使VG的掃描方向不同，其對應的ID-VD曲線是基本重合的。這對於TFT在邏輯電路、感測器等方面的應用是很重要的。
實施例6
本發明實施例6的薄膜電晶體100C與本發明實施例5的薄膜電晶體100 C結構基本相同，其區別為，所述第一子電介質層1031為反常遲滯材料層，採用磁控濺射法製備的SiO2 層；所述第二子電介質層1032為正常遲滯材料層，採用ALD法製備的Al2 O3 層。由於隔絕空氣和固定電荷摻雜，實施例6的薄膜電晶體100C成為雙極型。
本實施例還還製備比較例10-11。比較例10與本實施例的區別僅為：所述電介質層103為如圖7所示的單層結構，且所述電介質層103也為採用ALD法製備的Al2 O3 層。比較例11與本實施例的區別僅為：所述第一子電介質層1031為正常遲滯材料，而第二子電介質層1032為反常遲滯材料層。比較結果參見表6。
本實施例的薄膜電晶體100C進行測量。比較例10-11以及本實施例的薄膜電晶體100C為雙極型。參見圖22和圖23，當採用磁控濺射法製備的SiO2 反常遲滯材料層與所述柵極102間隔設置時，對薄膜電晶體的遲滯曲線幾乎沒有影響。參見圖24，當採用磁控濺射法製備的SiO2 反常遲滯材料層與所述柵極102直接接觸設置時，薄膜電晶體100C的遲滯曲線被明顯減小甚至消除。
實施例7
本發明實施例7的薄膜電晶體100C與本發明實施例5的薄膜電晶體100 C結構基本相同，其區別為，所述第一子電介質層1031為反常遲滯材料層，採用磁控濺射法製備的SiO2 層；所述第二子電介質層1032為正常遲滯材料層，採用PECVD法製備的Si3 N4 層。
本實施例還還製備比較例12-13。比較例12與本實施例的區別僅為：所述電介質層103為如圖7所示的單層結構，且所述電介質層103也為採用PECVD法製備的Si3 N4 層。比較例13與本實施例的區別僅為：所述第一子電介質層1031為正常遲滯材料，而第二子電介質層1032為反常遲滯材料層。比較結果參見表7。
本實施例的薄膜電晶體100C進行測量。比較例12和本實施例的薄膜電晶體100C為N型。比較例13的薄膜電晶體為雙極型。由於比較例13的結構無法得到N型薄膜電晶體，故，本實施例與比較例13的遲滯曲線沒有比較意義。由於P型和N型的區別，導致P型的正常遲滯為逆時針，而N型的正常遲滯為順時針，但遲滯曲線本質是一樣的。參見圖25和圖26，相較於比較例12的採用PECVD法製備的單層Si3 N4 正常遲滯材料層的薄膜電晶體，採用磁控濺射法製備的SiO2 反常遲滯材料層，且反常遲滯材料層與所述柵極102直接接觸設置，薄膜電晶體100C的遲滯曲線被明顯減小甚至消除。
實施例8
本發明實施例8的薄膜電晶體100C與本發明實施例5的薄膜電晶體100 C結構基本相同，其區別為，所述第一子電介質層1031為反常遲滯材料層，採用磁控濺射法製備的SiO2 層；所述第二子電介質層1032為正常遲滯材料層，採用電子束蒸發法製備的SiO2 層。
本實施例還製備比較例14。比較例14與本實施例的區別僅為：所述第一子電介質層1031為正常遲滯材料，而第二子電介質層1032為反常遲滯材料層。比較結果參見表8。
本實施例的薄膜電晶體100C進行測量。比較例14和本實施例的薄膜電晶體100C為P型。參見圖27，比較例14的薄膜電晶體具有明顯的遲滯曲線。參見圖28，實施例8的薄膜電晶體100C的遲滯曲線被明顯減小甚至消除。
實施例9
本發明實施例9的薄膜電晶體100A與本發明實施例2的薄膜電晶體100 A結構基本相同，其區別為，所述半導體層104採用二硫化鉬二維奈米材料製備。
本實施例還製備比較例15-16。比較例15與本實施例的區別僅為：薄膜電晶體結構為100，所述電介質層103為採用熱氧化法製備的SiO2 層。比較例16與本實施例的區別僅為：所述電介質層103為採用ALD法製備的Al2 O3 層。比較結果參見表9。
本實施例的薄膜電晶體100A進行測量。比較例15-16和本實施例的薄膜電晶體100A為N型。參見圖29-30，比較例15-16的薄膜電晶體100A的正常遲滯曲線為順時針。參見圖31，本實施例的薄膜電晶體100A的遲滯曲線為逆時針，即反常遲滯曲線。由此可見，即使採用其他低維奈米半導體材料薄膜，採用磁控濺射法製備的氧化物層仍然具有反常遲滯曲線為作用。
實施例10
本發明實施例10的薄膜電晶體100C與本發明實施例5的薄膜電晶體100 C結構基本相同，其區別為，所述第一子電介質層1031為反常遲滯材料層，採用磁控濺射法製備的SiO2 層；所述第二子電介質層1032為正常遲滯材料層，採用ALD法製備的Al2 O3 層。
本實施例還製備比較例17。比較例17與本實施例的區別僅為：所述第一子電介質層1031為正常遲滯材料，而第二子電介質層1032為反常遲滯材料層。比較結果參見表10。
本實施例的薄膜電晶體100C進行測量。比較例17和本實施例的薄膜電晶體100C為N型。參見圖32，比較例17的薄膜電晶體具有明顯的遲滯曲線，且與比較例16遲滯曲線基本相同。參見圖33，實施例10的薄膜電晶體100C的遲滯曲線被明顯減小甚至消除。
實施例11
本發明實施例11的薄膜電晶體100與本發明實施例1的薄膜電晶體100 結構基本相同，其區別為，所述電介質層103為採用磁控濺射法製備的Al2 O3 層。本實施例分別採用不同的磁控濺射工藝參數製備厚度為10奈米、20奈米、100奈米、500奈米、1000奈米的Al2 O3 層作為電介質層103，結果均表明採用磁控濺射法製備的Al2 O3 層為反常遲滯材料。本實施例中，將實施例11的薄膜電晶體100與上述比較例2-3進行比較，結果參見表11。
本實施例的薄膜電晶體100進行測量。本實施例的薄膜電晶體100為P型。參見圖34和圖3-4可見，本實施例的薄膜電晶體100的遲滯曲線為順時針，即反常遲滯曲線。可以理解，採用磁控濺射法製備的Al2 O3 層為反常遲滯材料與其他正常遲滯材料形成雙層電介質層103，且使所述柵極102與所述反常遲滯材料層直接接觸，同樣可以起到減小或消除遲滯曲線的作用。
實施例12
請參閱圖35，本發明實施例12提供一種採用上述減小或消除遲滯曲線的薄膜電晶體100C的邏輯電路10。所述邏輯電路10包括兩個雙極性的頂柵型薄膜電晶體100C，且每個薄膜電晶體100C包括一基底101、一柵極102、一電介質層103、一半導體層104、一源極105和一漏極106。所述電介質層103為雙層結構，其包括層疊設置的第一子電介質層1031和第二子電介質層1032。所述兩個雙極性的薄膜電晶體100C的柵極102電連接，且所述兩個雙極性的薄膜電晶體100C的源極105或漏極106電連接。可以理解，本實施例中，所述邏輯電路10為一反向器。
具體地，所述兩個雙極性的薄膜電晶體100C共用一個基底101、共用一個漏極106、且共用一個柵極102。所述兩個雙極性的薄膜電晶體100C的半導體層104可以通過圖案化一連續的奈米碳管層製備。所述兩個雙極性的薄膜電晶體100C的第一子電介質層1031或第二子電介質層1032均為一次沈積製備的連續整體結構。所述第一子電介質層1031為採用磁控濺射法製備的SiO2 反常遲滯材料層。所述第二子電介質層1032為採用ALD法製備的Al2 O3 正常遲滯材料層。
本實施例還製備比較例18。比較例18與本實施例的區別僅為：所述第一子電介質層1031為正常遲滯材料，而第二子電介質層1032為反常遲滯材料層。比較結果參見表12。
本實施例對所述邏輯電路10的輸入輸出特性進行測試。參見圖36，比較例18的邏輯電路10的轉換閾值的差別達到1V以上。參見圖37，本實施例的邏輯電路10的轉換閾值的差別在0.1V左右。
本實施例還對所述邏輯電路10的頻率響應特性進行測試。實驗中，比較例18和本實施例的邏輯電路10的開態電流相同，以保證單個器件的遷移率相同，從而比較遲滯對於頻率回應的影響。參見圖38和39，為輸入頻率為0.1kHz和1kHz時，比較例18和本實施例的邏輯電路10的輸出響應。由圖38可見，輸入頻率為0.1kHz時，比較例18的邏輯電路10在低電平不穩定，而本實施例的邏輯電路10輸出反相方波性能良好。由圖39可見，輸入頻率為1kHz時，本實施例的邏輯電路10仍然能正常工作，而比較例18的邏輯電路10則已經完全沒有了低電平，上升沿下降沿延遲時間都明顯大於本實施例的邏輯電路10。
參見圖40，通過放大圖38的單一週期的頻率輸出波形，可以看到，本實施例的邏輯電路10上升沿與下降沿的延遲時間均小於比較例18的邏輯電路10。通過截止工作頻率計算公式f=1/(2*max(tr,tf))，可以得出在單個器件延遲時間類似的情況下，本實施例的邏輯電路10的截止工作頻率比比較例18的邏輯電路10高將近5倍。以上實驗結果說明了TFT遲滯對於邏輯電路穩定性以及頻率回應特性都存在很大的影響。故消除遲滯是非常必要的。而且，本發明通過消除遲滯，極大改善了邏輯電路10的電學性能。
實施例13
請參閱圖41，本發明實施例13提供一種採用上述減小或消除遲滯曲線的薄膜電晶體100C的邏輯電路10A。所述邏輯電路10 A包括一個N型的頂柵型薄膜電晶體100C和一個P型的頂柵型薄膜電晶體100C。所述N型薄膜電晶體100C包括一基底101、一柵極102、一電介質層103a、一半導體層104a、一源極105a和一漏極106。所述電介質層103a為雙層結構，其包括層疊設置的第一子電介質層1031和第二子電介質層1032a。所述P型薄膜電晶體100C包括一基底101、一柵極102、一電介質層103b、一半導體層104b、一源極105b和一漏極106。所述電介質層103b為雙層結構，其包括層疊設置的第一子電介質層1031和第二子電介質層1032b。所述N型薄膜電晶體100C和P型薄膜電晶體100C的柵極102電連接，且源極105或漏極106電連接。可以理解，本實施例中，所述邏輯電路10也為一反向器。
具體地，所述N型薄膜電晶體100C和P型薄膜電晶體100C共面設置，共用一個基底101、共用一個漏極106、且共用一個柵極102。所述N型薄膜電晶體100C和P型薄膜電晶體100C的半導體層104可以通過圖案化一連續的奈米碳管層製備。所述N型薄膜電晶體100C和P型薄膜電晶體100C的第一子電介質層1031為一次沈積製備的連續整體結構。所述N型薄膜電晶體100C的第二子電介質層1032a和P型薄膜電晶體100C的第二子電介質層1032b採用不同的正常遲滯材料層。所述第一子電介質層1031為採用磁控濺射法製備的SiO2 反常遲滯材料層。所述第二子電介質層1032a為採用PECVD法製備的Si3 N4 正常遲滯材料層。所述第二子電介質層1032b為採用熱氧化法製備的Y2 O3 正常遲滯材料層。
實施例14 請參閱圖42，本發明實施例14提供一種採用上述減小或消除遲滯曲線的薄膜電晶體100B和薄膜電晶體100C的邏輯電路10B。所述邏輯電路10B包括一個N型的頂柵型薄膜電晶體100C和一個P型的底柵極型薄膜電晶體100B。所述N型薄膜電晶體100C包括一基底101、一柵極102、一電介質層103a、一半導體層104a、一源極105a和一漏極106a。所述電介質層103a為雙層結構，其包括層疊設置的第一子電介質層1031a和第二子電介質層1032a。所述P型薄膜電晶體100B包括一柵極102、一電介質層103b、一半導體層104b、一源極105b和一漏極106b。所述電介質層103b為雙層結構，其包括層疊設置的第一子電介質層1031b和第二子電介質層1032b。所述N型薄膜電晶體100C和P型薄膜電晶體100B的柵極102電連接，且源極105a、105b或漏極106a、106b電連接。可以理解，本實施例中，所述邏輯電路10也為一反向器。
具體地，所述N型薄膜電晶體100C和P型薄膜電晶體100B層疊設置，共用一個基底101、且共用一個柵極102。所述N型薄膜電晶體100C直接設置於所述基底101表面。所述電介質層1031a和電介質層103b具有一通孔，所述漏極106b延伸通過該通孔與所述漏極106a電連接。所述P型薄膜電晶體100B設置於所述第一子電介質層1031a表面。所述第一子電介質層1031a和電介質層1031b均為採用磁控濺射法製備的SiO2反常遲滯材料層。所述第二子電介質層1032a為採用PECVD法製備的Si3 N4 正常遲滯材料層。所述第二子電介質層1032b為採用ALD製備的Al2 O3 正常遲滯材料層。
本發明具有以下優點：第一，採用磁控濺射法製備的氧化物材料作為電介質層可以得到具有反常遲滯曲線的薄膜電晶體；第二，採用正常遲滯材料和反常遲滯材料的雙層電介質層結構可以減小甚至消除遲滯曲線；第三，採用減小或消除遲滯曲線的薄膜電晶體製備的邏輯器件具有優異的電學性能。
綜上所述，本發明確已符合發明專利之要件，遂依法提出專利申請。惟，以上所述者僅為本發明之較佳實施例，自不能以此限制本案之申請專利範圍。舉凡習知本案技藝之人士援依本發明之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍內。
10,10A,10B‧‧‧邏輯電路
100,100A,100B,100C‧‧‧薄膜電晶體
101‧‧‧基底
102‧‧‧柵極
103,103a,103b‧‧‧電介質層
1031,1031a,1031b‧‧‧第一子電介質層
1032,1032a,1032b‧‧‧第二子電介質層
104,104a,104b‧‧‧半導體層
105,105a,105b‧‧‧源極
106,106a,106b‧‧‧漏極
圖1為本發明實施例1提供的薄膜電晶體的結構示意圖。
圖2為本發明實施例1的比較例1的薄膜電晶體的遲滯曲線測試結果。
圖3為本發明實施例1的比較例2的薄膜電晶體的遲滯曲線測試結果。
圖4為本發明實施例1的比較例3的薄膜電晶體的遲滯曲線測試結果。
圖5為本發明實施例1的比較例4的薄膜電晶體的遲滯曲線測試結果。
圖6為本發明實施例1提供的薄膜電晶體的遲滯曲線測試結果。
圖7為本發明實施例2提供的薄膜電晶體的結構示意圖。
圖8為本發明實施例2的比較例5的薄膜電晶體的遲滯曲線測試結果。
圖9為本發明實施例2的比較例6的薄膜電晶體的遲滯曲線測試結果。
圖10為本發明實施例2提供的薄膜電晶體的遲滯曲線測試結果。
圖11為本發明實施例3提供的薄膜電晶體的結構示意圖。
圖12為本發明實施例3的比較例7的薄膜電晶體的遲滯曲線測試結果。
圖13為本發明實施例3提供的薄膜電晶體的遲滯曲線測試結果。
圖14為本發明實施例3提供的薄膜電晶體的遲滯曲線消除的穩定性進行測試結果。
圖15為本發明實施例4的比較例8的薄膜電晶體的遲滯曲線測試結果。
圖16為本發明實施例4提供的薄膜電晶體的遲滯曲線測試結果。
圖17為本發明實施例5提供的薄膜電晶體的結構示意圖。
圖18為本發明實施例5的比較例9的薄膜電晶體的遲滯曲線測試結果。
圖19為本發明實施例5提供的薄膜電晶體的遲滯曲線測試結果。
圖20為本發明實施例5的比較例9的薄膜電晶體的輸出特性測試結果。
圖21為本發明實施例5提供的薄膜電晶體的輸出特性測試結果。
圖22為本發明實施例6的比較例10的薄膜電晶體的遲滯曲線測試結果。
圖23為本發明實施例6的比較例11的薄膜電晶體的遲滯曲線測試結果。
圖24為本發明實施例6提供的薄膜電晶體的遲滯曲線測試結果。
圖25為本發明實施例7的比較例12的薄膜電晶體的遲滯曲線測試結果。
圖26為本發明實施例7提供的薄膜電晶體的遲滯曲線測試結果。
圖27為本發明實施例8的比較例14的薄膜電晶體的遲滯曲線測試結果。
圖28為本發明實施例8提供的薄膜電晶體的遲滯曲線測試結果。
圖29為本發明實施例9的比較例15的薄膜電晶體的遲滯曲線測試結果。
圖30為本發明實施例9的比較例16的薄膜電晶體的遲滯曲線測試結果。
圖31為本發明實施例9提供的薄膜電晶體的遲滯曲線測試結果。
圖32為本發明實施例10的比較例17的薄膜電晶體的遲滯曲線測試結果。
圖33為本發明實施例10提供的薄膜電晶體的遲滯曲線測試結果。
圖34為本發明實施例11提供的薄膜電晶體的遲滯曲線測試結果。
圖35為本發明實施例12提供的邏輯電路的結構示意圖。
圖36為本發明實施例12的比較例18的邏輯電路的輸入輸出特性曲線。
圖37為本發明實施例12提供的邏輯電路的輸入輸出特性曲線。
圖38為本發明實施例12和比較例18的邏輯電路的在輸入頻率為0.1kHz的頻率輸出回應結果。
圖39為本發明實施例12和比較例18的邏輯電路的在輸入頻率為1kHz的頻率輸出回應結果。
圖40為圖39的單一週期的頻率輸出波形的放大圖。
圖41為本發明實施例13提供的邏輯電路的結構示意圖。
圖42為本發明實施例14提供的邏輯電路的結構示意圖。
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Claims (10)

  1. 一種薄膜電晶體，其包括； 一基底； 一柵極，所述柵極設置於所述基底的一表面； 一電介質層，所述電介質層設置於所述基底上且將所述柵極覆蓋； 一半導體層，所述半導體層設置於所述電介質層遠離所述基底的表面，且所述半導體層包括複數個奈米半導體材料； 一源極和一漏極，所述源極和漏極間隔設置於所述電介質層遠離所述基底的一側，且分別與所述半導體層電連接； 其改良在於，所述電介質層為採用磁控濺射法製備的氧化物層，且與所述柵極直接接觸。
  2. 如請求項1所述的薄膜電晶體，其中，所述氧化物為金屬氧化物。
  3. 如請求項1所述的薄膜電晶體，其中，所述金屬氧化物為Al2 O3 。
  4. 如請求項1所述的薄膜電晶體，其中，所述氧化物為SiO2 。
  5. 如請求項1所述的薄膜電晶體，其中，所述電介質層的厚度為10奈米~1000奈米。
  6. 如請求項1所述的薄膜電晶體，其中，所述奈米半導體材料為石墨烯、奈米碳管、MoS2 、WS2 、MnO2 、ZnO、MoSe2 、MoTe2 、TaSe2 、NiTe2 或Bi2 Te3 。
  7. 如請求項1所述的薄膜電晶體，其中，所述半導體層為1~5層奈米半導體材料。
  8. 如請求項1所述的薄膜電晶體，其中，所述基底的材料為二氧化矽、玻璃、聚合物、陶瓷或石英。
  9. 一種薄膜電晶體的製備方法，該方法包括： 提供一基底； 在所述基底表面沈積一柵極； 在所述基底表面採用磁控濺射法製備一氧化物層作為電介質層，且所述氧化物層將所述柵極覆蓋且與所述柵極直接接觸； 在所述電介質層表面製備一半導體層，所述半導體層包括複數個奈米材料； 在所述電介質層表面製備源極和漏極，且所述源極和漏極與所述半導體層電連接。
  10. 如請求項9所述的薄膜電晶體的製備方法，其中，所述磁控濺射前的真空度為小於10− 5 Pa，濺射的功率為150瓦~200瓦，濺射時的壓強為0.2帕~1帕。
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