WO2018010495A1 - 像素驱动电路及其驱动方法、阵列基板、显示装置 - Google Patents

像素驱动电路及其驱动方法、阵列基板、显示装置 Download PDF

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Publication number
WO2018010495A1
WO2018010495A1 PCT/CN2017/085883 CN2017085883W WO2018010495A1 WO 2018010495 A1 WO2018010495 A1 WO 2018010495A1 CN 2017085883 W CN2017085883 W CN 2017085883W WO 2018010495 A1 WO2018010495 A1 WO 2018010495A1
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Prior art keywords
unit
power supply
signal
potential
supply voltage
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PCT/CN2017/085883
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English (en)
French (fr)
Inventor
张杨
刘金良
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/570,883 priority Critical patent/US10424249B2/en
Priority to JP2017557185A priority patent/JP7114255B2/ja
Publication of WO2018010495A1 publication Critical patent/WO2018010495A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • Embodiments of the present invention relate to a pixel driving circuit and a driving method thereof, an array substrate, and a display device.
  • An organic light-emitting diode (OLED) display device has many advantages such as self-luminous, fast response, high contrast, wide viewing angle, and the like, and is a display device that has been widely concerned at present.
  • the OLED display device includes a plurality of pixels arranged in a matrix, and driving and controlling each pixel for gray scale display depends on a pixel driving circuit inside the pixel.
  • a screen display of an OLED display device is generally realized by driving a switching transistor to drive a corresponding OLED in a pixel.
  • the gate thereof will work under high bias for a long time, and the long-term high-biasing effect will make the physical characteristics of the driving switch tube unstable, and the threshold voltage of the driving switch tube may easily occur.
  • the drift phenomenon affects the output of the normal scan signal.
  • One embodiment of the present invention provides a pixel driving circuit including: a drift suppression unit, a data writing unit, a compensation unit, and a work unit.
  • the drift suppression unit is configured to receive a reference control signal and a reference signal, and output the reference signal under control of the reference control signal;
  • the data write unit configured to receive a gate control signal, a data signal, and a power supply a voltage signal, and outputting the data signal under control of the gate control signal and a power supply voltage signal;
  • the compensation unit is coupled to the drift suppression unit and connected to the data writing unit, and further to an output node Connected, the compensation unit is configured to receive a power voltage signal, and generate a driving signal and output to the output node;
  • the working unit is connected to the output node, and is also connected to a negative pole of the power source, and the working unit is configured to Operating under the drive of the drive signal.
  • a further embodiment of the present invention provides a driving method of a pixel driving circuit, where the pixel driving circuit includes: a drift suppression unit, a data writing unit, a compensation unit, and a working unit, wherein The common end of the compensation unit and the working unit is an output node, and the driving method includes a plurality of driving cycles, and each of the driving cycles includes:
  • the reference control signal and the reference signal are input to the drift suppression unit, so that the drift suppression unit outputs the reference signal having a potential less than 0 to the compensation unit under the control of the reference control signal;
  • a reference control signal and a reference signal are input to the drift suppression unit, so that the drift suppression unit outputs the reference signal to the compensation unit under the control of the reference control signal to cause the compensation
  • the unit is in an operating state; and inputs a power supply voltage signal at a low potential to the compensation unit to reset the potential of the output node to a reset potential;
  • a compensation period inputting a gate control signal, a data signal, and a power supply voltage signal at a high potential to the data writing unit to cause the data writing unit to be in the gate control signal and a power supply voltage signal at a high potential Controlling, outputting the data signal to the compensation unit; and inputting a power supply voltage signal at a high potential to the compensation unit, pulling the potential of the output node from the reset potential to a first potential;
  • a data writing period inputting a gate control signal, a data signal, and a power supply voltage signal at a high potential to the data writing unit, causing the data writing unit to be at the gate control signal and a power supply voltage at a high potential Outputting the data signal to the compensation unit under control of a signal; and causing the compensation unit to pull up the potential of the output node from the first potential by using the power supply voltage signal in a floating state To the second potential;
  • Still another embodiment of the present invention provides a pixel driving circuit including a drift suppressing unit, a data writing unit, a compensation unit, a working unit, and a first node.
  • a control end of the compensation unit is connected to the first node, a first end of the compensation unit is for connecting to a power voltage signal, and a second end of the compensation unit is connected to a first end of the working unit;
  • a control end of the drift suppression unit for connecting to a reference control signal, a first end of the drift suppression unit for connecting to a reference signal, a second end of the drift suppression unit being connected to the first node;
  • the data a first control end of the write unit for connecting to a gate control signal, a second control end of the data write unit for connecting to the power supply voltage signal, and a first end of the data write unit for Connected to a data signal, said A second end of the data writing unit is connected to the first node; a second end of the working unit is for connecting to a negative pole of the power source
  • Still another embodiment of the present invention provides an array substrate including the above pixel driving circuit.
  • Still another embodiment of the present invention provides a display device including the above array substrate.
  • FIG. 1A is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention.
  • FIG. 1B is a schematic structural diagram of a pixel driving circuit according to an example of an embodiment of the present invention.
  • FIG. 2 is a control timing diagram of a pixel driving circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a display device according to an embodiment of the present invention.
  • 1-drift suppression unit 2-data write unit; 3-compensation unit;
  • T3-third switch tube T4-four switch tube; Td-drive switch tube;
  • G1-reference control signal G3-gate control signal; G4-power control signal;
  • VDD-supply voltage signal VDD-supply voltage signal
  • ELVSS-power supply negative VDD-supply voltage signal
  • N_1-input node pos-output node
  • VSTRESS-reference signal VSTRESS-reference signal
  • one driving period of the pixel driving circuit includes: a drift suppression period p1, a reset period p2, a compensation period p3, a data writing period p4, and a working period p5.
  • the pixel driving circuit includes: a drift suppression unit (or a drift suppression sub-circuit), a data writing unit (or a data writing sub-circuit) 2, a compensation unit (or a compensation sub-circuit) 3, and a working unit (or a working sub-circuit) 4.
  • the compensation unit 3 includes a drive switch tube Td (see FIG. 1B).
  • the drift suppression unit 1 receives the reference control signal G1 and the reference signal VSTRESS, and the drift suppression unit 1 is for controlling the output of the reference signal VSTRESS to the compensation unit 3 under the control of the reference control signal G1 during the drift suppression period p1 and the reset period p2 Further, in the drift suppression period p1, for example, the potential of the reference signal VSTRESS is less than 0; in the compensation period p3, the data writing period p4, and the operation period p5, the drift suppression unit 1 has no signal output.
  • the data writing unit 2 receives the gate control signal G3, the data signal Data, and the power supply voltage signal VDD, the potential of the data signal Data is the data potential, and the data writing unit 2 is used for the compensation period p3 and the data writing period p4 at the gate
  • the data signal Data is output to the control terminal of the compensation unit 3 under the control of the pole control signal G3 and the power supply voltage signal VDD; in the drift suppression period p1, the reset period p2, and the operation period p5, the data writing unit 2 has no signal output.
  • the compensation unit 3 is connected to the drift suppression unit 1 and is connected to the data writing unit 2, the compensation unit 3 is also connected to the output node pos, and the compensation unit 3 receives the power supply voltage signal VDD; the compensation unit 3 For resetting the potential of the output node pos to a reset potential with the reference signal VSTRESS and the power supply voltage signal VDD at a low potential during the reset period p2; during the compensation period p3, the compensation unit 3 utilizes the data signal Data and is at a high level The power supply voltage signal VDD of the potential pulls the potential of the output node pos from the reset potential to the first potential; in the data writing period p4, the compensation unit 3 uses the data signal Data and the power supply voltage signal VDD in a floating state, The potential of the output node pos is pulled up from the first potential to the second potential; during the operating period p5, the compensation unit 3 generates a driving signal and outputs it to the output node pos under the action of the power supply voltage signal VDD at a high potential;
  • the working unit 4 is connected to the output node pos, which is also connected to the power supply negative ELVSS, which is used to operate under the driving of the driving signal during the operating period p5.
  • the operation of the above pixel driving circuit in one driving cycle is as follows.
  • the drift suppression unit 1 receives the reference control signal G1 and the reference signal VSTRESS, and the drift suppression unit 1 outputs the reference signal VSTRESS whose potential is less than 0 to the compensation unit 3 under the control of the reference control signal G1.
  • the drift suppression unit 1 receives the reference control signal G1 and the reference signal VSTRESS, and the drift suppression unit 1 outputs the reference signal VSTRESS to the compensation unit 3 under the control of the reference control signal G1, so that the compensation unit 3 is in operation.
  • the compensation unit 3 receives the power supply voltage signal VDD at a low potential, and resets the potential of the output node pos to the reset potential.
  • the data writing unit 2 receives the gate control signal G3, the data signal Data, and the power supply voltage signal VDD at a high potential, the data writing unit 2 at the gate control signal G3 and the power supply voltage signal VDD at a high potential. Under the control of the data signal Data is output to the compensation unit 3, while the compensation unit 3 receives the power supply voltage signal VDD at a high potential, and the potential of the output node pos is pulled up from the reset potential to the first potential.
  • the data writing unit 2 receives the gate control signal G3, the data signal Data, and the power supply voltage signal VDD at a high potential, and the data writing unit 2 is at the gate control signal G3 and the power supply voltage at a high potential. Under the control of the signal VDD, the data signal Data is output to the compensation unit 3, while the compensation unit 3 pulls the potential of the output node pos from the first potential to the second potential by using the power supply voltage signal VDD in a floating state.
  • the compensation unit 3 receives the power supply voltage signal VDD at a high potential, and the compensation unit 3 generates a driving signal under the action of the power supply voltage signal VDD at a high potential, and the driving signal drives the working unit 4 to operate.
  • the drift suppression unit 1 can be under the control of the reference control signal G1.
  • the reference signal VSTRESS whose potential is less than 0 is output to the compensation unit 3, and the gate potential of the drive switching transistor Td in the compensation unit 3 is changed to a negative potential; and when the gate potential of the driving switching transistor Td is a negative potential, the driving is performed.
  • the threshold voltage Vth of the switching transistor Td drifts to the negative direction, and when the threshold voltage Vth drifts to the negative direction, the degree of drift is much smaller than the threshold voltage Vth drifts to the positive direction; thus, in each driving cycle, the switching transistor is driven.
  • the gate potential can be alternately changed between the negative potential and the positive potential (high potential), and the threshold voltage Vth drifting due to the long-term operation of the gate of the driving switch Td in the compensation unit 3 under high bias is well avoided. The problem is to ensure the normal output of the scan signal.
  • the driving switch transistor Td may be any suitable driving transistor, and the driving transistor may be an amorphous silicon transistor, a polysilicon transistor, an oxide semiconductor transistor, or the like. It is worth noting that for the driving switch tube Td fabricated using an oxide semiconductor, the gate thereof is more susceptible to a single bias voltage, and when the oxide driving switch tube Td is used to drive the working unit 4 to operate, the present invention is The pixel driving circuit provided by the embodiment can also avoid the problem that the threshold voltage Vth drifts due to the operation of the gate of the oxide-driven switching transistor for a long time under high bias voltage, and the normal output of the scanning signal is ensured.
  • the potential of the power supply voltage signal VDD utilized by the compensation unit 3 has three states: high potential, low potential, and floating; wherein the compensation unit 3 utilizes floating
  • the state of the power supply voltage signal VDD refers to the power supply voltage signal VDD that the compensation unit 3 does not receive any potential.
  • the common end of the drift suppression unit 1, the data write unit 2, and the compensation unit 3 is the input node N_1, and the common end of the compensation unit 3 and the work unit 4 is the output node pos.
  • the pixel driving circuit provided by the embodiment of the present invention is described below by taking a circuit structure of a specific example shown in FIG. 1B as an example.
  • the drift suppression unit 1 of the pixel driving circuit may include a first switching transistor T1, and the control terminal of the first switching transistor T1 receives a reference control signal G1, and the first switching transistor The input end of T1 receives the reference signal VSTRESS, and the output end of the first switching transistor T1 is connected to the compensation unit 3.
  • the data writing unit 2 may include a second switching tube T2 and a third switching tube T3; the control end of the second switching tube T2 receives the power supply voltage signal VDD, and the input end of the second switching tube T2 is connected to the output end of the third switching tube T3.
  • the output end of the second switch tube T2 is connected to the compensation unit 3; the control end of the third switch tube T3 receives the gate control signal G3, and the input end of the third switch tube T3 receives the data signal Data.
  • the compensation unit 3 may include a driving switch tube Td, and the control end of the driving switch tube Td is connected to the drift suppressing unit 1 and connected to the data writing unit 2, and the input end of the driving switch tube Td receives the power supply voltage signal VDD, and the driving switch tube Td
  • the output terminal is connected to the output node pos; the first capacitor C1, the first end of the first capacitor C1 is connected to the control end of the driving switch tube Td, and the second end of the first capacitor C1 is connected to the output end of the driving switch tube Td.
  • the working unit 4 may include a light emitting device D having an anode connected to the output node pos, the cathode of the light emitting device D being connected to the power source negative electrode ELVSS, and the light emitting device D being capable of emitting light under the driving of the driving signal.
  • the light-emitting device D is, for example, a light-emitting diode, such as an organic light-emitting diode.
  • the working unit 4 may further include a second capacitor C2, the first end of the second capacitor C2 is connected to the anode of the light emitting device D, and the second end of the second capacitor C2 is connected to the cathode of the light emitting device D, Used to maintain the voltage across the light emitting device D.
  • the drift suppression period p1 outputs a reference signal VSTRESS whose potential is less than 0 to the compensation unit 3, so that the gate of the drive switching transistor Td in the compensation unit 3 is in a negative pressure state.
  • the reference control signal G1 is at a high potential, and the first switching transistor T1 is controlled to be turned on, so that the reference signal VSTRESS whose potential is less than 0 is output from the output terminal of the first switching transistor T1, so that the potential V N_1 of the input node N_1 is equal to
  • the potential of the reference signal VSTRESS ie, the negative potential
  • the power supply voltage signal VDD is at the low potential VDD_L, thereby controlling the second switching transistor T2 to be turned off, so that the data
  • the writing unit 2 has no signal output.
  • the reset period p2 resets the potential Vpos of the output node pos to the reset potential, and clears the information of the previous driving period.
  • the reference control signal G1 is at a high potential, and the first switching transistor T1 is controlled to be turned on, so that the reference signal VSTRESS (the potential of the reference signal VSTRESS at this stage is greater than or equal to the threshold voltage Vth of the driving switch Td) is from the first
  • the output end of the switch T1 is output such that the potential V N_1 of the input node N_1 is equal to the potential of the reference signal VSTRESS, so that the drive switch Td is in an on state, and at this time, the power supply voltage signal VDD is placed at the low potential VDD_L, so that the output node
  • the potential Vpos of the output node pos is pulled up from the reset potential to the first potential, and the potential Vpos of the output node pos is compensated.
  • the reference control signal G1 is at a low potential, and the first switching transistor T1 is controlled to be turned off, so that the first switching transistor T1 stops outputting the reference signal VSTRESS; and the power supply voltage signal VDD is placed at the high potential VDD_H, that is, the control can be performed.
  • the second switch tube T2 is turned on, and the third switch tube T3 is periodically turned on and off under the action of the gate control signal G3.
  • the gate control signal G3 controls the third switch tube T3 to be turned on
  • the signal Data_L (the low potential Data_L of the data signal Data is greater than or equal to the threshold voltage Vth of the driving switch tube Td) is output from the output end of the third switching transistor T3 to the input end of the second switching transistor T2, and then through the output of the second switching transistor T2.
  • the terminal outputs to the input node N_1 and the first capacitor C1 (stored in the first capacitor C1), and when the gate control signal G3 controls the third switch transistor T3 to be turned off, the low potential data signal Data_L stored in the first capacitor C1 N_1 input node to continue to maintain the potential V N_1, ensure driving switch transistor Td at this stage been in a state of conduction; at this stage, since the power supply voltage VDD is at a high potential signal VDD_H, and the driving switch transistor Td is turned Therefore, the potential Vpos of the output node pos rises from the reset potential, and the gate-source voltage Vgs of the driving switch Td starts to gradually decrease from (Data_L-VDD_L) until Vgs Vth, and the driving switch Td is turned off.
  • the output The potential Vpos Data_L-Vth of the node pos, (Data_L-Vth) is the first potential.
  • the drive switching transistor Td is turned off, and the power supply voltage signal VDD at the high potential VDD_H cannot be supplied to the output node pos, so the light-emitting device D still cannot emit light.
  • the data writing period p4 pulls up the potential Vpos of the output node pos from the first potential to the second potential to cancel the influence of the threshold voltage Vth of the driving switching transistor Td on the light emitting device D.
  • the reference control signal G1 is still at a low potential, that is, the first switching transistor T1 is still turned off, the first switching transistor T1 does not output the reference signal VSTRESS;
  • the power supply voltage signal VDD is still at the high potential VDD_H, so that the second switching transistor T2 continues to be turned on, the gate control signal G3 is at a high potential to turn on the third switching transistor T3, thereby controlling the third switching transistor T3 to output the high potential data signal Data_H to the input end of the second switching transistor T2, and then to the second
  • the switch tube T2 outputs the high potential data signal Data_H to the input node N_1 and the first capacitor C1, such that the potential V N_1 of the input node N_1 is the high potential Data_H of the data signal Data, and the variation of
  • the driving switch Td is turned on, and receives the power supply voltage signal VDD at the high potential VDD_H, so that the light-emitting device D can be driven to turn on and emit light.
  • the reference control signal G1 is at a low potential, and the first switching transistor T1 is controlled to be turned off; the gate control signal G3 is at a low potential, and the third switching transistor T3 is controlled to be turned off, so that the potential V N_1 of the input node N_1 is maintained at Data_H,
  • the driving switch Td is turned on, and the potential Vpos of the output node pos is kept at [Data_L-Vth+ ⁇ (Data_H-Data_L)], so the gate-source voltage Vgs of the driving switch Td is constant, that is:
  • Vgs (1- ⁇ )(Data_H-Data_L)+Vth Formula (2)
  • I D K[(1- ⁇ )(Data_H-Data_L)+Vth-Vth] 2
  • the operating current of the light-emitting device D is independent of the threshold voltage Vth of the driving switch tube Td, that is, the working current of the light-emitting device D caused by the drift of the threshold voltage Vth of the driving switch tube Td is well compensated.
  • the operating current of the light-emitting device D is also independent of Vdd, that is, the variation due to the voltage drop (IR Drop) of the power supply line can be compensated, so that the embodiment of the present disclosure ensures illumination
  • the brightness of the device D is constant, which ensures the stability of the operation of the pixel driving circuit.
  • the input node N_1 is in a floating state, and therefore, the potential V N_1 of the input node N_1 can be increased as the potential of the input terminal of the driving switch tube Td rises, so that the driving switch tube Td can be further A good opening provides a good compensation for the threshold voltage Vth of the drive switch Td.
  • this embodiment only introduces the provided pixel driving circuit by taking the above specific circuit structure as an example.
  • the drift suppression unit 1, the data writing unit 2, and the compensation unit of the pixel driving circuit 3 and the work unit 4 can also be implemented by other structures, which will not be described in detail herein.
  • the compensation unit 3 utilized by the above embodiment utilizes the power supply voltage signal VDD at a high potential and the power supply voltage signal VDD at a low potential, for example, by an external driving chip (not shown) of the array substrate.
  • the embodiment of the present invention may further include a power supply unit 5 connected to the compensation unit 3, the power supply unit 5 receiving the power control signal G4 and the power supply voltage signal VDD; For outputting the power supply voltage signal VDD at a low potential to the compensation unit 3 under the control of the power supply control signal G4 during the drift suppression period p1 and the reset period p2; during the compensation period p3 and the operation period p5, at the power supply control signal G4
  • the power supply voltage signal VDD at a high potential is output to the compensation unit 3 under the control; in the data writing period p4, the power supply voltage signal VDD received by the compensation unit 3 is in a floating state under the control of the power supply control signal G4.
  • the structure of the power supply unit 5 described above is various, and the example of FIG. 1B also gives a specific structure of the power supply unit 5 to explain the working process in detail, which is of course not limited to the given one. structure.
  • the power supply unit 5 includes a fourth switch tube T4.
  • the control end of the fourth switch tube T4 receives the power control signal G4, the input end of the fourth switch tube T4 receives the power supply voltage signal VDD, and the output end of the fourth switch tube T4 is connected to the compensation unit 3. .
  • the power supply control signal G4 is at a high potential, and the fourth switching transistor T4 is turned on, and the power supply voltage signal VDD is turned on.
  • the fourth switch tube T4 can also adopt a high-potential cut-off, low-potential switch tube.
  • the timing of the power control signal G4 of the fourth switch tube T4 is opposite to the timing of the power source control signal G4. Only during the data write period p4 is high, and the rest of the period is low.
  • the change state of the power supply voltage signal VDD can be only high potential and low potential, that is, the power supply voltage signal is well coordinated.
  • the present disclosure has been described by taking an N-type transistor as an example.
  • P-type transistors For different types of transistors, it is necessary to adjust the level of the control voltage of the control terminal of the transistor.
  • the N-type transistor For an N-type transistor, the N-type transistor is in an on state when the control signal is at a high level, and the N-type transistor is in an off state when the control signal is at a low level.
  • the P-type transistor is in an on state when the control voltage is at a low level, and the P-type transistor is in an off state when the control signal is at a high level.
  • the switch tube made of oxide is used as the drive switch tube Td in the pixel drive circuit, that is, the drive
  • the threshold voltage of the switching transistor Td is 0V.
  • the electric position of the reference signal VSTRESS is -16 V to achieve that it sets the potential V N_1 of the input node N_1 to a negative potential.
  • the potential of the reference signal VSTRESS is raised to 0V to realize that it will drive the switching transistor Td to be turned on; meanwhile, the potential of the power control signal G4 is placed at 25V, so that the fourth switching transistor T4 is turned on, and The low potential VDD_L of the power supply voltage signal VDD is placed at -4 V, so that the potential Vpos of the output node pos is reset to -4V.
  • the high potential VDD_H of the power supply voltage signal VDD is set to 20V
  • the low potential Data_L of the data signal Data is set to 0V, so that the potential Vpos of the output node pos is pulled up from -4V to 4V.
  • the high potential VDD_H of the power supply voltage signal VDD remains at 20V
  • the potential of the power supply control signal G4 is set to -5V
  • the fourth switching transistor T4 is turned off
  • the gate control signal G3 is placed at 25V.
  • the third switch T3 is turned on, and according to the actual high potential Data_H of the data signal Data, the data_H is written to the gate of the drive switch Td, and the potential Vpos of the output node pos is pulled up to the second potential.
  • the high potential VDD_H of the power supply voltage signal VDD remains at 20V, and the potential of the power control signal G4 is placed at 25V, so that the fourth switching transistor T4 is turned on; the driving switch tube Td is turned on, receiving VDD_H of 20V, Thereby, the driving light-emitting device D is turned on and emits light.
  • the embodiment of the present invention further provides a driving method of a pixel driving circuit for driving the pixel driving circuit provided by the above embodiment.
  • the pixel driving circuit includes: a drift suppression unit 1, a data writing unit 2, a compensation unit 3, and a working The unit 4, wherein the common end of the compensation unit 3 and the working unit 4 is an output node pos, the driving method includes a plurality of driving periods, each of which includes the following period.
  • the reference control signal G1 and the reference signal VSTRESS are input to the drift suppression unit 1, and the drift suppression unit 1 outputs the reference signal VSTRESS whose potential is less than 0 to the compensation unit 3 under the control of the reference control signal G1.
  • the reference control signal G1 and the reference signal VSTRESS are input to the drift suppression unit 1, so that the drift suppression unit 1 outputs the reference signal VSTRESS to the compensation unit 3 under the control of the reference control signal G1, so that the compensation unit 3 is in operation.
  • the compensation unit 3 is in operation.
  • the reference control signal G1 and the reference signal VSTRESS are input to the drift suppression unit 1, so that the drift suppression unit 1 outputs the reference signal VSTRESS to the compensation unit 3 under the control of the reference control signal G1, so that the compensation unit 3 is in operation.
  • the compensation unit 3 is in operation.
  • the compensation unit 3 is in operation.
  • the gate control signal G3, the data signal Data, and the power supply voltage signal VDD at a high potential are input to the data writing unit 2, so that the data writing unit 2 is at the gate control signal G3 and the power supply voltage signal at a high potential.
  • the data signal Data is output to the compensation unit 3; and the power supply voltage signal VDD at a high potential is input to the compensation unit 3, and the potential of the output node pos is pulled up from the reset potential to the first potential.
  • the gate control signal G3, the data signal Data, and the power supply voltage signal VDD at a high potential are input to the data writing unit 2, so that the data writing unit 2 is at the gate control signal G3 and the power source at a high potential.
  • the data signal Data is output to the compensation unit 3; and the compensation unit 3 pulls the potential of the output node pos from the first potential to the second potential by using the power supply voltage signal VDD in a floating state.
  • the power supply voltage signal VDD at a high potential is input to the compensation unit 3, so that the compensation unit 3 generates a driving signal under the action of the power supply voltage signal VDD at a high potential, and drives the working unit 4 to operate by the driving signal.
  • the drift suppressing unit 1 in the drift suppression period p1, can output the reference signal VSTRESS whose potential is less than 0 to the compensation unit 3 under the control of the reference control signal G1, and the compensation unit
  • the gate potential of the driving switch tube Td in 3 becomes a negative potential, so that the gate potential of the driving switching transistor Td can alternate between a negative potential and a positive potential (high potential) in each driving period, which is well avoided.
  • the problem that the threshold voltage Vth drifts due to the operation of the gate of the drive switching transistor Td in the compensation unit 3 for a long period of time under high bias voltage ensures the normal output of the scan signal.
  • the pixel driving circuit provided by the above embodiment may further include a power supply unit 5 connected to the compensation unit 3, the power supply unit 5 receiving the power supply control signal G4 and the power supply voltage signal VDD; to the power supply unit 5 during the drift suppression period p1 and the reset period p2
  • the power supply control signal G4 and the power supply voltage signal VDD at a low potential are input, so that the power supply unit 5 outputs the power supply voltage signal VDD at a low potential to the compensation unit 3 under the control of the power supply control signal G4; during the compensation period p3 and the working period p5 , the power supply unit 5 outputs the power supply voltage signal VDD at a high potential to the compensation unit 3 under the control of the power supply control signal G4; in the data writing period p4, causes the power supply unit 5 to compensate the unit under the control of the power supply control signal G4.
  • 3 The received power supply voltage signal VDD is in a floating state.
  • the embodiment further provides an array substrate, which includes one or more pixel driving circuits provided by the above technical solutions.
  • the pixel driving circuit provided by the above technical solutions is well avoided due to the compensation unit 3
  • the problem that the threshold voltage Vth of the gate of the middle drive switch Td is operated under high bias for a long time is drifted, and the normal output of the scan signal is ensured. Therefore, the array substrate provided in this embodiment also has these advantages.
  • the embodiment further provides a display device, which includes the above array substrate, and the display device can well avoid the threshold value caused by the long-term operation of the gate of the driving switch tube Td in the compensation unit 3 under high bias voltage.
  • the problem of voltage Vth drift ensures the normal output of the scan signal.
  • FIG. 3 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • the display panel includes an array substrate 8, which includes an array of a plurality of pixel units 81, each of which includes the pixel circuit of any of the above embodiments.
  • the display device may further include a data driving circuit 6 and a gate driving circuit 7 for respectively providing a data signal and a gate control signal, etc.; the display device may further include a chip or the like that supplies a power supply voltage signal (Vdd) or the like.
  • the data driving circuit 6 is electrically connected to the pixel unit 81 through the data line 61
  • the gate driving circuit 7 is electrically connected to the pixel unit 81 through the gate line 71.
  • the display device may be an AMOLED.
  • the display device may be an electronic paper, an OLED (Organic Light-Emitting Diode) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator. Any product or part that has a display function.
  • OLED Organic Light-Emitting Diode

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Abstract

一种像素驱动电路及其驱动方法、阵列基板（8）、显示装置。像素驱动电路包括：漂移抑制单元（1）、数据写入单元（2）、补偿单元（3）和工作单元（4）；漂移抑制单元（1）接收基准控制信号（G1）和基准信号（VSTRESS），漂移抑制单元（1）用于在漂移抑制时段（p1）和重置时段（p2），在基准控制信号（G1）的控制下将基准信号（VSTRESS）输出给补偿单元（3）；在漂移抑制时段（p1），基准信号（VSTRESS）的电位小于0。像素驱动电路用于驱动工作单元（4）工作。

Description

像素驱动电路及其驱动方法、阵列基板、显示装置 技术领域
本发明的实施例涉及一种像素驱动电路及其驱动方法、阵列基板、显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，以下简称OLED)显示装置具有自发光、反应速度快、对比度高、视角广等诸多优点，是目前受到广泛关注的一种显示装置。
OLED显示装置包括矩阵式排布的多个像素，驱动和控制每个像素进行灰阶显示依赖于像素内部的像素驱动电路。传统的像素驱动电路中，一般通过驱动开关管驱动像素中对应的OLED，来实现OLED显示装置的画面显示。该驱动开关管在工作过程中，其栅极会长期在高偏压下工作，而这种长时间的高偏压作用会使得驱动开关管的物理特性不稳定，容易导致驱动开关管出现阈值电压漂移的现象，影响正常扫描信号的输出。
发明内容
本发明的一个实施例提供了一种像素驱动电路，包括：漂移抑制单元、数据写入单元、补偿单元和工作单元。所述漂移抑制单元配置为接收基准控制信号和基准信号，并且在所述基准控制信号的控制下将所述基准信号输出；所述数据写入单元配置为接收栅极控制信号、数据信号和电源电压信号，并且在所述栅极控制信号和电源电压信号的控制下将所述数据信号输出；所述补偿单元与所述漂移抑制单元连接且与所述数据写入单元连接，还与输出节点连接，所述补偿单元配置为接收电源电压信号，以及生成一驱动信号并输出至所述输出节点；所述工作单元与所述输出节点连接，且还与电源负极连接，所述工作单元配置为在所述驱动信号的驱动下工作。
本发明的再一个实施例提供一种像素驱动电路的驱动方法，上述像素驱动电路包括：漂移抑制单元、数据写入单元、补偿单元和工作单元，其中所 述补偿单元和所述工作单元的公共端为输出节点，所述驱动方法包括多个驱动周期，每个所述驱动周期包括：
漂移抑制时段，向所述漂移抑制单元输入基准控制信号和基准信号，使所述漂移抑制单元在所述基准控制信号的控制下，将电位小于0的所述基准信号输出至所述补偿单元；
重置时段，向所述漂移抑制单元输入基准控制信号和基准信号，使所述漂移抑制单元在所述基准控制信号的控制下，将所述基准信号输出至所述补偿单元，使所述补偿单元处于工作状态；并向所述补偿单元输入处于低电位的电源电压信号，将所述输出节点的电位重置为重置电位；
补偿时段，向所述数据写入单元输入栅极控制信号、数据信号和处于高电位的电源电压信号，使所述数据写入单元在所述栅极控制信号和处于高电位的电源电压信号的控制下，将所述数据信号输出至所述补偿单元；并向所述补偿单元输入处于高电位的电源电压信号，将所述输出节点的电位从所述重置电位上拉至第一电位；
数据写入时段，向所述数据写入单元输入栅极控制信号、数据信号和处于高电位的电源电压信号，使所述数据写入单元在所述栅极控制信号和处于高电位的电源电压信号的控制下，将所述数据信号输出至所述补偿单元；并使所述补偿单元利用处于浮空状态的所述电源电压信号，将所述输出节点的电位从所述第一电位上拉至第二电位；
工作时段，向所述补偿单元输入处于高电位的电源电压信号，使所述补偿单元在所述处于高电位的电源电压信号的作用下生成一驱动信号，利用所述驱动信号驱动所述工作单元工作。
本发明的再一个实施例提供一种像素驱动电路，包括漂移抑制单元、数据写入单元、补偿单元、工作单元和第一节点。所述补偿单元的控制端连接到所述第一节点，所述补偿单元的第一端用于连接到电源电压信号，所述补偿单元的第二端连接到工作单元的第一端；所述漂移抑制单元的控制端用于连接到基准控制信号，所述漂移抑制单元的第一端用于连接到基准信号，所述漂移抑制单元的第二端连接到所述第一节点；所述数据写入单元的第一控制端用于连接到栅极控制信号，所述数据写入单元的第二控制端用于连接到所述电源电压信号，所述数据写入单元的第一端用于连接到数据信号，所述 数据写入单元的第二端连接到所述第一节点；所述工作单元的第二端用于连接到电源负极。
本发明的再一个实施例提供一种阵列基板，所述阵列基板包括上述像素驱动电路。
本发明的再一个实施例提供一种显示装置，所述显示装置包括上述阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1A为本发明实施例提供的像素驱动电路的结构示意图；
图1B为本发明实施例的一个示例提供的像素驱动电路的结构示意图；
图2为本发明实施例提供的像素驱动电路的控制时序图；
图3是本发明实施例提供的显示装置的示意图。
附图标记：
1-漂移抑制单元；       2-数据写入单元；      3-补偿单元；
4-工作单元；           5-电源单元；          p1-漂移抑制时段；
p2-重置时段；          p3-补偿时段；         p4-数据写入时段；
p5-工作时段；          T1-第一开关管；       T2-第二开关管；
T3-第三开关管；        T4-第四开关管；       Td-驱动开关管；
C1-第一电容；          C2-第二电容；         D-发光器件；
G1-基准控制信号；      G3-栅极控制信号；     G4-电源控制信号；
Data-数据信号；        VDD-电源电压信号；    ELVSS-电源负极；
N_1-输入节点；         pos-输出节点；        VSTRESS-基准信号。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描 述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了进一步说明本发明实施例提供的像素驱动电路及其驱动方法、阵列基板、显示装置，下面结合说明书附图进行详细描述。
请参阅图1A和图2，本发明实施例提供的像素驱动电路的一个驱动周期包括：漂移抑制时段p1、重置时段p2、补偿时段p3、数据写入时段p4和工作时段p5。该像素驱动电路包括：漂移抑制单元(或漂移抑制子电路)1、数据写入单元(或数据写入子电路)2、补偿单元(或补偿子电路)3和工作单元(或工作子电路)4。例如，补偿单元3包括驱动开关管Td(参见图1B)。
漂移抑制单元1接收基准控制信号G1和基准信号VSTRESS，漂移抑制单元1用于在漂移抑制时段p1和重置时段p2，在基准控制信号G1的控制下将基准信号VSTRESS输出至补偿单元3的控制端；而且，在漂移抑制时段p1，例如基准信号VSTRESS的电位小于0；在补偿时段p3、数据写入时段p4和工作时段p5，漂移抑制单元1均没有信号输出。
数据写入单元2接收栅极控制信号G3、数据信号Data和电源电压信号VDD，数据信号Data的电位为数据电位，数据写入单元2用于在补偿时段p3和数据写入时段p4，在栅极控制信号G3和电源电压信号VDD的控制下将数据信号Data输出至补偿单元3的控制端；在漂移抑制时段p1、重置时段p2和工作时段p5，数据写入单元2均没有信号输出。
补偿单元3与漂移抑制单元1连接且与数据写入单元2连接，补偿单元3还与输出节点pos连接，补偿单元3接收电源电压信号VDD；补偿单元3 用于在重置时段p2，利用基准信号VSTRESS和处于低电位的电源电压信号VDD，将输出节点pos的电位重置为重置电位；在补偿时段p3，补偿单元3利用数据信号Data和处于高电位的电源电压信号VDD，将输出节点pos的电位从重置电位上拉至第一电位；在数据写入时段p4，补偿单元3利用数据信号Data和处于浮空状态的电源电压信号VDD，将输出节点pos的电位从第一电位上拉至第二电位；在工作时段p5，补偿单元3在处于高电位的电源电压信号VDD的作用下，生成一驱动信号并输出至输出节点pos；在漂移抑制时段p1补偿单元3没有信号输出。
工作单元4与输出节点pos连接，工作单元4还与电源负极ELVSS连接，工作单元4用于在工作时段p5，在驱动信号的驱动下工作。
请参阅图1和图2，上述像素驱动电路在一个驱动周期的工作过程如下所述。
在漂移抑制时段p1，漂移抑制单元1接收基准控制信号G1和基准信号VSTRESS，漂移抑制单元1在基准控制信号G1的控制下，将电位小于0的基准信号VSTRESS输出至补偿单元3。
在重置时段p2，漂移抑制单元1接收基准控制信号G1和基准信号VSTRESS，漂移抑制单元1在基准控制信号G1的控制下，将基准信号VSTRESS输出至补偿单元3，使补偿单元3处于工作状态，同时补偿单元3接收处于低电位的电源电压信号VDD，实现将输出节点pos的电位重置为重置电位。
在补偿时段p3，数据写入单元2接收栅极控制信号G3、数据信号Data和处于高电位的电源电压信号VDD，数据写入单元2在栅极控制信号G3和处于高电位的电源电压信号VDD的控制下，将数据信号Data输出至补偿单元3，同时补偿单元3接收处于高电位的电源电压信号VDD，实现将输出节点pos的电位从重置电位上拉至第一电位。
在数据写入时段p4，数据写入单元2接收栅极控制信号G3、数据信号Data和处于高电位的电源电压信号VDD，数据写入单元2在栅极控制信号G3和处于高电位的电源电压信号VDD的控制下，将数据信号Data输出至补偿单元3，同时补偿单元3利用处于浮空状态的电源电压信号VDD，将输出节点pos的电位从第一电位上拉至第二电位。
在工作时段p5，补偿单元3接收处于高电位的电源电压信号VDD，补偿单元3在处于高电位的电源电压信号VDD的作用下生成一驱动信号，驱动信号驱动工作单元4工作。
根据上述像素驱动电路的结构和像素驱动电路在一个驱动周期的工作过程可知，本发明实施例提供的像素驱动电路中，在漂移抑制时段p1，漂移抑制单元1能够在基准控制信号G1的控制下将电位小于0的基准信号VSTRESS输出给补偿单元3，将补偿单元3中的驱动开关管Td的栅极电位变为负电位；在驱动开关管Td的栅极电位为负电位的情况下，驱动开关管Td的阈值电压Vth向负向漂移，而阈值电压Vth向负向漂移时，其漂移程度要远小于阈值电压Vth向正向漂移的程度；这样在每个驱动周期内，驱动开关管的栅极电位能够在负电位和正电位(高电位)之间交替变换，很好的避免了由于补偿单元3中驱动开关管Td的栅极长期处于高偏压下工作所导致的阈值电压Vth漂移的问题，保证了扫描信号的正常输出。
驱动开关管Td可以为各种适当的驱动晶体管，该驱动晶体管可以为非晶硅晶体管、多晶硅晶体管、氧化物半导体晶体管等。值得注意的是，对于使用氧化物半导体制作的驱动开关管Td，其栅极更容易受到单一偏压的影响，当采用这种氧化物驱动开关管Td来驱动工作单元4工作时，通过本发明实施例提供的像素驱动电路，同样能够避免由于氧化物驱动开关管的栅极长期处于高偏压下工作所导致的阈值电压Vth漂移的问题，保证了扫描信号的正常输出。
需要说明的是，本发明实施例所提供的像素驱动电路中，补偿单元3所利用的电源电压信号VDD的电位有三种状态：高电位、低电位和浮空；其中，补偿单元3利用浮空状态的电源电压信号VDD，是指补偿单元3不接收任何电位的电源电压信号VDD。
此外，漂移抑制单元1、数据写入单元2和补偿单元3的公共端为输入节点N_1，补偿单元3和工作单元4的公共端为输出节点pos。
下面以图1B所示的一个具体示例的电路结构为例对本发明实施例所提供的像素驱动电路进行介绍。
如图1所示，本实施所提供的像素驱动电路的漂移抑制单元1可包括第一开关管T1，该第一开关管T1的控制端接收基准控制信号G1，第一开关管 T1的输入端接收基准信号VSTRESS，第一开关管T1的输出端连接补偿单元3。
数据写入单元2可包括第二开关管T2和第三开关管T3；第二开关管T2的控制端接收电源电压信号VDD，第二开关管T2的输入端连接第三开关管T3的输出端，第二开关管T2的输出端连接补偿单元3；第三开关管T3的控制端接收栅极控制信号G3，第三开关管T3的输入端接收数据信号Data。
补偿单元3可包括驱动开关管Td，该驱动开关管Td的控制端连接漂移抑制单元1且连接数据写入单元2，该驱动开关管Td的输入端接收电源电压信号VDD，该驱动开关管Td的输出端连接输出节点pos；第一电容C1，该第一电容C1的第一端连接驱动开关管Td的控制端，该第一电容C1的第二端连接驱动开关管Td的输出端。
工作单元4可包括发光器件D，该发光器件D的阳极连接输出节点pos，该发光器件D的阴极连接电源负极ELVSS，发光器件D能够在驱动信号的驱动下发光。该发光器件D例如为发光二极管，例如有机发光二极管。
在另一个示例中，工作单元4还可以包括第二电容C2，该第二电容C2的第一端连接发光器件D的阳极，该第二电容C2的第二端连接发光器件D的阴极，以用于保持发光器件D两端的电压。
上述实施例提供的具体的像素驱动电路的工作过程在一个驱动周期内，依次包括以下五个时段：
漂移抑制时段p1，将电位小于0的基准信号VSTRESS输出至补偿单元3，使补偿单元3中的驱动开关管Td的栅极处于负压状态。在此时段内，基准控制信号G1处于高电位，控制第一开关管T1导通，从而电位小于0的基准信号VSTRESS从第一开关管T1的输出端输出，使输入节点N_1的电位VN_1等于基准信号VSTRESS的电位(即负电位)，即使得补偿单元3中的驱动开关管Td的栅极电位为负电位；电源电压信号VDD处于低电位VDD_L，从而控制第二开关管T2截止，使得数据写入单元2无信号输出。
重置时段p2，将输出节点pos的电位Vpos重置为重置电位，清除上一驱动周期的信息。在此时段内，基准控制信号G1处于高电位，控制第一开关管T1导通，从而基准信号VSTRESS(在此阶段基准信号VSTRESS的电位大于或等于驱动开关管Td的阈值电压Vth)从第一开关管T1的输出端输 出，使输入节点N_1的电位VN_1等于基准信号VSTRESS的电位，使驱动开关管Td处于导通状态，此时将电源电压信号VDD置于低电位VDD_L，就使得输出节点pos的电位Vpos变化为重置电位(即电源电压信号VDD的低电位VDD_L)；驱动开关管Td的栅源电压Vgs＝VN_1-Vpos>Vth，从而驱动开关管Td继续导通，输出节点pos的电位Vpos保持为VDD_L(即重置电位)；而且在此时段电源电压信号VDD处于低电位VDD_L，能够控制第二开关管T2截止，使得数据写入单元2无信号输出；需要说明的是，虽然在此时段内驱动开关管Td保持导通，但是由于Vpos＝VDD_L，因此并不足以使发光器件D打开并发光。
补偿时段p3，将输出节点pos的电位Vpos从重置电位拉高至第一电位，对输出节点pos的电位Vpos进行补偿。在此时段内，基准控制信号G1处于低电位，控制第一开关管T1截止，从而使第一开关管T1停止输出基准信号VSTRESS；同时将电源电压信号VDD置于高电位VDD_H，即能够控制第二开关管T2导通，而且第三开关管T3在栅极控制信号G3的作用下，周期性的导通和截止，当栅极控制信号G3控制第三开关管T3导通时，低电位数据信号Data_L(数据信号Data的低电位Data_L大于等于驱动开关管Td的阈值电压Vth)从第三开关管T3的输出端输出到第二开关管T2的输入端，再经第二开关管T2的输出端输出至输入节点N_1和第一电容C1(存储在第一电容C1内)中，当栅极控制信号G3控制第三开关管T3截止时，存储在第一电容C1中的低电位数据信号Data_L能够继续维持输入节点N_1的电位VN_1，保证驱动开关管Td在此阶段一直处于导通的状态；由于在此阶段电源电压信号VDD处于高电位VDD_H，且驱动开关管Td导通，使得输出节点pos的电位Vpos由重置电位开始上升，驱动开关管Td的栅源电压Vgs开始由(Data_L-VDD_L)逐渐减小，直至Vgs＝Vth，驱动开关管Td截止，此时，输出节点pos的电位Vpos＝Data_L-Vth，(Data_L-Vth)即为第一电位。需要说明的是，在此阶段内，当Vgs>Vth时，虽然驱动开关管Td导通，但是输出节点pos的电位Vpos并不是很高，不足以驱动发光器件D打开并发光，当Vgs＝Vth时，驱动开关管Td截止，处于高电位VDD_H的电源电压信号VDD无法输送至输出节点pos，因此发光器件D仍然无法发光。
数据写入时段p4，将输出节点pos的电位Vpos从第一电位上拉至第二 电位，以消除驱动开关管Td的阈值电压Vth对发光器件D的影响。在此时段内，基准控制信号G1仍然处于低电位，即第一开关管T1仍然截止，第一开关管T1不会输出基准信号VSTRESS；电源电压信号VDD仍然处于高电位VDD_H，使第二开关管T2继续导通，栅极控制信号G3处于高电位将第三开关管T3导通，从而控制第三开关管T3将高电位数据信号Data_H输出至第二开关管T2的输入端，再由第二开关管T2将高电位数据信号Data_H输出至输入节点N_1和第一电容C1，这样输入节点N_1的电位VN_1即为数据信号Data的高电位Data_H，输入节点N_1的电位VN_1的变化量即为高电位数据信号Data_H与低电位数据信号Data_L之差(Data_H-Data_L)；接着将栅极控制信号G3处于低电位，使第三开关管T3截止，由存储在第一电容C1中的高电位数据信号Data_H继续维持驱动开关管Td的导通；在此时段控制驱动开关管Td的输入端不接收任何电位的电源电压信号VDD，即驱动开关管Td接收浮空状态的电源电压信号VDD，使第一电容C1产生电容自举效应，将输出节点pos的电位Vpos由(Data_L-Vth)自举为第二电位，由于输入节点N_1的电位VN_1的变化量为(Data_H-Data_L)，因此输出节点pos的变化量应为α(Data_H-Data_L)，其中α＝C1/(C1+C2)，从而第二电位应为：Vpos＝Data_L-Vth+α(Data_H-Data_L)。需要说明的是，在此时段内，由于驱动晶体管不接收电源电压信号VDD，因此发光器件D不会发光。
工作时段p5，驱动开关管Td导通，并接收处于高电位VDD_H的电源电压信号VDD，从而能够驱动发光器件D打开并发光。在此时段内，基准控制信号G1处于低电位，控制第一开关管T1截止；栅极控制信号G3处于低电位，控制第三开关管T3截止，从而输入节点N_1的电位VN_1保持在Data_H，驱动开关管Td导通，输出节点pos的电位Vpos保持在[Data_L-Vth+α(Data_H-Data_L)]不变，因此驱动开关管Td的栅源电压Vgs恒定，即：
Vgs＝VN_1-Vpos＝Data_H-[Data_L-Vth+α(Data_H-Data_L)]    公式(1)
Vgs＝(1-α)(Data_H-Data_L)+Vth           公式(2)
根据发光器件D的工作电流的计算公式：
ID＝K(Vgs-Vth)2                    公式(3)
其中，K为常数，将上述公式(2)代入公式(3)中，能够得到：
ID＝K[(1-α)(Data_H-Data_L)+Vth-Vth]2
ID＝K[(1-α)(Data_H-Data_L)]2         公式(4)
根据上述公式(4)可以看出发光器件D的工作电流与驱动开关管Td的阈值电压Vth无关，即很好的补偿了驱动开关管Td由于阈值电压Vth漂移导致的发光器件D的工作电流的差异，而且由上述公式(4)可以看出发光器件D的工作电流与Vdd也无关，即可以补偿由于电源线的压降(IR Drop)导致的变化，因此本公开的实施例既保证了发光器件D发光亮度恒定，又保证了像素驱动电路工作的稳定性。
此外，在工作时段p5，输入节点N_1处于浮空的状态，因此，输入节点N_1的电位VN_1能够随着驱动开关管Td的输入端电位的升高而升高，使得驱动开关管Td能够更好的打开，对驱动开关管Td的阈值电压Vth起到很好的补偿作用。
另外，本实施例仅以上述具体的电路结构为例对所提供的像素驱动电路进行介绍，在本发明的其它实施例中，像素驱动电路的漂移抑制单元1、数据写入单元2、补偿单元3和工作单元4还可各自采用其它的结构实现，在此不再详述。
上述实施例提供的补偿单元3所利用处于高电位的电源电压信号VDD和处于低电位的电源电压信号VDD，例如可由阵列基板的外部驱动芯片(未示出)提供。
基于上述示例性的像素驱动电路，请继续参阅图1A，本发明实施例还可以包括与补偿单元3连接的电源单元5，该电源单元5接收电源控制信号G4和电源电压信号VDD；电源单元5用于在漂移抑制时段p1和重置时段p2，在电源控制信号G4的控制下将处于低电位的电源电压信号VDD输出至补偿单元3；在补偿时段p3和工作时段p5，在电源控制信号G4的控制下将处于高电位的电源电压信号VDD输出至补偿单元3；在数据写入时段p4，在电源控制信号G4的控制下使补偿单元3接收的电源电压信号VDD处于浮空状态。
上述电源单元5的结构多种多样，图1B的示例同样给出了一种电源单元5的具体结构，以对其工作过程进行详细说明，当然不仅限于给出的这种 结构。
电源单元5包括第四开关管T4，第四开关管T4的控制端接收电源控制信号G4，第四开关管T4的输入端接收电源电压信号VDD，第四开关管T4的输出端连接补偿单元3。例如，以第四开关管T4高电位导通、低电位截止为例，在漂移抑制时段p1和重置时段p2，电源控制信号G4为高电位，第四开关管T4导通，电源电压信号VDD为低电位VDD_L，从而第四开关管T4的输出端输出低电位的电源电压信号VDD；在补偿时段p3和工作时段p5，电源控制信号G4仍高电位，第四开关管T4保持导通，电源电压信号VDD为高电位VDD_H，从而第四开关管T4的输出端输出高电位的电源电压信号VDD；在数据写入时段p4，电源控制信号G4为低电位，第四开关管T4截止，从而第四开关管T4的输出端的电位浮空，即驱动开关管Td不利用任何电位的电源电压信号VDD。当然，第四开关管T4也可采用高电位截止、低电位导通的开关管，这种情况下，第四开关管T4的电源控制信号G4的时序与前述电源控制信号G4的时序相反，即仅在数据写入时段p4为高电位，其余时段均为低电位。
上述技术方案中，通过增加用于控制电源电压信号VDD输入到补偿单元3的电源单元5，使得电源电压信号VDD的变化状态可以仅为高电位和低电位，即很好的协调了电源电压信号VDD对数据写入单元2和补偿单元3的作用。
在上述描述中，本公开以N型晶体管为例进行说明。但是，本领域技术人员可以了解，本公开的实施例也可以通过P型晶体管实现。对于不同类型的晶体管，需要调整晶体管的控制端的控制电压的电平。例如，对于N型晶体管，在控制信号为高电平时，该N型晶体管处于开启状态；而在控制信号为低电平时，N型晶体管处于截止状态。例如，对于P型晶体管时，在控制电压为低电平时，该P型晶体管处于开启状态；而在控制信号为高电平时，P型晶体管处于截止状态。
为了更清楚的说明上述实施例提供的像素驱动电路的工作过程，下面给出具体示例。
实施例一
选用氧化物制作的开关管作为像素驱动电路中的驱动开关管Td，即驱动 开关管Td的阈值电压为0V。
在漂移抑制时段p1，将基准信号VSTRESS的电位置为-16V，以实现其将输入节点N_1的电位VN_1置于负电位。
在重置时段p2，将基准信号VSTRESS的电位升为0V，以实现其将驱动开关管Td导通；同时将电源控制信号G4的电位置于25V，使第四开关管T4导通，并将电源电压信号VDD的低电位VDD_L置于-4V，使得输出节点pos的电位Vpos被重置为-4V。
在补偿时段p3，将电源电压信号VDD的高电位VDD_H置于20V，将数据信号Data的低电位Data_L置于0V，实现将输出节点pos的电位Vpos由-4V上拉至4V。
在数据写入时段p4，电源电压信号VDD的高电位VDD_H仍保持20V，将电源控制信号G4的电位置于-5V，使第四开关管T4截止，将栅极控制信号G3置于25V，使第三开关管T3导通，根据数据信号Data实际的高电位Data_H，实现将Data_H写入到驱动开关管Td的栅极，且实现将输出节点pos的电位Vpos上拉至第二电位。
在工作时段p5，电源电压信号VDD的高电位VDD_H仍保持20V，同时将电源控制信号G4的电位置于25V，使第四开关管T4导通；驱动开关管Td导通，接收20V的VDD_H，从而实现驱动发光器件D打开并发光。
本发明实施例还提供了一种像素驱动电路的驱动方法，用于驱动上述实施例提供的像素驱动电路，上述像素驱动电路包括：漂移抑制单元1、数据写入单元2、补偿单元3和工作单元4，其中补偿单元3和工作单元4的公共端为输出节点pos，驱动方法包括多个驱动周期，每个驱动周期包括如下时段。
漂移抑制时段p1，向漂移抑制单元1输入基准控制信号G1和基准信号VSTRESS，使漂移抑制单元1在基准控制信号G1的控制下，将电位小于0的基准信号VSTRESS输出至补偿单元3。
重置时段p2，向漂移抑制单元1输入基准控制信号G1和基准信号VSTRESS，使漂移抑制单元1在基准控制信号G1的控制下，将基准信号VSTRESS输出至补偿单元3，使补偿单元3处于工作状态；并向补偿单元3输入处于低电位的电源电压信号VDD，将输出节点pos的电位重置为重置电 位。
补偿时段p3，向数据写入单元2输入栅极控制信号G3、数据信号Data和处于高电位的电源电压信号VDD，使数据写入单元2在栅极控制信号G3和处于高电位的电源电压信号VDD的控制下，将数据信号Data输出至补偿单元3；并向补偿单元3输入处于高电位的电源电压信号VDD，将输出节点pos的电位从重置电位上拉至第一电位。
数据写入时段p4，向数据写入单元2输入栅极控制信号G3、数据信号Data和处于高电位的电源电压信号VDD，使数据写入单元2在栅极控制信号G3和处于高电位的电源电压信号VDD的控制下，将数据信号Data输出至补偿单元3；并使补偿单元3利用处于浮空状态的电源电压信号VDD，将输出节点pos的电位从第一电位上拉至第二电位。
工作时段p5，向补偿单元3输入处于高电位的电源电压信号VDD，使补偿单元3在处于高电位的电源电压信号VDD的作用下生成一驱动信号，利用驱动信号驱动工作单元4工作。
本发明实施例提供的像素驱动电路的驱动方法中，在漂移抑制时段p1，漂移抑制单元1能够在基准控制信号G1的控制下将电位小于0的基准信号VSTRESS输出给补偿单元3，将补偿单元3中的驱动开关管Td的栅极电位变为负电位，使得在每个驱动周期内，驱动开关管Td的栅极电位能够在负电位和正电位(高电位)之间交替，很好的避免了由于补偿单元3中驱动开关管Td的栅极长期处于高偏压下工作所导致的阈值电压Vth漂移的问题，保证了扫描信号的正常输出。
上述实施例提供的像素驱动电路还可以包括与补偿单元3连接的电源单元5，电源单元5接收电源控制信号G4和电源电压信号VDD；在漂移抑制时段p1和重置时段p2，向电源单元5输入电源控制信号G4和处于低电位的电源电压信号VDD，使电源单元5在电源控制信号G4的控制下将处于低电位的电源电压信号VDD输出至补偿单元3；在补偿时段p3和工作时段p5，使电源单元5在电源控制信号G4的控制下将处于高电位的电源电压信号VDD输出至补偿单元3；在数据写入时段p4，使电源单元5在电源控制信号G4的控制下将补偿单元3接收的电源电压信号VDD处于浮空状态。
当上述像素驱动电路中引入电源单元5时，其对应的驱动方法所产生的 有益效果已在上述结构实施例部分描述，此处不再说明。
本实施例还提供了一种阵列基板，该阵列基板包括一个或多个以上各技术方案所提供的像素驱动电路，由于以上各技术方案所提供的像素驱动电路很好的避免了由于补偿单元3中驱动开关管Td的栅极长期处于高偏压下工作所导致的阈值电压Vth漂移的问题，保证了扫描信号的正常输出，因此本实施例所提供的阵列基板也具有这些优点。
本实施例还提供了一种显示装置，该显示装置包括上述阵列基板，该显示装置很好的避免了由于补偿单元3中驱动开关管Td的栅极长期处于高偏压下工作所导致的阈值电压Vth漂移的问题，保证了扫描信号的正常输出。
图3是本公开一个实施例提供的一种显示装置的示意性框图。该显示面板包括阵列基板8，该阵列基板8包括由多个像素单元81构成的阵列，每个像素单元81包括上述任一实施例的像素电路。该显示装置还可以包括数据驱动电路6和栅极驱动电路7，以用于分别提供数据信号和栅极控制信号等；该显示装置还可以包括提供电源电压信号(Vdd)等的芯片等。数据驱动电路6通过数据线61与像素单元81电连接，栅极驱动电路7通过栅线71与像素单元81电连接。当各个子像素单元中的发光元件为OLED时，则该显示装置可以为AMOLED。
需要说明的是，本实施例所提供的显示装置可以为电子纸、OLED(Organic Light-Emitting Diode，有机发光二极管)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2016年7月13日递交的中国专利申请第201610551788.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (22)

  1. 一种像素驱动电路，包括：
    漂移抑制单元，所述漂移抑制单元配置为接收基准控制信号和基准信号，并且在所述基准控制信号的控制下将所述基准信号输出；
    数据写入单元，所述数据写入单元配置为接收栅极控制信号、数据信号和电源电压信号，并且在所述栅极控制信号和电源电压信号的控制下将所述数据信号输出；
    补偿单元，所述补偿单元与所述漂移抑制单元连接且与所述数据写入单元连接，还与输出节点连接，所述补偿单元配置为接收电源电压信号，以及生成一驱动信号并输出至所述输出节点；
    工作单元，所述工作单元与所述输出节点连接，且还与电源负极连接，所述工作单元配置为在所述驱动信号的驱动下工作。
  2. 根据权利要求1所述的像素驱动电路，其中，所述漂移抑制单元包括第一开关管，
    所述第一开关管的控制端接收所述基准控制信号，所述第一开关管的输入端接收所述基准信号，所述第一开关管的输出端连接所述补偿单元。
  3. 根据权利要求1所述的像素驱动电路，其中，所述数据写入单元包括第二开关管和第三开关管；
    所述第二开关管的控制端接收电源电压信号，所述第二开关管的输入端连接所述第三开关管的输出端，所述第二开关管的输出端连接所述补偿单元；所述第三开关管的控制端接收所述栅极控制信号，所述第三开关管的输入端接收所述数据信号。
  4. 根据权利要求1所述的像素驱动电路，其中，所述补偿单元包括：
    驱动开关管，所述驱动开关管的控制端连接所述漂移抑制单元且连接所述数据写入单元，所述驱动开关管的输入端接收所述电源电压信号，所述驱动开关管的输出端连接所述输出节点；
    第一电容，所述第一电容的第一端连接所述驱动开关管的控制端，所述第一电容的第二端连接所述驱动开关管的输出端。
  5. 根据权利要求1所述的像素驱动电路，其中，所述工作单元包括：
    发光器件，所述发光器件的阳极连接所述输出节点，所述发光器件的阴极连接所述电源负极，所述发光器件用于在所述驱动信号的驱动下发光。
  6. 根据权利要求5所述的像素驱动电路，其中，所述工作单元还包括：
    第二电容，所述第二电容的第一端连接所述发光器件的阳极，所述第二电容的第二端连接所述发光器件的阴极。
  7. 根据权利要求1～6中任一项所述的像素驱动电路，其中，所述像素驱动电路还包括电源单元，所述电源单元与所述补偿单元连接，配置为接收电源控制信号和所述电源电压信号。
  8. 根据权利要求7所述的像素驱动电路，其中，所述电源单元包括：第四开关管，
    所述第四开关管的控制端接收所述电源控制信号，所述第四开关管的输入端接收所述电源电压信号，所述第四开关管的输出端连接所述补偿单元。
  9. 一种像素驱动电路的驱动方法，所述像素驱动电路包括：漂移抑制单元、数据写入单元、补偿单元和工作单元，其中所述补偿单元和所述工作单元的公共端为输出节点，所述驱动方法包括多个驱动周期，每个所述驱动周期包括：
    漂移抑制时段，向所述漂移抑制单元输入基准控制信号和基准信号，使所述漂移抑制单元在所述基准控制信号的控制下，将电位小于0的所述基准信号输出至所述补偿单元；
    重置时段，向所述漂移抑制单元输入基准控制信号和基准信号，使所述漂移抑制单元在所述基准控制信号的控制下，将所述基准信号输出至所述补偿单元，使所述补偿单元处于工作状态；并向所述补偿单元输入处于低电位的电源电压信号，将所述输出节点的电位重置为重置电位；
    补偿时段，向所述数据写入单元输入栅极控制信号、数据信号和处于高电位的电源电压信号，使所述数据写入单元在所述栅极控制信号和处于高电位的电源电压信号的控制下，将所述数据信号输出至所述补偿单元；并向所述补偿单元输入处于高电位的电源电压信号，将所述输出节点的电位从所述重置电位上拉至第一电位；
    数据写入时段，向所述数据写入单元输入栅极控制信号、数据信号和处于高电位的电源电压信号，使所述数据写入单元在所述栅极控制信号和处于 高电位的电源电压信号的控制下，将所述数据信号输出至所述补偿单元；并使所述补偿单元利用处于浮空状态的所述电源电压信号，将所述输出节点的电位从所述第一电位上拉至第二电位；
    工作时段，向所述补偿单元输入处于高电位的电源电压信号，使所述补偿单元在所述处于高电位的电源电压信号的作用下生成一驱动信号，利用所述驱动信号驱动所述工作单元工作。
  10. 根据权利要求9所述的像素驱动电路的驱动方法，所述像素驱动电路还包括与所述补偿单元连接的电源单元，所述电源单元接收电源控制信号和所述电源电压信号；
    在所述漂移抑制时段和所述重置时段，向所述电源单元输入电源控制信号和处于低电位的电源电压信号，使所述电源单元在所述电源控制信号的控制下将处于低电位的电源电压信号输出至所述补偿单元；
    在所述补偿时段和所述工作时段，使所述电源单元在所述电源控制信号的控制下将处于高电位的电源电压信号输出至所述补偿单元；
    在所述数据写入时段，使所述电源单元在所述电源控制信号的控制下将所述补偿单元接收的所述电源电压信号处于浮空状态。
  11. 一种阵列基板，包括权利要求1～8中任一项所述的像素驱动电路。
  12. 一种显示装置，包括权利要求11所述的阵列基板。
  13. 一种像素驱动电路，包括：漂移抑制单元、数据写入单元、补偿单元、工作单元、第一节点和第二节点，其中，
    所述补偿单元的控制端连接到所述第一节点，所述补偿单元的第一端用于接收电源电压信号，所述补偿单元的第二端连接到所述第二节点；
    所述漂移抑制单元的控制端用于接收基准控制信号，所述漂移抑制单元的第一端用于接收基准信号，所述漂移抑制单元的第二端连接到所述第一节点；
    所述数据写入单元的第一控制端用于接收栅极控制信号，所述数据写入单元的第二控制端用于接收所述电源电压信号，所述数据写入单元的第一端用于接收数据信号，所述数据写入单元的第二端连接到所述第一节点；
    所述工作单元的第一端连接到所述第二节点，所述工作单元的第二端用于连接到电源负极。
  14. 根据权利要求13所述的像素驱动电路，还包括电源单元，其中，所述电源单元的控制端用于接收电源控制信号，所述电源单元的第一端用于接收所述电源电压信号，所述电源单元的的第二端用于连接到所述补偿单元的第一端。
  15. 根据权利要求13～14任一所述的像素驱动电路，其中，所述漂移抑制单元包括第一开关管，
    所述第一开关管的控制端用于接收所述基准控制信号，所述第一开关管的输入端用于接收所述基准信号，所述第一开关管的输出端连接所述第一节点。
  16. 根据权利要求13～14任一所述的像素驱动电路，其中，所述数据写入单元包括第二开关管和第三开关管；
    所述第二开关管的控制端用于接收所述电源电压信号，所述第二开关管的输入端连接所述第三开关管的输出端，所述第二开关管的输出端连接所述第一节点；
    所述第三开关管的控制端用于接收所述栅极控制信号，所述第三开关管的输入端用于接收所述数据信号。
  17. 根据权利要求13～14任一所述的像素驱动电路，其中，所述补偿单元包括驱动开关管和第一电容，
    所述驱动开关管的控制端连接所述第一节点，所述驱动开关管的输入端用于接收所述电源电压信号，所述驱动开关管的输出端连接所述第二节点；
    所述第一电容的第一端连接所述第一节点，所述第一电容的第二端连接所述第二节点。
  18. 根据权利要求13～14任一所述的像素驱动电路，其中，所述工作单元包括发光器件，
    所述发光器件的阳极连接所述第二节点，所述发光器件的阴极连接所述电源负极，所述发光器件用于在驱动信号的驱动下发光。
  19. 根据权利要求18所述的像素驱动电路，其中，所述工作单元还包括：第二电容，
    所述第二电容的第一端连接所述发光器件的阳极，所述第二电容的第二端连接所述发光器件的阴极。
  20. 根据权利要求14所述的像素驱动电路，其中，所述电源单元包括第四开关管，
    所述第四开关管的控制端用于接收所述电源控制信号，所述第四开关管的输入端用于接收所述电源电压信号，所述第四开关管的输出端连接所述补偿单元。
  21. 一种根据权利要求13的像素驱动电路的驱动方法，包括多个驱动周期，每个所述驱动周期包括：
    漂移抑制时段，向所述漂移抑制单元输入所述基准控制信号和所述基准信号，使所述漂移抑制单元在所述基准控制信号的控制下，将电位小于0的所述基准信号输出至所述补偿单元；
    重置时段，向所述漂移抑制单元输入所述基准控制信号和所述基准信号，使所述漂移抑制单元在所述基准控制信号的控制下，将所述基准信号输出至所述补偿单元，使所述补偿单元处于工作状态；向所述补偿单元输入处于低电位的所述电源电压信号，将所述输出节点的电位重置为重置电位；
    补偿时段，向所述数据写入单元输入所述栅极控制信号、所述数据信号和处于高电位的所述电源电压信号，使所述数据写入单元在所述栅极控制信号和处于高电位的所述电源电压信号的控制下，将所述数据信号输出至所述补偿单元；向所述补偿单元输入处于高电位的所述电源电压信号，将所述输出节点的电位从所述重置电位上拉至第一电位；
    数据写入时段，向所述数据写入单元输入所述栅极控制信号、所述数据信号和处于高电位的所述电源电压信号，使所述数据写入单元在所述栅极控制信号和处于高电位的所述电源电压信号的控制下，将所述数据信号输出至所述补偿单元；使所述补偿单元利用处于浮空状态的所述电源电压信号，将所述输出节点的电位从所述第一电位上拉至第二电位；
    工作时段，向所述补偿单元输入处于高电位的电源电压信号，使所述补偿单元在所述处于高电位的电源电压信号的作用下生成一驱动信号，利用所述驱动信号驱动所述工作单元工作。
  22. 根据权利要求21所述的驱动方法，其中，所述像素驱动电路还包括与所述补偿单元连接的电源单元，所述电源单元接收电源控制信号和所述电源电压信号，所述方法还包括：
    在所述漂移抑制时段和所述重置时段，在所述电源控制信号的控制下将处于低电位的所述电源电压信号输出至所述补偿单元；在所述补偿时段和所述工作时段，在所述电源控制信号的控制下将处于高电位的所述电源电压信号输出至所述补偿单元；在所述数据写入时段，在所述电源控制信号的控制下使所述补偿单元接收的所述电源电压信号处于浮空状态。
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