WO2017220026A1 - 发光二极管及其制作方法 - Google Patents

发光二极管及其制作方法 Download PDF

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Publication number
WO2017220026A1
WO2017220026A1 PCT/CN2017/089811 CN2017089811W WO2017220026A1 WO 2017220026 A1 WO2017220026 A1 WO 2017220026A1 CN 2017089811 W CN2017089811 W CN 2017089811W WO 2017220026 A1 WO2017220026 A1 WO 2017220026A1
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WIPO (PCT)
Prior art keywords
chip
region
carrier
emitting diode
layer
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PCT/CN2017/089811
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English (en)
French (fr)
Inventor
于平
李威霆
陈国扬
李慎初
潘科豪
林治民
吕宗霖
赖仁雄
余韦廷
Original Assignee
亿光电子工业股份有限公司
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Publication of WO2017220026A1 publication Critical patent/WO2017220026A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages

Definitions

  • the present invention relates to a light emitting diode and a method of fabricating the same, and more particularly to a package structure of a light emitting diode and a method of fabricating the same.
  • CSP chip scale package
  • SMT Surface Mount Technology
  • the invention provides a light emitting diode with better structural reliability and luminous efficiency.
  • the invention also provides a method for fabricating a light emitting diode for fabricating the above light emitting diode.
  • the light emitting diode of the present invention comprises a chip, a carrier and an encapsulating material.
  • the carrier board includes: a conductive region having an upper surface and a lower surface; an insulating region covering at least a portion of the conductive region; wherein the conductive region includes at least one first contact region, and the lower surface of the conductive region is not covered by the insulating region Between the adjacent first contact regions, a first spacing; at least one second contact region, the region of the upper surface of the conductive region not covered by the insulating region, and a second between the adjacent second contact regions The spacing; wherein the first spacing is greater than the second spacing.
  • the encapsulating material covers part of the surface of the chip directly or indirectly.
  • the packaging material of the light emitting diode of the present invention is a light transmissive material, including silica gel, quartz, glass, light transmissive ceramic, thermoplastic resin, and thermosetting resin.
  • the encapsulating material may also include a fluorescent substance or light scattering particles.
  • the LED of the present invention has a third pitch between adjacent second contact regions, and the first pitch is greater than the third pitch, and the third pitch is less than or equal to the second pitch.
  • the light emitting diode of the present invention has an insulating region of the carrier including a first insulating layer, a second insulating layer, and a third insulating layer, and the second insulating layer is located between the first insulating layer and the third insulating layer.
  • the first insulating layer has at least one first opening
  • the second insulating layer has at least one second opening
  • the third insulating layer has at least one third opening, and a portion of the lower surface and a portion of the upper surface of the conductive region of the carrier are respectively exposed The first opening and the third opening.
  • the conductive region of the LED of the present invention also includes a plurality of conductive layer structures, wherein adjacent conductive layers are connected by at least one conductive via.
  • the LED of the present invention also includes a protective layer disposed on the carrier and surrounding the chip directly or indirectly, at least one side of the protective layer being substantially coplanar with at least one side of the carrier.
  • the LED of the present invention has a packaging material directly or indirectly covering at least a portion of the surface of the chip that is relatively far from the carrier and at least a portion of the surface of the protective layer, and at least one side of the encapsulation material and at least one of the protective layer. One side is substantially coplanar.
  • the LED of the present invention may be partially disposed between the chip and the protective layer.
  • the LED of the present invention has a chip having a surface having a surface that is spaced from the upper surface of the conductive region of the carrier by a distance less than a surface of the chip having no other surface of the electrode and the conductive region of the carrier. The distance from the surface.
  • the chip of the light emitting diode of the present invention is flip-chip mounted on the second contact region of the carrier.
  • the light emitting diode of the present invention may include an electrostatic protection component disposed on the carrier.
  • the light emitting diode of the present invention may include a surface coating disposed on at least one of an upper surface and a lower surface of the conductive region of the carrier.
  • the second contact region and the first contact region of the conductive region of the light emitting diode of the present invention are respectively recessed in the insulating region.
  • a method of fabricating a light emitting diode of the present invention includes the following steps of: providing a carrier. At least one chip is disposed on the carrier board, and the chip has a top surface and a bottom surface opposite to each other, wherein the top surface is away from the carrier board. paste A release layer is attached to the top surface of the chip, wherein the front projection area of the release layer on the carrier is greater than or equal to the orthographic projection area of the chip on the carrier.
  • the carrier plate carrying the chip and the release layer is placed in a concave mold such that the release layer is located at a bottom of the concave mold, and a gap is formed between one side of the chip and an inner surface of the concave mold.
  • a protective layer is formed on the side of the chip in the gap.
  • the concave mold and the release layer are removed to expose a top surface of the chip and a surface of the protective layer, wherein the top surface of the chip is substantially coplanar with the surface of the protective layer.
  • the chip is electrically connected to the carrier through the conductive region, wherein the first spacing between the first contact regions of the carrier is greater than the second spacing between the second contact regions, thus
  • the first contact area of the carrier board can increase the contact area of the light emitting diode with the circuit board, and the problem of short circuit caused by solder overflow can be avoided.
  • FIG. 1 is a cross-sectional view of a light emitting diode according to an embodiment of the invention.
  • FIG. 2 is a cross-sectional view of a light emitting diode according to another embodiment of the present invention.
  • FIG 3 is a cross-sectional view of a light emitting diode according to another embodiment of the present invention.
  • FIG. 4 is a cross-sectional view showing a light emitting diode according to another embodiment of the present invention.
  • FIG. 5 is a cross-sectional view showing a light emitting diode according to another embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of a light emitting diode according to another embodiment of the present invention.
  • FIG. 7A is a cross-sectional view of a light emitting diode according to another embodiment of the present invention.
  • FIG. 7B is a schematic top view of the carrier of the light emitting diode of FIG. 7A.
  • FIG. 7C is a cross-sectional view taken along line I-I of FIG. 7B.
  • FIG. 8 is a cross-sectional view showing a carrier board according to another embodiment of the present invention.
  • FIG. 9A is a schematic top view of a carrier board according to an embodiment of the invention.
  • 9B is a cross-sectional view taken along line A-A of FIG. 9B.
  • 9C is a cross-sectional view taken along line B-B of FIG. 9B.
  • FIG. 10 is a cross-sectional view showing a light emitting diode according to another embodiment of the present invention.
  • FIG. 11 is a cross-sectional view showing a light emitting diode according to another embodiment of the present invention.
  • FIG. 12A is a schematic top view of a light emitting diode according to another embodiment of the present invention.
  • FIG. 12B is a partial perspective view of the light emitting diode of FIG. 12A.
  • FIG. 13 is a top plan view of a light emitting diode according to another embodiment of the present invention.
  • FIG. 14A is a top plan view of a carrier board according to another embodiment of the present invention.
  • Figure 14B is a bottom plan view of the carrier of Figure 14A.
  • FIG. 15A is a schematic top view of a carrier board according to another embodiment of the present invention.
  • FIG. 15A is a schematic top view of a carrier board according to another embodiment of the present invention.
  • FIG. 15B is a schematic top view of a carrier board according to another embodiment of the present invention.
  • 16A-16F are schematic cross-sectional views showing a method of fabricating an LED according to an embodiment of the invention.
  • FIG. 17A is a schematic top view of a light emitting diode according to another embodiment of the present invention.
  • 17B is a cross-sectional view taken along line C-C of FIG. 17A.
  • 112b3, 112g2, 112h2 second conductive layer
  • the LED 100a of the present embodiment includes a carrier 110a, a chip 130a, and a package material 140a.
  • the carrier 110a includes a conductive region 112a and an insulating region 114a.
  • the conductive region 112a has an upper surface S1 and a lower surface S2.
  • the insulating region 114a covers at least a portion of the conductive region 112a, and a portion of the upper surface S1 of the conductive region 112a is not covered by the insulating region 114a, which is referred to as a second contact region CP (only two are schematically shown in FIG.
  • the portion of the lower surface S2 is not covered by the insulating region 114a, and is referred to as a first contact region SP (only two are schematically shown in FIG. 1), wherein the adjacent first contact regions SP have a first pitch P1 therebetween.
  • the chip electrodes 120a (two are schematically shown in FIG. 1) of the chip 130a are directly or indirectly in contact with the second contact regions CP of the conductive regions 112a, respectively, wherein the adjacent second contact regions CP have a second pitch P2 therebetween. And the first pitch P1 is greater than the second pitch P2.
  • the chip 130a is electrically connected to the carrier 110a via the chip electrode 120a.
  • the encapsulation material 140a may directly or indirectly cover a portion of the surface of the chip 130a. In FIG. 1, the encapsulation material 140a covers a top surface 132a of the chip 130a that is relatively far from the carrier 110a.
  • the carrier 110a of the present embodiment is embodied as a single-layer metal substrate, wherein the insulating region 114a includes a first insulating layer 114a1, a second insulating layer 114a2, and a third insulating layer 114a3, and the conductive region 112a It is at least one conductive layer 112a1.
  • the second insulating layer 114a2 is located between the first insulating layer 114a1 and the third insulating layer 114a3, wherein the first insulating layer 114a1 has at least one first opening 115a1, and the second insulating layer 114a2 has at least one second opening 115a2, and
  • the three insulating layers 114a3 have at least one third opening 115a3.
  • the conductive region 112a is located in the second opening 115a2 and is substantially flush with the second insulating layer 114a2.
  • the conductive region 112a has an upper surface S1 and a lower surface S2, and the first opening 115a1 exposes a portion of the lower surface S2 of the conductive region 112a.
  • the third opening 115a3 exposes a portion of the upper surface S1 of the conductive region 112a.
  • the conductive region 112a and the second insulating layer 114a2 are substantially in the same horizontal plane.
  • the materials of the first insulating layer 114a1, the second insulating layer 114a2, and the third insulating layer 114a3 may be the same or different, and the conductive region 112a may be made of copper foil, silver, gold, aluminum or other metal materials having electrical conductivity and thermal conductivity. .
  • the chip electrode 120a of the present embodiment is located on a bottom surface 134a of the chip 130a that is relatively far from the top surface 132a.
  • the chip 130a is flip-chip bonded to the conductive region 112a of the carrier 110a by the chip electrode 120a. Electrical connection.
  • the distance between the bottom surface 134a of the chip 130a and the upper surface S1 of the conductive region 112a is smaller than the distance between the top surface 132a of the chip 130a and the upper surface S1 of the conductive region 112a.
  • the chip 130a For example, a blue light emitting diode chip, a red light emitting diode chip, a white light emitting diode chip or an ultraviolet light emitting diode chip.
  • the light emitting diode 100a of the present embodiment may further include at least one first surface coating 150a or at least one second surface coating 160a.
  • the first surface coating 150a is disposed in the second contact region CP of the conductive region 112a and directly contacts the upper surface S1 of the conductive region 112a.
  • the first surface coating 150a is located between the chip electrode 120a and the conductive region 112a.
  • the second surface coating layer 160a is disposed in the first contact region SP of the conductive region 112a and directly contacts the lower surface S2 of the conductive region 112a.
  • the material of the first surface coating layer 150a and the second surface coating layer 160a is selected from a metal material which is convenient for subsequent solid crystal printing, such as silver, gold, gold tin, nickel silver (Ni/Ag). , nickel-palladium gold (Ni/Pt/Au) coating or other suitable metal or alloy.
  • a metal material which is convenient for subsequent solid crystal printing, such as silver, gold, gold tin, nickel silver (Ni/Ag). , nickel-palladium gold (Ni/Pt/Au) coating or other suitable metal or alloy.
  • the thickness of the first surface coating layer 150a of the present embodiment is smaller than the thickness of the third insulating layer 114a3, that is, the second contact region CP is recessed in the third insulating layer 114a3, when the chip electrode 120a is to be used
  • the second contact region CP of the conductive region 112a is directly or indirectly contacted, the problem that the two chip electrodes 120a are electrically connected due to solder overflow can be avoided, thereby causing a short circuit.
  • the above solder is, for example, a gold ball, a solder paste, a eutectic bonding material or an anisotropic conductive paste.
  • the thickness of the second surface coating layer 160a of the present embodiment is smaller than the thickness of the first insulating layer 114a1, that is, the first contact region SP is recessed in the first insulating layer 114a1, when the light emitting diode 100a is soldered When soldering to other circuit boards (not shown), it is possible to avoid the problem that the solder overflows to the adjacent first contact region SP and causes a short circuit.
  • the light emitting diode 100a of the present embodiment may further include a protective layer 170a, wherein the protective layer 170a is disposed on the carrier 110a and disposed directly or indirectly around the chip 130a.
  • the protective layer 170a directly contacts the peripheral surface 136a of the chip 130a, and at least one side of the protective layer 170a is substantially coplanar with at least one side of the carrier 110a.
  • the material of the protective layer 170a is, for example, silica gel or epoxy-based and doped with one of titanium dioxide, silicon dioxide, zirconium oxide, boron nitride or a combination thereof.
  • the protective layer 170a may also have a reflective function that reflects more than 30%, preferably 50% or more, and more preferably 70% or more of light from the chip 130a.
  • the encapsulating material 140a of the present embodiment is a light transmissive material, and may include silica gel, quartz, glass, light transmissive ceramic, thermoplastic resin, thermosetting resin, and may also include a fluorescent substance or light scattering particles.
  • the encapsulation material 140a directly or indirectly covers at least a portion of the top surface 132a of the chip 130a that is relatively far from the carrier 110a and at least a portion of the surface of the protective layer 170a.
  • the fluorescent substance is, for example, a garnet series material of an aluminate, a silicate series material, a nitride series material, a phosphate series material, a sulfide series material, or a niobate salt, and the like, and is not limited thereto.
  • the phosphor may be selected from one or more of the following groups: ⁇ -SiAlON, Sr 5 (PO 4 ) 3 Cl:Eu 2+ , (Sr,Ba)MgAl 10 O 17 :Eu 2+ , (Sr,Ba) 3 MgSi 2 O 8 :Eu 2+ , SrAl 2 O 4 :Eu 2+ , SrBaSiO 4 :Eu 2+ , CdS:In, CaS:Ce 3+ ,Y 3 (Al , Gd) 5 O 12 :Ce 3+ , (Y,Gd) 3 Al 5 O 12 :Ce 3+ , Y 3 Al 5 O 12 :Ce 3+ , Y 3 (Al,Ga) 5 O 12 :Ce 3 + , Lu 3 Al 5 O 12 :Ce 3+ , (Y,Lu) 3 Al 5 O 12 :Ce 3+ , Lu 3 (Al,Ga) 5 O 12
  • the above-mentioned encapsulating material 140a is a light transmissive material, preferably an epoxy resin composition or a siloxane based resin composition.
  • the encapsulating material may be doped with a diffusing agent, a thickener, an antioxidant, or other materials that increase the light extraction efficiency or light uniformity of the chip 130a, which is still claimed in the present invention. The scope.
  • the chip 130a of the present embodiment is electrically connected to the carrier 110a via the chip electrode 120a, wherein the first pitch P1 between the first contact regions SP of the carrier 110a is greater than the second between the second contact regions CP.
  • the pitch P2 is such that when the LED 100a is soldered to the circuit board, a wider electrical connection region can be provided to avoid the short circuit problem caused by solder overflow when the device is hit.
  • the first contact area SP of the carrier 110a having a wide cross-sectional area The contact area of the light emitting diode 100a with the solder can also be increased, thereby improving the heat dissipation effect and the soldering stability of the carrier 110a.
  • the first contact region SP can be disposed to be recessed in the insulating region 114a, the problem of solder overflow and short circuit can be further avoided. Therefore, the light emitting diode 100a of the present embodiment can be applied to a micro LED or a chip scale package.
  • FIG. 2 is a cross-sectional view of a light emitting diode according to another embodiment of the present invention.
  • the LED 100b of the present embodiment is similar to the LED 100a of FIG. 1.
  • the encapsulation material 140b of the present embodiment directly or indirectly covers the chip 130a and the portion of the encapsulation material 140b.
  • the area is between the chip 130a and the protective layer 170b.
  • the LED 100c of the present embodiment is similar to the LED 100b of FIG. 2, and the difference between the two is that in the embodiment, the two chip electrodes 120c are respectively located on the bottom surface 134a and the top surface of the chip 130c.
  • the chip 130c is, for example, a vertical chip in which the chip electrode 120c located on the bottom surface 134a is directly disposed on the carrier 110a, for example.
  • the other chip electrode 120c located on the top surface 132a is electrically connected to the carrier 110a via a wire W1.
  • the LED 100d of the present embodiment is similar to the LED 100c of FIG. 3, and the difference between the two is that the chip 130d of the embodiment is, for example, a horizontal chip, wherein the two chip electrodes of the chip 130d are 120d is located on the top surface 132a of the chip 130d, and the two chip electrodes 120d are electrically connected to the carrier 110a through the wires W2, respectively.
  • the chip 130d of the embodiment is, for example, a horizontal chip, wherein the two chip electrodes of the chip 130d are 120d is located on the top surface 132a of the chip 130d, and the two chip electrodes 120d are electrically connected to the carrier 110a through the wires W2, respectively.
  • FIG. 5 is a cross-sectional view showing a light emitting diode according to another embodiment of the present invention.
  • the light emitting diode 100e of the present embodiment is similar to the light emitting diode 100a of FIG. 1.
  • the conductive region 112b of the carrier 110b of the embodiment includes a plurality of conductive layer structures. And adjacent two conductive layers are connected by at least one conductive via 112b2.
  • the insulating region 114b of the carrier 110b of the present embodiment includes a first insulating layer 114b1, a second insulating layer 114b2, and a third insulating layer 114b3, wherein the second insulating layer 114b2 is located on the first insulating layer 114b1. Between the third insulating layers 114b3.
  • the conductive region 112b of the carrier 110b includes at least one first conductive layer 112b1, at least one conductive via 112b2, and at least one second guide Electrical layer 112b3.
  • the first conductive layer 112b1 and the second conductive layer 112b3 are respectively located on opposite sides of the second insulating layer 114b2.
  • the conductive vias 112b2 penetrate through the second insulating layer 114b2 and are electrically connected to the first conductive layer 112b1 and the second conductive layer 112b3.
  • the first conductive layer 112b1 has a lower surface S2, and the second conductive layer 112b3 has an upper surface S1.
  • the insulating region 114b covers at least a portion of the conductive region 112b.
  • the portion of the upper surface S1 of the conductive region 112b is not covered by the insulating region 114b, and is called the second contact region CP.
  • the lower surface S2 of the conductive region 112b is not covered by the insulating region 114b. It is a first contact region SP in which a first pitch P1 is formed between adjacent first contact regions SP.
  • the chip electrodes 120a of the chip 130a are in direct or indirect contact with the second contact regions CP of the conductive regions 112b, respectively, wherein the adjacent second contact regions CP have a second pitch P2 between them, and the first pitch P1 is greater than the second pitch P2. .
  • the chip 130a is electrically connected to the carrier 110b through the chip electrode 120a.
  • the first pitch P1 between the first contact regions SP of the carrier 110b of the embodiment is greater than the second pitch P2 between the second contact regions CP, when the LED 100e is soldered to other circuit boards, the printing can be avoided. Short circuit problem caused by solder overflow.
  • the first contact area SP of the carrier board 110b having a wide cross-sectional area can also increase the contact area of the LED 100e with the circuit board, thereby improving the heat dissipation effect and the soldering stability of the carrier board 110b.
  • the first contact region SP can be disposed to be recessed in the insulating region 114b, the problem of solder overflow and short circuit can be further avoided. Therefore, the light emitting diode 100e of the present embodiment can be applied to a micro LED or a chip scale package.
  • FIG. 6 is a cross-sectional view of a light emitting diode according to another embodiment of the present invention.
  • the LED 100f of the present embodiment is similar to the LED 100e of FIG. 5, and the difference between the two is that the encapsulation material 140b of the present embodiment directly or indirectly covers the chip 130a and a portion thereof is located on the chip 130a. Between the protective layers 170b. That is, the encapsulation material 140b of the present embodiment is filled in the gap between the chip 130a and the protective layer 170b, and the protective layer 170b directly contacts the encapsulation material 140b.
  • FIG. 7A is a cross-sectional view of a light emitting diode according to another embodiment of the present invention.
  • FIG. 7B is a schematic top view of the carrier of the light emitting diode of FIG. 7A.
  • 7C is a cross-sectional view taken along line I-I of FIG. 7B.
  • the carrier in Fig. 7A is a section along the line II-II of Fig. 7B.
  • the light emitting diode 100g of the present embodiment is similar to the light emitting diode 100a of FIG. 1.
  • the insulating region 114g of the carrier 110g of the present embodiment includes a first insulating layer 114g1 and A second insulating layer 114g2.
  • the conductive region 112g includes at least one first conductive layer 112g1, at least one second conductive layer 112g2, and an extended pattern 113g.
  • the first insulating layer 114g1 has at least one first opening 115g1.
  • the first conductive layer 112g1 has a lower surface S2 and is located within the first opening 115g1 to form a first contact region SP.
  • Second insulating layer 114g2 There is at least one second opening 115g2.
  • the second conductive layer 112g2 has an upper surface S1 disposed on the first conductive layer 112g1 and located in the second opening 115g2 to form a second contact region CP.
  • the extension pattern 113g connects the second conductive layers 112g2 of the different element regions, but the extension pattern 113g does not connect the second conductive layers 112g2 in the same element region. However, in other embodiments, the extension pattern 113g may also connect the first conductive layer 112g1 of different component regions or penetrate the first insulating layer 114g1 and the second insulating layer 114g2, which are still within the scope of the present invention.
  • the structural shape of the conductive region 112g and the extension pattern 113g may be formed by stamping, etching, or the like, and the material of the insulating region 114g may use a solder resist commonly used for semiconductors, which has suitable heat resistance and workability.
  • a reflective material such as titanium dioxide, silicon dioxide, zirconium oxide, boron nitride or any combination of the foregoing may be added to the insulating region 114g to improve the light-emitting effect of the light-emitting diode 100g.
  • a surface coating (not shown) may be added on the upper surface S1 or the lower surface S2 of the conductive region 112g to avoid oxidation or moisture of the conductive region 112g.
  • the second conductive layer 112g2 of the present embodiment protrudes from the second insulating layer 114g2, and the chip electrode 120a directly or indirectly contacts the second conductive layer 112g2 or, for example, directly contacts the second conductive layer 112g2.
  • Surface coating (not shown).
  • the pitch P1 between the first contact regions SP is larger than the pitch P3 between the second contact regions CP, and the pitch P1 between the first contact regions SP is also larger than the pitch P2 between the chip electrodes.
  • the orthographic projection of the second conductive layer 112g2 on the first conductive layer 112g1 at least partially overlaps the first conductive layer 112g1. As shown in FIG.
  • the first conductive layer 112g1 and the second conductive layer 112g2 are stacked in a stepped shape.
  • the encapsulation material 140g covers the chip 130a, for example, directly or indirectly.
  • at least one side of the encapsulating material 140g is coplanar with at least one side of the carrier 110g.
  • FIG. 8 is a cross-sectional view showing a carrier board according to another embodiment of the present invention.
  • the carrier 110h of the present embodiment is similar to the carrier 110g of FIG. 7A, and the difference is that the second conductive layer 112h2 of the conductive region 112h of the embodiment is on the first conductive layer 112h1.
  • the upper orthographic projection completely overlaps the first conductive layer 112h1.
  • the width of the second opening 115h2 of the second insulating layer 114h2 is greater than the width of the first opening 115h1 of the first insulating layer 114h1 such that the width of the second conductive layer 112h2 is greater than the width of the first conductive layer 112h1, thereby forming an upper width
  • the narrow conductive region 112h can make the insulating region 114h have a good coupling force when covering the conductive region 112h, and reduce the occurrence of the conductive region 112h and the insulating region 114h falling off.
  • FIG. 9A is a schematic top view of a carrier board according to an embodiment of the invention.
  • 9B is a cross-sectional view taken along line A-A of FIG. 9A.
  • 9C is a cross-sectional view taken along line B-B of FIG. 9A.
  • the carrier 110j of the present embodiment is similar to the carrier 110h of FIG. 8, and the difference is that the insulating region 114j of the carrier 110j of the present embodiment includes the first insulation.
  • the layer 114j1 and the second insulating layer 114j2 further include a third insulating layer 114j3 disposed on the portion of the second conductive layer 112h2 and the second insulating layer 114j2.
  • the partial upper surface S1 of the second conductive layer 112h2 is not covered by the third insulating layer 114j3, and the height of the second insulating layer 114j2 between the second contact regions CP is not higher than the height of the second contact region CP, which can avoid subsequent chip bonding.
  • the time is blocked by the insulating region 114j.
  • FIG. 10 is a cross-sectional view showing a light emitting diode according to another embodiment of the present invention.
  • the LED 100k of the present embodiment is similar to the LED 100g of FIG. 7A.
  • the LED 100k of the present embodiment further includes a protective layer 170k disposed on the carrier 110g. It is disposed directly and indirectly around the chip 130a.
  • the encapsulation material 140k directly or indirectly covers the chip 130a.
  • at least one side of the protective layer 170k is coplanar with at least one side of the carrier 110g.
  • FIG. 11 is a cross-sectional view showing a light emitting diode according to another embodiment of the present invention.
  • the LED 100m of the present embodiment is similar to the LED 100g of FIG. 7A, and the difference between the two is that the LED 100m of the present embodiment further includes a protective layer 170m disposed on the carrier 110g. It is disposed directly and indirectly around the chip 130a.
  • the protective layer 170m covers at least a peripheral surface 136m of the chip 130m, a portion of the upper surface S1 of the second conductive layer 112g2, and a first surface 111g of the carrier 110g.
  • the encapsulation material 140m directly or indirectly covers the top surface 132a of the chip 130a and the protective layer 170m, and at least one side of the encapsulation material 140m and at least one of the protection layers 170m
  • One side or at least one side of the carrier 110g is coplanar.
  • FIG. 12A is a schematic top view of a light emitting diode according to another embodiment of the present invention.
  • FIG. 12B is a partial perspective view of the light emitting diode of FIG. 12A. Please refer to FIG. 5, FIG. 12A and FIG. 12B at the same time.
  • the light-emitting diode 100n of the present embodiment is similar to the light-emitting diode 100e of FIG. 5, and the difference between the two is that the light-emitting diode 100n of the present embodiment has a structure before being singulated, and includes a plurality of chips 130a respectively disposed on the carrier 110b. On the component area.
  • the carrier layer 110b includes a plurality of first connection layers 113b1 and a second connection layer 113b2, wherein the first connection layer 113b1 is used to connect, for example, the second conductive layer 112b3 of a different element region, and the second connection layer 113b2 is used.
  • a negatively charged first conductive layer 112b1 is connected to different element regions.
  • the second conductive layers 112b3 located in the respective element regions of the same row (for example, the first row) are connected to each other by the first connection layer 113b1, and are finally electrically connected to the positive electrode of the same row (for example, the first row).
  • Test point E1 is used to connect, for example, the second conductive layer 112b3 of a different element region
  • Test point E1 a negatively charged first conductive layer 112b1 is connected to different element regions.
  • the second conductive layers 112b3 located in the respective element regions of the same row (for example, the first row) are connected to each other by the first connection layer
  • the first conductive layers 112b1 located in the respective element regions of the same column (for example, the first column) are connected to each other by the second connection layer 113b2, and the most The final connection is to the negative test point E2 of the same column (for example, the first column).
  • the second conductive layer 112b3, which is connected to each other under the chip 130a by the first connection layer 113b1, is located in a diagonally opposite direction of the first conductive layer 112b1 connected to the second connection layer 113b2.
  • the arrangement extending direction of the positive electrode test point E1 is an arrangement extending direction perpendicular to the negative electrode test point E2.
  • FIG. 12B is a partial perspective view of the light emitting diode of FIG. 12A.
  • the carrier board having the double-layer metal substrate has two upper and lower conductive layers, so that the first connection layer 113b1 for performing positive electrode interconnection and the second connection layer 113b2 for performing negative electrode interconnection can be respectively disposed on the second insulation.
  • the first connection layer 113b1 is located obliquely above the second connection layer 113b2, so that the second conductive layer 112b3 connecting the positive electrodes of the different element regions and the first conductive layer 112b1 connecting the negative electrodes can be shifted from each other. And avoid the problem of short circuit.
  • the circuit configuration of the double-layer metal substrate is more convenient for electrically connecting the conductive layers of adjacent element regions of the same column or the same row.
  • the phosphor coating operation can be performed in the process, and the color and brightness of the light emitted by the chip 130a in each component region can be electrically measured. It can be known whether the coating condition of the phosphor is satisfactory, in order to determine whether to stop or continue the above coating operation, and the phosphor coating can be sprayed, dispensed or covered with a fluorescent patch or other phosphor package. For example, when the phosphor coating condition on the chip 130a disposed in the component region is to be known, the positive electrode probe and the negative electrode probe may be respectively pressed against one of the positive electrode test points E1 and one of the negative electrode test points E2.
  • the phosphor coating condition of the chip 130a at the relative position can be known. After the phosphor coating process or other phosphor packaging process is completed, the singulation can be performed to obtain a plurality of individual light emitting diodes, such as the light emitting diode 100e of FIG. It is worth mentioning that the LED after cutting may leave an electrical residual point on at least one side of the LED 100e. For example, in this embodiment, one side of the LED 100n may be left to connect adjacent Two electrical residual points of the first connection layer 113b1 and the second connection layer 113b2 (shown in FIG. 12A) of the element region, and the first side of the light emitting diode 100n leaves a portion for connecting adjacent element regions An electrical residual point of the second connection layer 113b2. In short, each of the LEDs 100n after cutting has at least a plurality of electrical residual points, which may be located at the same horizontal plane or different horizontal planes, and the position of the electrical residual points is not limited thereto.
  • the reason why the electrical measurement points (ie, the positive electrode test point E1 and the negative electrode test point E2) are disposed on the front surface of the carrier having the two-layer metal substrate is that there is a double-layer metal substrate or a single-layer metal substrate.
  • the thickness of the carrier board is very thin, so in the process, it needs to be on the carrier board with single/double metal substrate.
  • the back side is additionally adhered to a relatively hard carrier substrate to facilitate subsequent processing without damaging the substrate during the process to cause yield problems.
  • the slave since the current spot measurement is performed from the back surface of the integrated circuit board, in the case where the back surface of the carrier board having the single/double metal substrate is adhered with a carrier substrate (not shown), the slave has a single/double It is not feasible to perform spot measurement on the back side of the carrier of the layer metal substrate. Therefore, if spot testing is performed on a carrier board equipped with a chip, it is necessary to extend the electrical measurement point to the front side of the carrier board so that it can be spot-measured from the front side of the carrier board. Since the circuit configuration of the carrier board having the double-layer metal substrate in this embodiment can realize the pre-measurement point on the front side of the carrier board, it can meet the requirements of the subsequent procedures for performing the spot measurement. It is additionally mentioned that after the above packaging process is completed, the carrier substrate can be torn off and then subjected to a subsequent singulation cutting step.
  • FIG. 13 is a top plan view of a light emitting diode according to another embodiment of the present invention.
  • the light emitting diode 100p of the present embodiment is similar to the light emitting diode 100n of FIG. 12A, and the difference between the two is that the direction in which the positive electrode test point E1' extends is, for example, parallel to the negative test point E2'. Arrange the direction. In other words, the arrangement direction of the different positive test points E1, E1' and the negative test points E2, E2' can be selected according to different circuit configuration requirements.
  • FIG. 14A is a top plan view of a carrier board according to another embodiment of the present invention.
  • Figure 14B is a bottom plan view of the carrier of Figure 14A.
  • the carrier 110q of the embodiment may be a single-layer metal substrate or a double-layer metal substrate, which is not limited herein.
  • the third pitch P3 between the second contact regions CP of the conductive regions 112q of the carrier 110q is, for example, 200 micrometers, and the first spacing between the first contact regions SP can be made by the combination of the insulating regions 114q and the conductive regions 112q.
  • P1 is adjusted to, for example, 250 micrometers, but the adjustment of the pitch is not limited thereto.
  • FIG. 15A and 15B are schematic top views of a carrier board according to another embodiment of the present invention.
  • the carrier 110r of the present embodiment is similar to the carrier 110q of FIG. 14A, and the difference between the two is that at least one electrostatic protection component is disposed on the carrier 110r of the embodiment. 180a, wherein the electrostatic protection element 180a is, for example, a Zener diode or a transient suppression diode (TSV).
  • TSV transient suppression diode
  • the chip, the carrier, and the electrostatic protection component of the embodiments of the present invention may exhibit quadrangular combinations of different lengths, and the invention is not limited thereto.
  • the shape of the partial conductive region 112q of FIG. 14A, FIG. 14B and FIG. 15A may have a beveled shape, for example, but the beveled shape is only for the purpose of identifying the positive and negative electrodes, and the shape may be designed.
  • the square shape (such as the conductive region 112s of FIG. 15B) or other shapes is not limited thereto.
  • the carrier plates 110a, 110b, 110g, 110h, 110j, 110q, 110r, 110s of the present embodiment for example, the design of a single-layer metal substrate or a double-layer metal substrate
  • the chip size without the substrate can be facilitated.
  • 100e, 100f, 100g, 100k, 100m, 100n, and 100p are soldered to other subsequent boards, the short circuit caused by the tin can be avoided.
  • the design of the carrier plates 110a, 110b, 110g, 110h, 110j, 110q, 110r, 110s can also maintain or further improve the contact area with the solder during the subsequent soldering, heat dissipation effect and reliability.
  • the electrostatic protection elements 180a may be disposed on the carrier plates 110r and 110s of the embodiment to protect the chips 130a, 130c, and 130d from electrostatic damage.
  • the LEDs 100n, 100p of the present embodiment may further have positive electrode test points E1, E1' and negative electrode test points E2, E2' on the front side of the carrier plate 110b to facilitate electrical measurement during the manufacturing process.
  • FIG. 16A-16F are schematic cross-sectional views showing a method of fabricating an LED according to an embodiment of the invention.
  • the manufacturing method of the light emitting diode of this embodiment includes the following fabrication steps.
  • a carrier 110t is provided.
  • the carrier 110t may be, for example, the above-described carrier plates 110a, 110b, 110g, 110h, 110j, 110q, 110r, 110s, which may be a single-layer metal substrate, a double-layer metal substrate, or may be a removable load carrier.
  • the substrate that does not need to be removed is exemplified below, but the invention is not limited thereto.
  • At least one chip 130t is disposed on the carrier 110t, wherein the chip 130t has a top surface 132t and a bottom surface 134t opposite to each other, and the bottom surface 134t of the chip 130t is disposed on the carrier 110t.
  • the face 132t is away from the carrier 110t.
  • a plurality of chips 130t are disposed on the carrier 110t, and a single chip may be used in the embodiment of the present invention.
  • the chip 130t may be a flip-chip LED chip, a vertical LED chip, or a horizontal LED chip, which is not limited herein.
  • a release layer 10 is attached on the top surface 132t of the chip 130t, wherein the orthographic projection area of the release layer 10 on the carrier 110t is greater than or equal to the orthographic projection of the chip 130t on the carrier 110t. area.
  • the release layer 10 is, for example, a thermal release adhesive layer.
  • the release layer 10 may also have other characteristics that do not damage adjacent structures when tearing off.
  • the carrier chip 130t and the carrier 110t of the release layer 10 are placed upside down in a concave mold 30, so that the release layer 10 is located at the bottom 32 of the concave mold 30, and the chip 130t and the inner surface of the concave mold 30 ( There is a gap between the first surrounding surface 34 and the second surrounding surface 38).
  • a backing 20 is attached to the surface of the carrier 110t relatively far from the chip 130t.
  • a protective layer 170t is formed on the side of the chip 130t.
  • Figure 16E remove the concave The mold 30, the backing 20 and the release layer 10 are exposed to expose a top surface 132t of the chip 130t and a surface 172t of the protective layer 170t to expose a top surface 132t of the chip 130t and a surface 172t of the protective layer 170t, wherein the chip The top surface 132t of 130t is substantially coplanar with the surface 172t of the protective layer 170t.
  • the step of removing the release layer 10 includes heating the release layer 10, wherein the temperature of the heated release layer 10 is between 150 degrees and 270 degrees, and the time for heating the release layer 10 is between 10 seconds and 3 minutes.
  • the release layer 10 of the embodiment is embodied as a thermal release adhesive layer, when the thermal release adhesive layer is to be removed, the carrier 110t only needs to be heated to 100 degrees or more, for example, about 170 degrees up and down for about 3 minutes. Left or right, or for example, a higher temperature can be used, and the heated release layer can be removed in a matter of seconds. Since the heated release adhesive layer loses its viscosity at a high temperature, the thermal release adhesive layer can be easily removed without damaging the chip 130t and the already formed protective layer 170t.
  • ethyl acetate may also be used to remove the overflow residue of the heated release layer and/or to remove other residues using alcohol.
  • FIG. 16F directly or indirectly, forms an encapsulation material 140t on the top surface 132t of the chip 130t and the surface 172t of the protective layer 170t.
  • the encapsulating material 140t is, for example, a light transmissive material, and may include, for example, silica gel, quartz, glass, light transmissive ceramic, thermoplastic resin, thermosetting resin.
  • the encapsulating material may also include a fluorescent substance or light scattering particles. But it is not limited to this.
  • the above encapsulating material can be replaced with a fluorescent patch, for example, and the invention is not limited thereto. So far, the fabrication of light-emitting diodes that have not been singulated has been completed.
  • a removable substrate may be used, that is, the LED chip is disposed on the detachable substrate, and the LED chip is disposed.
  • the removable substrate is placed in a mold and the protective layer surrounding the chip is formed by the above method, and then the release layer is removed and subjected to subsequent processes or applications.
  • the subsequent process is, for example, after the release layer is removed, the package material is formed on a surface of the chip or the chip and the protective layer away from the detachable substrate, and then the detachable substrate is removed, and the single substrate is removed.
  • Body process cutting process
  • the singulated packaged chip can be directly used as a substrate-less chip-size package, or can be disposed on the single-layer metal substrate or the double-layer metal substrate (for example, the carrier plates 110a, 110b, and 110g, 110h, 110j, 110q, 110r, 110s).
  • the subsequent process is, for example, performing a singulation process such as dicing after the release layer is removed, and arranging the singulated structure having the chip and the protective layer surrounding the chip on the single-layer metal.
  • the process of encapsulating the material is performed on the substrate or the two-layer metal substrate (for example, the above-mentioned carrier plates 110a, 110b, 110g, 110h, 110j, 110q, 110r, 110s).
  • the LED chip can be directly disposed on the single-layer metal substrate or the double-layer metal substrate as described above (for example, the carrier plates 110a, 110b, 110g, 110h, 110j, 110q, 110r, 110s), and then used.
  • the above process method is to form a protective layer surrounding the chip.
  • the invention is not limited to the above examples.
  • FIG. 17A is a schematic top view of a light emitting diode according to another embodiment of the present invention.
  • 17B is a cross-sectional view taken along line C-C of FIG. 17A.
  • the LED 100u of the present embodiment further includes at least one electrostatic protection component 180u disposed on the carrier 110u, wherein the protective layer 170u covers the electrostatic protection component 180u, and the encapsulation material 140u is directly or indirectly configured.
  • the above electrostatic protection element 180u is, for example, a Zener diode or a transient suppression diode (TSV).
  • TSV transient suppression diode
  • the electrostatic protection element 180u when the electrostatic protection element 180u is disposed on the same carrier 110u together with the chip 130u, since it is known that the electrostatic protection element is generally black, light of the adjacent chip 130u is absorbed, resulting in a decrease in luminous efficiency of the chip 130u.
  • the periphery of the electrostatic protection element 180u of the present embodiment has a protective layer 170u which can reflect light emitted from the adjacent chip 130u, so that the luminance of the entire light emitting diode 100u can be improved.
  • the electrostatic protection element 180u can be disposed on the carrier 110u by using, for example, a flux to avoid a problem of short circuit caused by overflow of tin.
  • the chip is electrically connected to the carrier through the conductive region, wherein the first spacing between the first contact regions of the carrier is greater than the second spacing between the second contact regions. Therefore, when the light emitting diode is soldered to other circuit boards, the first contact area of the carrier board can increase the contact area of the light emitting diode with the solder, and the problem of short circuit caused by solder overflow can be avoided.
  • the above design can also maintain the heat dissipation effect and reliability of the carrier.
  • the carrier board of the present invention can also be provided with an electrostatic protection component to protect the chip from electrostatic damage.
  • the carrier layer of the present invention may also be provided with a protective layer, thereby protecting the light emitting diode and increasing the brightness (lumen number) of the light emitting diode.
  • the LED of the embodiment may further have a positive test point and a negative test point on the front side of the carrier to facilitate electrical measurement during the manufacturing process.

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Abstract

提供一种发光二极管（100a），包括一载板（110a）、一芯片（130a）以及一封装材料（140a）。载板（110a）包括一导电区（112a）以及一绝缘区（114a）。导电区（112a）具有一上表面（S1）与一下表面（S2）。绝缘区（114a）覆盖一部分导电区（112a）。导电区（112a）包括至少一第一接触区（SP），位于导电区（112a）的下表面（S2）未被绝缘区（114a）覆盖的区域。相邻的第一接触区（SP）之间具有一第一间距（P1）。导电区（112a）亦包括至少一第二接触区（CP），位于导电区（112a）的上表面（S1）未被绝缘区（114a）覆盖的区域。相邻的第二接触区（CP）之间具有一第二间距（P2），其中该第一间距（P1）大于该第二间距（P2）。芯片（130a）通过芯片电极（120a）与载板（110a）电性相接。封装材料（140a）至少覆盖芯片（130a）的相对远离载板（110a）的一顶面（132a）。

Description

发光二极管及其制作方法 技术领域
本发明是关于一种发光二极管及其制作方法，且特别是关于一种发光二极管的封装结构及其制作方法。
背景技术
为满足电子产品的轻薄短小的需求，作为电子产品的核心元件的半导体封装体也朝微型化(Miniaturization)的方向发展。近年来，业界发展出一种芯片尺寸封装体(Chip Scale Package，CSP)的微型化半导体封装体，其特点是：封装体积与发光二极管芯片尺寸的比值不大于1.2倍。在此体积的限制下，设置在发光二极管芯片的底面的电极之间的间距也会变得更会狭窄。由于传统芯片尺寸封装体(CSP)的发光二极管芯片底面的电极间距过窄，因此将芯片尺寸封装体焊接在其他板材上时，容易溢锡至两电极之间而造成短路的风险，且不利于表面贴焊技术(Surface Mount Technology，简称SMT)的应用。此外，除了提升可靠度之外，进一步提升芯片尺寸封装体的发光效率，亦是业界不断追求的目标。
发明内容
本发明提供一种发光二极管，其具有较佳的结构可靠度与发光效率。
本发明还提供一种发光二极管的制作方法，其用以制作上述的发光二极管。
本发明的发光二极管，其包括一芯片、一载板以及一封装材料。载板包括：一导电区，具有一上表面与一下表面；一绝缘区，覆盖至少一部分导电区；其中导电区包括至少一第一接触区，位于导电区的下表面未被绝缘区覆盖的区域，相邻的第一接触区之间具有一第一间距；至少一第二接触区，位于导电区的上表面未被绝缘区覆盖的区域，相邻的第二接触区之间具有一第二间距；其中第一间距大于第二间距。封装材料是直接或间接覆盖芯片的部分表面。
于一实施态样中，本发明的发光二极管的封装材料为透光材料，包括硅胶、石英、玻璃、透光陶瓷、热塑性树脂、热固性树脂。封装材料亦可包括荧光物质或光散射颗粒。
于一实施态样中，本发明的发光二极管，其中相邻的第二接触区之间尚有一第三间距，而第一间距大于第三间距，且第三间距小于或等于第二间距。
于一实施态样中，本发明的发光二极管，其载板的绝缘区包括第一绝缘层、第二绝缘层以及第三绝缘层，第二绝缘层位于第一绝缘层与第三绝缘层之间，第一绝缘层具有至少一个第一开口，第二绝缘层具有至少一个第二开口，第三绝缘层具有至少一个第三开口，载板的导电区的部分下表面与部分上表面分别露出于第一开口与第三开口。
于另一实施态样中，本发明的发光二极管的导电区亦包括一多个导电层结构，其中相邻二导电层之间以至少一导电通孔相连。
于另一实施态样中，本发明的发光二极管亦包括一保护层配置于载板上且直接或间接环绕芯片，保护层的至少一边与载板的至少一边实质上共平面。
于再一实施态样中，本发明的发光二极管，其封装材料直接或间接覆盖芯片的相对远离载板的至少部分表面与保护层的至少部分表面，且封装材料的至少一边与保护层的至少一边实质上共平面。
于再一实施态样中，本发明的发光二极管，其封装材料也可部分配置于芯片与保护层之间。
于再一实施态样中，本发明的发光二极管其芯片具有一电极的一表面与载板的导电区的上表面的距离小于芯片不具有电极的一另一表面与载板的导电区的上表面的距离。
于又一实施态样中，本发明的发光二极管的芯片以倒装焊的方式配置于载板的第二接触区上。
于另一实施态样中，本发明的发光二极管可包括一静电保护元件，配置于载板上。
于另一实施态样中，本发明的发光二极管可包括一表面涂层，配置于载板的导电区的上表面与下表面至少其中的一个上。
于另一实施态样中，本发明的发光二极管的导电区的第二接触区与第一接触区分别凹陷于绝缘区中。
本发明的发光二极管的制作方法，其包括以下制作步骤：提供一载板。配置至少一芯片于载板上，芯片具有彼此相对的一顶面与一底面，其中顶面远离载板。贴 附一离型层于芯片的顶面上，其中离型层于载板上的正投影面积大于或等于芯片于载板上的正投影面积。将承载芯片与离型层的载板倒置于一凹型模具中，使离型层位于凹型模具的一底部，且芯片的一侧面与凹型模具的一内面之间具有一空隙。于空隙中形成一保护层于芯片的侧面。移除凹型模具与离型层，以暴露出芯片的顶面与保护层的一表面，其中芯片的顶面与保护层的表面实质上共平面。直接或间接形成一封装材料于芯片的顶面与保护层的表面。
基于上述，在本发明的发光二极管中，芯片通过导电区与载板电性连接，其中载板的第一接触区之间的第一间距大于第二接触区之间的第二间距，因此当发光二极管通过焊料而焊接至其他电路板时，载板的第一接触区可增加发光二极管与电路板的接触面积，且可以避免焊料溢流导致短路的问题。
附图概述
本发明的特征、性能由以下的实施例及其附图进一步描述。
图1绘示为本发明的一实施例的一种发光二极管的剖面示意图。
图2绘示为本发明的另一实施例的一种发光二极管的剖面示意图。
图3绘示为本发明的另一实施例的一种发光二极管的剖面示意图。
图4绘示为本发明的另一实施例的一种发光二极管的剖面示意图。
图5绘示为本发明的另一实施例的一种发光二极管的剖面示意图。
图6绘示为本发明的另一实施例的一种发光二极管的剖面示意图。
图7A绘示为本发明的另一实施例的一种发光二极管的剖面示意图。
图7B绘示为图7A的发光二极管的载板的俯视示意图。
图7C绘示为沿图7B的线I-I的剖面示意图。
图8绘示为本发明的另一实施例的一种载板的剖面示意图。
图9A绘示为本发明的一实施例的一种载板的俯视示意图。
图9B绘示为沿图9B的线A-A的剖面示意图。
图9C绘示为沿图9B的线B-B的剖面示意图。
图10绘示为本发明的另一实施例的一种发光二极管的剖面示意图。
图11绘示为本发明的另一实施例的一种发光二极管的剖面示意图。
图12A绘示为本发明的另一实施例的一种发光二极管的俯视示意图。
图12B绘示为图12A的发光二极管的局部立体示意图。
图13绘示为本发明的另一实施例的一种发光二极管的俯视示意图。
图14A绘示为本发明的另一实施例的一种载板的俯视示意图。
图14B绘示为图14A的载板的仰视示意图。
图15A绘示为本发明的另一实施例的一种载板的俯视示意图。
图15B绘示为本发明的另一实施例的一种载板的俯视示意图。
图16A至图16F绘示为本发明的一实施例的一种发光二极管的制作方法的剖面示意图。
图17A绘示为本发明的另一实施例的一种发光二极管的俯视示意图。
图17B绘示为沿图17A的线C-C的剖面示意图。
图中元件标号说明如下：
10：离型层
20：背胶
30：凹型模具
32：底部
34：第一周围表面
38：第二周围表面
100a、100b、100c、100d、100e、100f、100g、100k、100m、100n、100p、100u：发光二极管
110a、110b、110g、110h、110j、110q、110r、110s、110t、110u：载板
111a、111g：第一表面
112a、112b、112g、112h、112q、112s：导电区
112a1：导电层
112b1、112g1、112h1：第一导电层
112b2：导电通孔
112b3、112g2、112h2：第二导电层
113b1：第一连接层
113b2：第二连接层
113g：延伸图案
114a、114b、114g、114h、114j、114q：绝缘区
114a1、114b1、114g1、114h1、114j1：第一绝缘层
114a2、114b2、114g2、114h2、114j2：第二绝缘层
114a3、114b3、114j3：第三绝缘层
115a1：第一开口
115a2：第二开口
115a3：第三开口
120a、120c、120d：芯片电极
130a、130c、130d、130t、130u：芯片
132a、132t：顶面
134a、134t：底面
136a、136m：周围表面
140a、140b、140g、140k、140m、140t、140u：封装材料
150a：第一表面涂层
160a：第二表面涂层
170a、170b、170k、170m、170t、170u：保护层
172t：表面
180a、180u：静电保护元件
CP：第二接触区
E1、E1’：正极测试点
E2、E2’：负极测试点
SP：第一接触区
P1：第一间距
P2：第二间距
P3：第三间距
S1：上表面
S2：下表面
本发明的较佳实施方式
图1绘示为本发明的一实施例的一种发光二极管的剖面示意图。请参考图1，本实施例的发光二极管100a包括一载板110a、一芯片130a以及一封装材料140a。载板110a包括一导电区112a以及一绝缘区114a。导电区112a具有一上表面S1与一下表面S2。绝缘区114a覆盖至少一部分导电区112a，导电区112a的部分上表面S1未被绝缘区114a所覆盖，称为第二接触区CP(图1中仅示意地绘示两个)，导电区112a的部分下表面S2未被绝缘区114a所覆盖，称为第一接触区SP(图1中仅示意地绘示两个)，其中相邻的第一接触区SP之间具有一第一间距P1。芯片130a的芯片电极120a(图1中示意地绘示两个)分别与导电区112a的第二接触区CP直接或间接接触，其中相邻的第二接触区CP之间具有一第二间距P2，且第一间距P1大于第二间距P2。芯片130a通过芯片电极120a与载板110a电性连接。封装材料140a可直接或间接覆盖芯片130a的部分表面，于图1中，封装材料140a覆盖芯片130a相对远离载板110a的一顶面132a。
详细来说，本实施例的载板110a具体化为一单层金属基板，其中绝缘区114a包括一第一绝缘层114a1、一第二绝缘层114a2以及一第三绝缘层114a3，而导电区112a为至少一个导电层112a1。第二绝缘层114a2位于第一绝缘层114a1与第三绝缘层114a3之间，其中第一绝缘层114a1具有至少一个第一开口115a1，而第二绝缘层114a2具有至少一个第二开口115a2，且第三绝缘层114a3具有至少一个第三开口115a3。导电区112a位于第二开口115a2内且与第二绝缘层114a2实质上齐平设置，导电区112a具有上表面S1与下表面S2，而第一开口115a1暴露出导电区112a的部分下表面S2，且第三开口115a3暴露出导电区112a的部分上表面S1。导电区112a与第二绝缘层114a2实质上位于同一水平面。此处，相邻的第二接触区CP之间具有一第二间距P2，相邻的第一接触区SP之间具有一第一间距P1，其中第一间距P1大于第二间距。第一绝缘层114a1、第二绝缘层114a2以及第三绝缘层114a3的材质可相同或不同，而导电区112a材质可为铜箔、银、金、铝或其他具有导电性与导热性的金属材料。
如图1所示，本实施例的芯片电极120a位于芯片130a的相对远离顶面132a的一底面134a上，其中芯片130a借由芯片电极120a以倒装焊的方式与载板110a的导电区112a电性连接。换句话说，芯片130a的底面134a与导电区112a的上表面S1的距离小于芯片130a的顶面132a与导电区112a的上表面S1的距离。此处，芯片130a 例如是蓝光发光二极管芯片、红光发光二极管芯片、白光发光二极管芯片或紫外光发光二极管芯片。
为了避免载板110a的导电区112a氧化或受潮，本实施例的发光二极管100a例如可更包括至少一个第一表面涂层150a或至少一个第二表面涂层160a。第一表面涂层150a配置于导电区112a的第二接触区CP内，且直接接触导电区112a的上表面S1。第一表面涂层150a位于芯片电极120a与导电区112a之间。第二表面涂层160a配置于导电区112a的第一接触区SP内，且直接接触导电区112a的下表面S2。此处，第一表面涂层150a与第二表面涂层160a的材质是选自可使后续固晶打件较为方便的金属材料，例如是银、金、金锡、镍银(Ni/Ag)、镍钯金(Ni/Pt/Au)镀层或其他适当的金属或合金。
如图1所示，由于本实施例的第一表面涂层150a的厚度小于第三绝缘层114a3的厚度，即第二接触区CP是凹陷于第三绝缘层114a3中，因此当将芯片电极120a与导电区112a的第二接触区CP直接或间接接触时，可以避免两芯片电极120a之间因焊料溢流而电性连接，进而导致短路的问题。上述的焊料例如是金球、锡膏、共晶接合材料或异方性导电胶。同理，由于本实施例的第二表面涂层160a的厚度小于第一绝缘层114a1的厚度，即第一接触区SP是凹陷于第一绝缘层114a1中，因此当将发光二极管100a借由焊料而焊接至其他电路板(未绘示)时，可以避免焊料溢流至相邻的第一接触区SP而导致短路的问题。
此外，本实施例的发光二极管100a可更包括一保护层170a，其中保护层170a配置于载板110a上且直接或间接环绕芯片130a设置。此处，保护层170a直接接触芯片130a的周围表面136a，且保护层170a的至少一边与载板110a的至少一边实质上共平面。此处，保护层170a的材料例如是硅胶或以环氧树脂为基底并掺杂有二氧化钛、二氧化硅、氧化锆、氮化硼其中之一或上述其组合。保护层170a亦可具有反射的功能，其可反射来自于芯片130a的30％以上，较佳为50％以上，更加为70％以上的光线。
另外，请再参考图1，本实施例的封装材料140a为透光材料，可包括硅胶、石英、玻璃、透光陶瓷、热塑性树脂、热固性树脂，亦可包括荧光物质或光散射颗粒。封装材料140a直接或间接覆盖芯片130a的相对远离载板110a的至少部分顶面132a与保护层170a的至少部分表面。此处，荧光物质例如是铝酸盐的石榴石系列材料、 硅酸盐系列材料、氮化物系列材料、磷酸盐系列材料、硫化物系列材料或钪酸盐等，于此并不加以限制。更具体来说，荧光粉可选自由下述所构成的群组中的一或多者：β-SiAlON、Sr5(PO4)3Cl：Eu2+、(Sr，Ba)MgAl10O17：Eu2+、(Sr，Ba)3MgSi2O8：Eu2+、SrAl2O4：Eu2+、SrBaSiO4：Eu2+、CdS：In、CaS：Ce3+、Y3(Al，Gd)5O12：Ce3+、(Y，Gd)3Al5O12：Ce3+、Y3Al5O12：Ce3+、Y3(Al，Ga)5O12：Ce3+、Lu3Al5O12：Ce3+、(Y，Lu)3Al5O12：Ce3+、Lu3(Al，Ga)5O12：Ce3+、(Y，Lu)3(Al，Ga)5O12：Ce3+、Ca3Sc2Si3O12：Ce3+、SrSiON：Eu2+、ZnS：Al3+，Cu+、CaS：Sn2+、CaS：Sn2+，F、CaSO4：Ce3+，Mn2+、LiAlO2：Mn2+、BaMgAl10O17：Eu2+，Mn2+、ZnS：Cu+，Cl-、Ca3WO6：U、Ca3SiO4C12：Eu2+、SrxBayClzAl2O4-z/2：Ce3+，Mn2+(X：0.2、Y：0.7、Z：1.1)、Ba2MgSi2O7：Eu2+、Ba2SiO4：Eu2+、Ba2Li2Si2O7：Eu2+、ZnO：S、ZnO：Zn、Ca2Ba3(PO4)3Cl：Eu2+、BaAl2O4：Eu2+、SrGa2S4：Eu2+、ZnS：Eu2+、Ba5(PO4)3Cl：U、Sr3WO6：U、CaGa2S4：Eu2+、SrSO4：Eu2+，Mn2+、ZnS：P、ZnS：P3-，Cl-、ZnS：Mn2+、CaS：Yb2+，Cl、Gd3Ga4O12：Cr3+、CaGa2S4：Mn2+、Na(Mg，Mn)2LiSi4O10F2：Mn、ZnS：Sn2+、Y3Al5O12：Cr3+、SrB8O13：Sm2+、MgSr3Si2O8：Eu2+，Mn2+、_-SrO·3B2O3：Sm2+、ZnS-CdS、ZnSe：Cu+，Cl、ZnGa2S4：Mn2+、ZnO：Bi3+、BaS：Au，K、ZnS：Pb2+、ZnS：Sn2+，Li+、ZnS：Pb，Cu、CaTiO3：Pr3+、CaTiO3：Eu3+、Y2O3：Eu3+、(Y，Gd)2O3：Eu3+、CaS：Pb2+，Mn2+、YPO4：Eu3+、Ca2MgSi2O7：Eu2+，Mn2+、Y(P，V)O4：Eu3+、Y2O2S：Eu3+、SrAl4O7：Eu3+、CaYAlO4：Eu3+、LaO2S：Eu3+、LiW2O8：Eu3+，Sm3+、(Sr，Ca，Ba，Mg)10(PO4)6Cl2：Eu2+，Mn2+、Ba3MgSi2O8：Eu2+，Mn2+、ZnS：Mn2+，Te2+、Mg2TiO4：Mn4+、K2SiF6：Mn4+、SrS：Eu2+、Na1.23K0.42Eu0.12TiSi4O11、Na1.23K0.42Eu0.12TiSi5O13：Eu3+、CdS：In，Te、CaAlSiN3：Eu2+、CaSiN3：Eu2+、(Ca，Sr)2Si5N8：Eu2+、以及Eu2W2O7。上述的封装材料140a为透光材料，较佳系环氧基树脂组合物或硅氧烷基树脂组合物。于其他未绘示的实施例中，封装材料内亦可掺杂有扩散剂、增稠剂、抗氧化剂或其他可增加芯片130a出光效率或光均匀度的材料，此仍属于本发明所欲保护的范围。
简言之，本实施例的芯片130a通过芯片电极120a与载板110a电性连接，其中载板110a的第一接触区SP之间的第一间距P1大于第二接触区CP之间的第二间距P2，因此当发光二极管100a焊接至电路板时，能提供较宽阔的电性连接区域，避免打件时焊料溢流而造成的短路问题。此外，截面积较宽的载板110a的第一接触区SP 还可增加发光二极管100a与焊料的接触面积，进而提升载板110a的散热效果与焊接稳定度。再者，因为第一接触区SP可设置成为凹陷于绝缘区114a中，因此更能进一步避免焊料溢流而导致短路的问题。故，本实施例的发光二极管100a可应用于微型发光二极管(micro LED)或芯片级封装(chip scale package)中。
在此必须说明的是，下述实施例沿用前述实施例的元件标号与部分内容，其中采用相同的标号来表示相同或近似的元件，并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例，下述实施例不再重复赘述。
图2绘示为本发明的另一实施例的一种发光二极管的剖面示意图。请同时参考图1与图2，本实施例的发光二极管100b与图1的发光二极管100a相似，两者的差异在于：本实施例的封装材料140b直接或间接覆盖芯片130a且封装材料140b的部分区域位于芯片130a与保护层170b之间。
图3绘示为本发明的另一实施例的一种发光二极管的剖面示意图。请同时参考图2与图3，本实施例的发光二极管100c与图2的发光二极管100b相似，两者的差异在于：本实施例中，两芯片电极120c分别位于芯片130c的底面134a与顶面132a上。意即，芯片130c例如是一垂直式芯片，其中位于底面134a的芯片电极120c例如是直接配置于载板110a上。另一位于顶面132a的芯片电极120c则是通过一导线W1电性连结于载板110a。
图4绘示为本发明的另一实施例的一种发光二极管的剖面示意图。请同时参考图3与图4，本实施例的发光二极管100d与图3的发光二极管100c相似，两者的差异在于：本实施例芯片130d例如是一水平式芯片，其中芯片130d的两芯片电极120d皆位于芯片130d的顶面132a，且两芯片电极120d分别通过导线W2而电性连接于载板110a。
图5绘示为本发明的另一实施例的一种发光二极管的剖面示意图。请同时参考图1与图5，本实施例的发光二极管100e与图1的发光二极管100a相似，两者的差异在于：本实施例的载板110b的导电区112b包括一多个导电层结构，且相邻二导电层之间以至少一导电通孔112b2相连。详细来说，本实施例的载板110b的绝缘区114b包括一第一绝缘层114b1、一第二绝缘层114b2以及一第三绝缘层114b3，其中第二绝缘层114b2位于第一绝缘层114b1与第三绝缘层114b3之间。载板110b的导电区112b包括至少一个第一导电层112b1、至少一个导电通孔112b2以及至少一个第二导 电层112b3。第一导电层112b1与第二导电层112b3分别位于第二绝缘层114b2的相对两侧上。导电通孔112b2贯穿第二绝缘层114b2且电性连接至第一导电层112b1与第二导电层112b3。第一导电层112b1具有下表面S2，第二导电层112b3具有上表面S1。绝缘区114b覆盖至少一部分导电区112b，导电区112b的部分上表面S1未被绝缘区114b所覆盖，称为第二接触区CP，导电区112b部分下表面S2未被绝缘区114b所覆盖，称为第一接触区SP，其中相邻的第一接触区SP之间具有一第一间距P1。芯片130a的芯片电极120a分别与导电区112b的第二接触区CP直接或间接接触，其中相邻的第二接触区CP之间具有一第二间距P2，且第一间距P1大于第二间距P2。芯片130a通过芯片电极120a与载板110b电性连接。
由于本实施例载板110b的第一接触区SP之间的第一间距P1大于第二接触区CP之间的第二间距P2，因此当发光二极管100e焊接至其他电路板时，能避免打件时焊料溢流而造成的短路问题。此外，截面积较宽的载板110b的第一接触区SP还可增加发光二极管100e与电路板的接触面积，进而提升载板110b的散热效果与焊接稳定度。再者，因为第一接触区SP可设置为凹陷于绝缘区114b中，因此更能进一步避免焊料溢流而导致短路的问题。故，本实施例的发光二极管100e可应用于微型发光二极管(micro LED)或芯片级封装(chip scale package)中。
图6绘示为本发明的另一实施例的一种发光二极管的剖面示意图。请同时参考图5与图6，本实施例的发光二极管100f与图5的发光二极管100e相似，两者的差异在于：本实施例的封装材料140b直接或间接覆盖芯片130a且一部分位于芯片130a与保护层170b之间。也就是说，本实施例的封装材料140b会填充于芯片130a与保护层170b之间的间隙内，而保护层170b直接接触封装材料140b。
图7A绘示为本发明的另一实施例的一种发光二极管的剖面示意图。图7B绘示为图7A的发光二极管的载板的俯视示意图。图7C绘示为沿图7B的线I-I的剖面示意图。须说明的是，图7A中的载板是沿着图7B的线II-II的剖面。请同时参考图1与图7A，本实施例的发光二极管100g与图1的发光二极管100a相似，两者的差异在于：本实施例的载板110g的绝缘区114g包括一第一绝缘层114g1以及一第二绝缘层114g2。导电区112g包括至少一个第一导电层112g1、至少一个第二导电层112g2与延伸图案113g。第一绝缘层114g1具有至少一个第一开口115g1。第一导电层112g1具有下表面S2且位于第一开口内115g1，形成第一接触区SP。第二绝缘层114g2具 有至少一个第二开口115g2。第二导电层112g2具有上表面S1，配置于第一导电层112g1上且位于第二开口115g2内，形成第二接触区CP。
请参考图7B与图7C。图7B中绘示多个元件区，图中的虚线方框仅框示出一个元件区范围。延伸图案113g连接不同元件区的第二导电层112g2，但延伸图案113g并不会连接同一元件区中的第二导电层112g2。但于其他实施例中，延伸图案113g亦可连接不同元件区的第一导电层112g1，或贯穿第一绝缘层114g1与第二绝缘层114g2，此仍属于本发明所欲保护的范围。上述导电区112g与延伸图案113g的结构形状可通过冲压、蚀刻等方式来形成，而绝缘区114g的材料则可使用半导体常用的防焊漆，其具有合宜的耐热性及可加工性。另外，亦可以在绝缘区114g元中添加反射材料，例如二氧化钛、二氧化硅、氧化锆、氮化硼或前述的任意组合，以提高发光二极管100g的出光效果。当然，于其他未绘示的实施例中，亦可增设表面涂层(图未显示)于导电区112g的上表面S1或下表面S2上，以避免导电区112g氧化或受潮。
请再参考图7A，本实施例的第二导电层112g2突出于第二绝缘层114g2，而芯片电极120a直接或间接接触第二导电层112g2，或例如直接接触配置于第二导电层112g2上的表面涂层(图未显示)。此处，其中第一接触区SP之间的间距P1大于第二接触区CP之间的间距P3，且第一接触区SP之间的间距P1亦大于芯片电极之间的间距P2。第二导电层112g2于第一导电层112g1上的正投影至少部分重叠于第一导电层112g1，如图7A所示，第一导电层112g1与第二导电层112g2堆叠成阶梯状。封装材料140g例如直接或间接覆盖芯片130a。此处，封装材料140g的至少一边与载板110g的至少一边为共平面。
图8绘示为本发明的另一实施例的一种载板的剖面示意图。请同时参考图7A与图8，本实施例的载板110h与图7A的载板110g相似，两者的差异在于：本实施例的导电区112h的第二导电层112h2于第一导电层112h1上的正投影完全重叠于第一导电层112h1。第二绝缘层114h2的第二开口115h2的宽度大于第一绝缘层114h1的第一开口115h1的宽度，以使第二导电层112h2的宽度大于第一导电层112h1的宽度，借此形成上宽下窄的导电区112h，可使绝缘区114h在覆盖导电区112h时具有良好的耦合力，减少导电区112h与绝缘区114h脱落的情况发生。
图9A绘示为本发明的一实施例的一种载板的俯视示意图。图9B绘示为沿图9A的线A-A的剖面示意图。图9C绘示为沿图9A的线B-B的剖面示意图。请同时参考 图8、图9A、图9B以及图9C，本实施例的载板110j与图8的载板110h相似，两者的差异在于：本实施例的载板110j的绝缘区114j除了包括第一绝缘层114j1与第二绝缘层114j2之外，还更包括一第三绝缘层114j3，配置于部分第二导电层112h2上与第二绝缘层114j2上。第二导电层112h2的部分上表面S1未被第三绝缘层114j3覆盖，第二接触区CP之间的第二绝缘层114j2高度不会高于第二接触区CP的高度，可以避免后续芯片接合时被绝缘区114j所阻碍。
图10绘示为本发明的另一实施例的一种发光二极管的剖面示意图。请同时参考图7A与图10，本实施例的发光二极管100k与图7A的发光二极管100g相似，两者的差异在于：本实施例的发光二极管100k更包括一保护层170k，配置于载板110g上且直接或间接环绕芯片130a设置。封装材料140k直接或间接覆盖芯片130a。此处，保护层170k的至少一边与载板110g的至少一边共平面。
图11绘示为本发明的另一实施例的一种发光二极管的剖面示意图。请同时参考图7A与图11，本实施例的发光二极管100m与图7A的发光二极管100g相似，两者的差异在于：本实施例的发光二极管100m更包括一保护层170m，配置于载板110g上且直接或间接环绕芯片130a设置。保护层170m至少覆盖芯片130m的一周围表面136m、第二导电层112g2的部分上表面S1与载板110g的一第一表面111g。芯片电极120a之间与第二导电层112g2之间存在有一间隙S，而封装材料140m直接或间接覆盖芯片130a的顶面132a与保护层170m，且封装材料140m的至少一边与保护层170m的至少一边或载板110g的至少一边共平面。
图12A绘示为本发明的另一实施例的一种发光二极管的俯视示意图。图12B绘示为图12A的发光二极管的局部立体示意图。请同时参考图5、图12A与图12B。本实施例的发光二极管100n与图5的发光二极管100e相似，两者的差异在于：本实施例的发光二极管100n为未单体化前的结构，其包括多个芯片130a分别配置于载板110b的元件区上。上述载板110b包括多个第一连接层113b1与第二连接层113b2，其中第一连接层113b1用以连接不同元件区的例如正电性的第二导电层112b3，第二连接层113b2用以连接不同元件区的例如负电性的第一导电层112b1。详细来说，位于同一行(例如第一行)的各个元件区的第二导电层112b3借由第一连接层113b1而相互连接，且最终电性连接至同一行(例如第一行)的正极测试点E1。位于同一列(例如第一列)的各个元件区的第一导电层112b1借由第二连接层113b2而相互连接，且最 终电性连接至同一列(例如第一列)的负极测试点E2。每一芯片130a下方借由第一连接层113b1相互连接的第二导电层112b3，位于借由与第二连接层113b2相互连接的第一导电层112b1的斜对角方向。上述正极测试点E1的排列延伸方向是垂直于负极测试点E2的排列延伸方向。
图12B绘示为图12A的发光二极管的局部立体示意图。为了更方便解说，请参考图12B。上述具有双层金属基板的载板因具有上下两层导电层，因此用来进行正极互连的第一连接层113b1以及用来进行负极互连的第二连接层113b2可分别配置于第二绝缘层114b2的相对两侧上，且第一连接层113b1位于第二连接层113b2的斜上方，如此可以将连接不同元件区的正极的第二导电层112b3与连接负极的第一导电层112b1相互错开而避免短路的问题。如此一来，双层金属基板的电路配置更能便于将同一列或同一行的相邻元件区的导电层层进行电性连接。
借由上述具有双层金属基板的载板的设计，可于制程中进行荧光粉涂布作业的当下，同时电性测量各个元件区的芯片130a所发出的光线通过荧光粉后的色泽与亮度，则可得知荧光粉的涂布情况是否满足所需，以便于判断是否停止或继续上述涂布作业，前述荧光粉涂布可为喷涂、点胶或覆盖荧光贴片或其他荧光粉封装方式。举例来说，当欲得知配置于元件区的芯片130a上的荧光粉涂布状况，则可分别将正极探针与负极探针点压于其中一正极测试点E1与其中一负极测试点E2，即可得知相对位置的芯片130a的荧光粉涂布状况。当完成荧光粉的涂布制程或其他的荧光粉封装制程之后，即可进行单体化的切割，以获得多个颗独立的发光二极管，如图5的发光二极管100e。值得一提的是，切割完后的发光二极管，在发光二极管100e的至少一侧会留下电性残留点，例如本实施例中，在发光二极管100n的一侧会留下用来连接相邻元件区的第一连接层113b1与第二连接层113b2(如图12A所示)的二个电性残留点，而在发光二极管100n的相对一侧会留下用来连接相邻元件区的第二连接层113b2的一个电性残留点。简言之，切割完后的每个发光二极管100n至少有多个电性残留点，这些电性残留点可以位于同一水平面或不同水平面，于此不加以限制电性残留点的位置。
此外，本实施例将电性测量点(即正极测试点E1与负极测试点E2)配置于具有双层金属基板的载板的正面的理由在于，无论是具有双层金属基板或单层金属基板的载板的厚度皆是非常的薄，因此在制程过程中，需要在具有单/双层金属基板的载板的 背面额外粘附一层相对较硬的承载基板，以便于后续制程的进行而不至于在制程过程中损坏基板造成良率问题。另外，由于目前的点测是从集成电路板的背面进行，在具有单/双层金属基板的载板的背面皆粘附有承载基板(未绘示)的情况下，则从具有单/双层金属基板的载板的背面进行点测已然不可行。因此若要针对配置有芯片的载板进行点测，则需要将电性测量点延伸至载板的正面，使其可以由载板的正面进行点测。由于本实施例具有双层金属基板的载板的电路配置能够实现在载板的正面建立前测点，因此能符合后续程序的需进行点测的需求。额外一提的是，在完成上述封装制程之后，即可以将承载基板撕除，并接着进行后续单体化切割步骤。
图13绘示为本发明的另一实施例的一种发光二极管的俯视示意图。请同时参考图12A与图13，本实施例的发光二极管100p与图12A的发光二极管100n相似，两者的差异在于：正极测试点E1’的排列延伸方向例如是平行于负极测试点E2’的排列方向。换言之，可以依照不同的电路配置需求而选择不同的正极测试点E1、E1’与负极测试点E2、E2’的排列方向。
图14A绘示为本发明的另一实施例的一种载板的俯视示意图。图14B绘示为图14A的载板的仰视示意图。请同时参考图14A与图14B，本实施例的载板110q可为单层金属基板或双层金属基板，于此并不加以限制。载板110q的导电区112q的第二接触区CP之间的第三间距P3例如是200微米，借由绝缘区114q与导电区112q的搭配，可使第一接触区SP之间的第一间距P1调整至例如是250微米，但间距的调整幅度并不以此为限。
图15A、图15B绘示为本发明的另一实施例的一种载板的俯视示意图。请同时参考图14A与图15A、图15B，本实施例的载板110r与图14A的载板110q相似，两者的差异在于：本实施例的载板110r上更配置有至少一静电保护元件180a，其中静电保护元件180a例如是齐纳二极管(Zener)或瞬态抑制二极管(TSV)。本发明实施例的芯片、载板与静电保护元件可呈现不同长度的四边形组合，本发明不以此为限。
值得一提的是，图14A、图14B以及图15A的部分导电区112q的形状例如可具有斜边形状，然而此具有斜边形状仅是便于辨识正负极的用，亦可以将此形状设计为方形(如图15B的导电区112s)或其他形状，本发明并不以此为限。
借由本实施例的载板110a、110b、110g、110h、110j、110q、110r、110s的设计(例如是单层金属基板或双层金属基板的设计)，可便于将原本无基板的芯片尺寸 封装体的较短的芯片电极间距，借由具有单/双层金属基板的载板，而使第一接触区的间距进行扩开的效果，以便后续将发光二极管100a、100b、100c、100d、100e、100f、100g、100k、100m、100n、100p焊接于后续其他电路板上时，能够避免溢锡所导致的短路问题。此外，上述载板110a、110b、110g、110h、110j、110q、110r、110s的设计亦可维持或进而提升后续焊接时与焊料的接触面积、散热效果与可靠度。此外，本实施例的载板110r、110s上亦可配置静电保护元件180a，可保护芯片130a、130c、130d免于静电伤害。另外，本实施例的发光二极管100n、100p于载板110b的正面还可以具有正极测试点E1、E1’与负极测试点E2、E2’，以方便制作过程中电性测量之用。
图16A至图16F绘示为本发明的一实施例的一种发光二极管的制作方法的剖面示意图。本实施例的发光二极管的制作方法，其包括以下制作步骤。首先，请参考图16A，提供一载板110t。此处，载板110t可例如是上述的载板110a、110b、110g、110h、110j、110q、110r、110s，即可为单层金属基板、双层金属基板，或亦可以是卸除式承载基板或无需卸除的基板。以下以无需卸除的基板作为解说范例，但本发明并不以此为限。
接着，请再参考图16A，配置至少一芯片130t于载板110t上，其中芯片130t具有彼此相对的一顶面132t与一底面134t，且芯片130t的底面134t配置于载板110t上，而顶面132t远离载板110t。如图16A所示，绘示多个芯片130t配置于载板110t上，本发明的实施例也可以使用单一芯片。此处，芯片130t可以是覆晶式发光二极管芯片、垂直式发光二极管芯片或水平式发光二极管芯片，于此并不加以限制。
接着，请参考图16B，贴附一离型层10于芯片130t的顶面132t上，其中离型层10于载板110t上的正投影面积大于或等于芯片130t于载板110t上的正投影面积。此处。离型层10例如为一热化离型胶层。当然，于其他实施例中，离型层10亦可为其他具有撕除时不会破坏相邻结构的特性。
接着，请参考图16C，将承载芯片130t与离型层10的载板110t倒放于一凹型模具30内，使离型层10位于凹型模具30底部32，且芯片130t与凹型模具30内面(如第一周围表面34与第二周围表面38)之间具有空隙。
接着，请再参考图16C，贴附一背胶20于载板110t相对远离芯片130t的表面上。紧接着，图16D，形成一保护层170t于芯片130t侧面。之后，图16E，移除凹 型模具30、背胶20与离型层10，以暴露出芯片130t的顶面132t与保护层170t的一表面172t，以暴露出芯片130t的顶面132t与保护层170t的表面172t，其中芯片130t的顶面132t与保护层170t的表面172t实质上共平面。此处，移除离型层10的步骤包括加热离型层10，其中加热离型层10的温度介于150度至270度，而加热离型层10的时间介于10秒至3分钟。由于本实施例的离型层10具体化为热化离型胶层，当欲移除热化离型胶层时，只需将载板110t加热至100度以上，例如170度上下约3分钟左右，或是例如可以用更高的温度，且只需数秒即可移除热化离型胶层。由于热化离型胶层在高温下失去粘性之后，即可轻松卸除热化离型胶层，而不伤及芯片130t与已经形成的保护层170t。
此外，于其他实施例中，于移除热化离型胶层之后，亦可使用醋酸乙酯清除热化离型胶层的溢胶残留物及/或使用酒精清除其他残留物。
最后，图16F，直接或间接形成一封装材料140t于芯片130t的顶面132t与保护层170t的表面172t上。此处，封装材料140t例如为该封装材料为透光材料，例如可包括硅胶、石英、玻璃、透光陶瓷、热塑性树脂、热固性树脂。封装材料亦可包括荧光物质或光散射颗粒。但并不以此为限。上述封装材料例如可替换为荧光贴片，本发明不以此为限。至此，已完成尚未单体化的发光二极管的制作。
简言之，通过上述的发光二极管的制作方法，可以制作出保护层170t的高度与芯片130t的高度实质上相同的发光二极管，借此可提升发光二极管亮度(流明数)。
値得一提的是，虽然上述是以无需卸除的基板来作为解说范例，但亦可使用可卸除式基板，亦即将LED芯片配置于可卸除式基板上，并将配置有LED芯片的可卸除式基板倒置于模具中，并利用上述方法形成围绕芯片的保护层之后，再卸除离型层，并进行后续制程或应用。上述后续制程例如是，于卸除离型层后，先形成封装材料于芯片或芯片与保护层的远离可卸除式基板的一表面上后，再移除可卸除式基板，并进行单体化制程(切割制程)。之后可将单体化后的封装芯片直接作为无基板的芯片尺寸封装体来使用，或是将其配置于上述单层金属基板或双层金属基板上(例如上述载板110a、110b、110g、110h、110j、110q、110r、110s)。于其他实施例中，上述后续制程例如是，于卸除离型层后，进行切割等单体化制程，并将单体化的具有芯片与围绕芯片的保护层的结构配置于上述单层金属基板或双层金属基板上(例如上述载板110a、110b、110g、110h、110j、110q、110r、110s)，之后再进行封装材料的制程。于另一 实施例中，例如可将LED芯片直接配置于如前述的单层金属基板或双层金属基板上(例如上述载板110a、110b、110g、110h、110j、110q、110r、110s)，之后再利用上述制程方法以形成围绕芯片的保护层。然而本发明不以上述范例为限。
图17A绘示为本发明的另一实施例的一种发光二极管的俯视示意图。图17B绘示为沿图17A的线C-C的剖面示意图。请同时参考图17A与图17B，本实施例的发光二极管100u更包括至少一静电保护元件180u，配置于载板110u上，其中保护层170u覆盖静电保护元件180u，而封装材料140u直接或间接配置于保护层170u与芯片130u上。上述静电保护元件180u例如是齐纳二极管(Zener)或瞬态抑制二极管(TSV)。
此外，当静电保护元件180u与芯片130u一起配置于同一载板110u上时，由于已知静电保护元件通常是黑色的，因此会吸收邻近芯片130u的光线，导致芯片130u的发光效率降低。然而，本实施例的静电保护元件180u的外围具有保护层170u，其可以反射来自于邻近芯片130u所发出的光线，因此可以提高发光二极管100u整体的发光亮度。额外一提的是，可以利用例如是助焊剂将静电保护元件180u配置于载板110u上，以避免溢锡而造成短路问题。
综上所述，在本发明的发光二极管中，芯片通过导电区与载板电性连接，其中载板的第一接触区之间的第一间距大于第二接触区之间的第二间距，因此当发光二极管焊接至其他电路板时，载板的第一接触区可增发光二极管与焊料的接触面积，且可以避免焊料溢流导致短路的问题。此外，上述的设计亦可以维持载板的散热效果与可靠度。再者，本发明的载板上亦可配置静电保护元件，可保护芯片免于静电伤害。此外，本发明的载板上亦可配置保护层，借此可保护发光二极管并提升发光二极管亮度(流明数)。另外，本实施例的发光二极管于载板的正面还可以具有正极测试点与负极测试点，以方便制作过程中电性测量之用。

Claims (18)

  1. 一发光二极管，包括：
    一芯片；
    一载板，包括：
    一导电区，具有一上表面与一下表面；
    一绝缘区，覆盖至少一部分该导电区；
    其中该导电区包括至少一第一接触区与至少一第二接触区，该第一接触区位于该导电区的该下表面未被该绝缘区覆盖的区域，相邻的该第一接触区之间具有一第一间距，该第二接触区位于该导电区的该上表面未被该绝缘区覆盖的区域，相邻的该第二接触区之间具有一第二间距，且该第一间距大于该第二间距；以及
    一封装材料，直接或间接覆盖该芯片的部分表面。
  2. 如权利要求1所述的发光二极管，其特征在于，两相邻的该第二接触区之间还有一第三间距，而该第一间距大于该第三间距，且该第三间距小于或等于该第二间距。
  3. 如权利要求1所述的发光二极管，其特征在于，该载板的该绝缘区包括一第一绝缘层、一第二绝缘层以及一第三绝缘层，该第二绝缘层位于该第一绝缘层与该第三绝缘层之间，该第一绝缘层具有至少一个第一开口，该第二绝缘层具有至少一个第二开口，该第三绝缘层具有至少一个第三开口，该载板的该导电区的部分该下表面与部分该上表面分别露出于该第一开口与该第三开口。
  4. 如权利要求1所述的发光二极管，其特征在于，该导电区包括一多个导电层结构，相邻二导电层之间以至少一导电通孔相连。
  5. 如权利要求1所述的发光二极管，包括：
    一保护层，配置于该载板上且直接或间接环绕该芯片，该保护层的至少一边与该载板的至少一边实质上共平面。
  6. 如权利要求5所述的发光二极管，其特征在于，该封装材料直接或间接覆盖该芯片的相对远离载板的至少部分表面与该保护层的至少部分表面，且该封装材料的至少一边与该保护层的至少一边实质上共平面。
  7. 如权利要求5所述的发光二极管，其特征在于，该封装材料的部分区域位于该芯片与该保护层之间。
  8. 如权利要求1所述的发光二极管，其特征在于，该芯片具有一电极的一表面与该载板的该导电区的该上表面的距离小于该芯片不具有该电极的一另一表面与该载板的该导电区的该上表面的距离。
  9. 如权利要求1所述的发光二极管，其特征在于，该芯片以倒装焊的方式配置于该载板的该第二接触区上。
  10. 如权利要求1所述的发光二极管，更包括：
    一静电保护元件，配置于该载板上。
  11. 如权利要求1所述的发光二极管，其特征在于，该封装材料为透光材料。
  12. 如权利要求11所述的发光二极管，其特征在于，该封装材料包括硅胶、石英、玻璃、透光陶瓷、热塑性树脂、热固性树脂。
  13. 如权利要求11所述的发光二极管，其特征在于，该封装材料包括荧光物质或光散射颗粒。
  14. 如权利要求1所述的发光二极管，更包括：
    至少一表面涂层，配置于该载板的该导电区的该上表面与该下表面至少其中的一个上。
  15. 如权利要求1所述的发光二极管，其特征在于，该第二接触区与该第一接触区分别凹陷于该绝缘区中。
  16. 一种发光二极管的制作方法，包括：
    提供一载板；
    配置至少一芯片于该载板上，该芯片具有彼此相对的一顶面与一底面，其中该顶面远离该载板；
    贴附一离型层于该芯片的该顶面上，其中该离型层于该载板上的正投影面积大于或等于该芯片于该载板上的正投影面积；
    将承载该芯片与该离型层的该载板倒置于一凹型模具中，使该离型层位于该凹型模具的一底部，且该芯片的一侧面与该凹型模具的一内面之间具有一空隙；
    于该空隙中形成一保护层于该芯片的该侧面；
    移除该凹型模具与该离型层，以暴露出该芯片的该顶面与该保护层的一表面，其中该芯片的该顶面与该保护层的该表面实质上共平面；以及
    直接或间接形成一封装材料于该芯片的该顶面与该保护层的该表面。
  17. 如权利要求16所述的发光二极管的制作方法，其特征在于，该离型层为一热化离型胶层。
  18. 如权利要求16所述的发光二极管的制作方法，其特征在于，该载板包括：
    一导电区，具有一上表面与一下表面；以及
    一绝缘区，覆盖至少一部分该导电区；
    至少一第一接触区，位于该导电区的该下表面未被该绝缘区覆盖的区域，
    至少一第二接触区，位于该导电区的该上表面未被该绝缘区覆盖的区域，该第二接触区用以电性连接该芯片；
    其中两相邻的该第一接触区之间具有第一间距，而两相邻的该第二接触区之间具有第二间距，且该第一间距大于该第二间距。
PCT/CN2017/089811 2016-06-23 2017-06-23 发光二极管及其制作方法 WO2017220026A1 (zh)

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