WO2017219968A1 - 横向绝缘栅双极型晶体管及其制造方法 - Google Patents

横向绝缘栅双极型晶体管及其制造方法 Download PDF

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WO2017219968A1
WO2017219968A1 PCT/CN2017/089279 CN2017089279W WO2017219968A1 WO 2017219968 A1 WO2017219968 A1 WO 2017219968A1 CN 2017089279 W CN2017089279 W CN 2017089279W WO 2017219968 A1 WO2017219968 A1 WO 2017219968A1
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trench
doping concentration
junction
bipolar transistor
well
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PCT/CN2017/089279
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English (en)
French (fr)
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祁树坤
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无锡华润上华半导体有限公司
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Priority to JP2018566861A priority Critical patent/JP6806805B2/ja
Priority to EP17814706.2A priority patent/EP3474330B1/en
Priority to US16/311,276 priority patent/US10770572B2/en
Priority to KR1020187036722A priority patent/KR102158345B1/ko
Publication of WO2017219968A1 publication Critical patent/WO2017219968A1/zh

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Definitions

  • the present invention relates to a semiconductor process, and more particularly to a lateral insulated gate bipolar transistor, and to a method of fabricating a lateral insulated gate bipolar transistor.
  • LIGBTs Lateral Insulated-Gate Bipolar Transistors
  • LDMOS lateral double-diffused MOSFETs
  • the turn-off time is long, so there is a problem that the power consumption is too large. Since the on-resistance and the off-time are inversely related to the hole concentration, how to balance the on-resistance and the off-time is the direction for continuous improvement of the LIGBT device.
  • a lateral insulated gate bipolar transistor comprising a substrate, an anode end and a cathode end on the substrate, and a drift region and a gate between the anode end and the cathode end, the anode end including N on the substrate a type of buffer, a P-well in the N-type buffer, an N+ region in the P-well, a trench above the N+ region surrounded by the P-well portion, polysilicon in the trench, a P+ junction on both sides of the trench, and an N+ junction on both sides of the P+ junction.
  • a method for fabricating a lateral insulated gate bipolar transistor includes: implanting N-type ions into a silicon wafer, and pushing a well to form an N-type buffer; depositing a hard mask layer on the surface of the silicon wafer, and using light Etching and etch etching, etching the hard mask layer out of the trench window; etching silicon under the trench window to form a trench; performing pad oxidation, in the trench The inner surface forms a pad oxide layer; the pad oxide layer has a thickness on the sidewall of the trench that is greater than the thickness at the bottom of the trench; P-type ions are implanted into the trench window, and ions pass through the oxide layer a P-well is formed in the N-type buffer around the trench; an oxide layer is deposited in the trench, and an oxide film is formed on the sidewall of the trench after etching, and a sidewall structure is formed on both sides of the trench; Injecting N-type ions into the trench, forming an N+ region by self-aligned implantation
  • the laterally insulated gate bipolar transistor injects a large number of holes on the one hand, forming a significant conductance modulation effect to reduce the on-state resistance; on the other hand, when the device is turned off, the N+ region and the N+ junction can be It quickly absorbs minority holes and greatly reduces the turn-off loss.
  • FIG. 1 is a schematic cross-sectional view of a laterally insulated gate bipolar transistor in an embodiment
  • FIG. 2 is a flow chart showing a method of fabricating a laterally insulated gate bipolar transistor in an embodiment.
  • semiconductor used herein is a technical term commonly used by those skilled in the art.
  • the P+ type is simply represented as a heavily doped P-type, P-type representative.
  • P type with doping concentration P-type represents P type with light doping concentration
  • N+ type represents N type with heavy doping concentration
  • N type represents N type with medium doping concentration
  • N type represents light doping concentration N type.
  • the lateral insulated gate bipolar transistor technology has a problem that the turn-off period is long, which leads to a low turn-on voltage drop due to the conductance modulation effect, and a problem that the turn-off time is long due to residual minority in the drift region. Therefore, how to balance the on-state voltage drop and turn-off time becomes the direction of continuous improvement of the lateral insulated gate bipolar transistor.
  • the anode terminal includes an N-type buffer 42 on substrate 10, a P-well 44 in N-type buffer 42, an N+ region 46 in P-well 44, a trench above portion of N+ region 46 surrounded by P-well 44, trench The polysilicon 74 in the trench, the P+ junction 53 on both sides of the trench, and the N+ junction 55 on both sides of the P+ junction 53.
  • the cathode end includes a P-region 52 on the substrate 10, a P-type body region 54 and an emitter N+ region 56 in the P-region 52, and a cathode as an electrode of the emitter.
  • Metal 64 is a schematic structural view of a laterally insulated gate bipolar transistor in an embodiment, including a substrate 10, an anode terminal and a cathode terminal on the substrate 10, and a drift region 30 and a gate between the anode terminal and the cathode terminal.
  • the anode terminal includes an N-type buffer 42 on substrate 10, a P-well 44 in N-type buffer 42,
  • the collector including the P+ junction 53 and the N+ junction 55
  • the N+ region 46, the P well 44, and the N-type buffer 42 form a low resistance path for hole injection, which starts faster.
  • the residual minority holes in the drift region 30 are extracted, which ensures a fast switching speed and achieves the purpose of fast shutdown.
  • the groove is a structure in which the bottom is narrow and the top is wide and gradually widens from the bottom to the upper to form a slope.
  • the N-type buffer 42 has a doping concentration that is less than the doping concentration of the P-well 44, and the P-well 44 has a doping concentration that is less than the doping concentration of the P+ junction 53 and the N+ junction 55.
  • the doping concentration of the N-type buffer 42 is 2E 15 to 5E 15 cm -3
  • the doping concentration of the P well 44 is 4E 17 to 8E 17 cm -3 , P + junction 53 and N + junction 55 .
  • the doping concentration is 5E 20 to 10E 20 cm -3 .
  • the anode end further includes an oxide layer on the inner surface of the trench.
  • the oxide layer includes an oxide film 72 on the sidewall of the trench and a sidewall structure 72a on both sides of the bottom of the trench. Oxide vacancies are present in the middle of the bottom of the trench such that the polysilicon 74 within the trench is in direct contact with the underlying N+ region 46.
  • the polysilicon 74 on both sides of the bottom of the trench is N+ heavily doped polysilicon, and the doping concentration is on the order of E 21 to E 22 cm -3 .
  • Silicon-on-insulator (SOI) technology is gaining increasing importance in HVIC and SPIC applications, while IGBT devices are low on-resistance due to high input impedance and conductance modulation effects in power device applications. Increasingly important. Compared with bulk silicon isolation devices, SOI's LIGBT devices have low leakage, low on-resistance, high input impedance, high package density, fast switching, significant noise reduction and feasible under high temperature operation due to slot isolation. Sexuality, a wider range of applications in automotive electronics, home electronics and communications and industrial applications. It is especially important to require high efficiency hole injection and significant conductance modulation to reduce the on-state resistance, but also to increase the device accordingly.
  • the LIGBT shown in FIG. 1 is a silicon-on-insulator type lateral insulated gate bipolar transistor (SOI-LIGBT) including a buried oxide layer 20 between a substrate 10 and a drift region 30, wherein the substrate 10 is a P-type substrate.
  • the drift region 30 is an N-type drift region.
  • FIG. 2 is a flow chart showing a method of fabricating a laterally insulated gate bipolar transistor in an embodiment, including:
  • a hard mask layer is deposited on the surface of the silicon wafer, and a photoresist is coated on the surface of the hard mask layer for photolithography, and the hard mask exposed under the photoresist is etched away to form a trench window.
  • the silicon below is exposed.
  • the hard mask layer is a silicon nitride layer. In other embodiments, other hard masks known in the art may also be employed.
  • a pad oxide layer is also formed prior to depositing the hard mask layer.
  • the structure is formed by etching to form a top width and a narrow bottom portion which are gradually narrowed from the top to the bottom to form a slope.
  • the oxidation rate of the liner oxide is different, and the thickness of the oxide layer of the sidewall is greater than the thickness of the oxide layer at the bottom.
  • P-type ions are implanted into the trench window, and ions pass through the oxide layer to form a P-well in the N-type buffer region around the trench. Since the thickness of the oxide layer on the sidewall of the trench is greater than the thickness of the oxide layer at the bottom, the concentration distribution of the P-type ions in the P well is affected accordingly.
  • TEOS tetraethyl orthosilicate
  • Other processes known in the art may also be used to form the oxide layer in other embodiments.
  • an anisotropic etch is used to form an oxide film on the sidewall of the trench, and on both sides of the bottom of the trench The sidewall structure is formed, and a void of the oxide layer is formed in the middle of the bottom of the trench as a window of N+ implantation in step S270.
  • N-type ions are implanted into the trench, and an N+ region is formed by self-aligned (Self-aligned) implantation under the barrier of the oxide film and the sidewall spacer.
  • the N+ region formed by the self-aligned implant forms a vertical vertical NPN with the P-well and the N-type buffer as a key minority carrier lifetime control means.
  • the step of depositing polysilicon further includes a step of rinsing the silicon dioxide in the vicinity of the N+ region to remove the silicon dioxide impurities.
  • the polysilicon 74 is heavily doped with N+ and has a doping concentration of the order of E 21 to E 22 cm -3 .
  • Thermal annealing to activate dopant ions in the P-well, N+ regions, and the like. After the annealing is completed, the manufacturing process of other regions of the device, such as a CMOS process, is performed.
  • the annealing is performed accordingly, and then the subsequent process of the device is performed.
  • the injection in step S250 is performed multiple times to obtain a more slowly doped concentration gradient, optimize the impurity profile of the P-well, and even achieve a substantially constant doping concentration in a certain region. It helps to increase the magnification of the N+/P-/N-triode and speed up the extraction of holes.
  • FIG. 1 A schematic structural view of a lateral insulated gate bipolar transistor fabricated by the above method is shown in FIG.
  • the laterally insulated gate bipolar transistor injects a large number of holes during forward conduction, forming a significant conductance modulation effect to reduce the on-state resistance; on the other hand, the N+ region and the N+ junction can be quickly turned off when the device is turned off.
  • the ground absorption of minority pockets greatly reduces the turn-off loss. That is, by optimizing the collector of the LIGBT, the deep collector P-well and the P+ junction are introduced through the trench structure, and the N+ polysilicon and the N+ region are formed, and a widely distributed electron/hole current channel is formed during the forward conduction to improve the current capability.
  • the optimized collector helps to collect fewer sub-holes faster and reduces turn-off time.
  • the doping concentration of the N-type buffer 42 is 2E 15 to 5E 15 cm -3
  • the doping concentration of the P well 44 is 4E 17 to 8E 17 cm -3 , P + junction 53 and N + junction 55 .
  • the doping concentration is 5E 20 to 10E 20 cm -3 .

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Abstract

一种横向绝缘栅双极型晶体管及其制造方法，所述横向绝缘栅双极型晶体管包括衬底(10)、衬底(10)上的阳极端和阴极端，以及位于阳极端与阴极端之间的漂移区(30)和栅极(62)，所述阳极端包括衬底(10)上的N型缓冲区(42)，N型缓冲区(42)内的P阱(44)，P阱(44)内的N+区(46)，位于N+区(46)上方的被所述P阱(44)部分包围的沟槽，沟槽内的多晶硅(74)，沟槽两侧的P+结(53)，以及P+结(53)两侧的N+结(55)。

Description

横向绝缘栅双极型晶体管及其制造方法 技术领域
本发明涉及半导体工艺，特别是涉及一种横向绝缘栅双极型晶体管，还涉及一种横向绝缘栅双极型晶体管的制造方法。
背景技术
横向绝缘栅双极型晶体管(Lateral Insulated-Gate Bipolar Transistor，LIGBT)常用于高压功率驱动集成电路的输出级，与横向双扩散金属氧化物半导体场效应管(Lateral Double-diffused MOSFET，LDMOS)的单载子降低导通电阻相比，LIGBT结构由于电子、空穴的双载子注入形成电导调制效应能带来较低的导通电阻。
但在关断时，LIGBT的漂移区中由于残留少子空穴，关断时间偏长，故存在功耗偏大的问题。由于导通电阻及和关断时间与空穴浓度呈相反关系，因此如何在导通电阻和关断时间之间取得平衡，成为LIGBT器件持续改进的方向。
发明内容
基于此，有必要提供一种在保证低导通电阻的基础上能够快速关断的横向绝缘栅双极型晶体管及其制造方法。
一种横向绝缘栅双极型晶体管，包括衬底、衬底上的阳极端和阴极端，以及位于阳极端与阴极端之间的漂移区和栅极，所述阳极端包括衬底上的N型缓冲区，所述N型缓冲区内的P阱，所述P阱内的N+区，位于所述N+区上方的被所述P阱部分包围的沟槽，所述沟槽内的多晶硅，所述沟槽两侧的P+结，以及所述P+结两侧的N+结。
一种横向绝缘栅双极型晶体管的制造方法，包括：向硅晶圆注入N型离子，并推阱形成N型缓冲区；在所述硅晶圆表面淀积硬掩膜层，并使用光刻胶进行沟槽光刻和刻蚀，将所述硬掩膜层刻蚀出沟槽窗口；刻蚀所述沟槽窗口下方的硅，形成沟槽；进行衬垫氧化，在所述沟槽的内表面形成衬垫氧化层；所述衬垫氧化层在沟槽侧壁的厚度大于在沟槽底部的厚度；向所述沟槽窗口内注入P型离子，离子穿过所述氧化层在所述沟槽周围的N型缓冲区内形成P阱；在所述沟槽内淀积氧化层，刻蚀后在沟槽侧壁形成氧化膜、在沟槽底部两侧形成侧墙结构；向所述沟槽内注入N型离子，在所述氧化膜和侧墙的阻挡下通过自对准注入形成N+区；在所述沟槽内淀积多晶硅，刻蚀后将所述硬掩膜层剥除；对所述P阱和所述N+区进行退火；通过光刻和刻蚀在所述沟槽的两侧形成P+结、在所述P+结的两侧形成N+结。
上述横向绝缘栅双极型晶体管一方面在正向导通时，注入大量的空穴，形成显著的电导调制效应来降低开态电阻；另一方面，在器件关断时，N+区和N+结可以很快地吸收少子空穴，极大地降低了关断损耗。
附图说明
通过附图中所示的本发明的优选实施例的更具体说明，本发明的上述及其它目的、特征和优势将变得更加清晰。在全部附图中相同的附图标记指示相同的部分，且并未刻意按实际尺寸等比例缩放绘制附图，重点在于示出本发明的主旨。
图1是一实施例中横向绝缘栅双极型晶体管的截面示意图；
图2是一实施例中横向绝缘栅双极型晶体管的制造方法的流程图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使 对本发明的公开内容更加透彻全面。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易地将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
横向绝缘栅双极型晶体管技术由于漂移区较长，导致在电导调制效应带来低导通压降的同时，会伴随漂移区中由于残留少子导致的关断时间偏长的问题。因此如何在开态压降和关断时间之间取得平衡，成为横向绝缘栅双极型晶体管持续改进的方向。
图1是一实施例中横向绝缘栅双极型晶体管的结构示意图，包括衬底10，衬底10上的阳极端和阴极端，以及位于阳极端与阴极端之间的漂移区30和栅极62(栅极62底部的栅氧化层在图1中省略了)。阳极端包括衬底10上的N型缓冲区42，N型缓冲区42内的P阱44，P阱44内的N+区46，位于N+区46上方被P阱44部分包围的沟槽，沟槽内的多晶硅74，沟槽两侧的P+结53，以及P+结53两侧的N+结55。阴极端包括衬底10上的P-区52，P-区52内的P型体区54及发射极N+区56，以及作为发射极的电极的阴极 金属64。
上述横向绝缘栅双极型晶体管，当栅极62正偏时，器件沟道打开，电子电流由发射极的N+区56穿过P-区52的沟道进入漂移区30、N型缓冲区42和N+区46；当集电极正偏时，空穴开始由集电极的P阱44通过较大面积的PN结注入进N型缓冲区42中，实现了高效率多路径的多子空穴注入，极大降低了导通电阻。当LIGBT反向关断时，集电极(包括P+结53和N+结55)正向偏置，N+区46、P阱44及N型缓冲区42形成空穴注入的低阻路径，开始较快地抽取漂移区30中残余的少子空穴，保证了较快的开关速度，达到快速关断的目的。
在图1所示的实施例中，沟槽为底部窄、顶部宽的由下向上逐渐变宽形成坡度的结构。
在图1所示的实施例中，N型缓冲区42掺杂浓度小于P阱44的掺杂浓度，P阱44的掺杂浓度小于P+结53和N+结55的掺杂浓度。在其中一个实施例中，N型缓冲区42的掺杂浓度为2E15～5E15cm-3，P阱44的掺杂浓度为4E17～8E17cm-3，P+结53和N+结55的掺杂浓度为5E20～10E20cm-3。
在图1所示的实施例中，阳极端还包括沟槽内表面的氧化层。氧化层包括位于沟槽侧壁的氧化膜72和位于沟槽底部两侧的侧墙结构72a。沟槽底部的中部存在氧化层空缺使得沟槽内的多晶硅74直接与下方的N+区46接触。
在本实施例中，位于沟槽底部两侧的多晶硅74为N+重掺杂多晶硅，掺杂浓度为E21～E22cm-3量级。
绝缘体上硅(SOI)技术正在HVIC及SPIC应用领域体现出愈来愈大的重要性，而IGBT器件则由于高输入阻抗及电导调制效应带来的低导通电阻特性，在功率器件应用领域中日益占据重要地位。相比于体硅结隔离型器件，SOI的LIGBT器件由于槽式隔离带来的低漏电、低开态电阻、高输入阻抗、高封装密度、快速开关、降噪效果显著及高温工作下的可行性，在汽车电子、家用电子及通信和工业应用上取得较为广泛的应用。尤为重要的是需要高效率的空穴注入及显著的电导调制效应来降低开态电阻，但也相应增加了器件 关断时，少子空穴无法较快湮灭引起的关断损耗。图1所示的LIGBT为绝缘体上硅型横向绝缘栅双极型晶体管(SOI-LIGBT)，包括位于衬底10和漂移区30之间的埋氧层20，其中衬底10为P型衬底，漂移区30为N-型漂移区。
图2是一实施例中横向绝缘栅双极型晶体管的制造方法的流程图，包括：
S210，向硅晶圆注入N型离子，并推阱形成N型缓冲区。
S220，淀积硬掩膜层，并进行沟槽光刻和刻蚀，将硬掩膜层刻蚀出沟槽窗口。
在硅晶圆表面淀积硬掩膜层，并在硬掩膜层表面涂覆光刻胶进行光刻，将光刻后光刻胶下露出的硬掩膜刻蚀掉，形成沟槽窗口，将下方的硅露出。在本实施例中，硬掩膜层为氮化硅层。在其他实施例中，也可以采用本领域习知的其他硬掩膜。
在其中一个实施例中，在淀积硬掩膜层之前还要形成焊盘(pad)氧化层。
S230，刻蚀沟槽窗口下方的硅，形成沟槽。
在本实施例中，是刻蚀形成顶部宽、底部窄的由上向下逐渐变窄形成坡度的结构。
S240，进行衬垫氧化，在沟槽的内表面形成衬垫氧化层。
由于沟槽的侧壁和底部的晶向不同，因此衬垫氧化层(liner oxide)的氧化速度也就存在差异，侧壁的氧化层厚度大于底部的氧化层厚度。
S250，注入P型离子，在沟槽周围的N型缓冲区内形成P阱。
向沟槽窗口内注入P型离子，离子穿过氧化层在沟槽周围的N型缓冲区内形成P阱。由于沟槽侧壁的氧化层厚度大于底部的氧化层厚度，因此会相应地对P阱中P型离子的浓度分布造成影响。
S260，在沟槽内淀积氧化层，刻蚀后在沟槽侧壁形成氧化膜、在沟槽底部两侧形成侧墙结构。
在本实施例中，是以正硅酸乙酯(TEOS)为反应剂进行化学气相淀积，形成二氧化硅层。在其他实施例中也可以采用本领域习知的其他工艺生成氧化层。淀积后采用各向异性刻蚀在沟槽侧壁形成氧化膜、在沟槽底部两侧形 成侧墙结构，并在沟槽底部的中部形成氧化层的空缺，作为步骤S270中N+注入的窗口。
S270，注入N型离子，在氧化膜和侧墙的阻挡下通过自对准注入形成N+区。
向沟槽内注入N型离子，在氧化膜和侧墙的阻挡下通过自对准(Self-Align)注入形成N+区。
自对准注入形成的N+区与P阱和N型缓冲区形成纵向的垂直NPN作为关键的少子寿命控制手段。
S280，在沟槽内淀积多晶硅，刻蚀后将硬掩膜层剥除。
淀积多晶硅并将沟槽外多余的多晶硅刻蚀掉，然后将硬掩膜层去除。在本实施例中，淀积多晶硅的步骤之前还包括对N+区域附近的二氧化硅进行漂洗的步骤，以将二氧化硅杂质去除。
在本实施例中，多晶硅74为N+重掺杂，掺杂浓度为E21～E22cm-3量级。
S290，对P阱和N+区进行退火。
热退火以激活P阱、N+区等区域的掺杂离子。退火完成后执行器件其他区域的制造工艺，例如CMOS工艺。
S310，通过光刻和刻蚀在沟槽的两侧形成P+结、在P+结的两侧形成N+结。
注入完成后也要相应进行退火，之后进行器件的后段制程。
在其中一个实施例中，步骤S250的注入是进行多次注入，以获得变化更缓的掺杂浓度梯度，优化P阱的杂质分布形貌，甚至可以达到在一定区域内掺杂浓度基本不变，有助于提升N+/P-/N-三极管的放大倍数、加快空穴的抽取速度。
采用上述方法制造的横向绝缘栅双极型晶体管的结构示意图如图1所示。该横向绝缘栅双极型晶体管在正向导通时，注入大量的空穴，形成显著的电导调制效应来降低开态电阻；另一方面，在器件关断时，N+区和N+结可以很快地吸收少子空穴，极大地降低了关断损耗。即通过优化LIGBT的集电极， 通过沟槽结构引入深集电极P阱和P+结，并形成N+多晶硅和N+区，正向导通时形成分布较宽的电子/空穴电流通道，提高电流能力。反向阻断时，优化的集电极有助于更快收集少子空穴，降低关断时间。在其中一个实施例中，N型缓冲区42的掺杂浓度为2E15～5E15cm-3，P阱44的掺杂浓度为4E17～8E17cm-3，P+结53和N+结55的掺杂浓度为5E20～10E20cm-3。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种横向绝缘栅双极型晶体管，包括：
    衬底；
    阴极端，位于所述衬底上；
    阳极端，位于所述衬底上，所述阳极端包括位于所述衬底上的N型缓冲区，位于所述N型缓冲区内的P阱，位于所述P阱内的N+区，位于所述N+区上方的被所述P阱部分包围的沟槽，位于所述沟槽内的多晶硅，位于所述沟槽两侧的P+结，以及位于所述P+结两侧的N+结；
    漂移区，位于所述阳极端和阴极端之间；以及
    栅极，位于所述阳极端和阴极端之间。
  2. 根据权利要求1所述的横向绝缘栅双极型晶体管，其特征在于，所述沟槽为底部窄且顶部宽的由下向上逐渐变宽形成坡度的结构。
  3. 根据权利要求1所述的横向绝缘栅双极型晶体管，其特征在于，所述N型缓冲区的掺杂浓度小于所述P阱的掺杂浓度，所述P阱的掺杂浓度小于所述P+结和N+结的掺杂浓度。
  4. 根据权利要求3所述的横向绝缘栅双极型晶体管，其特征在于，所述N型缓冲区的掺杂浓度为2E15～5E15cm-3，所述P阱的掺杂浓度为4E17～8E17cm-3，所述P+结和N+结的掺杂浓度为5E20～10E20cm-3。
  5. 根据权利要求1所述的横向绝缘栅双极型晶体管，其特征在于，所述阳极端还包括所述沟槽内表面的氧化层，所述氧化层包括位于沟槽侧壁的氧化膜和位于沟槽底部两侧的侧墙结构，所述沟槽底部的中部存在氧化层空缺使得所述多晶硅直接与下方的所述N+区接触。
  6. 根据权利要求1所述的横向绝缘栅双极型晶体管，其特征在于，所述多晶硅的掺杂浓度为1E21～10E22cm-3。
  7. 根据权利要求1所述的横向绝缘栅双极型晶体管，其特征在于，所述横向绝缘栅双极型晶体管为绝缘体上硅型横向绝缘栅双极型晶体管，所述横向绝缘栅双极型晶体管还包括位于衬底和漂移区之间的埋氧层，所述衬底为 P型衬底，所述漂移区为N型漂移区。
  8. 一种横向绝缘栅双极型晶体管的制造方法，包括：
    向硅晶圆注入N型离子，并推阱形成N型缓冲区；
    在所述硅晶圆表面淀积硬掩膜层，并使用光刻胶进行沟槽光刻和刻蚀，将所述硬掩膜层刻蚀出沟槽窗口；
    刻蚀所述沟槽窗口下方的硅，形成沟槽；
    进行衬垫氧化，在所述沟槽的内表面形成衬垫氧化层；所述衬垫氧化层在沟槽侧壁的厚度大于在沟槽底部的厚度；
    向所述沟槽窗口内注入P型离子，离子穿过所述氧化层在所述沟槽周围的N型缓冲区内形成P阱；
    在所述沟槽内淀积氧化层，刻蚀后在沟槽侧壁形成氧化膜、在沟槽底部两侧形成侧墙结构；
    向所述沟槽内注入N型离子，在所述氧化膜和侧墙的阻挡下通过自对准注入形成N+区；
    在所述沟槽内淀积多晶硅，刻蚀后将所述硬掩膜层剥除；
    对所述P阱和所述N+区进行退火；以及
    通过光刻和刻蚀在所述沟槽的两侧形成P+结、在所述P+结的两侧形成N+结。
  9. 根据权利要求8所述的方法，其特征在于，所述硬掩膜层为氮化硅层。
  10. 根据权利要求8所述的方法，其特征在于，所述在所述沟槽内淀积氧化层，刻蚀后在沟槽侧壁形成氧化膜、在沟槽底部两侧形成侧墙结构的步骤，是以正硅酸乙酯为反应剂进行化学气相淀积，并进行各向异性刻蚀。
  11. 根据权利要求8所述的方法，其特征在于，所述在所述沟槽内淀积多晶硅的步骤之前、所述向所述沟槽内注入N型离子的步骤之后，还包括进行氧化层漂洗的步骤。
  12. 根据权利要求8所述的方法，其特征在于，所述向所述沟槽窗口内注入P型离子，离子穿过所述氧化层在所述沟槽周围的N型缓冲区内形成P 阱的步骤中，是进行多次注入，以获得变化更缓的掺杂浓度梯度。
  13. 根据权利要求8所述的方法，其特征在于，所述N型缓冲区的掺杂浓度小于所述P阱的掺杂浓度，所述P阱的掺杂浓度小于所述P+结和N+结的掺杂浓度。
  14. 根据权利要求8所述的方法，其特征在于，所述N型缓冲区的掺杂浓度为2E15～5E15cm-3，所述P阱的掺杂浓度为4E17～8E17cm-3，所述P+结和N+结的掺杂浓度为5E20～10E20cm-3。
  15. 根据权利要求8所述的方法，其特征在于，所述横向绝缘栅双极型晶体管为绝缘体上硅型横向绝缘栅双极型晶体管，所述衬底为P型衬底，所述漂移区为N型漂移区。
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