WO2017206769A1 - Printed circuit board - Google Patents

Printed circuit board Download PDF

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Publication number
WO2017206769A1
WO2017206769A1 PCT/CN2017/085583 CN2017085583W WO2017206769A1 WO 2017206769 A1 WO2017206769 A1 WO 2017206769A1 CN 2017085583 W CN2017085583 W CN 2017085583W WO 2017206769 A1 WO2017206769 A1 WO 2017206769A1
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WIPO (PCT)
Prior art keywords
layer
strain
printed circuit
circuit board
layers
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PCT/CN2017/085583
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French (fr)
Chinese (zh)
Inventor
龚云隆
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华为技术有限公司
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Publication of WO2017206769A1 publication Critical patent/WO2017206769A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B7/00—Measuring arrangements characterised by the use of electric or magnetic techniques
    • G01B7/16—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring the deformation in a solid, e.g. by resistance strain gauge
    • G01B7/18—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring the deformation in a solid, e.g. by resistance strain gauge using change in resistance
    • G01B7/20—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring the deformation in a solid, e.g. by resistance strain gauge using change in resistance formed by printed-circuit technique
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L1/00—Measuring force or stress, in general
    • G01L1/20—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress
    • G01L1/22—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress using resistance strain gauges

Definitions

  • the invention relates to the field of circuit boards, in particular to a printed circuit board assembly (PCB) for testing strain on a printed circuit board assembly (PCBA).
  • PCB printed circuit board assembly
  • PCBA printed circuit board assembly
  • the stress failure problem of the PCBA inside the terminal becomes prominent and complicated, and the stress refers specifically to the object.
  • the stress failure specifically means that when the device or PCBA is excessively deformed, the yield limit or fatigue limit of the device or PCBA material is exceeded, thereby causing device or PCBA failure.
  • the stress of the PCBA needs to be tested to achieve quality control of the terminal.
  • the strain gauge is mounted at a local point position on the PCBA to test the stress of the PCBA.
  • the local points are placed on the upper surface or the lower surface of the PCBA.
  • the specific test process is as follows: the strain gauge is placed on the local point position, so that the strain gauge is stretched together with the strain received by the local point, and the metal foil in the strain gauge is elongated or shortened according to the strain.
  • the metal foil is mechanically elongated or shortened, the electrical resistance of the metal foil also changes.
  • the leads of the strain gauges are connected to a dedicated device, and the resistance change of the metal foil is measured in different scenarios, and the strain at the local point position is obtained according to the change in the resistance.
  • the prior art PCBA stress testing scheme still has the following defects: 1) the existing PCBA stress test cannot fully cover the entire board, and the effectiveness of the stress test is reduced; 2) the strain gauge is placed at the local point When the components in the original position on the PCBA are removed and the lead space is opened, the stress test can be realized; and the connection line of the attached strain gauges is easily broken during the test, resulting in a decrease in the accuracy of the test results.
  • This paper describes a printed circuit board to test the overall board stress of PCBA, improving the effectiveness and accuracy of stress testing.
  • embodiments of the present application provide a printed circuit board including a plurality of conductive layers and an insulating layer separating the conductive layers, the plurality of conductive layers being spaced apart from the plurality of insulating layers.
  • the PCB further includes a strained array layer disposed between adjacent insulating layers.
  • the strained array layer is placed between the insulating layer near the top layer and the adjacent insulating layer in the PCB board, or
  • the strain array layer is placed between the insulating layer near the bottom layer and the adjacent insulating layer in the PCB.
  • the multi-layer conductive layer and the multi-layer insulating layer are distributed between the PCB boards.
  • the strain array layer is disposed between adjacent insulating layers in the PCB board, specifically referring to the strain array.
  • the layer replaces the conductive layer between adjacent insulating layers in the PCB.
  • the strain array layer is specifically a line of a semiconductor medium that can undergo an impedance change when mechanical deformation occurs under the action of an external force.
  • the number of strain array layers is one or two.
  • the strain array layer When set to one, the strain array layer is disposed in the PCB board near the top layer or adjacent to the adjacent insulating layer of the bottom layer; when set to two, the strain array layer is disposed in the PCB board near the top layer and near the bottom layer Between adjacent insulation layers.
  • the strained array layer is coupled to a processor mounted on the conductive layer, and the processor is configured to acquire strain data of the PCB through the strained array layer and transmit the collected strain data to the terminal.
  • the strain data is the impedance change value of the strain array layer. Since the strain array layer is pressed into the PCB board, the impedance change of the strain array layer is the actual deformation state of the PCB board.
  • the impedance change value collected by the processor is also the strain data of the PCB board.
  • the solution provided by the invention can test the whole board stress of the PCBA, has high coverage, realizes testing the stress of the PCBA, and improves the effectiveness and accuracy of the stress test.
  • FIG. 1 is a schematic structural diagram of a PCB according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another PCB according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a strain array layer according to an embodiment of the present invention.
  • the structure of the PCB board described in the embodiments of the present invention is for the purpose of more clearly explaining the technical solutions of the embodiments of the present invention, and does not constitute a limitation of the technical solutions provided by the embodiments of the present invention.
  • the technical solution provided by the embodiment of the present invention is applicable to similar technical problems.
  • FIG. 1 is a schematic structural diagram of a PCB board according to an embodiment of the present invention.
  • a multilayer PCB board is taken as an example for description.
  • the PCB board includes a conductive sheet 110, an insulating layer 120, and a strained array layer 130.
  • the PCB board specifically refers to a light board having a conductive layer 110, an insulating layer 120, and a strain array layer 130.
  • the light board specifically refers to a PCB board that is not soldered with electronic components
  • the PCBA specifically refers to Various electronic devices are assembled on the PCB by a surface encapsulation process.
  • the top layer or the bottom layer of the conductive layer 110 is mounted with electronic devices, and the electronic device is mounted on the surface of the top or bottom conductive layer 110 by a surface mount technology (SMT), and the PCB board has many
  • SMT surface mount technology
  • the layer conductive layer 110 is distributed between the plurality of insulating layers 120, and the strain array layer 130 is disposed between the adjacent insulating layers 120, as shown in FIG.
  • the multilayer PCB board is composed of the conductive layer 110 and the insulating layer 120.
  • the conductive layer 110 can be specific It is realized by a copper layer for conducting electricity; the insulating layer is specifically realized by an insulating medium for performing insulation.
  • the strain array layer 130 is placed between the insulating layer 120 near the top layer and the adjacent insulating layer 120 in the PCB board, or the strain array layer 130 is placed in the PCB board adjacent to the insulating layer 120 of the bottom layer and adjacent Between the insulating layers 120, as shown in FIG.
  • the strain array layer 130 is placed adjacent to the PCB board. Between the layers 120, specifically, the conductive layer 110 between the adjacent insulating layers 120 in the PCB board is replaced with the strained array layer 130.
  • the surface conductive layer 110 or the bottom conductive layer 110 is used for mounting or soldering electronic devices to electrically connect the electronic devices to each other.
  • the strain array layer 130 may be specifically a sheet-like structure of a semiconductor medium.
  • the length and width data of the strain array layer 130 are the same as the length and width data of the PCB.
  • the strain array layer 130 is composed of a plurality of strain gauges, wherein each strain gauge has a serpentine line, that is, a plurality of strain gauges have serpentine lines forming a strain array layer 130 for amplifying the impedance change. .
  • the strain array layer 130 is as shown in FIG.
  • the strain gauge labeled 1 in the figure is a horizontal strain gauge having a horizontal meandering line for amplifying the deformation in the horizontal direction;
  • the strain gauge labeled 2 in the figure is a vertical strain gauge having a vertical meandering line for The deformation in the vertical direction is enlarged;
  • the strain gauge labeled 3 in the figure is a 45-degree directional strain gauge having a 45-degree meandering line for amplifying the deformation in the 45-degree direction.
  • the meandering line of the strain gauge in the strain array layer 130 can be mechanically deformed under the action of external force, and an impedance change occurs.
  • the electronic device mounted on the top or bottom conductive layer 110 collects the impedance change value of the meandering line, and then determines The stress of the PCB.
  • the electronic device mounted on the top or bottom conductive layer 110 can be directly connected to the meandering line of the strain gauge layer 130 in the strain array layer 130, without the need for lead measurement, thereby improving test convenience and stability. .
  • the strain array layer 130 may be one or two according to the number of layers of the PCB board. For example, when the PCB board has four layers or less than four layers, one strain array layer 130 may be disposed; when the PCB board has more than four layers, for example, six layers and eight layers One or two strain array layers 130 may be provided. When set to one, the strain array layer 130 is disposed in the PCB board near the top layer or between adjacent insulating layers near the bottom layer; when set to two, the strain array layer 130 is disposed in the PCB board near the top layer And between adjacent insulating layers near the bottom layer.
  • the electronic devices are mounted or soldered on the top conductive layer 110 and the bottom conductive layer 110 of the PCB, and the electronic device includes a processor. It can be understood that the conductive layer 110 may further include other electronic devices that implement the function of the PCB, such as resistors, capacitors, and the like.
  • the processor may acquire the strain data of the PCB board through the strain array layer 130, and send the collected strain data to the terminal, where the strain data is the impedance change value of the strain array layer 130.
  • the processor can measure the impedance change value in the PCB board in real time through the strain array layer 130, store it, and send the impedance change value to the terminal, and the terminal analyzes the deformation of the PCB board through professional software. Since the strain array layer 130 has been pressed into the PCB board, the impedance variation of the strain array layer 130 is also the actual deformation state of the PCB board.
  • the impedance change value collected by the processor is also the strain data of the PCB board.
  • the strain array layer 130 is pressed into the PCB board, the whole board stress of the PCBA can be tested, the coverage rate is high, and the effectiveness of the stress test is improved; during the test, there is no need to eradicate Conductive layer 110
  • the original components do not need to open lead space, and have little influence on the test results; and the components on the conductive layer are mounted on the conductive layer 110 by SMT technology, which is simple and reliable, has no connection line, and improves the accuracy of the stress test.
  • strain array layer 130 provided by the embodiment of the present invention can also be placed in the structural member to measure the overall stress of the structural member.

Abstract

A printed circuit board (PCB) for testing strain of a printed circuit board assembly comprises: multiple electrically-conductive layers (110); insulating layers (120) separating the electrically-conductive layers (110); and a strain array layer (130) disposed between the insulating layers (120). The invention enables a stress test to be performed on an entire PCB and has a high coverage rate, thereby realizing a stress test on an entire PCB, and increasing validity and accuracy of the stress test.

Description

印刷电路板A printed circuit board 技术领域Technical field
本发明涉及电路板领域，尤其涉及多层印刷电路板(Printed Circuit Board简称：PCB)对印刷电路板组件(Printed Circuit Board Assembly，简称：PCBA)进行应变的测试。The invention relates to the field of circuit boards, in particular to a printed circuit board assembly (PCB) for testing strain on a printed circuit board assembly (PCBA).
背景技术Background technique
目前，随着智能终端尺寸的增大，但终端的厚度越来越薄，且终端内元器件数量越来越多，终端内部PCBA的应力失效问题变得突出复杂，所述应力具体是指物体由于外因(受力、湿度、温度场变化等)而发生变形时，在物体内各部分之间产生相互作用的内力，以抵抗这种外因的作用，并试图使物体从变形后的位置恢复到变形前的位置。所述应力失效具体是指当器件或PCBA变形过大时，超出了器件或PCBA材料的屈服极限或疲劳极限，进而产生器件或PCBA失效。在终端的生产、测试、组装、使用过程中，需对PCBA的应力进行测试，以实现对终端的质量控制。At present, with the increase of the size of the smart terminal, but the thickness of the terminal is getting thinner and thinner, and the number of components in the terminal is increasing, the stress failure problem of the PCBA inside the terminal becomes prominent and complicated, and the stress refers specifically to the object. When deformation occurs due to external factors (force, humidity, temperature field changes, etc.), an internal force of interaction occurs between the various parts of the object to resist the external cause and attempt to restore the object from the deformed position to The position before the deformation. The stress failure specifically means that when the device or PCBA is excessively deformed, the yield limit or fatigue limit of the device or PCBA material is exceeded, thereby causing device or PCBA failure. During the production, testing, assembly, and use of the terminal, the stress of the PCBA needs to be tested to achieve quality control of the terminal.
现有技术中，采用在PCBA上的局部点位置贴装应变片的方式，以实现对PCBA的应力进行测试，一般情况，局部点均置于PCBA的上表面或者下表面。In the prior art, the strain gauge is mounted at a local point position on the PCBA to test the stress of the PCBA. Generally, the local points are placed on the upper surface or the lower surface of the PCBA.
具体测试过程为：将应变片贴装在局部点位置上，使应变片随着局部点受到的应变一起伸缩，在应变片中的金属箔材会随着应变伸长或缩短。在金属箔材机械性地伸长或缩短时，金属箔材的电阻也会随之变化。将应变片的引线连接到专用设备上，在不同场景中测量金属箔材的电阻变化，根据该电阻变化得到局部点位置处的应变情况。The specific test process is as follows: the strain gauge is placed on the local point position, so that the strain gauge is stretched together with the strain received by the local point, and the metal foil in the strain gauge is elongated or shortened according to the strain. When the metal foil is mechanically elongated or shortened, the electrical resistance of the metal foil also changes. The leads of the strain gauges are connected to a dedicated device, and the resistance change of the metal foil is measured in different scenarios, and the strain at the local point position is obtained according to the change in the resistance.
但是，现有技术中的PCBA的应力测试方案仍存在下述缺陷：1)现有PCBA的应力测试无法对整板进行全面覆盖，应力测试的有效性降低；2)在局部点贴装应变片时，需将PCBA上原有位置的元器件铲除，开辟引线空间，才可实现应力测试；且贴装应变片的连接线在测试过程中容易断，导致测试结果的准确率降低。However, the prior art PCBA stress testing scheme still has the following defects: 1) the existing PCBA stress test cannot fully cover the entire board, and the effectiveness of the stress test is reduced; 2) the strain gauge is placed at the local point When the components in the original position on the PCBA are removed and the lead space is opened, the stress test can be realized; and the connection line of the attached strain gauges is easily broken during the test, resulting in a decrease in the accuracy of the test results.
发明内容Summary of the invention
本文描述了一种印刷电路板，以实现对PCBA的整板应力进行测试，提高应力测试的有效性以及准确率。This paper describes a printed circuit board to test the overall board stress of PCBA, improving the effectiveness and accuracy of stress testing.
一方面，本申请的实施例提供一种印刷电路板，该PCB板包括多层导电层以及将导电层分开的绝缘层，多层导电层与多层绝缘层相间分布。该PCB板还包括：应变阵列层，应变阵列层置于相邻绝缘层之间。In one aspect, embodiments of the present application provide a printed circuit board including a plurality of conductive layers and an insulating layer separating the conductive layers, the plurality of conductive layers being spaced apart from the plurality of insulating layers. The PCB further includes a strained array layer disposed between adjacent insulating layers.
在一个可能的设计中，应变阵列层置于PCB板中靠近顶层的绝缘层与相邻的绝缘层之间，或者，In one possible design, the strained array layer is placed between the insulating layer near the top layer and the adjacent insulating layer in the PCB board, or
应变阵列层置于PCB板中靠近底层的绝缘层与相邻的绝缘层之间。The strain array layer is placed between the insulating layer near the bottom layer and the adjacent insulating layer in the PCB.
在描述PCB板结构时，PCB板中多层导电层与多层绝缘层相间分布，在本发明实施例中，应变阵列层置于PCB板中相邻绝缘层之间，具体是指将应变阵列层替换PCB板中相邻绝缘层之间的导电层。In the description of the PCB structure, the multi-layer conductive layer and the multi-layer insulating layer are distributed between the PCB boards. In the embodiment of the present invention, the strain array layer is disposed between adjacent insulating layers in the PCB board, specifically referring to the strain array. The layer replaces the conductive layer between adjacent insulating layers in the PCB.
应变阵列层具体为半导体介质的线路，该半导体介质可在外界力的作用下产生机械变形时，发生阻抗变化。 The strain array layer is specifically a line of a semiconductor medium that can undergo an impedance change when mechanical deformation occurs under the action of an external force.
在一个可能的设计中，应变阵列层的个数为1个或2个。当设置为一个时，该应变阵列层设置在PCB板中靠近顶层，或者靠近底层的相邻绝缘层之间；当设置为2个时，该应变阵列层设置在PCB板中靠近顶层以及靠近底层的相邻绝缘层之间。In one possible design, the number of strain array layers is one or two. When set to one, the strain array layer is disposed in the PCB board near the top layer or adjacent to the adjacent insulating layer of the bottom layer; when set to two, the strain array layer is disposed in the PCB board near the top layer and near the bottom layer Between adjacent insulation layers.
在一个可能的设计中，应变阵列层与导电层上贴装的处理器连接，处理器用于通过应变阵列层采集PCB板的应变数据，并将采集的应变数据发送至终端。其中，应变数据即为应变阵列层的阻抗变化值，由于应变阵列层已压合在PCB板内，因此，应变阵列层的阻抗变化也即是PCB板的实际变形状态。处理器采集的阻抗变化值也即是PCB板的应变数据。In one possible design, the strained array layer is coupled to a processor mounted on the conductive layer, and the processor is configured to acquire strain data of the PCB through the strained array layer and transmit the collected strain data to the terminal. The strain data is the impedance change value of the strain array layer. Since the strain array layer is pressed into the PCB board, the impedance change of the strain array layer is the actual deformation state of the PCB board. The impedance change value collected by the processor is also the strain data of the PCB board.
相较于现有技术，本发明提供的方案可以对PCBA的整板应力进行测试，覆盖率高，实现对PCBA的应力进行测试，提高应力测试的有效性以及准确率。Compared with the prior art, the solution provided by the invention can test the whole board stress of the PCBA, has high coverage, realizes testing the stress of the PCBA, and improves the effectiveness and accuracy of the stress test.
附图说明DRAWINGS
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。显而易见地，下面附图中反映的仅仅是本发明的一部分实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得本发明的其他实施方式。而所有这些实施例或实施方式都在本发明的保护范围之内。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art description will be briefly described below. Obviously, only some embodiments of the present invention are reflected in the following drawings, and other embodiments of the present invention can be obtained according to the drawings without any inventive labor for those skilled in the art. . All such embodiments or implementations are within the scope of the invention.
图1为本发明实施例提供的一种PCB结构示意图；1 is a schematic structural diagram of a PCB according to an embodiment of the present invention;
图2为本发明实施例提供的另一种PCB结构示意图；2 is a schematic structural diagram of another PCB according to an embodiment of the present invention;
图3为本发明实施例提供的应变阵列层示意图。FIG. 3 is a schematic diagram of a strain array layer according to an embodiment of the present invention.
具体实施方式detailed description
下面将结合附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings. It is apparent that the described embodiments are only a part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without departing from the inventive scope are the scope of the present invention.
本发明实施例描述的PCB板的结构是为了更加清楚的说明本发明实施例的技术方案，并不构成对于本发明实施例提供的技术方案的限定，本领域普通技术人员可知，随着新业务场景的出现，本发明实施例提供的技术方案对于类似的技术问题，同样适用。The structure of the PCB board described in the embodiments of the present invention is for the purpose of more clearly explaining the technical solutions of the embodiments of the present invention, and does not constitute a limitation of the technical solutions provided by the embodiments of the present invention. The technical solution provided by the embodiment of the present invention is applicable to similar technical problems.
如图1所示，图1为本发明实施例提供的一种PCB板结构示意图。在本发明实施例中以多层PCB板为例进行说明。该PCB板包括导电层110(copper sheet)，绝缘层120(prepreg)，以及应变阵列层130。As shown in FIG. 1 , FIG. 1 is a schematic structural diagram of a PCB board according to an embodiment of the present invention. In the embodiment of the present invention, a multilayer PCB board is taken as an example for description. The PCB board includes a conductive sheet 110, an insulating layer 120, and a strained array layer 130.
在本发明实施例中，所述PCB板具体是指具有导电层110、绝缘层120以及应变阵列层130的光板，该光板具体是指未焊接电子器件的PCB板，所述PCBA具体是指将各种电子器件通过表面封装工艺组装在PCB板上。In the embodiment of the present invention, the PCB board specifically refers to a light board having a conductive layer 110, an insulating layer 120, and a strain array layer 130. The light board specifically refers to a PCB board that is not soldered with electronic components, and the PCBA specifically refers to Various electronic devices are assembled on the PCB by a surface encapsulation process.
其中，顶层或者底层的导电层110上贴装有电子器件，电子器件通过表面贴装技术(Sur-face Mount Technology，简称：SMT)贴装在顶层或者底层的导电层110表面，PCB板中多层导电层110与多层绝缘层120相间分布，应变阵列层130置于相邻绝缘层120之间，如图1所示。Wherein, the top layer or the bottom layer of the conductive layer 110 is mounted with electronic devices, and the electronic device is mounted on the surface of the top or bottom conductive layer 110 by a surface mount technology (SMT), and the PCB board has many The layer conductive layer 110 is distributed between the plurality of insulating layers 120, and the strain array layer 130 is disposed between the adjacent insulating layers 120, as shown in FIG.
可以理解的是，多层PCB板由导电层110和绝缘层120组成。其中，导电层110可具体 由铜层实现，用于进行导电；绝缘层具体由绝缘介质实现，用于进行绝缘。It can be understood that the multilayer PCB board is composed of the conductive layer 110 and the insulating layer 120. Wherein, the conductive layer 110 can be specific It is realized by a copper layer for conducting electricity; the insulating layer is specifically realized by an insulating medium for performing insulation.
在一个例子中，应变阵列层130置于PCB板中靠近顶层的绝缘层120与相邻的绝缘层120之间，或者，应变阵列层130置于PCB板中靠近底层的绝缘层120与相邻的绝缘层120之间，如图2所示。In one example, the strain array layer 130 is placed between the insulating layer 120 near the top layer and the adjacent insulating layer 120 in the PCB board, or the strain array layer 130 is placed in the PCB board adjacent to the insulating layer 120 of the bottom layer and adjacent Between the insulating layers 120, as shown in FIG.
需要说明的是，在描述PCB板结构时，PCB板中多层导电层110与多层绝缘层120相间分布，因此，在本发明实施例中，应变阵列层130置于PCB板中相邻绝缘层120之间，具体是指用应变阵列层130替换PCB板中相邻绝缘层120之间的导电层110。It should be noted that, when describing the structure of the PCB board, the plurality of conductive layers 110 and the plurality of insulating layers 120 are distributed between the PCB boards. Therefore, in the embodiment of the present invention, the strain array layer 130 is placed adjacent to the PCB board. Between the layers 120, specifically, the conductive layer 110 between the adjacent insulating layers 120 in the PCB board is replaced with the strained array layer 130.
在本发明实施例中，表层导电层110或者底层导电层110均是用来贴装或焊接电子器件，以使电子器件相互连接导通。In the embodiment of the present invention, the surface conductive layer 110 or the bottom conductive layer 110 is used for mounting or soldering electronic devices to electrically connect the electronic devices to each other.
其中，应变阵列层130可具体为半导体介质的片状结构，应变阵列层130的长、宽数据与PCB板的长、宽数据相同。应变阵列层130由多个应变片组成，其中，每个应变片具有蛇形线路，也即是多个应变片具有的蛇行线路构成应变阵列层130，该蛇行线路用于对阻抗的变化进行放大。如图3所示的应变阵列层130。图中标号为1的应变片为水平方向应变片，其具有水平蛇行线路，用于放大水平方向的形变；图中标号为2的应变片为垂直方向应变片，其具有垂直蛇行线路，用于放大垂直方向的形变；图中标号为3的应变片为45度方向应变片，其具有45度蛇行线路，用于放大45度方向的形变。The strain array layer 130 may be specifically a sheet-like structure of a semiconductor medium. The length and width data of the strain array layer 130 are the same as the length and width data of the PCB. The strain array layer 130 is composed of a plurality of strain gauges, wherein each strain gauge has a serpentine line, that is, a plurality of strain gauges have serpentine lines forming a strain array layer 130 for amplifying the impedance change. . The strain array layer 130 is as shown in FIG. The strain gauge labeled 1 in the figure is a horizontal strain gauge having a horizontal meandering line for amplifying the deformation in the horizontal direction; the strain gauge labeled 2 in the figure is a vertical strain gauge having a vertical meandering line for The deformation in the vertical direction is enlarged; the strain gauge labeled 3 in the figure is a 45-degree directional strain gauge having a 45-degree meandering line for amplifying the deformation in the 45-degree direction.
应变阵列层130中应变片的蛇行线路可在外界力的作用下产生机械变形，发生阻抗变化，贴装在顶层或者底层导电层110上的电子器件对蛇行线路的阻抗变化值进行采集，进而确定PCB整板的应力。在本发明实施例中，贴装在顶层或者底层导电层110上的电子器件可直接与应变阵列层130中应变片的蛇行线路进行连接，无需采用引线方式测量，提高了测试方便性和稳定性。The meandering line of the strain gauge in the strain array layer 130 can be mechanically deformed under the action of external force, and an impedance change occurs. The electronic device mounted on the top or bottom conductive layer 110 collects the impedance change value of the meandering line, and then determines The stress of the PCB. In the embodiment of the present invention, the electronic device mounted on the top or bottom conductive layer 110 can be directly connected to the meandering line of the strain gauge layer 130 in the strain array layer 130, without the need for lead measurement, thereby improving test convenience and stability. .
在本发明实施例中，根据PCB板具有的层数，可设置应变阵列层130为1个或2个。例如，当PCB板具有的层数为四层，或者小于四层时，可设置1个应变阵列层130；当PCB板具有的层数大于四层时，如，六层板，8层板时，可设置1个或2个应变阵列层130。当设置为1个时，该应变阵列层130设置在PCB板中靠近顶层，或者靠近底层的相邻绝缘层之间；当设置为2个时，该应变阵列层130设置在PCB板中靠近顶层以及靠近底层的相邻绝缘层之间。In the embodiment of the present invention, the strain array layer 130 may be one or two according to the number of layers of the PCB board. For example, when the PCB board has four layers or less than four layers, one strain array layer 130 may be disposed; when the PCB board has more than four layers, for example, six layers and eight layers One or two strain array layers 130 may be provided. When set to one, the strain array layer 130 is disposed in the PCB board near the top layer or between adjacent insulating layers near the bottom layer; when set to two, the strain array layer 130 is disposed in the PCB board near the top layer And between adjacent insulating layers near the bottom layer.
可以理解的是，当PCB板中设置2个应变阵列层130时，2个应变阵列层可以相互修正，使结果更为准确可靠。It can be understood that when two strain array layers 130 are disposed in the PCB, the two strain array layers can be mutually corrected, so that the result is more accurate and reliable.
在本发明实施例中，PCB板的顶层导电层110和底层导电层110上均贴装或焊接有电子器件，电子器件包括处理器。可以理解的是，导电层110上还可包括其它实现PCB板功能的电子器件，例如，电阻，电容等。In the embodiment of the present invention, electronic devices are mounted or soldered on the top conductive layer 110 and the bottom conductive layer 110 of the PCB, and the electronic device includes a processor. It can be understood that the conductive layer 110 may further include other electronic devices that implement the function of the PCB, such as resistors, capacitors, and the like.
处理器可通过应变阵列层130采集PCB板的应变数据，并将采集的应变数据发送至终端，所述应变数据即为应变阵列层130的阻抗变化值。具体地，处理器可通过应变阵列层130实时测量PCB板中阻抗变化值，并进行存储，将阻抗变化值发送至终端，终端通过专业软件分析PCB板的变形情况。由于应变阵列层130已压合在PCB板内，因此，应变阵列层130的阻抗变化也即是PCB板的实际变形状态。处理器采集的阻抗变化值也即是PCB板的应变数据。The processor may acquire the strain data of the PCB board through the strain array layer 130, and send the collected strain data to the terminal, where the strain data is the impedance change value of the strain array layer 130. Specifically, the processor can measure the impedance change value in the PCB board in real time through the strain array layer 130, store it, and send the impedance change value to the terminal, and the terminal analyzes the deformation of the PCB board through professional software. Since the strain array layer 130 has been pressed into the PCB board, the impedance variation of the strain array layer 130 is also the actual deformation state of the PCB board. The impedance change value collected by the processor is also the strain data of the PCB board.
本发明实施例提供的PCB板，由于将应变阵列层130压合在PCB板内，可以对PCBA的整板应力进行测试，覆盖率高，提高应力测试的有效性；在测试过程中，无需铲除导电层110 上原有的元器件，也无需开辟引线空间，对测试结果影响小；且导电层上的元器件通过SMT技术贴装在导电层110上，简单可靠，无连接线，提高应力测试的准确率。According to the PCB board provided by the embodiment of the present invention, since the strain array layer 130 is pressed into the PCB board, the whole board stress of the PCBA can be tested, the coverage rate is high, and the effectiveness of the stress test is improved; during the test, there is no need to eradicate Conductive layer 110 The original components do not need to open lead space, and have little influence on the test results; and the components on the conductive layer are mounted on the conductive layer 110 by SMT technology, which is simple and reliable, has no connection line, and improves the accuracy of the stress test.
可以理解的是，本发明实施例提供的应变阵列层130还可置于结构件中，以实现对结构件整体应力进行测量。It can be understood that the strain array layer 130 provided by the embodiment of the present invention can also be placed in the structural member to measure the overall stress of the structural member.
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。 The specific embodiments of the present invention have been described in detail with reference to the preferred embodiments of the present invention. All modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims (5)

  1. 一种印刷电路板，所述印刷电路板包括多层导电层以及将所述导电层分开的绝缘层，其特征在于，所述印刷电路板还包括：A printed circuit board comprising a plurality of conductive layers and an insulating layer separating the conductive layers, wherein the printed circuit board further comprises:
    应变阵列层，所述应变阵列层置于相邻绝缘层之间。A strained array layer disposed between adjacent insulating layers.
  2. 根据权利要求1所述的印刷电路板，其特征在于，所述应变阵列层置于相邻绝缘层之间具体为，The printed circuit board according to claim 1, wherein the strain array layer is disposed between adjacent insulating layers, specifically
    所述应变阵列层置于所述印刷电路板中靠近顶层的绝缘层与相邻的绝缘层之间，或者，The strain array layer is disposed between the insulating layer adjacent to the top layer and the adjacent insulating layer in the printed circuit board, or
    所述应变阵列层置于所述印刷电路板中靠近底层的绝缘层与相邻的绝缘层之间。The strain array layer is disposed between the insulating layer adjacent to the bottom layer and the adjacent insulating layer in the printed circuit board.
  3. 根据权利要求1-2任一项所述的印刷电路板，其特征在于，所述应变阵列层具体为半导体介质的线路。The printed circuit board according to any one of claims 1 to 2, wherein the strained array layer is specifically a line of a semiconductor medium.
  4. 根据权利要求3所述的印刷电路板，其特征在于，所述应变阵列层的个数为1个或2个。The printed circuit board according to claim 3, wherein the number of the strain array layers is one or two.
  5. 根据权利要求4所述的印刷电路板，其特征在于，所述应变阵列层与所述导电层上贴装的处理器连接，所述处理器用于通过所述应变阵列层采集所述印刷电路板的应变数据，并将采集的所述应变数据发送至终端。 The printed circuit board according to claim 4, wherein said strain array layer is coupled to a processor mounted on said conductive layer, said processor for collecting said printed circuit board through said strain array layer The strain data is sent to the terminal.
PCT/CN2017/085583 2016-05-30 2017-05-23 Printed circuit board WO2017206769A1 (en)

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