WO2017206769A1 - Carte de circuit imprimé - Google Patents

Carte de circuit imprimé Download PDF

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Publication number
WO2017206769A1
WO2017206769A1 PCT/CN2017/085583 CN2017085583W WO2017206769A1 WO 2017206769 A1 WO2017206769 A1 WO 2017206769A1 CN 2017085583 W CN2017085583 W CN 2017085583W WO 2017206769 A1 WO2017206769 A1 WO 2017206769A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
strain
printed circuit
circuit board
layers
Prior art date
Application number
PCT/CN2017/085583
Other languages
English (en)
Chinese (zh)
Inventor
龚云隆
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2017206769A1 publication Critical patent/WO2017206769A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B7/00—Measuring arrangements characterised by the use of electric or magnetic techniques
    • G01B7/16—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring the deformation in a solid, e.g. by resistance strain gauge
    • G01B7/18—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring the deformation in a solid, e.g. by resistance strain gauge using change in resistance
    • G01B7/20—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring the deformation in a solid, e.g. by resistance strain gauge using change in resistance formed by printed-circuit technique
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L1/00—Measuring force or stress, in general
    • G01L1/20—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress
    • G01L1/22—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress using resistance strain gauges

Definitions

  • the invention relates to the field of circuit boards, in particular to a printed circuit board assembly (PCB) for testing strain on a printed circuit board assembly (PCBA).
  • PCB printed circuit board assembly
  • PCBA printed circuit board assembly
  • the stress failure problem of the PCBA inside the terminal becomes prominent and complicated, and the stress refers specifically to the object.
  • the stress failure specifically means that when the device or PCBA is excessively deformed, the yield limit or fatigue limit of the device or PCBA material is exceeded, thereby causing device or PCBA failure.
  • the stress of the PCBA needs to be tested to achieve quality control of the terminal.
  • the strain gauge is mounted at a local point position on the PCBA to test the stress of the PCBA.
  • the local points are placed on the upper surface or the lower surface of the PCBA.
  • the specific test process is as follows: the strain gauge is placed on the local point position, so that the strain gauge is stretched together with the strain received by the local point, and the metal foil in the strain gauge is elongated or shortened according to the strain.
  • the metal foil is mechanically elongated or shortened, the electrical resistance of the metal foil also changes.
  • the leads of the strain gauges are connected to a dedicated device, and the resistance change of the metal foil is measured in different scenarios, and the strain at the local point position is obtained according to the change in the resistance.
  • the prior art PCBA stress testing scheme still has the following defects: 1) the existing PCBA stress test cannot fully cover the entire board, and the effectiveness of the stress test is reduced; 2) the strain gauge is placed at the local point When the components in the original position on the PCBA are removed and the lead space is opened, the stress test can be realized; and the connection line of the attached strain gauges is easily broken during the test, resulting in a decrease in the accuracy of the test results.
  • This paper describes a printed circuit board to test the overall board stress of PCBA, improving the effectiveness and accuracy of stress testing.
  • embodiments of the present application provide a printed circuit board including a plurality of conductive layers and an insulating layer separating the conductive layers, the plurality of conductive layers being spaced apart from the plurality of insulating layers.
  • the PCB further includes a strained array layer disposed between adjacent insulating layers.
  • the strained array layer is placed between the insulating layer near the top layer and the adjacent insulating layer in the PCB board, or
  • the strain array layer is placed between the insulating layer near the bottom layer and the adjacent insulating layer in the PCB.
  • the multi-layer conductive layer and the multi-layer insulating layer are distributed between the PCB boards.
  • the strain array layer is disposed between adjacent insulating layers in the PCB board, specifically referring to the strain array.
  • the layer replaces the conductive layer between adjacent insulating layers in the PCB.
  • the strain array layer is specifically a line of a semiconductor medium that can undergo an impedance change when mechanical deformation occurs under the action of an external force.
  • the number of strain array layers is one or two.
  • the strain array layer When set to one, the strain array layer is disposed in the PCB board near the top layer or adjacent to the adjacent insulating layer of the bottom layer; when set to two, the strain array layer is disposed in the PCB board near the top layer and near the bottom layer Between adjacent insulation layers.
  • the strained array layer is coupled to a processor mounted on the conductive layer, and the processor is configured to acquire strain data of the PCB through the strained array layer and transmit the collected strain data to the terminal.
  • the strain data is the impedance change value of the strain array layer. Since the strain array layer is pressed into the PCB board, the impedance change of the strain array layer is the actual deformation state of the PCB board.
  • the impedance change value collected by the processor is also the strain data of the PCB board.
  • the solution provided by the invention can test the whole board stress of the PCBA, has high coverage, realizes testing the stress of the PCBA, and improves the effectiveness and accuracy of the stress test.
  • FIG. 1 is a schematic structural diagram of a PCB according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another PCB according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a strain array layer according to an embodiment of the present invention.
  • the structure of the PCB board described in the embodiments of the present invention is for the purpose of more clearly explaining the technical solutions of the embodiments of the present invention, and does not constitute a limitation of the technical solutions provided by the embodiments of the present invention.
  • the technical solution provided by the embodiment of the present invention is applicable to similar technical problems.
  • FIG. 1 is a schematic structural diagram of a PCB board according to an embodiment of the present invention.
  • a multilayer PCB board is taken as an example for description.
  • the PCB board includes a conductive sheet 110, an insulating layer 120, and a strained array layer 130.
  • the PCB board specifically refers to a light board having a conductive layer 110, an insulating layer 120, and a strain array layer 130.
  • the light board specifically refers to a PCB board that is not soldered with electronic components
  • the PCBA specifically refers to Various electronic devices are assembled on the PCB by a surface encapsulation process.
  • the top layer or the bottom layer of the conductive layer 110 is mounted with electronic devices, and the electronic device is mounted on the surface of the top or bottom conductive layer 110 by a surface mount technology (SMT), and the PCB board has many
  • SMT surface mount technology
  • the layer conductive layer 110 is distributed between the plurality of insulating layers 120, and the strain array layer 130 is disposed between the adjacent insulating layers 120, as shown in FIG.
  • the multilayer PCB board is composed of the conductive layer 110 and the insulating layer 120.
  • the conductive layer 110 can be specific It is realized by a copper layer for conducting electricity; the insulating layer is specifically realized by an insulating medium for performing insulation.
  • the strain array layer 130 is placed between the insulating layer 120 near the top layer and the adjacent insulating layer 120 in the PCB board, or the strain array layer 130 is placed in the PCB board adjacent to the insulating layer 120 of the bottom layer and adjacent Between the insulating layers 120, as shown in FIG.
  • the strain array layer 130 is placed adjacent to the PCB board. Between the layers 120, specifically, the conductive layer 110 between the adjacent insulating layers 120 in the PCB board is replaced with the strained array layer 130.
  • the surface conductive layer 110 or the bottom conductive layer 110 is used for mounting or soldering electronic devices to electrically connect the electronic devices to each other.
  • the strain array layer 130 may be specifically a sheet-like structure of a semiconductor medium.
  • the length and width data of the strain array layer 130 are the same as the length and width data of the PCB.
  • the strain array layer 130 is composed of a plurality of strain gauges, wherein each strain gauge has a serpentine line, that is, a plurality of strain gauges have serpentine lines forming a strain array layer 130 for amplifying the impedance change. .
  • the strain array layer 130 is as shown in FIG.
  • the strain gauge labeled 1 in the figure is a horizontal strain gauge having a horizontal meandering line for amplifying the deformation in the horizontal direction;
  • the strain gauge labeled 2 in the figure is a vertical strain gauge having a vertical meandering line for The deformation in the vertical direction is enlarged;
  • the strain gauge labeled 3 in the figure is a 45-degree directional strain gauge having a 45-degree meandering line for amplifying the deformation in the 45-degree direction.
  • the meandering line of the strain gauge in the strain array layer 130 can be mechanically deformed under the action of external force, and an impedance change occurs.
  • the electronic device mounted on the top or bottom conductive layer 110 collects the impedance change value of the meandering line, and then determines The stress of the PCB.
  • the electronic device mounted on the top or bottom conductive layer 110 can be directly connected to the meandering line of the strain gauge layer 130 in the strain array layer 130, without the need for lead measurement, thereby improving test convenience and stability. .
  • the strain array layer 130 may be one or two according to the number of layers of the PCB board. For example, when the PCB board has four layers or less than four layers, one strain array layer 130 may be disposed; when the PCB board has more than four layers, for example, six layers and eight layers One or two strain array layers 130 may be provided. When set to one, the strain array layer 130 is disposed in the PCB board near the top layer or between adjacent insulating layers near the bottom layer; when set to two, the strain array layer 130 is disposed in the PCB board near the top layer And between adjacent insulating layers near the bottom layer.
  • the electronic devices are mounted or soldered on the top conductive layer 110 and the bottom conductive layer 110 of the PCB, and the electronic device includes a processor. It can be understood that the conductive layer 110 may further include other electronic devices that implement the function of the PCB, such as resistors, capacitors, and the like.
  • the processor may acquire the strain data of the PCB board through the strain array layer 130, and send the collected strain data to the terminal, where the strain data is the impedance change value of the strain array layer 130.
  • the processor can measure the impedance change value in the PCB board in real time through the strain array layer 130, store it, and send the impedance change value to the terminal, and the terminal analyzes the deformation of the PCB board through professional software. Since the strain array layer 130 has been pressed into the PCB board, the impedance variation of the strain array layer 130 is also the actual deformation state of the PCB board.
  • the impedance change value collected by the processor is also the strain data of the PCB board.
  • the strain array layer 130 is pressed into the PCB board, the whole board stress of the PCBA can be tested, the coverage rate is high, and the effectiveness of the stress test is improved; during the test, there is no need to eradicate Conductive layer 110
  • the original components do not need to open lead space, and have little influence on the test results; and the components on the conductive layer are mounted on the conductive layer 110 by SMT technology, which is simple and reliable, has no connection line, and improves the accuracy of the stress test.
  • strain array layer 130 provided by the embodiment of the present invention can also be placed in the structural member to measure the overall stress of the structural member.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

La présente invention concerne une carte de circuit imprimé (PCB) qui permet d'essayer la résistance d'un ensemble carte de circuit imprimé et qui comprend : une pluralité de couches conductrices de l'électricité (110); des couches isolantes (120) séparant les couches conductrices de l'électricité (110); une couche de matrice de résistance (130) disposée entre les couches isolantes (120). L'invention permet d'effectuer un essai de résistance sur l'ensemble d'une carte de circuit imprimé (PCB) et présente un taux de couverture élevé, permettant ainsi d'effectuer un essai de résistance sur l'ensemble d'une carte de circuit imprimé (PCB), et d'augmenter la validité et la précision de l'essai de résistance.
PCT/CN2017/085583 2016-05-30 2017-05-23 Carte de circuit imprimé WO2017206769A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610375181.5A CN107449349A (zh) 2016-05-30 2016-05-30 印刷电路板
CN201610375181.5 2016-05-30

Publications (1)

Publication Number Publication Date
WO2017206769A1 true WO2017206769A1 (fr) 2017-12-07

Family

ID=60479644

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/085583 WO2017206769A1 (fr) 2016-05-30 2017-05-23 Carte de circuit imprimé

Country Status (2)

Country Link
CN (1) CN107449349A (fr)
WO (1) WO2017206769A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11541901B2 (en) 2019-10-25 2023-01-03 Faurecia Interior Systems, Inc. Opening switch for a vehicle

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112179310A (zh) * 2019-07-02 2021-01-05 中兴通讯股份有限公司 印制电路板pcb的处理方法及装置
CN112188759B (zh) * 2020-09-22 2021-11-16 江南大学 一种应变片阵列电路的直书写打印方法
CN114441943B (zh) * 2022-01-28 2024-01-30 苏州浪潮智能科技有限公司 应变检测方法、装置、计算机设备及存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09125264A (ja) * 1995-11-02 1997-05-13 Nippon Soken Inc 抵抗体膜と配線膜の接続方法
JP2000340916A (ja) * 1999-05-27 2000-12-08 Ricoh Co Ltd プリント配線板
JP2001015882A (ja) * 1999-07-02 2001-01-19 Nec Corp 歪みゲージ内蔵回路基板およびその製造方法
CN1930929A (zh) * 2004-01-16 2007-03-14 揖斐电株式会社 多层印刷电路板和印刷电路板用测试体

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201266074Y (zh) * 2008-08-07 2009-07-01 和硕联合科技股份有限公司 应变感应模块

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09125264A (ja) * 1995-11-02 1997-05-13 Nippon Soken Inc 抵抗体膜と配線膜の接続方法
JP2000340916A (ja) * 1999-05-27 2000-12-08 Ricoh Co Ltd プリント配線板
JP2001015882A (ja) * 1999-07-02 2001-01-19 Nec Corp 歪みゲージ内蔵回路基板およびその製造方法
CN1930929A (zh) * 2004-01-16 2007-03-14 揖斐电株式会社 多层印刷电路板和印刷电路板用测试体

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11541901B2 (en) 2019-10-25 2023-01-03 Faurecia Interior Systems, Inc. Opening switch for a vehicle

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Publication number Publication date
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