WO2017202304A1 - 一种开关机电路 - Google Patents

一种开关机电路 Download PDF

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Publication number
WO2017202304A1
WO2017202304A1 PCT/CN2017/085533 CN2017085533W WO2017202304A1 WO 2017202304 A1 WO2017202304 A1 WO 2017202304A1 CN 2017085533 W CN2017085533 W CN 2017085533W WO 2017202304 A1 WO2017202304 A1 WO 2017202304A1
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WIPO (PCT)
Prior art keywords
switch
cpu
circuit
voltage
pmos transistor
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PCT/CN2017/085533
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English (en)
French (fr)
Inventor
黄林智
代东飞
汪绪茂
朱警怡
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中兴通讯股份有限公司
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Publication of WO2017202304A1 publication Critical patent/WO2017202304A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the invention relates to the field of communication and computer, in particular to a switch circuit.
  • the soft shutdown/soft boot is mainly achieved by adding a switch to the control loop of the terminal.
  • the first long press of the switch enables the main loop to be powered on, the CPU starts after the boot, the terminal runs, and the terminal runs.
  • the input/output (GPIO) is constantly monitored to monitor the switch change; the second touch of the switch causes the control loop to jump, triggering a software-software soft shutdown of the CPU.
  • the above soft-boot/soft-shutdown method is insufficient in that it can be self-locked after the CPU is started, and the button of the corresponding switch can be released.
  • the boot requires a long press of about 1 second, long press time is not easy for the user to grasp, the user experience is poor, and can not be touched.
  • an embodiment of the present invention provides a switch circuit.
  • an embodiment of the present invention provides a switch circuit including: a PMOS transistor, a switch, a triode, and an RC parallel circuit;
  • the source of the PMOS tube is connected to an external power input end, and the drain is used as an internal power input end, and the internal power input end provides a high level for the pre-powering interface of the CPU after voltage conversion;
  • the switch is connected to a source of the PMOS transistor and the external power input end;
  • a base of the triode is connected to a pre-powering interface of the CPU and the RC parallel circuit, a collector is connected to the gate of the PMOS transistor, and the emitter is grounded;
  • the RC parallel circuit connects the base of the triode to a pre-powered interface of the CPU.
  • the RC parallel circuit includes at least: a first capacitor and a first resistor, the first capacitor is connected in parallel with the first resistor, and one end of the parallel connection is connected to a base of the transistor and a pre-powering interface of the CPU The other end is grounded.
  • the first capacitor has a value of 0.01 uF to 22 uF.
  • At least one voltage dividing resistor is further connected in series between the base of the triode and the RC parallel circuit, and at least one voltage dividing resistor is further connected in series between the RC parallel circuit and the pre-powering interface of the CPU.
  • a second capacitor is further connected in parallel between the source and the gate of the PMOS transistor, and the second capacitor is connected in series between the external power input terminal and the switch.
  • At least two voltage dividing resistors are further connected in series between the external power input terminal and the switch, one of the two voltage dividing resistors is connected in parallel with the second capacitor, and the other is opposite to the second capacitor In series.
  • At least one voltage dividing resistor is further connected in series between the gate of the PMOS transistor and the collector of the transistor.
  • the switch is a single-pole single-throw reset switch, one end is connected to the gate of the PMOS tube, and the other ends are grounded.
  • the end of the switch connected to the source of the PMOS transistor is further connected to a jump voltage input terminal, and the jump voltage input terminal provides a transition from a high level to a low level when the switch is turned on.
  • the CPU causes the CPU to initiate a shutdown mechanism.
  • At least one voltage dividing resistor is further connected in series between the switch and the jump voltage input terminal.
  • the switch circuit provided by the embodiment of the invention includes: a PMOS transistor, a switch, a triode, and an RC parallel circuit; wherein the source of the PMOS transistor is connected to an external power input terminal, and the drain is used as an internal power input terminal, and the internal power input is The terminal is pre-powered by the CPU after voltage conversion.
  • the interface is provided with a high level; the switch is connected to the source of the PMOS transistor and the external power input terminal; the base of the transistor is connected to the pre-powering interface of the CPU and the RC parallel circuit, and the collector is connected a gate of the PMOS transistor, an emitter grounded; the RC parallel circuit connecting a base of the transistor and a pre-powering interface of the CPU.
  • the predetermined function of the booting can be perfectly realized by the self-locking switch part of the pre-power-on voltage.
  • the circuit has the advantages of simple structure and low cost, and realizes a hard-touching on the premise of retaining the soft-shutdown function, and realizes the soft shutdown and the soft shutdown.
  • Hard boot suitable for terminal devices such as set-top boxes, can be booted without a long press, improving the user experience.
  • FIG. 1 is a schematic structural diagram of a circuit of a switch machine according to an embodiment of the present invention
  • FIG. 2 is a schematic topological diagram of voltage conversion according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of internal connection of a CPU according to an embodiment of the present invention.
  • the switch circuit provided by the embodiment of the present invention may include: a PMOS transistor VT2.
  • Switch S1 triode VT3, RC parallel circuit.
  • the 2 pin of the PMOS transistor VT2 is the source
  • the 3 pin is the drain
  • the 1 pin is the gate
  • the 1 pin of the triode VT3 is the base
  • the 2 pin is the emitter
  • the 3 pin is the emitter.
  • the source of the PMOS transistor VT2 is connected to the external power input terminal 12VIN, and the drain is used as the internal power input terminal AO_12V.
  • the internal power input terminal AO_12V provides a high level AO_3.3V for the pre-powered interface of the CPU after voltage conversion.
  • the switch S1 is connected to the source of the PMOS transistor VT2 and the external power input terminal 12VIN; the base of the transistor VT3 is connected to the pre-powering interface POWER_CTRL of the CPU and the RC parallel circuit, and the collector is connected.
  • the gate of the PMOS transistor VT2 is connected to the emitter; the RC parallel circuit connects the base of the transistor and the pre-powering interface POWER_CTRL of the CPU.
  • the RC parallel circuit may include a resistor R49 and a capacitor C137, and the resistor R49 and the capacitor C137 are connected in parallel.
  • the RC parallel circuit is grounded at one end, and the other end is connected to the base of the transistor VT3 and the pre-powered interface POWER_CTRL of the CPU.
  • the RC parallel circuit may also include a plurality of resistors and capacitors, and the specific implementation form may be directly considered based on related technologies, and will not be described again.
  • the source of the PMOS transistor VT2 is connected to the external power input terminal 12VIN.
  • the external power input terminal 12VIN is represented by the socket X1, and the three pins 1/2/3 of the socket X1 are connected with the VT2 of the VT2. Pin, 2 pin and 3 pin ground (GND).
  • the external power input can also be implemented by other types of ports, and will not be described again.
  • the external power supply provides an input voltage of 12V through the external power supply input.
  • the drain of the PMOS transistor VT2 is used to supply the input voltage AO_12V of the external power source to the inside of the terminal, that is, it can be used as an internal power input terminal, and the voltage of the internal power input terminal is also 12V.
  • the internal power input is voltage-converted to provide a high level (3.3V) to the CPU's pre-power-on interface POWER_CTRL.
  • the drain of the PMOS transistor VT2 can be connected to the pre-power-on interface POWER_CTRL of the CPU through one or several conversion circuits DC-DC, and the high-voltage interface of the CPU is provided with a high level for the pre-power-on interface POWER_CTRL of the CPU. . As shown in FIG.
  • the drain of the PMOS transistor is also connected with a capacitor C18.
  • One end of the capacitor C18 is connected to the drain of the PMOS transistor, and the other end is grounded to protect the circuit.
  • the switching circuit DC-DC converts the input voltage AO_12V into a high level voltage AO_3.3V suitable for the pre-powering interface POWER_CTRL of the CPU.
  • the gate of the PMOS transistor VT2 is connected to the collector of the transistor VT3. As shown in FIG. 1, in the embodiment of the present invention, the gate of the PMOS transistor VT2 is connected to the collector of the transistor VT3 through two resistors (R5 and R6), and the resistors R5 and R6 function as a voltage divider.
  • the resistor R5 is connected between the gate of the PMOS transistor VT2 and the point B of FIG. 1, and the resistor R6 is connected between the point B and the collector of the transistor VT3.
  • the emitter of the transistor VT3 is grounded, and the base is connected to the pre-powering interface POWER_CTRL of the CPU.
  • the base of the transistor VT3 is connected to the pre-powering interface POWER_CTRL of the CPU through two resistors (R45 and R117).
  • R45 is connected between the base of the transistor VT3 and the non-ground terminal of the RC parallel circuit
  • the R117 is connected between the non-ground terminal of the RC parallel circuit and the pre-powered interface POWER_CTRL of the CPU, and the resistors R45 and R117 are both divided. Pressure effect.
  • the voltage difference between the base and the emitter of the transistor VT3 can reach its turn-on voltage by the voltage division of the two resistors (R45 and R117);
  • the voltage division of the two resistors (R45 and R117) can ensure that the base voltage of the triode VT3 is lower than its turn-on voltage, avoiding the situation of restarting.
  • the switch S1 is a single-pole single-throw switch, 2/3/4 feet are grounded, and the 1 pin is respectively connected to the power input terminal 12VIN and the CPU's trip voltage input interface POWER_DET.
  • a resistor R4, a resistor R119, and a diode VD2 are connected between the power supply input terminal 12VIN and the switch S1.
  • the resistor R4 and the resistor R119 function as a voltage divider
  • the diode VD2 power input terminal 12VIN is unidirectionally connected to the switch S1 (the point A to the point C between the point B and the S1 in FIG. 1).
  • the values of R4 and R119 can be obtained according to the MOS tube specifications to produce a stable partial pressure.
  • a diode VD1 and a resistor R44 are connected between the switch S1 and the transition voltage input interface POWER_DET.
  • the resistor R44 acts as a voltage divider.
  • the diode VD1 causes the trip voltage input interface POWER_DET to be unidirectionally connected to the switch S1. (In Figure 1 A point from point A to point C between POWER_DET and S1).
  • a capacitor is further connected in parallel between the source and the gate of the PMOS transistor VT2, and the charging process of the capacitor is a process of establishing a voltage between the source and the gate of the PMOS transistor VT2.
  • the source of the PMOS transistor VT2 is saturated with the gate, the source of the PMOS transistor VT2 is connected to the drain, and the drain will have a voltage of 12V.
  • a capacitor C10 is connected in parallel between the source and the B point of the PMOS transistor VT2, and the gate of the PMOS transistor VT2 is connected to the point B through the resistor R5, which is equivalent to the capacitor C10 connected in parallel with the source and gate of the PMOS transistor VT2.
  • the capacitor C10 is connected in parallel with the resistor R4, and the charging process of the capacitor C10 is a process of establishing a voltage between the source and the gate of the PMOS transistor VT2.
  • the external power supply 12VIN coming in from the socket X1 passes through the drain and source of the PMOS transistor VT2 to become AO_12V, and is sent to the input end of each conversion circuit DC-DC, and is connected to the pre-powering interface of the CPU after the conversion circuit DC-DC.
  • POWER_CTRL which is the main loop of the switch circuit of the embodiment of the present invention.
  • the main circuit is controlled by a control loop.
  • the control loop of the switch circuit of the embodiment of the present invention mainly includes a switch S1 and a triode VT3, and the control loop is connected to the gate of the PMOS transistor VT2.
  • the PMOS transistor VT2 is an important device. When there is no voltage difference between the drain and the gate of the PMOS transistor VT2, the VT2 does not open and the main loop does not pass. When there is a voltage difference between the drain and the gate of the PMOS transistor VT2, VT2 starts to open, and when the voltage difference between the drain and the gate of the PMOS transistor VT2 reaches the conduction voltage difference of the PMOS transistor, the PMOS transistor VT2 is saturated and turned on. When the source and the drain of the PMOS transistor VT2 are turned on, the main loop is turned on.
  • the switch S1 in the embodiment of the present invention is preferably a 50 mA, 12 DC single-pole single-throw reset tact switch.
  • a 50 mA, 12 DC single pole single throw black round handle resets the tact switch.
  • the pins 1 and 2 of the switch S1 can be connected. After the ms time, the pins 1 and 2 of the switch S1 will be automatically disconnected.
  • the power cable is plugged into the power socket X1.
  • the switch S1 is not pressed, the VT2 is not turned on.
  • the main circuit of the switch circuit shown in Figure 1 is unreachable, and the CPU is not powered and does not work.
  • the power input terminals 12VIN, C10, R119, VD2, and S1 form a loop to the ground.
  • the C10 is charged, and the process of establishing the voltage of the C10 is VT2.
  • the voltage is synchronously established on R4, and the power input terminals 12VIN, R4, R119, VD2, and S1 form a loop.
  • the C10 charging is completed, and the loop composed of the power input terminals 12VIN, C10, R119, VD2, and S1 is disconnected, and the loops composed of the power input terminals 12VIN, R4, R119, VD2, and S1 are generated on the R4 and R119.
  • a stable partial voltage after the voltage is divided, the voltage between the source (2 feet) and the gate (1 pin) of the PMOS transistor VT2 reaches a voltage at which the VT2 is saturated.
  • the saturation voltage of the PMOS transistor VT2 is generally between 2.2V and 10V.
  • point B in FIG. 1 is about 8V to ground.
  • the voltage, that is, the 1 pin of the PMOS transistor VT2, that is, the voltage on the gate is 8V, and at this time, the voltage of the PMOS transistor VT2 has 12V on the 2 pin.
  • the source 2 pin and the gate 1 of the PMOS transistor VT2 A voltage difference of 4V is formed between them, so that VT2 is saturated and turned on, the source and drain of VT2 are connected, and the drain of VT2 (3 legs) has a voltage of 12V, so that the main loop is open and the drain of VT2 is leaked.
  • the pole will supply 12V to the conversion loop DC-DC.
  • the input terminal AO_12V of the conversion circuit DC-DC has a voltage of 12V
  • the AO_3.3V at its output terminal can have a voltage of 3.3V
  • the pre-power is supplied to the CPU.
  • Interface POWER_CTRL is supplied to the CPU.
  • AO_3.3V from the output of the conversion loop DC-DC is connected to the pre-power-on interface POWER_CTRL through a pull-up resistor R.
  • the pre-power-on interface POWER_CTRL is connected to the CPU's enable interface ENABLE and the CPU's control interface CPU_CTRL.
  • the base (1 pin) of the transistor VT3 establishes a bias voltage, and VT3 turns on.
  • the power input terminals 12VIN, R4, R6, VT3 form a loop to ground.
  • the voltage division of the resistors R4 and R6 maintains a required voltage difference between the source and the gate of the PMOS transistor VT2.
  • the switch S1 is turned off, the PMOS transistor VT2 is still in a saturated conduction state, the drain of the PMOS transistor VT2 still provides 12V voltage to the conversion loop DC-DC, and the conversion loop DC-DC provides a stable 3.3V voltage.
  • the pre-powered interface POWER_CTRL of the CPU in this way, can be self-locked in the ms-level time after the switch S1 is manually pressed, giving the user a perfect feeling of one touch.
  • CPU_CTRL pulls up the pull-up to implement CPU control of this pin.
  • CPU_CTRL is the GPIO port of the CPU, which can realize the pull-down control. In this embodiment, pulling to 3.3V through a small internal resistance is the control during normal operation.
  • the pin can be connected to the ground, and the level of the pin is low, thereby controlling the shutdown.
  • the shutdown process of the power-on and switch circuit shown in Figure 1 is as follows: When the power is turned off, the toggle switch S1 is pressed, and the jump voltage input terminal POWER_DET connected to the CPU terminal IO port provides a high level from 3.3V to a low level. The jump, after the CPU detects this jump, it will start the shutdown mechanism. First, the CPU turns off all levels of application, especially the hard disk-related read and write operations, and starts the power-down process of the conversion loop DC-DC after confirming that the hard disk is no longer working, and converts the loop DC-DC to the CPU's pre-power-on interface.
  • POWER_CTRL sends a low level, which in turn lowers the base (1 pin) voltage of the transistor VT3, turns off VT3, there is no voltage drop between the source and the gate of the PMOS transistor VT2, the PMOS transistor VT2 is not turned on, and the PMOS transistor VT2
  • the drain and source are turned off, after the VT2 is turned off, the drain of the PMOS transistor VT2 stops supplying 12V voltage to the conversion loop DC-DC, the conversion loop DC-DC is also turned off, and the output of the conversion loop DC-DC is also The power will be cut off and the pre-powered interface POWER_CTRL of the CPU is powered off.
  • the base voltage of the triode VT2 is much lower than 0.7V, even if the CPU can not maintain the POWER_CTRL low level during the power-down process, the base voltage of the triode VT2 will be kept far. Below 0.7V, to avoid the phenomenon of power-on restart, stable shutdown.
  • an RC parallel circuit is used at the pre-power-on interface POWER_CTRL of the CPU, and the RC parallel circuit is a key component of the switch circuit of the embodiment of the present invention.
  • the selection of the capacitor C137 is very important. Because the hard boot time is very fast, if there is no such capacitor or the capacitor is too small, it will cause a restart after the soft shutdown. If the capacitor is too large, it may not be hard to boot. Because the capacitor is an unstable device and easy to age, its usable range will directly affect the normal operation of the switch circuit.
  • a resistor R49 is connected in parallel across the capacitor C137 to form an RC parallel circuit.
  • the value should match the internal pull-up resistor of the CPU (such as the resistor R shown in Figure 3).
  • the pull-up resistor of a CPU is 68K.
  • the resistor R49 is preferably 27K.
  • the capacitor C127 can be selected from 0.01uF to 22uF. In the actual circuit, the capacitor C127 is selected to be 4.7uF to ensure stable and reliable operation of the soft start circuit.
  • the switch circuit of the embodiment of the invention simultaneously implements a soft shutdown and a hard boot, and can be used for a similar terminal device such as a set top box.
  • the switch circuit provided by the embodiment of the invention includes: a PMOS transistor, a switch, a triode, and an RC parallel circuit; wherein the source of the PMOS transistor is connected to an external power input terminal, and the drain is used as an internal power input terminal, and the internal power input is Providing a high level for the pre-power-on interface of the CPU after voltage conversion; the switch is connected to the source of the PMOS tube and the external power input end; the base of the triode is connected to the pre-powered of the CPU An interface and the RC parallel circuit, a collector connected to a gate of the PMOS transistor, and an emitter grounded; the RC parallel circuit connecting a base of the transistor and a pre-powering interface of the CPU.
  • the predetermined function of the booting can be perfectly realized by the self-locking switch part of the pre-power-on voltage.
  • the circuit has the advantages of simple structure and low cost, and realizes a hard-touching on the premise of retaining the soft-shutdown function, and realizes the soft shutdown and the soft shutdown.
  • Hard boot suitable for terminal devices such as set-top boxes, you can boot without long press.

Abstract

一种开关机电路，包括：PMOS管、开关、三极管、RC并联电路；其中，所述PMOS管的源极连接外部电源输入端，漏极作为内部电源输入端，该内部电源输入端通过转换回路连接CPU的预上电接口，所述转换回路将内部电源输入端的电压转换为所述CPU的预上电接口的高电平电压；所述开关连接所述PMOS管的源极和所述外部电源输入端；所述三极管的基极连接所述CPU的预上电接口和所述RC并联电路，集电极连接所述PMOS管的栅极，发射极接地。完美实现了开机的预定功能，在保留软关机功能的前提下，实现了一触硬开机，适用于机顶盒等终端设备。

Description

一种开关机电路 技术领域
本发明涉及通讯与计算机领域，尤指一种开关机电路。
背景技术
目前，很多终端都采用软关机/软开机的方式关机/开机。这样，一方面能够保护终端的某些内部器件，另一方面还能在不使用时使得终端完全彻底断电。目前，软关机/软开机主要通过如下方式实现：在终端的控制回路加入一个开关，该开关的第一次长按能让主回路上电开机，开机后CPU启动，终端运行，在终端运行过程中一直监测输入/输出(GPIO)，以监测开关变化；该开关的第二次碰触，引起控制回路跳变，从而触发CPU的软件保护性软关机。上述软开机/软关机的方法，不足在于需要等CPU启动后能自锁，才能松开相应开关的按键。一般来说，开机需要长按1秒左右，长按时间对于用户来说不好把握，用户体验差，而且不能做到一触开机。
在软关机的基础上，对于终端的一触快速开机，目前还未提出有效的解决方案。
发明内容
为了解决上述技术问题，本发明实施例提供了一种开关机电路。
为了达到本发明实施例目的，本发明实施例提供了一种开关机电路，包括：PMOS管、开关、三极管、RC并联电路；其中，
所述PMOS管的源极连接外部电源输入端，漏极作为内部电源输入端，该内部电源输入端经过电压转换后为CPU的预上电接口提供高电平；
所述开关连接所述PMOS管的源极和所述外部电源输入端；
所述三极管的基极连接所述CPU的预上电接口和所述RC并联电路， 集电极连接所述PMOS管的栅极，发射极接地；
所述RC并联电路连接所述三极管的基极和所述CPU的预上电接口。
其中，所述RC并联电路至少包括：第一电容和第一电阻，所述第一电容与第一电阻并联，所述并联的一端连接所述三极管的基极和所述CPU的预上电接口，另一端接地。
其中，所述第一电容的取值为0.01uF到22uF。
其中，所述三极管的基极与所述RC并联电路之间还串联有至少一个分压电阻，所述RC并联电路与所述CPU的预上电接口之间还串联有至少一个分压电阻。
其中，所述PMOS管的源极与栅极之间还并联有第二电容，所述第二电容串联在所述外部电源输入端和所述开关之间。
其中，在所述外部电源输入端与所述开关之间还串联有至少两个分压电阻，所述两个分压电阻中一个与所述第二电容并联，另一个与所述第二电容串联。
其中，所述PMOS管的栅极与所述三极管的集电极之间还串联有至少一个分压电阻。
其中，所述开关为单刀单掷复位开关，一端连接所述PMOS管的栅极，其他端接地。
其中，所述开关连接所述PMOS管源极的一端还连接跳变电压输入端，所述跳变电压输入端在所述开关接通时提供一个由高电平到低电平的跳变给所述CPU，使得所述CPU启动关机机制。
其中，所述开关与所述跳变电压输入端之间还串联有至少一个分压电阻。
本发明实施例提供的开关机电路，包括：PMOS管、开关、三极管、RC并联电路；其中，所述PMOS管的源极连接外部电源输入端，漏极作为内部电源输入端，该内部电源输入端经过电压转换后为CPU的预上电 接口提供高电平；所述开关连接所述PMOS管的源极和所述外部电源输入端；所述三极管的基极连接所述CPU的预上电接口和所述RC并联电路，集电极连接所述PMOS管的栅极，发射极接地；所述RC并联电路连接所述三极管的基极和所述CPU的预上电接口。如此，能够通过预上电电压自锁开关部分，完美实现开机的预定功能，该电路结构简单，成本低廉，在保留软关机功能的前提下，实现了一触硬开机，同时实现了软关机与硬开机，适用于机顶盒等终端设备，不需要长按即可开机，提升了用户体验。
本发明实施例的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本发明的技术方案，并不构成对本发明技术方案的限制。
图1为本发明实施例开关机电路的结构示意图；
图2为本发明实施例电压转换的拓扑示意图；
图3为本发明实施例CPU内部连接示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，下文中将结合附图对本发明的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行。并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
如图1所示，本发明实施例提供的开关机电路可包括：PMOS管VT2、 开关S1、三极管VT3、RC并联电路。图1中，PMOS管VT2的2脚为源极，3脚为漏极，1脚为栅极。三极管VT3的1脚为基极，2脚为发射极，3脚为发射极。
其中，所述PMOS管VT2的源极连接外部电源输入端12VIN，漏极作为内部电源输入端AO_12V，该内部电源输入端AO_12V经过电压转换后为CPU的预上电接口提供高电平AO_3.3V；所述开关S1连接所述PMOS管VT2的源极和所述外部电源输入端12VIN；所述三极管VT3的基极连接所述CPU的预上电接口POWER_CTRL和所述RC并联电路，集电极连接所述PMOS管VT2的栅极，发射极接地；所述RC并联电路连接所述三极管的基极和所述CPU的预上电接口POWER_CTRL。
其中，RC并联电路可包括电阻R49和电容C137，电阻R49和电容C137并联。RC并联电路一端接地，另一端连接三极管VT3的基极和CPU的预上电接口POWER_CTRL。实际应用中，RC并联电路还可包含多个电阻和电容，其具体实现形式可基于相关技术直接想到，不再赘述。
其中，PMOS管VT2的源极连接外部电源输入端12VIN，本发明实施例中用插座X1表示该外部电源输入端12VIN，插座X1的三个脚1/2/3中，1脚连接VT2的2脚，2脚和3脚接地(GND)。实际应用中，外部电源输入端也可以通过其他形式的端口实现，不再赘述。本发明实施例中，外部电源通过外部电源输入端提供12V的输入电压。
其中，PMOS管VT2的漏极用来将外部电源的输入电压AO_12V提供到终端内部，即可以作为内部电源输入端，内部电源输入端的电压也为12V。该内部电源输入端经过电压转换后为CPU的预上电接口POWER_CTRL提供高电平(3.3V)。具体的，PMOS管VT2的漏极可通过一个或几个转换电路DC-DC连接CPU的预上电接口POWER_CTRL，由转换电路DC-DC变压之后为CPU的预上电接口POWER_CTRL提供高电平。如图1所示，PMOS管的漏极还连接有电容C18，电容C18一端连接PMOS管的漏极，另一端接地，起到保护电路的作用。如图2所示，转 换电路DC-DC将输入电压AO_12V转换为适合CPU的预上电接口POWER_CTRL的高电平电压AO_3.3V。
其中，PMOS管VT2的栅极连接三极管VT3的集电极。如图1所示，本发明实施例中，PMOS管VT2的栅极通过两个电阻(R5和R6)连接到三极管VT3的集电极，电阻R5和R6起到分压作用。其中，电阻R5连接在PMOS管VT2的栅极和图1的B点之间，电阻R6连接在B点与三极管VT3的集电极之间。
其中，三极管VT3的发射极接地，基极连接CPU的预上电接口POWER_CTRL。如图1所示，本发明实施例中，三极管VT3的基极通过两个电阻(R45和R117)连接到CPU的预上电接口POWER_CTRL。其中，R45连接在三极管VT3的基极与RC并联电路的非接地端之间，R117连接在RC并联电路的非接地端与CPU的预上电接口POWER_CTRL之间，电阻R45和R117均起到分压作用。在CPU的预上电接口POWER_CTRL为高电平3.3V时，通过两个电阻(R45和R117)的分压作用，使得三极管VT3的基极与发射极之间压差能够达到其开启电压；在关机时，即使有残压，通过两个电阻(R45和R117)的分压，也能确保三极管VT3的基极电压低于其开启电压，避免出现重开机的情况。
其中，开关S1为单刀单掷开关，2/3/4脚均接地，1脚分别连接电源输入端12VIN和CPU的跳变电压输入接口POWER_DET。如图1所示，在电源输入端12VIN与开关S1之间连接有电阻R4、电阻R119和二极管VD2。其中，电阻R4和电阻R119起到分压作用，二极管VD2电源输入端12VIN到开关S1单向导通(图1中B点和S1之间的A点到C点单向导通)。实际应用中，可以根据MOS管规格得到R4和R119的值，使其产生稳定的分压。
如图1所示，开关S1和跳变电压输入接口POWER_DET之间还连接有二极管VD1和电阻R44，电阻R44起到分压的作用，二极管VD1使得跳变电压输入接口POWER_DET到开关S1单向导通(图1中 POWER_DET和S1之间的A点到C点单向导通)。
本发明实施例中，在PMOS管VT2的源极与栅极之间还并联有电容，该电容的充电过程即为PMOS管VT2的源极与栅极之间建立电压的过程，一旦其两端电压达到导通阈值，那么PMOS管VT2的源极与栅极饱和导通，PMOS管VT2的源极与漏极相通，漏极上将会有12V的电压。如图1所示，PMOS管VT2的源极与B点之间并联有电容C10，PMOS管VT2的栅极通过电阻R5接到B点，相当于电容C10并联在PMOS管VT2的源极与栅极之间，电容C10与电阻R4并联，电容C10的充电过程即为PMOS管VT2的源极和栅极之间建立电压的过程。
其中，从插座X1进来的外部电源12VIN经过PMOS管VT2的漏极、源极成为AO_12V，送往各个转换回路DC-DC的输入端，经过转换回路DC-DC后接到CPU的预上电接口POWER_CTRL，这是本发明实施例开关机电路的主回路。主回路由控制回路控制，如图1所示，本发明实施例开关机电路的控制回路主要包括开关S1和三极管VT3，控制回路连接到PMOS管VT2的栅极。
其中，PMOS管VT2是个重要器件，PMOS管VT2的漏极和栅极没有压差时，VT2不打开，主回路不通。当PMOS管VT2的漏极和栅极间有电压差时，VT2开始打开，在PMOS管VT2的漏极和栅极间的电压差达到PMOS管的导通压差时，PMOS管VT2饱和导通，PMOS管VT2的源极与漏极间导通，则主回路导通。
需说明的是，本发明实施例中的开关S1优选为50mA、12DC的单刀单掷复位轻触开关。例如，可为50mA、12DC的单刀单掷黑色圆柄复位轻触开关。轻触开关S1，即可将开关S1的1、2脚连接，ms级时间后开关S1的1、2脚将自动断开。电源线插入电源插座X1，没有按下开关S1时，VT2不导通，图1所示的开关机电路的主回路不通，CPU没有上电不工作。
图1所示的开关机电路的开机流程如下：
当电源线插入电源插座X1，按下开关S1的瞬间，电源输入端12VIN、C10、R119、VD2、S1到地组成一个回路，此时，为C10充电，C10充电建立电压的过程即为VT2的栅极和源极间建立电压的过程。同时，R4上同步建立电压，电源输入端12VIN、R4、R119、VD2、S1组成一个回路。ms级时间后C10充电完成，电源输入端12VIN、C10、R119、VD2、S1到地组成的回路断开，电源输入端12VIN、R4、R119、VD2、S1组成的回路中R4和R119上会产生稳定的分压，分压后在PMOS管VT2的源极(2脚)和栅极(1脚)之间电压达到使VT2饱和导通的电压。本例中，PMOS管VT2的饱和电压一般为2.2V到10V之间，本实施例中，通过为C10充电，以及R4和R119的分压作用，使得图1中B点对地约有8V的电压，即PMOS管VT2的1脚即栅极上会有8V的电压，而此时PMOS管VT2的2脚上有12V的电压，如此，在PMOS管VT2的源极2脚与栅极1脚之间形成了4V的压差，使得VT2饱和导通，VT2的源极和漏极相通，VT2的漏极(3脚)上也就有了12V的电压，这样，主回路通，VT2的漏极会向转换回路DC-DC提供12V的电压。
主回路通了以后，如图2所示，转换回路DC-DC的输入端AO_12V有了12V的电压，那么在其输出端AO_3.3V即可有3.3V的电压，提供给CPU的预上电接口POWER_CTRL。
如图3所示，在CPU内部，来自转换回路DC-DC的输出端的AO_3.3V通过一个上拉电阻R接到了预上电接口POWER_CTRL。在CPU内部，预上电接口POWER_CTRL连接CPU的使能接口ENABLE和CPU的控制接口CPU_CTRL。
如图1所示，转换回路DC-DC的输出端向POWER_CTRL提供3.3V的电压之后，三极管VT3的基极(1脚)建立偏置电压，VT3导通。电源输入端12VIN、R4、R6、VT3到地形成回路，此时，电阻R4和R6的分压使得PMOS管VT2的源极和栅极之间保持需要的压差。此时，开关S1断开，PMOS管VT2仍然处于饱和导通状态，PMOS管VT2漏极仍提供12V电压给转换回路DC-DC，转换回路DC-DC提供稳定的3.3V电压给 CPU的预上电接口POWER_CTRL，如此，在人为按下开关S1后ms级时间里就能完成自锁，给用户一触开机的完美感受。
另外，在CPU程序完全起来后，CPU_CTRL拉起上拉，实现CPU对这个管脚的控制。其中，CPU_CTRL是CPU的GPIO口，可以实现拉高拉低控制。本实施例中，通过一个小内阻拉到3.3V，就是正常工作时的控制，等到CPU要关机时可把这个管脚接到地，这个管脚电平即为低，从而控制关机。
图1所示的开关机电路的关机流程如下：关机时，按下轻触开关S1，与CPU端IO口相连的跳变电压输入端POWER_DET会提供一个由高电平3.3V到低电平0的跳变，CPU检测到这个跳变后，会启动关机机制。首先，CPU关掉各级应用，尤其是关掉硬盘相关的读写操作，在确认硬盘不再工作后启动转换回路DC-DC的下电流程，转换回路DC-DC给CPU的预上电接口POWER_CTRL送出低电平，进而拉低三极管VT3的基极(1脚)电压，关断VT3，PMOS管VT2的源极和栅极之间无压降，PMOS管VT2不导通，PMOS管VT2的漏极和源极间关断，VT2关断后，，PMOS管VT2的漏极停止提供12V电压给转换回路DC-DC，转换回路DC-DC也会关闭，转换回路DC-DC的输出端也会断电，CPU的预上电接口POWER_CTRL断电。虽然会有残压，但因为R49的分压，使得三极管VT2的基极电压远低于0.7V，即使CPU在掉电过程中不能维持送出POWER_CTRL低电平也会保持三极管VT2的基极电压远低于0.7V，从而避免出现上电重启的现象，能稳定关机。
需要说明的是，本发明实施例在CPU的预上电接口POWER_CTRL处使用了一个RC并联电路，该RC并联电路是本发明实施例开关机电路的关键器件。其中，电容C137的选值很重要。因为硬开机的时间非常之快，如果没有这个电容或者电容太小，在软关机后会引起重启。此电容如果数值太大，又可能会做不到硬开机。又因为电容是个不稳定器件又容易老化，其可用范围将直接影响开关机电路的正常工作。本发明实施例中，在电容C137两端并联一个电阻R49，形成RC并联电路。电阻R49的数 值要配合CPU内部上拉电阻(如图3所示的电阻R)，比如某CPU的上拉电阻是68K，为使分压后的电压能超过三极管VT3的开启电压，电阻R49优选为27K，使得电容C127的可选范围能从0.01uF到22uF之间。实际电路中，电容C127选为4.7uF，保证软开机电路的稳定可靠运行。
本发明实施例的开关机电路同时实现了软关机和硬开机，可用于机顶盒等类似的终端设备。
虽然本发明所揭露的实施方式如上，但所述的内容仅为便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。
工业实用性
本发明实施例提供的开关机电路，包括：PMOS管、开关、三极管、RC并联电路；其中，所述PMOS管的源极连接外部电源输入端，漏极作为内部电源输入端，该内部电源输入端经过电压转换后为CPU的预上电接口提供高电平；所述开关连接所述PMOS管的源极和所述外部电源输入端；所述三极管的基极连接所述CPU的预上电接口和所述RC并联电路，集电极连接所述PMOS管的栅极，发射极接地；所述RC并联电路连接所述三极管的基极和所述CPU的预上电接口。如此，能够通过预上电电压自锁开关部分，完美实现开机的预定功能，该电路结构简单，成本低廉，在保留软关机功能的前提下，实现了一触硬开机，同时实现了软关机与硬开机，适用于机顶盒等终端设备，不需要长按即可开机。

Claims (10)

  1. 一种开关机电路，包括：PMOS管、开关、三极管、RC并联电路；其中，
    所述PMOS管的源极连接外部电源输入端，漏极作为内部电源输入端，该内部电源输入端经过电压转换后为CPU的预上电接口提供高电平；
    所述开关连接所述PMOS管的源极和所述外部电源输入端；
    所述三极管的基极连接所述CPU的预上电接口和所述RC并联电路，集电极连接所述PMOS管的栅极，发射极接地；
    所述RC并联电路连接所述三极管的基极和所述CPU的预上电接口。
  2. 根据权利要求1所述的开关机电路，其中，所述RC并联电路至少包括：第一电容和第一电阻，所述第一电容与第一电阻并联，所述并联的一端连接所述三极管的基极和所述CPU的预上电接口，另一端接地。
  3. 根据权利要求2所述的开关机电路，其中，所述第一电容的取值为0.01uF到22uF。
  4. 根据权利要求1、2或3所述的开关机电路，其中，所述三极管的基极与所述RC并联电路之间还串联有至少一个分压电阻，所述RC并联电路与所述CPU的预上电接口之间还串联有至少一个分压电阻。
  5. 根据权利要求1所述的开关机电路，其中，所述PMOS管的源极与栅极之间还并联有第二电容，所述第二电容串联在所述外部电源输入端和所述开关之间。
  6. 根据权利要求5所述的开关机电路，其中，在所述外部电源输入端与所述开关之间还串联有至少两个分压电阻，所述两个分压电阻中一个与所述第二电容并联，另一个与所述第二电容串联。
  7. 根据权利要求1或5所述的开关机电路，其中，所述PMOS管的栅极与所述三极管的集电极之间还串联有至少一个分压电阻。
  8. 根据权利要求1所述的开关机电路，其中，所述开关为单刀单掷复位开关，一端连接所述PMOS管的栅极，其他端接地。
  9. 根据权利要求1或8所述的开关机电路，其中，所述开关连接所述PMOS管源极的一端还连接跳变电压输入端，所述跳变电压输入端在所述开关接通时提供一个由高电平到低电平的跳变给所述CPU，使得所述CPU启动关机机制。
  10. 根据权利要求9所述的开关机电路，其中，所述开关与所述跳变电压输入端之间还串联有至少一个分压电阻。
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