WO2017201826A1 - 数模转换器及具有该数模转换器的显示面板 - Google Patents
数模转换器及具有该数模转换器的显示面板 Download PDFInfo
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- WO2017201826A1 WO2017201826A1 PCT/CN2016/089364 CN2016089364W WO2017201826A1 WO 2017201826 A1 WO2017201826 A1 WO 2017201826A1 CN 2016089364 W CN2016089364 W CN 2016089364W WO 2017201826 A1 WO2017201826 A1 WO 2017201826A1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/76—Simultaneous conversion using switching tree
Definitions
- the present invention relates to the field of digital-to-analog conversion technologies, and in particular, to a digital-to-analog converter and a display panel having the same.
- LCD TVs are popular among people because of their small size, light weight and superior display quality. With the development of economic technology, resources are becoming scarcer. Therefore, how to use less resources to design LCD panels with superior display quality has become an urgent problem to be solved today.
- the circuit drive system of the display panel (such as a liquid crystal panel) includes a data control module, a power conversion module, a Gamma voltage drive module, a data drive module, and a scan drive module.
- the cost of data drive module accounts for a large proportion of the cost of the entire circuit drive system.
- the digital-to-analog converter in the data-driven module has a large number of transistors. Referring to Figure 1, in a 5-bit digital-to-analog converter, 5 rows of transistors require 32 transistors per row. The structure is complicated, due to the large number of transistors required, the cost is also Higher.
- the present invention provides a digital-to-analog converter having a simple structure and a display panel having the same.
- the present invention provides a digital-to-analog converter comprising N rows of transistors, the number of transistors in each row being halved in a row relative to the front row, the number of transistors in the N rows of transistors being M, N are natural numbers, N is greater than 1, and M is between 1 and N.
- Each transistor includes a conductive terminal, an input terminal, and an output terminal.
- the number of transistors in the first row is 2 N
- the last row The number of transistors is two, the input end of the first row of transistors is used to connect 2 N voltage signals, and each row of transistors includes half of the first transistor and half of the second transistor, the first transistor and the first The two transistors have opposite conduction levels.
- the input terminals of the first transistor of the rear row and the input terminal of the second transistor of the rear row are respectively connected to the output ends of the first transistors of the front row.
- the output ends of the second transistors of the front row are respectively connected to the output ends of the first transistors of the front row, and the output ends of the second transistors of the rear row are respectively connected to the output ends of the first transistors of the rear row,
- the conductive terminals of a row of transistors are connected to each other for receiving a high level signal or a low level signal representing a digital signal, and the outputs of the two transistors of the last row of transistors are connected to each other for outputting a converted analog signal. .
- the transistor is a field effect transistor
- the conduction end is a gate of the FET
- the input end is a drain of the FET
- the output end is the FET The source.
- the first transistor is an N-channel field effect transistor
- the second transistor is a P-channel field effect transistor
- the transistor is a triode
- the conduction end is a base of the triode
- the input end is a collector of the triode
- the output end is an emitter of the triode.
- a conductive end of the first transistor is used to be turned on when receiving a low level signal
- a conductive end of the second transistor is used to be turned on when receiving a high level signal
- the present invention also provides a display panel comprising the above-described digital to analog converter.
- the display panel is a liquid crystal panel.
- the display panel includes 2 N voltage terminals, and the 2 N voltage terminals are used to output the 2 N different voltage signals.
- the invention has the beneficial effects that the digital-to-analog converter provided by the invention comprises a plurality of rows of transistors, and the rear row of transistors is only half of the number of the front row, and can be completely realized by using fewer transistors during digital-to-analog conversion, and has a simple structure and a simple structure. The cost of the digital to analog converter is greatly reduced.
- FIG. 1 is a connection circuit diagram of a conventional digital-to-analog converter.
- FIG. 2 is a circuit connection diagram of a preferred embodiment of a digital to analog converter of a display panel of the present invention.
- a display panel (not shown) includes a digital-to-analog converter including N rows of transistors, and the number of transistors in each row is halved in a row relative to the front row, the N
- the number of transistors included in the row of transistors is: M and N are natural numbers, N is greater than 1, and M is between 1 and N.
- Each transistor includes a conductive terminal, an input terminal, and an output terminal.
- the number of transistors in the first row is 2N, and the number of transistors in the last row is 2.
- the display panel further includes 2N different voltage output terminals. In the embodiment, the N is 5.
- the voltage terminal is used for outputting 2N different voltage signals (V1, V2, V3, ... V32), and the input terminals of the first row of transistors are used for respectively connecting 2N different voltage signals (V1, V2, V3, ...V32).
- Each row of transistors includes a half of the first transistor 101 and a half of the second transistor 102.
- the first transistor 101 and the second transistor 102 have opposite conduction levels.
- the first transistor The conduction end of 101 is used to be turned on when receiving a low level signal
- the conduction end of the second transistor 102 is used to be turned on when receiving a high level signal.
- an input end of the first transistor 101 in the rear row and an input end of the second transistor 102 in the rear row are respectively connected to the output ends of the first transistors 101 of the front row, the front row
- An output end of the second transistor 102 is respectively connected to an output end of the first transistor 101 of the front row
- an output end of the second transistor 102 of the rear row is respectively connected to an output end of the first transistor 101 of the rear row, each row
- the conductive terminals of the transistors are connected to each other for receiving a high level signal or a low level signal (D0, D1, D2, D3, D4) representing a digital signal, and outputs of the two transistors of the last row of transistors Interconnected for outputting a converted analog signal Vout.
- the transistor is a field effect transistor
- the transistor is a field effect transistor
- the conduction end is a gate of the FET
- the input end is a drain of the FET.
- the output is the source of the FET.
- Vout output is equal to V1. ,. . .
- V32 the signal D3, D1, D2, D3, D4 signal D3 Low level, others high level, Vout equals V24.
- the transistor is a triode
- the conduction end is a base of the triode
- the input end is a collector of the triode
- the output end is an emitter of the triode
- the number of transistors in each row of the digital-to-analog converter in this embodiment is halved by one row in the back row, and the structure is simple, and a plurality of transistors can be saved in the case of converting the same digital signal, thereby making The cost of digital to analog converters is also low.
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- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Analogue/Digital Conversion (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
一种数模转换器,包括N排晶体管,每排晶体管的数量按后排相对前排逐一减半布设,每一晶体管包括一导通端、一输入端及一输出端,第一排晶体管的输入端用于连接多个模拟信号,任意相邻的两排晶体管中,后排的第一晶体管(101)的输入端和后排第二晶体管(102)的输入端分别连接前排的第一晶体管(101)的输出端,前排的第二晶体管(102)的输出端分别连接前排的第一晶体管(101)的输出端,后排的第二晶体管(102)的输出端分别连接后排第一晶体管(101)的输出端,每一排晶体管的导通端均相互连通,最后一排晶体管的两个晶体管的输出端相互连接,上述数模转换器利用较少的晶体管可以实现数模转换,减少了数模转换器的占地,同时大大降低了数模转换器的成本。
Description
本发明涉及数模转换技术领域,尤其涉及一种数模转换器及具有该数模转换器的显示面板。
液晶电视因其体积小,重量轻,显示质量优越而深受人们的喜爱。随着经济技术的发展,资源日益匮乏,因此,怎样使用较少的资源设计显示质量优越的液晶面板成为当今亟待解决的问题。
显示面板(例如液晶面板)的电路驱动系统包括数据控制模块,电源转换模块,Gamma电压驱动模块,数据驱动模块,扫描驱动模块。其中数据驱动模块成本占整个电路驱动系统成本中较大的比例。数据驱动模块中数模转换器由于包含的晶体管数量多,参阅图1,在5位数模转换器中,5排晶体管,每排需要32个晶体管,结构复杂,由于需要的晶体管很多,成本也较高。
发明内容
为克服现有技术的不足,本发明提供一种结构简单的数模转换器及具有该数模转换器的显示面板。
本发明提供一种数模转换器,包括N排晶体管,每排晶体管的数量按后排相对前排逐一减半布设,所述N排晶体管包含的晶体管数量为M、N为自然数,N大于1,M在1至N之间取值,每一晶体管包括一导通端、一输入端及一输出端,第一排晶体管的数量为2N,最后一排晶体管的数量为2,所述第一排晶体管的输入端用于连接2N个电压信号,每一排晶体管包括半数的第一晶体管及半数的第二晶体管,所述第一晶体管和所述第二晶体管的导通电平相反,任意相邻的两排晶体管中,后排的第一晶体管的输入端和后排第二晶体管的输入端分别连接所述前排的第一晶体管的输出端,所述前排的第二晶体管的输出端分别连接所述前排的第一晶体管的输出端,所述后排的第二晶体管的输出端分别连接所述后排第一晶体管的输出端,每一排晶体管的导通端均相互连
通用于接受一代表数字信号的高电平信号或低电平信号,所述最后一排晶体管的两个晶体管的输出端相互连接用于输出一转换模拟信号。
进一步地,所述晶体管为场效应管,所述导通端为所述场效应管的栅极,所述输入端为所述场效应管的漏极,所述输出端为所述场效应管的源极。
进一步地,所述第一晶体管为N沟道场效应管,所述第二晶体管为P沟道场效应管。
进一步地,所述晶体管为三极管,所述导通端为所述三极管的基极,所述输入端为所述三极管的集电极,所述输出端为所述三极管的发射极。
进一步地,所述第一晶体管的导通端用于在接收低电平信号而导通,所述第二晶体管的导通端用于在接收高电平信号而导通
本发明还提供一种显示面板,所述显示面板包括上述的数模转换器。
进一步地,所述显示面板为液晶面板。
进一步地,所述显示面板包括2N个电压端,所述2N个电压端用于输出所述2N个不同的电压信号。
本发明的有益效果:本发明所提供的数模转换器包括多排晶体管,后排晶体管相对前排只有一半的数量,在进行数模转换时可以用较少的晶体管完全实现,结构简单,同时大大降低了数模转换器的成本。
图1为现有的数模转换器的连接电路图。
图2为本发明显示面板的数模转换器较佳实施方式的电路连接图。
下面,将结合附图对本发明各实施例作详细介绍。
请参阅图2,一显示面板(图未示)包括一数模转换器,所述数模转换器包括N排晶体管,每排晶体管的数量按后排相对前排逐一减半布设,所述N排晶
体管包括的晶体管的数量为:M、N为自然数,N大于1,M在1至N之间取值。每一晶体管包括一导通端、一输入端及一输出端,第一排晶体管的数量为2N,最后一排晶体管的数量为2。所述显示面板还包括2N个不同的电压输出端,在本实施例中,所述N为5。所述电压端用于输出2N个不同的电压信号(V1,V2,V3,…V32),所述第一排晶体管的输入端用于分别连接2N个不同的电压信号(V1,V2,V3,…V32)。
每一排晶体管包括半数的第一晶体管101及半数的第二晶体管102,所述第一晶体管101和所述第二晶体管102的导通电平相反,在本实施例中,所述第一晶体管101的导通端用于在接收低电平信号而导通,所述第二晶体管102的导通端用于在接收高电平信号而导通。任意相邻的两排晶体管中,后排的第一晶体管101的输入端和后排第二晶体管102的输入端分别连接所述前排的第一晶体管101的输出端,所述前排的第二晶体管102的输出端分别连接所述前排的第一晶体管101的输出端,所述后排的第二晶体管102的输出端分别连接所述后排第一晶体管101的输出端,每一排晶体管的导通端均相互连通用于接受一代表数字信号的高电平信号或低电平信号(D0,D1,D2,D3,D4),所述最后一排晶体管的两个晶体管的输出端相互连接用于输出一转换模拟信号Vout。
在本实施例中,所述晶体管为场效应管,所述晶体管为场效应管,所述导通端为所述场效应管的栅极,所述输入端为所述场效应管的漏极,所述输出端为所述场效应管的源极。
在使用过程中,当所述信号D0,D1,D2,D3,D4为不同的高电平信号或低电平信号而代表一数字信号时,使不同的晶体管导通闭合而使Vout输出等于V1,。。。V32其中的一个。例如,当所述信号D0,D1,D2,D3,D4中的信号D3
为低电平,其他为高电平,Vout等于V24。
在另一实施例中,所述晶体管为三极管,所述导通端为所述三极管的基极,所述输入端为所述三极管的集电极,所述输出端为所述三极管的发射极。
相对现有技术,本实施例中的数模转换器的每排晶体管的数量按后排相对前排逐一减半布设,结构简单,在转换同样的数字信号的情况下可以节省很多晶体管,从而使数模转换器的成本也低。
虽然已经参照特定实施例示出并描述了本发明,但是本领域的技术人员将理解:在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下,可在此进行形式和细节上的各种变化。
Claims (12)
- 一种数模转换器,包括N排晶体管,其中,每排晶体管的数量按后排相对前排逐一减半布设,所述N排晶体管包含的晶体管数量为M、N为自然数,N大于1,M在1至N之间取值,每一晶体管包括一导通端、一输入端及一输出端,第一排晶体管的数量为2N,最后一排晶体管的数量为2,所述第一排晶体管的输入端用于连接2N个不同的电压信号,每一排晶体管包括半数的第一晶体管及半数的第二晶体管,所述第一晶体管和所述第二晶体管的导通电平相反,任意相邻的两排晶体管中,后排的第一晶体管的输入端和后排第二晶体管的输入端分别连接所述前排的第一晶体管的输出端,所述前排的第二晶体管的输出端分别连接所述前排的第一晶体管的输出端,所述后排的第二晶体管的输出端分别连接所述后排第一晶体管的输出端,每一排晶体管的导通端均相互连通用于接受一代表数字信号的高电平信号或低电平信号,所述最后一排晶体管的两个晶体管的输出端相互连接用于输出一转换模拟信号。
- 根据权利要求1所述的数模转换器,其中,所述晶体管为场效应管,所述导通端为所述场效应管的栅极,所述输入端为所述场效应管的漏极,所述输出端为所述场效应管的源极。
- 根据权利要求2所述的数模转换器,其中,所述第一晶体管为N沟道场效应管,所述第二晶体管为P沟道场效应管。
- 根据权利要求1所述的数模转换器,其中,所述晶体管为三极管,所述导通端为所述三极管的基极,所述输入端为所述三极管的集电极,所述输出端为所述三极管的发射极。
- 根据权利要求1所述的数模转换器,其中,所述第一晶体管的导通端用于在接收低电平信号而导通,所述第二晶体管的导通端用于在接收高电平信号而导通。
- 一种显示面板,其中,所述显示面板包括数模转换器,所述数模转换器包括N排晶体管,每排晶体管的数量按后排相对前排逐一减半布设,所述N排晶体管包含的晶体管数量为M、N为自然数,N大于1,M在1至N之间取值,每一晶体管包括一导通端、一输入端及一输出端,第一排晶体管的数量为2N,最后一排晶体管的数量为2,所述第一排晶体管的输入端用于连接2N 个不同的电压信号,每一排晶体管包括半数的第一晶体管及半数的第二晶体管,所述第一晶体管和所述第二晶体管的导通电平相反,任意相邻的两排晶体管中,后排的第一晶体管的输入端和后排第二晶体管的输入端分别连接所述前排的第一晶体管的输出端,所述前排的第二晶体管的输出端分别连接所述前排的第一晶体管的输出端,所述后排的第二晶体管的输出端分别连接所述后排第一晶体管的输出端,每一排晶体管的导通端均相互连通用于接受一代表数字信号的高电平信号或低电平信号,所述最后一排晶体管的两个晶体管的输出端相互连接用于输出一转换模拟信号。
- 根据权利要求6所述的显示面板,其中,所述晶体管为场效应管,所述导通端为所述场效应管的栅极,所述输入端为所述场效应管的漏极,所述输出端为所述场效应管的源极。
- 根据权利要求7所述的显示面板,其中,所述第一晶体管为N沟道场效应管,所述第二晶体管为P沟道场效应管。
- 根据权利要求6所述的显示面板,其中,所述晶体管为三极管,所述导通端为所述三极管的基极,所述输入端为所述三极管的集电极,所述输出端为所述三极管的发射极。
- 根据权利要求6所述的显示面板,其中,所述晶体管为三极管,所述导通端为所述三极管的基极,所述输入端为所述三极管的集电极,所述输出端为所述三极管的发射极。
- 根据权利要求6所述的显示面板,其中,所述显示面板为液晶面板。
- 根据权利要求6所述的显示面板,其中,所述显示面板包括2N个电压端,所述2N个电压端用于输出所述2N个不同的电压信号。
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| US7671773B2 (en) * | 2007-11-30 | 2010-03-02 | Infineon Technologies Ag | Jitter insensitive single bit digital to analog converter |
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| KR20070070992A (ko) * | 2005-12-29 | 2007-07-04 | 매그나칩 반도체 유한회사 | 소형 티에프티 구동 드라이버 아이시 제품의디지털-아날로그 컨버터 |
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| US10185166B2 (en) | 2019-01-22 |
| CN105810168A (zh) | 2016-07-27 |
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