WO2017198077A1 - 静电释放组件、阵列基板及其制备方法、显示面板 - Google Patents

静电释放组件、阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2017198077A1
WO2017198077A1 PCT/CN2017/083204 CN2017083204W WO2017198077A1 WO 2017198077 A1 WO2017198077 A1 WO 2017198077A1 CN 2017083204 W CN2017083204 W CN 2017083204W WO 2017198077 A1 WO2017198077 A1 WO 2017198077A1
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Prior art keywords
electrode
electrostatic discharge
discharge assembly
edge
auxiliary electrode
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PCT/CN2017/083204
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English (en)
French (fr)
Inventor
刘振定
潘晓东
胡志明
南春香
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US15/566,145 priority Critical patent/US10573640B2/en
Publication of WO2017198077A1 publication Critical patent/WO2017198077A1/zh
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • H10D86/441—Interconnections, e.g. scanning lines
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    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
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    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to an electrostatic discharge assembly, an array substrate, a method of fabricating the same, and a display panel.
  • Both the thin film transistor liquid crystal display and the active organic light emitting diode display comprise an array substrate, and a plurality of data lines and gate lines are disposed on the array substrate.
  • the discharge of charges on the data lines and the gate lines often causes breakdown of Electro-Static discharge (ESD), causing the data lines and the gate lines to be short-circuited, resulting in Poor display.
  • ESD Electro-Static discharge
  • An embodiment of the present disclosure provides an electrostatic discharge assembly including: a base substrate, a semiconductor layer disposed on the base substrate, a first insulating layer, a first auxiliary electrode, a first electrode, and a second electrode; wherein The first electrode and the second electrode are spaced apart from each other and are respectively in contact with the semiconductor layer, and the first auxiliary electrode is in contact with one of the first electrode and the second electrode, the first insulation A layer is disposed between the first electrode and the second electrode and the first auxiliary electrode.
  • the electrostatic discharge assembly further includes a second auxiliary electrode disposed spaced apart from the first auxiliary electrode, the second auxiliary electrode being in contact with the other of the first electrode and the second electrode.
  • an edge of at least one of the first auxiliary electrode, the second auxiliary electrode, the first electrode, and the second electrode includes a serrated edge.
  • first electrode and the second electrode are disposed in the same layer, and the first electrode and the second electrode include a first edge and a second edge opposite to each other, the first edge and the At least one of the second edges includes a serrated edge.
  • a portion of each of the first edge and the second edge is serrated, and the first edge has a zigzag shape in a direction in which the first edge or the second edge extends The portions and the serrated portions of the second edge are offset from each other.
  • first auxiliary electrode and the second auxiliary electrode are disposed in the same layer, and the first auxiliary electrode and the second auxiliary electrode include opposite third and fourth edges, At least one of the third edge and the fourth edge includes a serrated edge.
  • a portion of each of the third edge and the fourth edge is serrated, and the third edge has a zigzag shape in a direction in which the third edge or the fourth edge extends The portions and the zigzag portions of the fourth edge are offset from each other.
  • the electrostatic discharge assembly further includes a second insulating layer disposed between the semiconductor layer and the first auxiliary electrode.
  • the semiconductor layer is a polysilicon layer.
  • the electrostatic discharge assembly further includes at least one of a light shielding layer and an isolation layer disposed between the base substrate and the semiconductor layer, wherein a projection of the light shielding layer on the substrate substrate is completely covered Projection of the semiconductor layer on the substrate.
  • An array substrate includes a display area and a non-display area, and the above-described electrostatic discharge assembly located in the non-display area.
  • the array substrate further includes a gate line, a data line, and a common electrode line; wherein the gate line or the data line is connected to a first electrode of the electrostatic discharge assembly; the common electrode line a second electrode in the electrostatic discharge assembly is connected; or the gate line is connected to the first electrode in the electrostatic discharge assembly; the data line is connected to the second electrode in the electrostatic discharge assembly .
  • the first electrode and the second electrode in the electrostatic discharge assembly are disposed in the same layer as one of the gate line and the data line; or the display area further includes a pixel electrode, or a pixel An electrode and a common electrode, the first electrode and the second electrode in the electrostatic discharge assembly being disposed in the same layer as the pixel electrode or the common electrode.
  • the first auxiliary electrode in the electrostatic discharge assembly is disposed in the same layer as the gate line or the data line.
  • a method of fabricating an array substrate comprising: forming a display structure in a display area, and forming the electrostatic discharge assembly in a non-display area.
  • the electrostatic discharge assembly is formed in synchronization with the display structure.
  • the display structure includes a gate, a gate line, a source, a drain, a data line, and a pixel electrode; the first electrode and the second electrode and the gate, the gate line pass Forming the same patterning process; or, the first electrode and the second electrode are formed by the same patterning process as the source, the drain, and the data line; or, the first electrode and The second electricity The pole is formed by the same patterning process as the pixel electrode.
  • the display structure includes a common electrode; the first electrode and the second electrode are formed with the common electrode by the same patterning process.
  • the display structure includes a gate, a gate line, a source, a drain, and a data line; the first auxiliary electrode and the second auxiliary electrode pass the same pattern as the gate and the gate line The process is formed; or, the first auxiliary electrode and the second auxiliary electrode are formed by the same patterning process as the source, the drain, and the data line.
  • a display device includes the above array substrate.
  • the electrostatic discharge assembly in the embodiments of the present disclosure can improve the ESD resistance of the electrostatic discharge assembly.
  • FIG. 1(a) is a schematic structural view 1 of an electrostatic discharge assembly according to an embodiment of the present disclosure
  • FIG. 1(b) is a second schematic structural view of an electrostatic discharge assembly according to an embodiment of the present disclosure
  • FIG. 1(c) is a schematic structural view 3 of an electrostatic discharge assembly according to an embodiment of the present disclosure
  • FIG. 1(d) is a schematic structural view 4 of an electrostatic discharge assembly according to an embodiment of the present disclosure
  • FIG. 2( a ) is a top plan view showing a first auxiliary electrode and a second auxiliary electrode including a serrated tip in an electrostatic discharge assembly according to an embodiment of the present disclosure
  • FIG. 2(b) is a top plan view showing a first electrode and a second electrode including a serrated tip in an electrostatic discharge assembly according to an embodiment of the present disclosure
  • FIG. 2(c) is a top plan view showing a first auxiliary electrode, a second auxiliary electrode, a first electrode, and a second electrode each including a serrated tip in an electrostatic discharge assembly according to an embodiment of the present disclosure
  • FIG. 3 is a schematic top plan view of a first auxiliary electrode, a second auxiliary electrode, a first electrode, and a second electrode each including a partially serrated tip in an electrostatic discharge assembly according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural view 5 of an electrostatic discharge assembly according to an embodiment of the present disclosure.
  • FIG. 5 is a partial cross-sectional view showing a display area of an array substrate according to an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides an electrostatic discharge assembly, as shown in FIG. 1(a) and FIG. 1(b), including a semiconductor layer 20, an insulating layer 30, a first auxiliary electrode 401, and a first surface disposed on a base substrate 10.
  • the first electrode 50 and the second electrode 60 are in contact with the semiconductor layer 20; the first electrode 50 or the second electrode 60 is in contact with the first auxiliary electrode 401; the first auxiliary electrode 401, the semiconductor layer 20, and the first electrode 50 and
  • An insulating layer 30 is provided between the two electrodes 60 for isolation.
  • electrostatic discharge assembly in the embodiment of the present disclosure can be applied to any electronic device for performing electrostatic discharge.
  • the principle of electrostatic discharge of the electrostatic discharge assembly of the embodiment of the present disclosure is: since the first electrode 50 and the second electrode 60 are in contact with the semiconductor layer 20, when the electrostatic discharge assembly is used for electrostatic discharge, the first electrode 50, A conductive path can be formed between the semiconductor layer 20 and the second electrode 60, and the semiconductor layer 20 has a special property.
  • the first auxiliary electrode As the line electrostatic voltage increases on the first electrode 50 and the first auxiliary electrode 401, the first auxiliary electrode The electric field strength of the 401 pair of semiconductor layers 20 is also relatively increased, so that the semiconductor layer 20 generates an inverted charge forming channel to facilitate the flow of electrostatic current.
  • the semiconductor layer 20 is equivalent to a small resistance, and the conductive path can electrostatically release and neutralize the electric charge.
  • the semiconductor layer 20 channel is equivalent to a low resistance, thereby performing electrostatic discharge and neutralization on a high electrostatic voltage with a large current.
  • the above electrostatic discharge assembly when applied to an array substrate, it can be used to solve static electricity generated by a data line or a gate line.
  • the data line is connected to the first electrode 50 in the electrostatic discharge assembly
  • the common electrode line is connected to the second electrode 60 in the electrostatic discharge assembly.
  • the data The current on the line can flow to the common electrode line through the first electrode 50 and the semiconductor layer 20, so that the small current on the data line is gradually released and neutralized; as the electrostatic voltage generated on the data line gradually increases (for example, 50V ⁇ 300V), the semiconductor layer 20 is under the action of high voltage, The electric resistance is reduced, so that the electrostatic current generated on the data line can flow rapidly to the common electrode line through the first electrode 50 and the semiconductor layer 20, so that a large current on the data line is released and neutralized; when static electricity is generated on the data line When the voltage is relatively large (300V to 1KV), on the one hand, the resistance of the semiconductor layer 20 is reduced by the high voltage, so that the electrostatic current on the data line can quickly flow to the common electrode line through the first electrode 50 and the semiconductor layer 20.
  • the voltage is relatively large (300V to 1KV)
  • the resistance of the semiconductor layer 20 is reduced by the high voltage, so that the electrostatic current on the data line can quickly flow to the common electrode line through the first electrode 50 and the semiconductor layer
  • the current on the data line is quickly released and neutralized.
  • the first electrode 50 and the second electrode 60 are oppositely disposed, when the voltage on the data line is large, the first electrode 50 and the second electrode 60 may also be The current on the data line is released and neutralized; on the other hand, since the first electrode 50 or the second electrode 60 is also connected to the first auxiliary electrode 401, the current on the data line can also be performed through the first auxiliary electrode 401. Release and neutralize.
  • the specific arrangement positions of the semiconductor layer 20, the first auxiliary electrode 40, the first electrode 50, and the second electrode 60 in the electrostatic discharge device are not limited as long as the first electrode 50 and the second electrode 60 are in contact with the semiconductor layer 20.
  • the semiconductor layer 20, the insulating layer 30, the first auxiliary electrode 401, and the first electrode 50 and the second electrode 60 may be sequentially formed on the base substrate 10.
  • a first auxiliary electrode 401, an insulating layer 30, a semiconductor layer 20, and first and second electrodes 50 and 60 are sequentially formed on the base substrate 10.
  • the first auxiliary electrode 401 may be in contact with the first electrode 50 or in contact with the second electrode 60 through a via hole on the insulating layer 30.
  • the first auxiliary electrode 401 is disposed between the first electrode 50, the second electrode 60, and the semiconductor layer 20, and the first auxiliary electrode 401 is in contact with the first electrode 50 or the second electrode 60, and the first electrode 50 and The second electrode 60 is in contact with the semiconductor layer 20, that is, corresponding to the first auxiliary electrode 401 being in contact with the semiconductor layer 40.
  • the first auxiliary electrode 401 can quickly open the conductive path in the semiconductor layer 20 for electrostatic discharge and neutralization.
  • the material of the semiconductor layer 20 is not limited, and may be, for example, amorphous silicon, polycrystalline silicon or the like.
  • the material of the insulating layer 30 is not limited, and may be, for example, an insulating material such as silicon nitride, silicon oxide or silicon oxynitride.
  • the materials of the first auxiliary electrode 401, the first electrode 50, and the second electrode 60 may be, for example, aluminum, tungsten, chromium, molybdenum or other metals, metal compounds, and alloys as long as they can conduct electricity.
  • the materials of the first auxiliary electrode 401, the first electrode 50, and the second electrode 60 may be the same or different.
  • Embodiments of the present disclosure provide an electrostatic discharge assembly due to a first electrode 50 and a second electrode 60
  • the semiconductor layer 20 is in contact with each other, so that when the electrostatic discharge assembly is used for electrostatic discharge, the first electrode 50, the semiconductor layer 20, and the second electrode 60 can form a conductive path. Since the resistance of the semiconductor layer 20 decreases with the increase of the voltage, the electrostatic discharge component can perform passive electrostatic discharge, that is, when the electrostatic voltage is small, the electrostatic discharge component can release and neutralize the electrostatic voltage with a small current. Active electrostatic discharge can be performed again, that is, as the electrostatic voltage increases, the ability of the electrostatic discharge assembly to release and neutralize large currents increases.
  • the first auxiliary electrode 401 since the first auxiliary electrode 401 is in contact with the first electrode 50 or the second electrode 60, when the current passing through the electrostatic discharge assembly is large, the first auxiliary electrode 401 can also release and neutralize a large current. Thereby the electrostatic discharge assembly can quickly release and neutralize static electricity.
  • the electrostatic discharge assembly in the embodiment of the present disclosure can perform corresponding release and neutralization of static electricity of different voltages, thereby improving the anti-ESD capability of the electrostatic discharge assembly.
  • the electrostatic current can be sequentially released and neutralized by the first electrode 50, the semiconductor layer 20, and the second electrode 60. Of course, it can also be sequentially performed by the second electrode 60, the semiconductor layer 20, and the first electrode 50. Release and neutralization, and thus the electrostatic discharge assembly can also perform a two-way flow.
  • the above-described electrostatic discharge assembly further includes a second auxiliary electrode 402 that is opposite to and insulated from the first auxiliary electrode 401.
  • the first auxiliary electrode 401 and the second auxiliary electrode 402 are spaced apart from each other.
  • the material of the second auxiliary electrode 402 and the material of the first auxiliary electrode 401 may be the same or different.
  • the material of the second auxiliary electrode 402 may be, for example, aluminum, tungsten, chromium, molybdenum or other metals, metal compounds, and alloys.
  • the second auxiliary electrode 402 may be in contact with the second electrode 60 through a via hole on the insulating layer 30.
  • both the first auxiliary electrode 401 and the second auxiliary electrode 402 can instantaneously release and neutralize the large current, so that the electrostatic discharge component can be quickly released. Neutralizes static electricity, increasing the ability of electrostatic discharge components to discharge and neutralize large currents.
  • the first auxiliary electrode 401 and the second auxiliary electrode 402 respectively include a serrated tip, that is, include serrations. And/or; the first electrode 50 and the second electrode 60 each include a serrated tip, that is, a serrated edge.
  • the first auxiliary electrode 401 and the second auxiliary electrode 402 are disposed in the same layer and the opposite sides of the first auxiliary electrode 401 and the second auxiliary electrode 402 respectively include a jagged tip and/or
  • the first electrode 50 and the second electrode 60 are disposed in the same layer, and opposite sides of the first electrode 50 and the second electrode 60 respectively include a serrated tip.
  • embodiments according to the present disclosure are not limited thereto, and an edge of at least one of the first auxiliary electrode, the second auxiliary electrode, the first electrode, and the second electrode may include a jagged edge.
  • the opposite sides of the first auxiliary electrode 401 and the second auxiliary electrode 402 respectively include a zigzag-shaped tip, and the opposite sides of the first electrode 50 and the second electrode 60 do not include a zigzag shape.
  • the tip of the shape; or, as shown in FIG. 2(c), the opposite sides of the first auxiliary electrode 401 and the second auxiliary electrode 402 respectively include a serrated tip, and the opposite sides of the first electrode 50 and the second electrode 60 are also Each includes a serrated tip.
  • first auxiliary electrode 401 and the second auxiliary electrode 402 may be all tips arranged in a zigzag shape as shown in FIGS. 2( a ) and 2 ( c ), or may be As shown in Figure 3, it is partially provided as a serrated tip.
  • the opposite side of the first electrode 50 and the second electrode 60 may be a tip end which is all provided in a zigzag shape as shown in Fig. 2(b), or may be a tip end portion which is partially provided in a zigzag shape as shown in Fig. 3.
  • the number of serrated tips included for the first auxiliary electrode 401, the second auxiliary electrode 402, the first electrode 50, and the second electrode 60 may be set according to the maximum voltage for discharge in the electrostatic discharge assembly. The greater the number of serrated tips, the faster the release of high voltage static electricity.
  • the first auxiliary electrode 401 and the second auxiliary electrode 402 are disposed in the same layer, and opposite sides of the first auxiliary electrode 401 and the second auxiliary electrode 402 are respectively provided with serrated tips, and/or first The electrode 50 and the second electrode 60 are disposed in the same layer, and the opposite sides of the first electrode 50 and the second electrode 60 are respectively provided with a zigzag-shaped tip. Since the tip-shaped shape is favorable for high-voltage transient discharge, when the electrostatic discharge component is required When the high voltage static electricity is released and neutralized, the zigzag tip provided on the opposite side of the first auxiliary electrode 401, the second auxiliary electrode 402, and/or the first electrode 50 and the second electrode 60 may be instantaneously performed. Discharge.
  • the spacing between the first electrode 50 and the second electrode 60 is in the range of 1 micrometer to 5 micrometers, and the spacing between the first auxiliary electrode 401 and the second auxiliary electrode 402 is between 1 micrometer and 5 micrometers.
  • the embodiment of the present disclosure is not particularly limited thereto, and the range of the above-described pitch may be adjusted according to actual conditions.
  • the first auxiliary electrode 401 and the second auxiliary electrode 402 are relatively close, if the opposite sides of the first auxiliary electrode 401 and the second auxiliary electrode 402 are all arranged in a zigzag tip, the first The serrated tip of the auxiliary electrode 401 is easily in contact with the serrated tip of the second auxiliary electrode 402, thereby causing the first auxiliary electrode 401 and the second auxiliary electrode 402 to be connected together, thereby making the above-mentioned electrostatic discharge assembly high.
  • the purpose of instantaneous release and neutralization of high voltage static electricity cannot be effectively achieved; similarly, if the opposite sides of the first electrode 50 and the second electrode 60 are all arranged in a zigzag tip, the first electrode 50 is sawtoothed. The tip of the electrode is easily contacted with the serrated tip of the second electrode 60, thereby causing the first electrode 50 and the second electrode 60 to be connected together, so that the above-mentioned electrostatic discharge assembly cannot effectively achieve instantaneous release and medium at high voltage. And the purpose of high voltage static electricity.
  • the tips on the first auxiliary electrode 401 and the second auxiliary electrode 402 are staggered from each other (for example, staggered from each other in the extending direction of the corresponding jagged edge); Or, the tips on the first electrode 50 and the tips on the second electrode 60 are offset from each other, which may be more advantageous for tip discharge (for example, staggered from each other in the extending direction of the corresponding jagged edges).
  • the tip of the first electrode 50 and the tip of the second electrode 60 are offset from each other, that is, the tip of the first electrode 50 and the tip of the second electrode 60 are integrally offset from each other; the first auxiliary electrode
  • the fact that the tips on the 401 and the second auxiliary electrode 402 are offset from each other means that the entire tip end on the first auxiliary electrode 401 is entirely offset from the tip on the first auxiliary electrode 401.
  • the semiconductor layer 20 is a polysilicon layer 201, here.
  • the insulating layer 30 includes a first sub-insulating layer 301 and a second sub-insulating layer 302. The first sub-insulating layer 301 is disposed between the polysilicon layer 201 and the first auxiliary electrode 401, and the second sub-insulating layer 302 is disposed at the An auxiliary electrode 401 is interposed between the first electrode 50 and the second electrode 60.
  • the polysilicon layer 201 can be formed by depositing a layer of amorphous silicon (a-Si) on the substrate 10, using ELA (Excimer Laser Annealing) or SPC (Solid Phase Crystallization). The crystallization is performed in such a manner as to form the polysilicon layer 201. Of course, the polysilicon layer 201 can also be formed directly.
  • a-Si amorphous silicon
  • SPC Solid Phase Crystallization
  • the material of the second sub-insulating layer 302 may be the same as or different from the material of the first sub-insulating layer 301.
  • the electrostatic discharge assembly in the embodiment of the present disclosure can quickly discharge static electricity due to high mobility of polysilicon and fast response speed.
  • the electrostatic discharge assembly further includes a semiconductor disposed on the base substrate 10.
  • the light shielding layer 70 and the isolation layer 80 on one side of the layer 20; the projection of the light shielding layer 70 on the base substrate 10 completely covers the projection of the semiconductor layer 20 on the base substrate 10.
  • the material of the light shielding layer 70 may be any ink, a resin polymer, a metal, or the like as long as it can be shielded from light.
  • the material of the isolation layer 80 may be an insulating material such as silicon nitride, silicon oxide or silicon oxynitride.
  • the light shielding layer 70 by providing the light shielding layer 70 and causing the projection of the light shielding layer 70 on the substrate substrate 10 to completely cover the projection of the semiconductor layer 20 on the substrate substrate 10, the influence of the illumination on the semiconductor layer 20 can be avoided. Thereby avoiding the effects on the electrostatic discharge assembly.
  • Embodiments of the present disclosure provide an array substrate including a display area and a non-display area, and the non-display area includes a plurality of the above-described electrostatic discharge assemblies.
  • the display area includes gate lines, data lines, and sub-pixels defined by intersections of gate lines and data lines, each of the sub-pixels including a thin film transistor including a gate, an insulating layer, a semiconductor layer, a source, and a drain.
  • each sub-pixel further includes a pixel electrode, and further may further include a common electrode and a common electrode line.
  • the array substrate is an array substrate of an Organic Light-Emitting Diode (OLED) display
  • each of the sub-pixels further includes an anode, an organic material functional layer, and a cathode.
  • FIG. 5 illustrates a partial cross-sectional view of a display area of an array substrate in accordance with an embodiment of the present disclosure.
  • the display region includes a gate electrode 100 formed on the base substrate 10, a gate insulating layer 200, an active layer 300, a source electrode 4001, a drain 4002, a passivation layer 500, a pixel electrode layer 600, and a flat surface. Layer 700 and pixel electrode 800.
  • the array substrate further includes a gate line formed integrally with the gate electrode 100 and a data line integrally formed with the source electrode 4001.
  • the structure shown in FIG. 5 is merely an exemplary structure, and embodiments according to the present disclosure are not limited thereto.
  • the layers in the electrostatic discharge assembly in the display zone and the non-display zone can be formed in the same patterning process to simplify the process, as will be described in more detail below.
  • the number of the electrostatic discharge components can be determined according to the needs of the array substrate. The number of data lines and gates that are electrostatically discharged is properly set.
  • Embodiments of the present disclosure provide an array substrate in which a plurality of electrostatic discharge assemblies are disposed in a non-display area, since each electrostatic discharge assembly can have low voltage static electricity, medium voltage static electricity or high voltage on the gate lines and data lines connected thereto.
  • the static electricity is respectively released and neutralized, thereby improving the ESD resistance of the array substrate and preventing the array substrate from being damaged.
  • the display area includes a gate line, a data line, and a common electrode line, wherein the gate line or the data line is connected to the first electrode 50 in the electrostatic discharge assembly; the common electrode line and the second electrode 60 in the electrostatic discharge assembly The gates are connected.
  • the gate line is connected to the first electrode 50 in the electrostatic discharge assembly; the data line is connected to the second electrode 60 in the electrostatic discharge assembly.
  • the gate line or the data line is connected to the first electrode 50 in the electrostatic discharge assembly, and only the gate line may be connected to the first electrode 50 in the electrostatic discharge assembly for releasing the gate line.
  • Electrostatic voltage; or, only the data line is connected to the first electrode 50 in the electrostatic discharge assembly for releasing the electrostatic voltage on the data line; of course, the gate line and the data line are both different from the different electrostatic discharge components.
  • An electrode 50 is connected, and the gate line and the data line are connected to different electrostatic discharge components for releasing electrostatic voltages on the gate lines and the data lines.
  • the first auxiliary electrode 401 is in contact with the first electrode 50, since the first electrode 50 is in contact with the semiconductor layer 20, it is the same as the first electrode 50, whether it is a gate line or a data line or a common electrode line.
  • the first auxiliary electrode 401 which is also in contact with the first electrode 50, so that when a large current is discharged, the charge on the gate line or the data line or the common electrode can be discharged through the first electrode or through the first An auxiliary electrode discharge; similarly, if the second auxiliary electrode 402 is in contact with the second electrode 60, since the second electrode 60 is in contact with the semiconductor layer 20, whether it is a gate line or a data line or a common electrode line, it is second The electrodes 60 are connected, i.e., are also connected to a second auxiliary electrode 402 that is in contact with the second electrode 60.
  • the gate line or the data line can only be connected to one of the first electrode 50 or the first auxiliary electrode 401 that is in contact with the first electrode 50, and if one gate line is connected to the first electrode 50, Connecting a gate line and the first auxiliary electrode 401 in contact with the first electrode 50 in the electrostatic discharge assembly may cause the two gate lines to be short-circuited; or a gate line is connected to the first electrode 50, a data line and the Connecting the first auxiliary electrode 401 in contact with the first electrode 50 in the electrostatic discharge assembly causes The gate line and the data line are shorted.
  • each common electrode line is usually connected to a constant potential, such as grounding or zeroing potential, so that while one common electrode line is connected to the first electrode 50, the other common electrode line can be connected to the first auxiliary electrode 401;
  • the connection between the two electrodes 60 and the first auxiliary electrode 402 is similar to that of the first electrode 50 and the second auxiliary electrode 402, and details are not described herein again.
  • the gate lines and the data lines may be connected to the first electrodes 50 in different static release assemblies, the common electrode lines and the electrostatic discharge The second electrode 60 in the assembly is connected.
  • the number of the electrostatic discharge components in the array substrate is at least equal to the sum of the number of gate lines and the number of data lines.
  • the gate line may be connected to the second electrode 60 in the electrostatic discharge assembly, and the data line is connected to the first electrode 50 in the electrostatic discharge assembly.
  • the number of the electrostatic discharge components in the array substrate should be at least larger than the gate line. And the number of the number of lines in the data line.
  • the first electrode 50 and the second electrode 60 in the electrostatic discharge assembly are disposed in the same layer as the gate line; or, the first electrode 50 and the second electrode 60 in the electrostatic discharge assembly are disposed in the same layer as the data line; or
  • the display region further includes a pixel electrode and a common electrode, and the first electrode 50 and the second electrode 60 of the electrostatic discharge assembly are disposed in the same layer as the pixel electrode or the common electrode.
  • the first electrode 50 and the second electrode 60 in the electrostatic discharge assembly may also be disposed in the same layer as the anode.
  • the first electrode 50 and the second electrode 60 and the gate line in the electrostatic discharge assembly are formed by the same patterning process, or the first electrode 50 and the second electrode 60 and the data line in the electrostatic discharge assembly are formed by the same patterning process. Or forming the first electrode 50 and the second electrode 60 and the pixel electrode or the common electrode in the electrostatic discharge assembly by the same patterning process.
  • the electrostatic discharge assembly can be fabricated while fabricating the gate line on the array substrate by using an existing process.
  • the first electrode 50 and the second electrode 60; or, the data line is disposed in the same layer as the first electrode 50 and the second electrode 60 in the electrostatic discharge assembly, and is fabricated in the electrostatic discharge assembly while the data line on the array substrate is fabricated
  • the first electrode 50 and the second electrode 60; or, the first electrode 50 and the second electrode 60 in the electrostatic discharge assembly are disposed in the same layer as the pixel electrode or the common electrode, so that the pixel electrode or the public can be fabricated by using an existing process. Making the first electrode 50 and the electrode simultaneously The second electrode 60, thus eliminating the need to add a new film layer and fabrication process, simplifies the fabrication process of the electrostatic discharge assembly.
  • the first auxiliary electrode 401 and the second auxiliary electrode 402 in the above-described electrostatic discharge assembly are disposed in the same layer as the gate line or the data line. That is, the first auxiliary electrode 401 and the second auxiliary electrode 402 and the gate line in the electrostatic discharge assembly are formed by the same patterning process, or the first auxiliary electrode 401 and the second auxiliary electrode in the electrostatic discharge assembly are formed by the same patterning process. 402 and data lines.
  • the first auxiliary electrode 401 and the second auxiliary electrode 402 in the electrostatic discharge assembly can be fabricated while fabricating the gate lines or data lines on the array substrate by using an existing process, without adding a new film layer and a manufacturing process. This simplifies the fabrication process of the electrostatic discharge assembly.
  • Embodiments of the present disclosure provide a method for fabricating an array substrate, comprising: forming a display structure in a display area, forming the above-mentioned electrostatic discharge assembly in a non-display area; and forming an electrostatic discharge assembly in synchronization with the display structure.
  • the display structure may include a gate, a gate line, a common electrode line, a source, a drain, a data line, a pixel electrode, and further may include a common electrode or the like.
  • structure in the electrostatic discharge assembly such as the first electrode 50, and which structure in the display structure are formed in synchronization.
  • the electrostatic discharge assembly and the display structure are formed synchronously, the electrostatic discharge assembly can be formed while forming the display structure, and the process of fabricating the array substrate is simplified without adding an additional process.
  • the first electrode 50 and the second electrode 60 are formed by the same patterning process as the gate and the gate line; or the first electrode 50 and the second electrode 60 pass through the same pattern as the source, the drain, and the data line.
  • the process is formed; or, the first electrode 50 and the second electrode 60 are formed by the same patterning process as the pixel electrode; or, the first electrode 50 and the second electrode 60 are formed by the same patterning process as the common electrode.
  • the first electrode 50 and the second electrode 60 are formed while forming the source, the drain, and the data line by using an existing process; or, the first electrode 50 and the second electrode 60 are formed while forming the pixel electrode. Or, the first electrode 50 and the second electrode 60 are formed while forming the gate electrode and the gate line; or, the first electrode 50 and the second electrode 60 are formed while forming the common electrode, so that no additional process is required, which is simplified The fabrication process of the array substrate.
  • the first auxiliary electrode 401 and the second auxiliary electrode 402 are formed by the same patterning process as the gate and the gate line; or the first auxiliary electrode 401 and the second auxiliary electrode 402 are connected to the source and the drain.
  • the pole and data lines are formed by the same patterning process.
  • first auxiliary electrode 401 and the second auxiliary electrode 402 are formed in different layers, the first auxiliary electrode 401, the second auxiliary electrode 402, and the first electrode 50 and the second electrode 60 are formed. It cannot be formed simultaneously with the gate or the gate line, or simultaneously with the source, drain, and data lines.
  • the first auxiliary electrode 401 and the second auxiliary electrode 402 are formed while forming the gate and the gate line by using an existing process; or, the first source, the drain, and the data line are formed while forming the first
  • the auxiliary electrode 401 and the second auxiliary electrode 402 are used to simplify the fabrication process of the array substrate without adding an additional process.
  • Embodiments of the present disclosure also provide a display device including the above array substrate.
  • the display device may be a display device of an LCD or a display device of an OLED.
  • the display device When the array substrate is an array substrate of the LCD, the display device further includes a pair of cassette substrates facing the array substrate, and the color film may be disposed on the array substrate or on the counter substrate.
  • Embodiments of the present disclosure provide a display device. Since the display device includes the above-described electrostatic discharge assembly, static electricity generated on the data lines and the gate lines can be released and neutralized, thereby preventing static electricity on the data lines and the gate lines. The display device is damaged, and the display device's ability to resist ESD is improved.

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Abstract

一种静电释放组件、阵列基板及其制备方法、显示面板。静电释放组件包括：衬底基板（10），设置在衬底基板（10）上的半导体层（20）、绝缘层（30）、第一辅助电极（401）、第一电极（50）和第二电极（60）；其中，第一电极（50）和第二电极（60）彼此间隔设置且分别与半导体层（20）接触，第一辅助电极（401）与第一电极（50）和第二电极（60）之一接触，绝缘层（30）设置在第一电极（50）和第二电极（60）二者与第一辅助电极（401）之间。静电释放组件可以用于释放与中和静电。

Description

静电释放组件、阵列基板及其制备方法、显示面板 技术领域
本公开涉及一种静电释放组件、阵列基板及其制备方法、显示面板。
背景技术
薄膜晶体管液晶显示器和有源式有机发光二极管显示器均包括阵列基板，阵列基板上均设置有大量的数据线和栅线。然而，在栅线和数据线的交叠部位，由于数据线和栅线上的电荷的释放经常会引起静电(Electro-Static discharge，简称ESD)击穿，使得数据线和栅线短路，从而导致显示不良。
发明内容
本公开的实施例提供一种静电释放组件，包括：衬底基板，设置在所述衬底基板上的半导体层、第一绝缘层、第一辅助电极、第一电极和第二电极；其中，所述第一电极和所述第二电极彼此间隔设置且分别与所述半导体层接触，所述第一辅助电极与所述第一电极和所述第二电极之一接触，所述第一绝缘层设置在所述第一电极和所述第二电极二者与所述第一辅助电极之间。
在一些示例中，静电释放组件还包括与第一辅助电极间隔设置的第二辅助电极，所述第二辅助电极与所述第一电极和所述第二电极中的另一者接触。
在一些示例中，所述第一辅助电极、所述第二辅助电极、所述第一电极和所述第二电极至少之一的边缘包括锯齿状边缘。
在一些示例中，所述第一电极和所述第二电极同层设置，所述第一电极和所述第二电极包括彼此相对的第一边缘和第二边缘，所述第一边缘和所述第二边缘至少之一包括锯齿状边缘。
在一些示例中，所述第一边缘和所述第二边缘各自的一部分为锯齿状，在所述第一边缘或所述第二边缘延伸的方向上，所述第一边缘的具有锯齿状的部分和所述第二边缘的具有锯齿状的部分彼此错开。
在一些示例中，所述第一辅助电极和所述第二辅助电极同层设置，所述第一辅助电极和所述第二辅助电极包括具有相对的第三边缘和第四边缘，所 述第三边缘和所述第四边缘至少之一包括锯齿状边缘。
在一些示例中，所述第三边缘和所述第四边缘各自的一部分为锯齿状，在所述第三边缘或所述第四边缘延伸的方向上，所述第三边缘的具有锯齿状的部分和所述第四边缘的具有锯齿状的部分彼此错开。
在一些示例中，静电释放组件还包括第二绝缘层，设置在所述半导体层与所述第一辅助电极之间。
在一些示例中，所述半导体层为多晶硅层。
在一些示例中，静电释放组件还包括设置在所述衬底基板与所述半导体层之间的遮光层和隔离层至少之一，其中所述遮光层在所述衬底基板上的投影完全覆盖所述半导体层在所述衬底基板上的投影。
根据本公开的实施例提供一种阵列基板，包括显示区和非显示区，以及位于所述非显示区中的上述静电释放组件。
在一些示例中，阵列基板还包括栅线、数据线以及公共电极线；其中，所述栅线或所述数据线与所述静电释放组件中的第一电极相连；所述公共电极线与所述静电释放组件中的第二电极相连；或者，所述栅线与所述静电释放组件中的所述第一电极相连；所述数据线与所述静电释放组件中的所述第二电极相连。
在一些示例中，所述静电释放组件中的所述第一电极和所述第二电极与所述栅线和所述数据线之一同层设置；或者所述显示区还包括像素电极，或像素电极和公共电极，所述静电释放组件中的所述第一电极和所述第二电极与所述像素电极或所述公共电极同层设置。
在一些示例中，所述静电释放组件中的第一辅助电极与所述栅线或所述数据线同层设置。
根据本公开的实施例提供一种阵列基板的制备方法，包括：在显示区形成显示结构，在非显示区形成上述静电释放组件。
在一些示例中，所述静电释放组件与所述显示结构同步形成。
在一些示例中，所述显示结构包括栅极、栅线、源极、漏极、数据线及像素电极；所述第一电极和所述第二电极与所述栅极、所述栅线通过同一次构图工艺形成；或者，所述第一电极和所述第二电极与所述源极、所述漏极、及所述数据线通过同一次构图工艺形成；或者，所述第一电极和所述第二电 极与所述像素电极通过同一次构图工艺形成。
在一些示例中，所述显示结构包括公共电极；所述第一电极和所述第二电极与所述公共电极通过同一次构图工艺形成。
在一些示例中，所述显示结构包括栅极、栅线、源极、漏极以及数据线；所述第一辅助电极和第二辅助电极与所述栅极、所述栅线通过同一次构图工艺形成；或者，所述第一辅助电极和第二辅助电极与所述源极、所述漏极、所述数据线通过同一次构图工艺形成。
根据本公开的实施例提供一种显示装置，包括上述阵列基板。
本公开实施例中的静电释放组件可以提高了静电释放组件的抗ESD的能力。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1(a)为本公开实施例提供的一种静电释放组件的结构示意图一；
图1(b)为本公开实施例提供的一种静电释放组件的结构示意图二；
图1(c)为本公开实施例提供的一种静电释放组件的结构示意图三；
图1(d)为本公开实施例提供的一种静电释放组件的结构示意图四；
图2(a)为本公开实施例提供的一种静电释放组件中第一辅助电极和第二辅助电极包括锯齿状的尖端的俯视结构示意图；
图2(b)为本公开实施例提供的一种静电释放组件中第一电极和第二电极包括锯齿状的尖端的俯视结构示意图；
图2(c)为本公开实施例提供的一种静电释放组件中第一辅助电极、第二辅助电极、第一电极和第二电极均包括锯齿状的尖端的俯视结构示意图；
图3为本公开实施例提供的一种静电释放组件中第一辅助电极、第二辅助电极、第一电极和第二电极均包括部分锯齿状的尖端的俯视结构示意图；
图4为本公开实施例提供的一种静电释放组件的结构示意图五；
图5为本公开实施例提供的阵列基板的显示区的局部截面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例提供一种静电释放组件,如图1(a)和图1(b)所示，包括设置在衬底基板10上的半导体层20、绝缘层30、第一辅助电极401、第一电极50和第二电极60；第一电极50和第二电极60相对设置(例如，第一电极50和第二电极60彼此间隔设置)。第一电极50和第二电极60与半导体层20均接触；第一电极50或第二电极60与第一辅助电极401接触；第一辅助电极401、半导体层20、以及第一电极50和第二电极60之间设置有绝缘层30隔离。
需要说明的是，本公开实施例中的静电释放组件可以应用在任意的电子设备中，用于进行静电释放。例如，显示器的阵列基板、集成电路等。
本公开实施例的静电释放组件进行静电释放的原理为：由于第一电极50和第二电极60与半导体层20均接触，因此，当该静电释放组件用于静电释放时，第一电极50、半导体层20和第二电极60之间便可形成一个导电通道，而半导体层20具有特殊的性能，随着线路静电电压于第一电极50和第一辅助电极401上的增加，第一辅助电极401对半导体层20电场强度也相对提高,致使半导体层20产生反相电荷形成通道后利于静电电流流过。此时，半导体层20相当于是个小电阻，所述导电通道可以对电荷进行静电释放与中和。进一步地，当静电电压越高时，半导体层20通道相当于低电阻，从而对高静电电压进行大电流进行静电释放与中和。
例如，当上述静电释放组件应用于阵列基板时，可用于解决数据线或栅线产生的静电。示例的，数据线与静电释放组件中的第一电极50相连，公共电极线与静电释放组件中的第二电极60相连，当数据线上产生的静电电压较小(例如＜50V)时，数据线上的电流可以通过第一电极50、半导体层20流向公共电极线，从而使得数据线上的小电流逐渐被释放与中和；随着数据线上产生的静电电压逐渐增大(例如50V～300V)，半导体层20在高电压的作用下， 电阻减小，因而数据线上产生的静电电流可以通过第一电极50、半导体层20快速流向公共电极线，从而使得数据线上的大电流被释放与中和；当数据线上产生的静电的电压较大(300V～1KV)时，一方面，半导体层20在高电压的作用下，电阻减小，因而数据线上的静电电流可以通过第一电极50、半导体层20快速流向公共电极线，从而使得数据线上的电流被快速释放和中和，此外，由于第一电极50和第二电极60相对设置，当数据线上的电压较大时，第一电极50和第二电极60也可以对数据线上的电流进行释放与中和；另一方面，由于第一电极50或第二电极60还与第一辅助电极401相连，因而数据线上的电流还可以通过第一辅助电极401进行释放与中和。
对于静电释放组件中半导体层20、第一辅助电极40、第一电极50和第二电极60具体设置位置不进行限定，只要第一电极50和第二电极60与半导体层20均接触即可。例如可以是如图1(a)或图1(c)所示的，在衬底基板10上依次形成半导体层20、绝缘层30、第一辅助电极401及第一电极50和第二电极60。在另一些示例中，如图1(b)所示的，在衬底基板10上依次形成第一辅助电极401、绝缘层30、半导体层20及第一电极50和第二电极60。
例如，第一辅助电极401可以通过绝缘层30上的过孔与第一电极50接触或者与第二电极60接触。
此处，第一辅助电极401设置在第一电极50、第二电极60与半导体层20之间，由于第一辅助电极401与第一电极50或第二电极60接触，而第一电极50和第二电极60与半导体层20接触，即，相当于第一辅助电极401与半导体层40接触，当所述导电通道中有电流经过时，由于第一辅助电极401与半导体层20的距离较近，因而第一辅助电极401可以使半导体层20中的导电通道快速打开，以进行静电释放与中和。
对于半导体层20的材料不进行限定，例如可以是非晶硅、多晶硅等。
对于绝缘层30的材料不进行限定，例如可以为氮化硅、氧化硅或氮氧化硅等绝缘材料。
对于第一辅助电极401、第一电极50和第二电极60的材料，只要能导电即可，例如可以为铝、钨、铬、钼或其它金属、金属化合物以及合金。第一辅助电极401、第一电极50和第二电极60的材料可以相同，也可以不同。
本公开实施例提供一种静电释放组件，由于第一电极50和第二电极60 与半导体层20均接触，因而当该静电释放组件用于静电释放时，第一电极50、半导体层20及第二电极60便可形成一个导电通道。由于半导体层20的电阻随着电压的增加，电阻减小，因而该静电释放组件既可以进行被动静电释放，即，当静电电压较小时，静电释放组件可以对静电电压进行小电流释放与中和，又可以进行主动静电释放，即，随着静电电压的增大，静电释放组件对大电流进行释放与中和的能力增加。进一步地，由于第一辅助电极401与第一电极50或第二电极60接触，因而当静电释放组件中经过的电流较大时，第一辅助电极401还可以对大电流进行释放与中和，从而使得静电释放组件可以快速释放和中和静电。本公开实施例中的静电释放组件可以对不同电压的静电进行相应的释放与中和，因而，提高了静电释放组件的抗ESD的能力。在此基础上，静电电流可以依次通过第一电极50、半导体层20和第二电极60进行释放与中和，当然也可以是，依次通过第二电极60、半导体层20和第一电极50进行释放和中和，因而该静电释放组件还可以进行对等双向流通。
例如，如图1(c)和图1(d)所示，上述静电释放组件还包括与第一辅助电极401相对且绝缘的第二辅助电极402。例如，第一辅助电极401和第二辅助电极402彼此间隔设置。
第二辅助电极402的材料和第一辅助电极401的材料可以相同，也可以不同。第二辅助电极402的材料例如可以为铝、钨、铬、钼或其它金属、金属化合物以及合金。第二辅助电极402可以通过绝缘层30上的过孔与第二电极60接触。
本公开实施例中，当静电释放组件中经过的电流较大时，第一辅助电极401和第二辅助电极402都可以对大电流进行瞬间释放与中和，从而使得静电释放组件可以快速释放与中和静电，提高了静电释放组件的大电流静电释放与中和的能力。
例如，如图2(a)、图2(b)、图2(c)或图3所示，第一辅助电极401和第二辅助电极402分别包括锯齿状的尖端，也就是说，包括锯齿状边缘；和/或；第一电极50和第二电极60分别包括锯齿状的尖端，也就是说，包括锯齿状边缘。例如，第一辅助电极401和所述第二辅助电极402同层设置且第一辅助电极401和所述第二辅助电极402的相对侧分别包括锯齿状的尖端和/ 或，第一电极50和所述第二电极60同层设置，且第一电极50和所述第二电极60的相对侧分别包括锯齿状的尖端。然而，根据本公开的实施例不限于此，也可以是第一辅助电极、第二辅助电极、第一电极和第二电极至少之一的边缘包括锯齿状边缘。
可以是如图2(a)所示的，第一辅助电极401和第二辅助电极402的相对侧分别包括锯齿状的尖端，第一电极50和第二电极60的相对侧不包括锯齿状的尖端；或者，如图2(b)所示的，第一辅助电极401和第二辅助电极402的相对侧不包括锯齿状的尖端，第一电极50和第二电极60的相对侧分别包括锯齿状的尖端；或者，如图2(c)所示的，第一辅助电极401和第二辅助电极402的相对侧分别包括锯齿状的尖端，第一电极50和第二电极60的相对侧也分别包括锯齿状的尖端。
此处，需要说明的是，第一辅助电极401和第二辅助电极402的相对侧可以是如图2(a)和图2(c)所示的全部设置成锯齿状的尖端，也可以是如图3所示的，部分设置成锯齿装的尖端。第一电极50和第二电极60的相对侧可以是如图2(b)所示的全部设置成锯齿状的尖端，也可以是如图3所示的部分设置成锯齿装的尖端。
对于第一辅助电极401、第二辅助电极402、第一电极50和第二电极60包括的锯齿状的尖端的个数，可根据静电释放组件中用于释放的最大电压进行设置。锯齿状的尖端的个数越多，越能够快速地释放高电压的静电。
本公开实施例中，第一辅助电极401和第二辅助电极402同层设置，且第一辅助电极401和第二辅助电极402的相对侧分别设置有锯齿状的尖端，和/或，第一电极50和第二电极60同层设置，且第一电极50和第二电极60的相对侧分别设置有锯齿状的尖端，由于尖端状的外形有利于高电压瞬间放电，因而当静电释放组件需要对高电压的静电进行释放与中和时，可以通过第一辅助电极401、第二辅助电极402，和/或，第一电极50和第二电极60的相对侧设置的锯齿状的尖端瞬间进行放电。
在一些示例中，第一电极50和第二电极60之间的间距在1微米至5微米的范围内，第一辅助电极401和第二辅助电极402之间的间距在1微米至5微米的范围内。然而，根据本公开的实施例对此没有特别限定，可以根据实际情况调整上述间距的范围。
在实际生产过程中，由于第一辅助电极401和第二辅助电极402的距离较近，若将第一辅助电极401和第二辅助电极402的相对侧，全部设置成锯齿状的尖端，则第一辅助电极401的锯齿状的尖端很容易和第二辅助电极402上锯齿状的尖端接触，因而会导致第一辅助电极401和第二辅助电极402连接在一起，从而使得上述静电释放组件在高电压时，不能有效达到瞬间释放与中和高电压静电目的；同理，若将第一电极50和第二电极60的相对侧，全部设置成锯齿状的尖端，则第一电极50的锯齿状的尖端很容易和第二电极60的锯齿状的尖端接触，因而会导致第一电极50和第二电极60连接在一起，从而使得上述静电释放组件在高电压时，不能有效达到瞬间释放和中和高电压的静电目的。
基于上述，在一些示例中，如图3所示，第一辅助电极401和第二辅助电极402上的尖端相互错开(例如，在相应的具有锯齿状的边缘的延伸方向上彼此错开)；和/或，第一电极50上的尖端与第二电极60上的尖端相互错开，如此可以更有利于尖端放电(例如，在相应的具有锯齿状的边缘的延伸方向上彼此错开)。
此处需要说明的是，第一电极50上的尖端与第二电极60上的尖端相互错开是指第一电极50上的尖端整体和第二电极60上的尖端整体相互错开；第一辅助电极401和第二辅助电极402上的尖端相互错开是指第一辅助电极401上的尖端整体与第一辅助电极401上的尖端整体相互错开。
基于上述，由于多晶硅具有高的迁移率、响应速度快等优点且多晶硅可以在低温下制作，因而，在一些示例中，如图1(a)所示，半导体层20为多晶硅层201，在此基础上，绝缘层30包括第一子绝缘层301和第二子绝缘层302，第一子绝缘层301设置在多晶硅层201与第一辅助电极401之间，第二子绝缘层302设置在第一辅助电极401与第一电极50和第二电极60之间。
多晶硅层201的制作过程例如可以是在衬底基板10上沉积一层非晶硅(a-Si)，采用ELA(Excimer Laser Annealing，准分子激光退火)或SPC(Solid Phase Crystallization，固相结晶化)的方式进行结晶，从而形成多晶硅层201。当然，也可以直接形成多晶硅层201。
第二子绝缘层302的材料可以和第一子绝缘层301的材料相同，也可以不同。
本公开实施例中，通过将半导体层20设置为多晶硅层201，由于多晶硅的迁移率高、响应速度快，因而本公开实施例中的静电释放组件能够快速释放静电。
在一些示例中，由于光照会影响半导体层20的漏电流，因而，为了避免光照对静电释放组件的影响，如图4所示，上述静电释放组件还包括设置在衬底基板10上的靠近半导体层20一侧的遮光层70和隔离层80；遮光层70在衬底基板10上的投影完全覆盖半导体层20在衬底基板10上的投影。
对于遮光层70的材料，只要能够遮光即可，例如可以为油墨、树脂聚合物、金属等。隔离层80的材料可以为氮化硅、氧化硅或氮氧化硅等绝缘材料。
本公开实施例中，通过设置遮光层70，且使遮光层70在衬底基板10上的投影完全覆盖半导体层20在衬底基板10上的投影，这样便可以避免光照对半导体层20的影响，进而避免了对静电释放组件的影响。
本公开实施例提供了一种阵列基板，包括显示区和非显示区，非显示区包括多个上述的静电释放组件。
显示区包括栅线、数据线，以及由栅线和数据线交叉限定的子像素，每个子像素包括薄膜晶体管，薄膜晶体管包括栅极、绝缘层、半导体层、源极和漏极。当该阵列基板为液晶显示器的(Liquid Crystal Display，简称LCD)阵列基板时，每个子像素还包括像素电极，进一步的还可以包括公共电极、公共电极线。当该阵列基板为有机电致发光二管(Organic Light-Emitting Diode，简称OLED)显示器的阵列基板时，每个子像素还包括阳极、有机材料功能层以及阴极。
图5示出了根据本公开一个实施例的阵列基板的显示区的局部截面图。如图5所示，显示区包括形成在衬底基板10上的栅极100、栅绝缘层200、有源层300、源极4001、漏极4002、钝化层500、像素电极层600、平坦化层700和像素电极800。另外，该阵列基板还包括与栅极100一体形成的栅线以及与源极4001一体形成的数据线。图5所示的结构仅仅为示例性结构，根据本公开的实施例不限于此。显示区内的各层与非显示区内的静电释放组件中的各层可以在同一构图工艺中形成以简化工艺，这在下文中会更加详细地描述。
需要说明的是，对于静电释放组件的个数，可根据阵列基板中需要进行 静电释放的数据线和栅极的条数进行合理设置。
本公开实施例提供一种阵列基板，在非显示区设置多个静电释放组件，由于每个静电释放组件都可以对与其相连的栅线和数据线上的低电压静电、中电压静电或高电压静电分别进行相对应的释放与中和，因而提高了阵列基板的抗ESD的能力，防止阵列基板受到破坏。
在一些示例中，显示区包括栅线、数据线以及公共电极线，其中，栅线或数据线与静电释放组件中的第一电极50相连；公共电极线与静电释放组件中的第二电极60栅极相连。
或者，栅线与静电释放组件中的第一电极50相连；数据线与静电释放组件中的第二电极60相连。
这样，可释放与中和栅极和/或数据线上的静电电压。
需要说明的是，本公开实施中栅线或数据线与静电释放组件中的第一电极50相连，可以是仅栅线与静电释放组件中的第一电极50相连，用于释放栅线上的静电电压；或者是，仅数据线与静电释放组件中的第一电极50相连，用于释放数据线上的静电电压；当然也可以是，栅线和数据线均与不同静电释放组件中的第一电极50相连，此时栅线和数据线与不同的静电释放组件相连，用于释放栅线和数据线上的静电电压。
本公开实施例中，若第一辅助电极401与第一电极50接触，由于第一电极50与半导体层20接触，因而无论是栅线或者数据线或者还是公共电极线，其与第一电极50相连，即相当于也和与第一电极50接触的第一辅助电极401相连，如此在大电流放电时，栅线或者数据线或者公共电极上的电荷可以既通过第一电极放电也可以通过第一辅助电极放电；同理，若第二辅助电极402与第二电极60接触，由于第二电极60与半导体层20接触，因而无论是栅线或者数据线或者还是公共电极线，其与第二电极60相连，即相当于也和与第二电极60接触的第二辅助电极402相连。
此处，需要说明的是，栅线或数据线只能和第一电极50或与第一电极50接触的第一辅助电极401中的一个相连，若一条栅线与第一电极50相连，另一条栅线和该静电释放组件中与第一电极50接触的第一辅助电极401相连，则会导致这两条栅线短路；或者，一条栅线与第一电极50相连，一条数据线和该静电释放组件中与第一电极50接触的第一辅助电极401相连，则会导致 栅线和数据线短路。可以理解的是，各条公共电极线通常接恒定电位，如接地或者接零电位，所以在一条公共电极线接第一电极50的同时，另一条公共电极线可以接第一辅助电极401；第二电极60和第一辅助电极402的连接与第一电极50和第二辅助电极402类似，在此不再赘述。
当需要对阵列基板中的栅线和数据线上的静电均进行释放与中和时，可以将栅线和数据线与不同的静释放组件中的第一电极50相连，公共电极线与静电释放组件中的第二电极60相连。此时，阵列基板中的静电释放组件的个数至少大于等于栅线条数和数据线条数之和。或者，可以将栅线与静电释放组件中的第二电极60相连，数据线与静电释放组件中的第一电极50相连，此时，阵列基板中的静电释放组件的个数至少应大于栅线和数据线中条数较多的个数。此处，需要说明的是，若数据线与栅线的条数不相同，数据线与栅线通过静电释放组件一一对应连接后，剩余的栅线或数据线可以通过公共电极线释放剩余的栅线或数据线上的电压。
在一些示例中，静电释放组件中的第一电极50和第二电极60与栅线同层设置；或者，静电释放组件中的第一电极50和第二电极60与数据线同层设置；或者，针对例如液晶显示器件而言，显示区还包括像素电极和公共电极，静电释放组件中的第一电极50和第二电极60与像素电极或公共电极同层设置。针对例如有机电致发光显示器件而言，静电释放组件中的第一电极50和第二电极60也可与阳极同层设置。
例如，通过同一次构图工艺形成静电释放组件中的第一电极50和第二电极60以及栅线，或者通过同一次构图工艺形成静电释放组件中的第一电极50和第二电极60以及数据线，或者通过同一次构图工艺形成静电释放组件中的第一电极50和第二电极60以及像素电极或公共电极。
本公开实施例中，由于栅线与静电释放组件中的第一电极50和第二电极60同层设置，因而可以利用现有工艺，在制作阵列基板上的栅线的同时制作静电释放组件中的第一电极50和第二电极60；或者，数据线与静电释放组件中的第一电极50和第二电极60同层设置，在制作阵列基板上的数据线的同时制作静电释放组件中的第一电极50和第二电极60；或者，将静电释放组件中的第一电极50和第二电极60与像素电极或公共电极同层设置，这样便可以利用现有工艺在制作像素电极或公共电极的同时制作第一电极50和 第二电极60，因而无需增加新的膜层和制作工艺，简化了静电释放组件的制作工艺。
在一些示例中，上述静电释放组件中的第一辅助电极401和第二辅助电极402与栅线或数据线同层设置。即，通过同一次构图工艺形成静电释放组件中的第一辅助电极401和第二辅助电极402与栅线，或者通过同一次构图工艺形成静电释放组件中的第一辅助电极401和第二辅助电极402与数据线。
本公开实施例，利用现有工艺在制作阵列基板上的栅线或数据线的同时可以制作静电释放组件中的第一辅助电极401和第二辅助电极402，无需增加新的膜层和制作工艺，因而简化了静电释放组件的制作工艺。
本公开实施例提供一种阵列基板的制备方法，包括：在显示区形成显示结构，在非显示区形成上述的静电释放组件；静电释放组件与显示结构同步形成。
显示结构可以包括栅极、栅线、公共电极线、源极、漏极、数据线、像素电极，进一步的还可以包括公共电极等。此处，对于静电释放组件中某一结构例如第一电极50与显示结构中的何种结构同步形成不进行限定。
本公开实施例中，由于静电释放组件和显示结构同步形成，因而可以在形成显示结构的同时形成静电释放组件，无需增加额外工艺，简化了阵列基板的制作工艺。
可选的，第一电极50和第二电极60与栅极、栅线通过同一次构图工艺形成；或者，第一电极50和第二电极60与源极、漏极及数据线通过同一次构图工艺形成；或者，第一电极50和第二电极60与像素电极通过同一次构图工艺形成；或者，第一电极50和第二电极60与公共电极通过同一次构图工艺形成。
本公开实施例，利用现有工艺在形成源极、漏极及数据线的同时形成第一电极50和第二电极60；或者，在形成像素电极的同时形成第一电极50和第二电极60；或者，在形成栅极、栅线的同时形成第一电极50和第二电极60；或者，在形成公共电极的同时形成第一电极50和第二电极60，这样便无需增加额外工艺，简化了阵列基板的制作工艺。
可选的，第一辅助电极401和第二辅助电极402与栅极、栅线通过同一次构图工艺形成；或者，第一辅助电极401和第二辅助电极402与源极、漏 极、数据线通过同一次构图工艺形成。
由于第一辅助电极401、第二辅助电极402与第一电极50、第二电极60是在不同层形成，因而第一辅助电极401、第二辅助电极402和第一电极50、第二电极60并不能与栅极、栅线同时形成，或与源极、漏极、数据线同时形成。
本公开实施例中，由于利用现有工艺在形成栅极、栅线的同时形成第一辅助电极401和第二辅助电极402；或者，在形成源极、漏极、数据线的同时形成第一辅助电极401和第二辅助电极402，这样便无需增加额外工艺，简化了阵列基板的制作工艺。
本公开实施例还提供了一种显示装置，包括上述的阵列基板。
显示装置可以为LCD的显示装置，也可以为OLED的显示装置。
当阵列基板为LCD的阵列基板时，显示装置还包括与阵列基板对盒的对盒基板，彩色膜片可以设置在阵列基板上，也可以设置在对盒基板上。
本公开实施例提供一种显示装置，由于该显示装置包括上述的静电释放组件，因而可以对数据线和栅线上产生的静电进行释放与中和，从而防止了数据线和栅线上的静电使显示装置受到破坏，提高了显示装置的抗ESD的能力。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。
本申请要求于2016年5月16日递交的中国专利申请第201610321379.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (20)

  1. 一种静电释放组件，包括：
    衬底基板，
    设置在所述衬底基板上的半导体层、第一绝缘层、第一辅助电极、第一电极和第二电极；
    其中，所述第一电极和所述第二电极彼此间隔设置且分别与所述半导体层接触，所述第一辅助电极与所述第一电极和所述第二电极之一接触，所述第一绝缘层设置在所述第一电极和所述第二电极二者与所述第一辅助电极之间。
  2. 根据权利要求1所述的静电释放组件，还包括与第一辅助电极间隔设置的第二辅助电极，所述第二辅助电极与所述第一电极和所述第二电极中的另一者接触。
  3. 根据权利要求2所述的静电释放组件，其中，所述第一辅助电极、所述第二辅助电极、所述第一电极和所述第二电极至少之一的边缘包括锯齿状边缘。
  4. 根据权利要求1或2所述的静电释放组件，其中，所述第一电极和所述第二电极同层设置，所述第一电极和所述第二电极包括彼此相对的第一边缘和第二边缘，所述第一边缘和所述第二边缘至少之一包括锯齿状边缘。
  5. 根据权利要求4所述的静电释放组件，其中，所述第一边缘和所述第二边缘各自的一部分为锯齿状，在所述第一边缘或所述第二边缘延伸的方向上，所述第一边缘的具有锯齿状的部分和所述第二边缘的具有锯齿状的部分彼此错开。
  6. 根据权利要求2所述的静电释放组件，其中，所述第一辅助电极和所述第二辅助电极同层设置，所述第一辅助电极和所述第二辅助电极包括具有相对的第三边缘和第四边缘，所述第三边缘和所述第四边缘至少之一包括锯齿状边缘。
  7. 根据权利要求6所述的静电释放组件，其中，所述第三边缘和所述第四边缘各自的一部分为锯齿状，在所述第三边缘或所述第四边缘延伸的方向上，所述第三边缘的具有锯齿状的部分和所述第四边缘的具有锯齿状的部分 彼此错开。
  8. 根据权利要求1-7任一项所述的静电释放组件，还包括第二绝缘层，设置在所述半导体层与所述第一辅助电极之间。
  9. 根据权利要求1-8任一项所述的静电释放组件，其中，所述半导体层为多晶硅层。
  10. 根据权利要求1-9任一项所述的静电释放组件，还包括设置在所述衬底基板与所述半导体层之间的遮光层和隔离层至少之一，
    其中所述遮光层在所述衬底基板上的投影完全覆盖所述半导体层在所述衬底基板上的投影。
  11. 一种阵列基板，包括显示区和非显示区，以及位于所述非显示区中的如权利要求1-10任一项所述的静电释放组件。
  12. 根据权利要求11所述的阵列基板，还包括栅线、数据线以及公共电极线；
    其中，所述栅线或所述数据线与所述静电释放组件中的第一电极相连；所述公共电极线与所述静电释放组件中的第二电极相连；
    或者，
    所述栅线与所述静电释放组件中的所述第一电极相连；所述数据线与所述静电释放组件中的所述第二电极相连。
  13. 根据权利要求12所述的阵列基板，其中，所述静电释放组件中的所述第一电极和所述第二电极与所述栅线和所述数据线之一同层设置；或者所述显示区还包括像素电极，或像素电极和公共电极，所述静电释放组件中的所述第一电极和所述第二电极与所述像素电极或所述公共电极同层设置。
  14. 根据权利要求12所述的阵列基板，其中，所述静电释放组件中的第一辅助电极与所述栅线或所述数据线同层设置。
  15. 一种阵列基板的制备方法，包括：
    在显示区形成显示结构，在非显示区形成权利要求1-10任一项所述的静电释放组件。
  16. 根据权利要求15所述的制备方法，其中，所述静电释放组件与所述显示结构同步形成。
  17. 根据权利要求15或16所述的制备方法，其中，所述显示结构包括栅极、栅线、源极、漏极、数据线及像素电极；
    所述第一电极和所述第二电极与所述栅极、所述栅线通过同一次构图工艺形成；或者，
    所述第一电极和所述第二电极与所述源极、所述漏极、及所述数据线通过同一次构图工艺形成；或者，
    所述第一电极和所述第二电极与所述像素电极通过同一次构图工艺形成。
  18. 根据权利要求15或16所述的制备方法，其中，所述显示结构包括公共电极；
    所述第一电极和所述第二电极与所述公共电极通过同一次构图工艺形成。
  19. 根据权利要求15或16所述的制备方法，其中，所述显示结构包括栅极、栅线、源极、漏极以及数据线；
    所述第一辅助电极和第二辅助电极与所述栅极、所述栅线通过同一次构图工艺形成；或者，
    所述第一辅助电极和第二辅助电极与所述源极、所述漏极、所述数据线通过同一次构图工艺形成。
  20. 一种显示装置，包括权利要求11-14任一项所述的阵列基板。
PCT/CN2017/083204 2016-05-16 2017-05-05 静电释放组件、阵列基板及其制备方法、显示面板 Ceased WO2017198077A1 (zh)

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